Display substrate and display device

Abstract

A display substrate includes a first display area. The first display area includes a plurality of display island areas separated from each other, and a light-transmitting area located between adjacent display island areas. The display island areas include a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on the substrate. At least one first pixel circuit is electrically connected to at least one first light-emitting element, and at least one first pixel circuit is configured to drive at least one first light-emitting element to emit light. First pixel circuits in adjacent display island areas in a first direction are electrically connected via a first signal line, and first pixel circuits in adjacent display island areas in a second direction are electrically connected via a second signal line. The first direction intersects the second direction. The material of the first signal line and the second signal line includes a transparent conductive material.

Description

Technical Field

[0001] This article relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, comprising: a first display area. The first display area comprises: a plurality of display island areas separated from each other, and a light-transmitting area located between adjacent display island areas. The display island areas comprise: a plurality of first pixel circuits and a plurality of first light-emitting elements provided on a substrate, at least one first pixel circuit of the plurality of first pixel circuits being electrically connected to at least one first light-emitting element of the plurality of first light-emitting elements, and the at least one first pixel circuit being configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas in a first direction are electrically connected via a first signal trace, and the first pixel circuits in adjacent display island areas in a second direction are electrically connected via a second signal trace; the first direction intersects the second direction; and the materials of the first signal trace and the second signal trace include a transparent conductive material.

[0006] In some exemplary embodiments, at least a portion of the first signal trace and the second signal trace is located in the light-transmitting area.

[0007] In some exemplary embodiments, the display island area includes: four first pixel circuits and four first light-emitting elements; the four first pixel circuits are electrically connected to the four first light-emitting elements in a one-to-one correspondence; and the four first pixel circuits are arranged sequentially along the first direction.

[0008] In some exemplary embodiments, the four first light-emitting elements include: one first light-emitting element emitting first color light, one first light-emitting element emitting second color light, and two first light-emitting elements emitting third color light.

[0009] In some exemplary embodiments, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in the same row, the two first light-emitting elements emitting the third color light are arranged in the same row, and the first light-emitting element emitting the first color light, one first light-emitting element emitting the third color light, the first light-emitting element emitting the second color light, and another first light-emitting element emitting the third color light are arranged in different columns.

[0010] In some exemplary embodiments, the light-emitting regions of the two first light-emitting elements emitting third color light do not overlap with the orthographic projection of the first pixel circuit electrically connected to the substrate. The light-emitting regions of the first light-emitting elements emitting first color light overlap with the orthographic projection of the first pixel circuit electrically connected to the substrate. The light-emitting regions of the first light-emitting elements emitting second color light overlap with the orthographic projection of the first pixel circuit electrically connected to the substrate.

[0011] In some exemplary embodiments, an orthographic projection of the first light-emitting element emitting light of the third color on the substrate overlaps with an orthographic projection of the second signal trace on the substrate.

[0012] In some exemplary embodiments, the multiple display island areas are arranged into multiple rows and columns, a row of display island areas includes multiple display island areas arranged along the first direction, and a column of display island areas includes multiple display island areas arranged along the second direction; two adjacent display island areas in at least one column of display island areas are arranged at least one row apart, and two adjacent display island areas in at least one row of display island areas are arranged at least one column apart.

[0013] In some exemplary embodiments, the display island region includes: a first first pixel circuit, a second first pixel circuit, a third first pixel circuit, and a fourth first pixel circuit sequentially arranged along a first direction. The third first pixel circuit in the display island region at the kth row and mth column is electrically connected to the first first pixel circuit at the k+1th row and m+1th column via the second signal routing line, and the fourth first pixel circuit in the display island region at the kth row and mth column is electrically connected to the second first pixel circuit at the k+1th row and m+1th column via the second signal routing line; where k and m are integers.

[0014] In some exemplary embodiments, the four first pixel circuits include a first first pixel circuit, a second first pixel circuit, a third first pixel circuit, and a fourth first pixel circuit arranged sequentially along a first direction. The second signal line electrically connected to the first first pixel circuit in the display island region and the second signal line electrically connected to the second first pixel circuit are at least partially parallel, and the second signal line electrically connected to the third first pixel circuit and the second signal line electrically connected to the fourth first pixel circuit are at least partially parallel. The second signal line electrically connected to the first first pixel circuit and the second signal line electrically connected to the fourth first pixel circuit are substantially symmetrical about a midline of the four first pixel circuits in the first direction, and the second signal line electrically connected to the second first pixel circuit and the second signal line electrically connected to the third first pixel circuit are substantially symmetrical about a midline of the four first pixel circuits in the first direction.

[0015] In some exemplary embodiments, the first signal trace and the second signal trace are located on a side of the first pixel circuit away from the substrate, and on a side of the first light-emitting element close to the substrate.

[0016] In some exemplary embodiments, the first signal trace and the second signal trace are in the same layer.

[0017] In some exemplary embodiments, the first signal trace is a straight line segment extending along the first direction, and the second signal trace is a broken line segment extending along the second direction.

[0018] In some exemplary embodiments, the first signal routing line includes: a first initial connection line transmitting a first initial signal, a first scan connection line transmitting a scan signal, a second scan connection line transmitting a first reset control signal, and a light emitting control line transmitting a light emitting control signal.

[0019] In some exemplary embodiments, the second signal trace includes: a data line, and a power connection line transmitting a first voltage signal.

[0020] In some exemplary embodiments, the display substrate further includes: a second display area located on at least one side of the first display area; the second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements arranged on the substrate, at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light.

[0021] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0022] In some exemplary embodiments, the display device further includes: a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate overlaps with the first display area of ​​the display substrate.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0025] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0026] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0027] Figure 3A and Figure 3B A partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0028] Figure 4 for Figure 3B A schematic diagram of a partial top view of the middle area S1;

[0029] Figure 5 for Figure 4 Schematic diagram of the local section along the Q-Q' direction;

[0030] Figure 6 for Figure 4 A partially enlarged schematic diagram of a display substrate after a semiconductor layer is formed;

[0031] Figure 7A for Figure 4 A partially enlarged schematic diagram of the display substrate after the first conductive layer is formed;

[0032] Figure 7B for Figure 7A A schematic diagram of the first conductive layer in FIG.

[0033] Figure 8A for Figure 4 A partially enlarged schematic diagram of the display substrate after the second conductive layer is formed;

[0034] Figure 8B for Figure 8A Schematic diagram of the second conductive layer;

[0035] Figure 9 for Figure 4 A partial enlarged schematic diagram of the display substrate after the third insulating layer is formed;

[0036] Figure 10A for Figure 4 A partial enlarged schematic diagram of the display substrate after the third conductive layer is formed;

[0037] Figure 10B for Figure 10A Schematic diagram of the third conductive layer;

[0038] Figure 11 for Figure 4 A partial enlarged schematic diagram of the display substrate after the fourth insulating layer is formed;

[0039] Figure 12A for Figure 4 A partially enlarged schematic diagram of a display substrate after a transparent conductive layer is formed;

[0040] Figure 12B for Figure 12A Schematic diagram of the transparent conductive layer;

[0041] Figure 13 for Figure 4 A partial enlarged schematic diagram of the display substrate after the fifth insulating layer is formed;

[0042] Figure 14A for Figure 4 A partial enlarged schematic diagram of the display substrate after the fourth conductive layer is formed;

[0043] Figure 14B for Figure 14A Schematic diagram of the fourth conductive layer;

[0044] Figure 15 for Figure 4 A partial enlarged schematic diagram of the display substrate after the sixth insulating layer is formed;

[0045] Figure 16A for Figure 4 A partial enlarged schematic diagram of a display substrate after the anode layer is formed;

[0046] Figure 16B for Figure 14A Schematic diagram of the middle anode layer;

[0047] Figure 17 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0049] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0050] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0051] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0052] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0053] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0054] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0055] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0056] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0057] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0058] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0059] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0060] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0061] An embodiment of the present disclosure provides a display substrate, comprising: a first display area. The first display area comprises: a plurality of display island areas separated from each other, and a light-transmitting area located between adjacent display island areas. The display island area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on a substrate. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas in the first direction are electrically connected through a first signal trace, and the first pixel circuits in adjacent display island areas in the second direction are electrically connected through a second signal trace. The material of the first signal trace and the second signal trace includes a transparent conductive material. The first direction intersects with the second direction. For example, the first direction and the second direction are perpendicular to each other.

[0062] The display substrate provided in this embodiment can help reduce the diffraction effect of the display substrate by centrally arranging multiple first pixel circuits and multiple first light-emitting elements in the display island area; moreover, the arrangement space of the first signal line and the second signal line can be increased, and the width of the first signal line and the second signal line can be increased, thereby reducing the load of the first signal line and the second signal line, and improving the display defects of the display substrate.

[0063] In some exemplary embodiments, at least portions of the first and second signal traces may be located in the light-transmitting region. In some examples, the first and second signal traces may extend from one display island region through the light-transmitting region to another display island region, thereby enabling signal transmission between first pixel circuits in adjacent display island regions. Furthermore, the first and second signal traces may be fabricated using a transparent conductive material to ensure light transmittance in the light-transmitting region.

[0064] In some exemplary embodiments, the display island area may include: four first pixel circuits and four first light-emitting elements. The four first pixel circuits and the four first light-emitting elements may be electrically connected in a one-to-one correspondence. The four first pixel circuits may be arranged sequentially along the first direction. In some examples, the four first pixel circuits and the four first light-emitting elements may form a pixel unit. However, this embodiment is not limited to this. In other examples, the display island area may include: two first pixel circuits and two first light-emitting elements, the two first pixel circuits and the two first light-emitting elements may be electrically connected in a one-to-one correspondence, and the two first pixel circuits may be arranged sequentially along the first direction.

[0065] In some exemplary embodiments, the four first light-emitting elements in the display island region may include: one first light-emitting element emitting a first color light, one first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light. For example, the first color light may be red light, the second color light may be blue light, and the third color light may be green light. However, this embodiment is not limited to this.

[0066] In some exemplary embodiments, within the display island area, a first light-emitting element emitting a first color light and a first light-emitting element emitting a second color light may be arranged in the same row, and two first light-emitting elements emitting a third color light may be arranged in the same row. A first light-emitting element emitting the first color light, one first light-emitting element emitting the third color light, a first light-emitting element emitting the second color light, and another first light-emitting element emitting the third color light may be arranged in different columns. In this example, a plurality of first light-emitting elements arranged along the first direction may be referred to as a row of first light-emitting elements, and a plurality of first light-emitting elements arranged along the second direction may be referred to as a column of first light-emitting elements.

[0067] In some exemplary embodiments, the orthographic projections of the light-emitting areas of the two first light-emitting elements emitting third color light in the display island area on the substrate may not overlap with the orthographic projections of the first pixel circuit electrically connected to the substrate. The orthographic projections of the light-emitting areas of the first light-emitting element emitting first color light on the substrate may overlap with the orthographic projections of the first pixel circuit electrically connected to the substrate. The orthographic projections of the light-emitting areas of the first light-emitting element emitting second color light on the substrate may overlap with the orthographic projections of the first pixel circuit electrically connected to the substrate. The arrangement of the first pixel circuit and the first light-emitting element in this example can increase the wiring freedom of the first signal line and the second signal line, and increase the line width of the first signal line and the second signal line, thereby alleviating the poor display caused by the excessive resistance of the first signal line and the second signal line. Moreover, the display effect of the display substrate can be ensured by compensating for the data signal received by the first pixel circuit electrically connected to the first light-emitting element emitting third color light.

[0068] In some exemplary embodiments, an orthographic projection of the first light-emitting element emitting the third color light on the substrate may overlap with an orthographic projection of the second signal trace on the substrate.

[0069] In some exemplary embodiments, the plurality of display islands in the first display area may be arranged into multiple rows and columns. A row of display islands may include multiple display islands arranged along a first direction, and a column of display islands may include multiple display islands arranged along a second direction. Two adjacent display islands in at least one column of display islands may be arranged at least one row apart, and two adjacent display islands in at least one row of display islands may be arranged at least one column apart. For example, two adjacent display islands in a column of display islands may be arranged one row apart, and two adjacent display islands in a row of display islands may be arranged one column apart. In this example, the display islands in adjacent rows may be misaligned in the second direction.

[0070] In some exemplary embodiments, the display island region may include: a first first pixel circuit, a second first pixel circuit, a third first pixel circuit, and a fourth first pixel circuit arranged sequentially along a first direction. The third first pixel circuit in the display island region at the kth row and mth column may be electrically connected to the first first pixel circuit at the k+1th row and m+1th column via a second signal trace, and the fourth first pixel circuit in the display island region at the kth row and mth column may be electrically connected to the second first pixel circuit at the k+1th row and m+1th column via a second signal trace; where k and m are integers.

[0071] In some exemplary embodiments, the four first pixel circuits of the display island area may include a first first pixel circuit, a second first pixel circuit, a third first pixel circuit, and a fourth first pixel circuit arranged in sequence along the first direction. The second signal line electrically connected to the first first pixel circuit of the display island area and the second signal line electrically connected to the second first pixel circuit may be at least partially parallel, and the second signal line electrically connected to the third first pixel circuit and the second signal line electrically connected to the fourth first pixel circuit may be at least partially parallel. The second signal line electrically connected to the first first pixel circuit and the second signal line electrically connected to the fourth first pixel circuit may be approximately symmetrical about a midline of the four first pixel circuits in the first direction, and the second signal line electrically connected to the second first pixel circuit and the second signal line electrically connected to the third first pixel circuit may be approximately symmetrical about a midline of the four first pixel circuits in the first direction.

[0072] In some exemplary embodiments, the first signal trace and the second signal trace may be located on a side of the first pixel circuit away from the substrate, and on a side of the first light-emitting element closer to the substrate. For example, the first signal trace and the second signal trace may be located on a side of a driver circuit layer away from the substrate, and the driver circuit layer may include multiple first pixel circuits.

[0073] In some exemplary embodiments, the first signal trace and the second signal trace may be located on the same layer. For example, the display substrate may include a transparent conductive layer, and the transparent conductive layer may include the first signal trace and the second signal trace. However, this embodiment is not limited to this. For example, the display substrate may include multiple transparent conductive layers, and the first signal trace and the second signal trace may be located on different transparent conductive layers.

[0074] In some exemplary embodiments, the first signal trace may be a straight line segment extending along a first direction, and the second signal trace may be a zigzag line segment extending along a second direction. In this example, by using a straight first signal trace segment to connect first pixel circuits in adjacent display islands in the first direction, and using a zigzag line segment to connect first pixel circuits in adjacent display islands in the second direction, the line widths of the first and second signal traces can be increased, reducing the load on the first and second signal traces, thereby improving display defects on the display substrate.

[0075] In some exemplary embodiments, the display substrate may further include a second display area located on at least one side of the first display area. The second display area may include a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate, wherein at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light.

[0076] The solution of this embodiment is illustrated below through some examples.

[0077] Figure 1 Schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a first display region A1 and a second display region A2. The second display region A2 may at least partially surround the first display region A1. For example, the second display region A2 may surround all four sides of the first display region A1.

[0078] In some examples, such as Figure 1 As shown, the first display area A1 can be a light-transmitting display area, and can also be called a Full Display With Camera (FDC) area; the second display area A2 can also be a normal display area. For example, the orthographic projection of a light sensor (such as a camera or other hardware) on the display substrate can be located in the first display area A1 of the display substrate. In some examples, such as Figure 1As shown, the first display area A1 can be circular, and the size of the orthographic projection of the light sensor on the display substrate can be smaller than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the light sensor on the display substrate can be smaller than or equal to the size of the inscribed circle of the first display area A1.

[0079] In some examples, such as Figure 1 As shown, the first display area A1 can be located in the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located in other locations such as the upper left corner or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0080] In some examples, such as Figure 1 As shown, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be a rectangle, a semicircle, a pentagon, or other shapes.

[0081] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0082] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0083] In some examples, a pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0084] In some examples, the shape of the light-emitting element can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0085] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited to this.

[0086] In some exemplary embodiments, Figure 2 As shown, the pixel circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7) and a storage capacitor Cst. The light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0087] In some exemplary embodiments, the seven transistors of the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield. In some possible implementations, the seven transistors of the pixel circuit may include P-type transistors and N-type transistors.

[0088] In some exemplary embodiments, the seven transistors of the pixel circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0089] In some exemplary embodiments, Figure 2As shown, the display substrate may include: a first scan line GL, a data line DL, a first power line VDD, a second power line VSS, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a second scan line RST1, and a third scan line RST2. In some examples, the first power line VDD may be configured to provide a constant first voltage signal to the pixel circuit, the second power line VSS may be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal may be greater than the second voltage signal. The first scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the emission control line EML may be configured to provide an emission control signal EM to the pixel circuit, the second scan line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the third scan line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, the second scan line RST1 electrically connected to the pixel circuit in the nth row can be electrically connected to the first scan line GL of the pixel circuit in the n-1th row so as to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) and the scan signal SCAN(n-1) can be the same. The third scan line RST2 of the pixel circuit in the nth row can be electrically connected to the first scan line GL of the pixel circuit in the nth row so as to be input with the scan signal SCAN(n), that is, the second reset control signal RESET2(n) and the scan signal SCAN(n) can be the same. Wherein, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be achieved. However, this embodiment is not limited to this.

[0090] In some exemplary embodiments, the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first initial signal and the second initial signal may be constant voltage signals, whose magnitudes may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.

[0091] In some exemplary embodiments, Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can also be referred to as a driving transistor. The gate of the fourth transistor T4 is electrically connected to the first scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The fourth transistor can also be referred to as a data writing transistor. The gate of the second transistor T2 is electrically connected to the first scan line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The second transistor can also be referred to as a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 may also be referred to as emission control transistors. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the second scan line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the third scan line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 may also be referred to as reset control transistors. A first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3 , and a second capacitor plate of the storage capacitor Cst is electrically connected to the first power line VDD.

[0092] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3, the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0093] The working process of the pixel circuit is described below. Figure 2The pixel circuit shown is described by taking as an example a case where all of the multiple transistors included are P-type transistors.

[0094] In some exemplary embodiments, during a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage.

[0095] The first phase is called the reset phase. The first reset control signal RESET1 provided by the second scan line RST1 is a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The scan signal SCAN provided by the first scan line GL is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting element EL does not emit light.

[0096] The second phase is called the data writing phase or the threshold compensation phase. The scan signal SCAN provided by the first scan line GL is a low-level signal, the first reset control signal RESET1 provided by the second scan line RST1, and the emission control signal EM provided by the emission control line EML are both high-level signals, and the data line DL outputs the data signal DATA. During this phase, since the first capacitor plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The scan signal SCAN is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second and fourth transistors T2 and T4 are turned on, causing the data voltage Vdata output by the data line DL to be provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor Cst. The voltage of the first capacitor plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the second initialization signal provided by the second initialization signal line INIT2 is supplied to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the second scan line RST1 is a high-level signal, turning off the first transistor T1. The emission control signal EM provided by the emission control signal line EML is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0097] The third phase is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal. The scan signal SCAN provided by the first scan line GL and the first reset control signal RESET1 provided by the second scan line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output from the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0098] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0099] I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 .

[0100] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0101] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0102] Figure 3A and Figure 3B FIG. 1 is a partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 3A and Figure 3B As shown, in a plane parallel to the display substrate, the first display area can include: a plurality of display island areas A11 separated from each other, and light-transmitting areas A12 located between adjacent display island areas A11. Each display island area A11 can be configured to display an image, and each light-transmitting area A12 can be configured to provide a space for light transmission.

[0103] In some examples, such as Figure 3AAs shown, within a plane parallel to the display substrate, the shapes of the multiple display islands A11 can be substantially identical. The display islands A11 can have smooth edges, thereby reducing light diffraction and improving photographic quality. The display islands A11 within the first display area can be independent of each other, while the light-transmitting areas A12 within the first display area can be connected. The light-transmitting areas A12 can surround the display islands A11.

[0104] In some examples, such as Figure 3A As shown, in a plane parallel to the display substrate, a plurality of display island areas A11 can be arranged into multiple rows and columns. A plurality of display island areas A11 arranged along the first direction X can be referred to as a row of display island areas, and a plurality of display island areas A11 arranged along the second direction Y can be referred to as a column of display island areas. The midlines of the plurality of display island areas A11 in a column of display island areas in the first direction X can be roughly aligned. Two adjacent display island areas A11 in a row of display island areas can be arranged one column apart. For example, if a display island area in the k-th row of display island areas is located in the m-th column, then a display island area adjacent to the display island area in the k-th row can be located in the m-2 column or in the m+2 column. Two adjacent display island areas A11 in a column of display island areas can be arranged one row apart. For example, if a display island area in the m-th column of display island areas is located in the k-th row, then a display island area adjacent to the display island area in the m-th column can be located in the k-2 row or in the k+2 row. Wherein, k and m are both integers. In this example, the display islands in adjacent rows may be misaligned in the second direction Y, and the display islands in adjacent columns may be misaligned in the first direction X.

[0105] In some examples, such as Figure 3B As shown, the first display area may include multiple first pixel circuits 11 and multiple first light-emitting elements 13. At least one first pixel circuit 11 may be electrically connected to at least one first light-emitting element 13, and at least one first pixel circuit 11 may be configured to drive the electrically connected at least one first light-emitting element 13 to emit light. In this example, the multiple first pixel circuits 11 and the multiple first light-emitting elements 13 in the first display area may be electrically connected in a one-to-one correspondence.

[0106] In some examples, such as Figure 3BAs shown, the multiple first light-emitting elements in the first display area may include: a first light-emitting element 13a emitting a first color light, a first light-emitting element 13b emitting a second color light, and first light-emitting elements 13c and 13d emitting a third color light. The multiple first light-emitting elements 11 in the first display area may be arranged according to a Pentile structure. Specifically, the first light-emitting element 13a emitting the first color light and the first light-emitting element 13b emitting the second color light may be alternately arranged in the i-th row, and the first light-emitting elements 13c and 13d emitting the third color light may be alternately arranged in the i+1-th row at a certain interval; in the i+2-th row adjacent to the i+1-th row, the first light-emitting element 13a emitting the first color light and the first light-emitting element 13b emitting the second color light may be alternately arranged; and the first light-emitting elements 13c and 13d emitting the third color light may be alternately arranged in the i+3-th row adjacent to the i+2-th row at a certain interval. Multiple rows of first light-emitting elements 11 may be repeatedly arranged according to the above rule. The first light-emitting element 13a emitting the first color light and the first light-emitting element 13b emitting the second color light arranged in the i-th row, as well as the first light-emitting elements 13c and 13d emitting the third color light arranged in the i-th row, can be arranged alternately. For example, the first light-emitting element 13a emitting the first color light and the first light-emitting element 13b emitting the second color light can be arranged alternately in the j-th column, and the first light-emitting elements 13c and 13d emitting the third color light can be arranged at regular intervals in the j+1-th column adjacent to the j-th column. The first light-emitting element 13a emitting the first color light and the first light-emitting element 13b emitting the second color light can be arranged alternately in the j+2-th column adjacent to the j+1-th column, and the first light-emitting elements 13c and 13d emitting the third color light can be arranged at regular intervals in the j+3-th column. Multiple columns of first light-emitting elements 11 can be repeatedly arranged according to the above rules. Wherein, i and j are both integers. In the present disclosure, a plurality of first light emitting elements arranged along the first direction X may be referred to as a row of first light emitting elements, and a plurality of first light emitting elements arranged along the second direction Y may be referred to as a column of first light emitting elements.

[0107] In some examples, such as Figure 3B As shown, the size of the first light-emitting element 13a emitting the first color light and the size of the first light-emitting element 13b emitting the second color light can be larger than the size of the first light-emitting element 13c or 13d emitting the third color light. For example, the first color light can be red, the second color light can be blue, and the third color light can be green. That is, the first light-emitting element emitting the first color light can be a red light-emitting element, the first light-emitting element emitting the second color light can be a blue light-emitting element, and the first light-emitting element emitting the third color light can be a green light-emitting element. However, this embodiment is not limited to this.

[0108] In some examples, such as Figure 3B As shown, the light-emitting area 130a of the first light-emitting element 13a emitting the first color light and the light-emitting area 130b of the first light-emitting element 13b emitting the second color light can be roughly rounded rectangles or circles. The light-emitting area 130c of the first light-emitting element 13c emitting the third color light and the light-emitting area 130d of the first light-emitting element 13d can be roughly elliptical. The light-emitting area 130a of the first light-emitting element 13a emitting the first color light can be smaller than the light-emitting area 130b of the first light-emitting element 13b emitting the second color light. The light-emitting area 130b of the first light-emitting element 13b emitting the second color light can be larger than the light-emitting area 130c of the first light-emitting element 13c emitting the third color light and the light-emitting area 130d of the first light-emitting element 13d. In this example, the light-emitting area of ​​a light-emitting element can be the portion of the light-emitting element located at the pixel opening of the pixel definition layer.

[0109] In some examples, such as Figure 3B As shown, a single display island A11 in the first display area may include four first pixel circuits 11 and four first light-emitting elements 13. The four first light-emitting elements 13 of the display island A11 may include a first light-emitting element 13a that emits light of the first color, a first light-emitting element 13b that emits light of the second color, and two first light-emitting elements 13c and 13d that emit light of the third color. The four first pixel circuits 11 of the display island A11 may be arranged sequentially along the first direction X. The four first pixel circuits 11 of the display island A11 may include a first pixel circuit 11a electrically connected to the first light-emitting element 13a that emits light of the first color, a first pixel circuit 11b electrically connected to the first light-emitting element 13c that emits light of the third color, a first pixel circuit 11c electrically connected to the first light-emitting element 13b that emits light of the second color, and a first pixel circuit 11d electrically connected to the first light-emitting element 13d that emits light of the third color. The first pixel circuits 11a, 11b, 11c, and 11d are arranged sequentially along the first direction X. In a display island area A11, the first light-emitting element 13a emitting the first color light and the first light-emitting element 13b emitting the second color light can be arranged in the same row, and the two first light-emitting elements 13c and 13d emitting the third color light can be arranged in the same row; the first light-emitting element 13a emitting the first color light, one first light-emitting element 13c emitting the third color light, the first light-emitting element 13b emitting the second color light and another first light-emitting element 13d emitting the third color light can be arranged in different columns.

[0110] In some examples, such as Figure 3BAs shown, within the display island area A11, the light-emitting area 130c of the first light-emitting element 13c emitting the third color light may not overlap with the orthographic projection of the first pixel circuit 11b electrically connected to it on the substrate. The light-emitting area 130d of the first light-emitting element 13d emitting the third color light may not overlap with the orthographic projection of the first pixel circuit 11d electrically connected to it on the substrate. The light-emitting area 130a of the first light-emitting element 13a emitting the first color light may overlap with the orthographic projection of the first pixel circuit 11a electrically connected to it on the substrate. The light-emitting area 130b of the first light-emitting element 13b emitting the second color light may overlap with the orthographic projection of the first pixel circuit 11c electrically connected to it on the substrate.

[0111] Figure 4 for Figure 3B Schematic diagram of a partial top view of the middle area S1. Figure 5 for Figure 4 Schematic diagram of the local cross-section along the Q-Q' direction. Figure 4 FIG. 3 illustrates two display islands adjacent to each other along the second direction Y and parts of two display islands adjacent to each other along the first direction X. FIG.

[0112] In some examples, such as Figure 4 and Figure 5 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 100, a driving circuit layer, a transparent conductive layer 24, a fourth conductive layer 25, and a light-emitting structure layer, sequentially disposed on the substrate. The driving circuit layer may include: a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23, sequentially disposed on the substrate 100. A first insulating layer 101 may be disposed between the semiconductor layer 20 and the first conductive layer 21, a second insulating layer 102 may be disposed between the first conductive layer 21 and the second conductive layer 22, and a third insulating layer 23 may be disposed between the second conductive layer 22 and the third conductive layer 23. A fourth insulating layer 104 may be disposed between the third conductive layer 23 and the transparent conductive layer 24. A fifth insulating layer 105 may be disposed between the transparent conductive layer 24 and the fourth conductive layer 25. A sixth insulating layer 106 may be disposed between the fourth conductive layer 25 and the anode layer 301. In some examples, the first to fourth insulating layers 101 to 104 may be inorganic insulating layers, and the fifth insulating layer 105 and the sixth insulating layer 106 may be organic insulating layers. However, this embodiment is not limited thereto.

[0113] In some examples, the light-emitting structure layer may include at least: an anode layer 301, a pixel definition layer 302, an organic light-emitting layer, and a cathode layer, which are sequentially arranged on the substrate 100. The anode layer 301 can be electrically connected to the pixel circuit of the driving circuit layer, the organic light-emitting layer can be connected to the anode layer 301, and the cathode layer can be connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the anode layer 301 and the cathode layer. An encapsulation structure layer can be provided on the side of the light-emitting structure layer away from the substrate 100. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer may be provided between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this disclosure.

[0114] Refer to the following Figures 4 to 16B The structure and preparation process of the display substrate are exemplified. The "patterning process" mentioned in the embodiment of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0115] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0116] (1) Provide a substrate. In some examples, the substrate 100 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen.

[0117] (2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate and patterned by a patterning process to form a semiconductor layer 20 disposed on the substrate. In some examples, the material of the semiconductor layer 20 can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0118] Figure 6 for Figure 4 A partially enlarged schematic diagram of a display substrate after forming a semiconductor layer. In some examples, such as Figure 6 As shown, the semiconductor layer 20 of a single display island area A11 in the first display area may include at least: a first active layer 310 of the first transistor T1 to a seventh active layer 370 of the seventh transistor T7 of four first pixel circuits. The first active layer 310 of the first transistor T1 to the seventh active layer 370 of the seventh transistor T7 of a first pixel circuit may be an interconnected integral structure.

[0119] In some examples, such as Figure 6 As shown, the first pixel circuit 11a in the display island area is used as an example for description. The first active layer 310, the second active layer 320, the fourth active layer 340, and the seventh active layer 370 of the first pixel circuit can be located on one side of the third active layer 330 of the first pixel circuit in the second direction Y, and the fifth active layer 350 and the sixth active layer 360 can be located on the other side of the third active layer 330 of the first pixel circuit in the second direction Y.

[0120] In some examples, such as Figure 6As shown, the first active layer 310 of the first pixel circuit may be U-shaped, the second active layer 320 may be L-shaped, the third active layer 330 may be n-shaped, and the fourth active layer 340, the fifth active layer 350, the sixth active layer 360, and the seventh active layer 370 may all be I-shaped. However, this embodiment is not limited thereto.

[0121] In some examples, such as Figure 6 As shown, the active layers 310 of the first transistor 31 through the active layer 370 of the seventh transistor 37 of the first pixel circuit can each include a first region, a second region, and a channel region located between the first and second regions. The first region 340-1 of the fourth active layer 340, the first region 350-1 of the fifth active layer 350, the second region 360-2 of the sixth active layer 360, and the second region 370-2 of the seventh active layer 370 can be provided separately. The first region 310-1 of the first active layer 310 can also serve as the first region 370-1 of the seventh active layer 370. The second region 310-2 of the first active layer 310 can also serve as the first region 320-1 of the second active layer 320. The second region 320-2 of the second active layer 320 can also serve as the second region 330-2 of the third active layer 330 and the first region 360-1 of the sixth active layer 360. The first region 330 - 1 of the third active layer 330 may simultaneously serve as the second region 340 - 2 of the fourth active layer 340 and the second region 350 - 2 of the fifth active layer 350 .

[0122] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate 100 having the aforementioned pattern formed thereon. The first conductive film is patterned through a patterning process to form a first insulating layer and a first conductive layer 21 disposed on the first insulating layer 101. In some examples, the first conductive layer 21 may also be referred to as a first gate metal layer.

[0123] Figure 7A for Figure 4 A partially enlarged schematic diagram of the display substrate after the first conductive layer is formed. Figure 7B for Figure 7A In some examples, such as Figure 7A and Figure 7BAs shown, the first conductive layer 21 of a single display island area in the first display area may include at least: a first scan line (for example, a first scan line GL(n), GL(n+1) or GL(n+2)), a third scan line (for example, a third scan line RST1(n), RST1(n+1), RST1(n+2)), a light-emitting control line (for example, a light-emitting control line EML(n), EML(n+1) or EML(n+2)), and a first capacitor plate 381 of a storage capacitor of a first pixel circuit. The first capacitor plate 381 of the storage capacitor of the first pixel circuit may also serve as a gate of the third transistor T3. The orthographic projection of the first capacitor plate 381 on the substrate may be a rectangle, for example, a rounded rectangle. The first scan line, the third scan line and the light-emitting control line may extend along a first direction X within the display island area. In one display island area, the first scan line may be located between the third scan line and the light-emitting control line.

[0124] In some examples, such as Figure 7A As shown, the overlapping region of the third scan line RST1(n) and the first active layer 310 can serve as the gate of the first transistor T1. The overlapping region of the first scan line GL(n) and the second active layer 320 can serve as the gate of the second transistor T2. The overlapping region of the first scan line GL(n) and the fourth active layer 340 can serve as the gate of the fourth transistor T4. The overlapping region of the first scan line GL(n) and the seventh active layer 370 can serve as the gate of the seventh transistor T7. The overlapping region of the emission control line EML(n) and the fifth active layer 350 can serve as the gate of the fifth transistor T5, and the overlapping region of the emission control line EML(n) and the sixth active layer 360 can serve as the gate of the sixth transistor T6. In this example, the first transistor T1 and the second transistor T2 can be dual-gate transistors. However, this embodiment is not limited to this.

[0125] In some examples, after forming the first conductive layer 21 , the light-transmitting area of ​​the first display region may include: a substrate 100 , and a first insulating layer 101 disposed on the substrate 100 .

[0126] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate 100 having the aforementioned pattern formed thereon. The second conductive film is patterned through a patterning process to form a second insulating layer 102 covering the first conductive layer 21 and a second conductive layer 22 disposed on the second insulating layer 102. In some examples, the second conductive layer 22 may also be referred to as a second gate metal layer.

[0127] Figure 8A for Figure 4 A partially enlarged schematic diagram of the display substrate after the second conductive layer is formed. Figure 8B for Figure 8AIn some examples, such as Figure 8A and Figure 8B As shown, the second conductive layer 22 of a single display island area in the first display area may include at least: a first initial signal line INIT1 and a second capacitor plate 382 of the storage capacitor of the first pixel circuit. The orthographic projection of the second capacitor plate 382 of the storage capacitor of the first pixel circuit on the substrate may overlap with the orthographic projection of the first capacitor plate 381 on the substrate. For example, the orthographic projection of the second capacitor plate 382 on the substrate may be approximately L-shaped. The first initial signal line INIT1 may extend along the first direction X within the display island area. The orthographic projection of the first initial signal line INIT1 on the substrate may be located on a side of the third scan line away from the first scan line.

[0128] In some examples, after forming the second conductive layer 22 , the light-transmitting area of ​​the first display region may include: a substrate 100 , and a first insulating layer 101 and a second insulating layer 102 disposed on the substrate 100 .

[0129] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate 100 having the aforementioned pattern formed thereon, and the third insulating film is patterned by a patterning process to form a third insulating layer 103 .

[0130] Figure 9 for Figure 4 A partial enlarged schematic diagram of a display substrate after forming a third insulating layer. Figure 9 As shown, the third insulating layer 103 of a single display island area in the first display area can be provided with a plurality of via holes, for example, including: a first via hole V1 to a seventeenth via hole V17. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first via hole V1 to the sixth via hole V6 can be removed to expose the surface of the semiconductor layer 20. The third insulating layer 103 and the second insulating layer 102 within the seventh via hole V7 to the thirteenth via hole V13 can be removed to expose the surface of the first conductive layer 21. The third insulating layer 103 within the fourteenth via hole V14 to the seventeenth via hole V17 can be removed to expose the surface of the second conductive layer 22.

[0131] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate 100 having the aforementioned pattern formed thereon, and the third conductive film is patterned through a patterning process to form a third conductive layer 23. In some examples, the third conductive layer 23 may also be referred to as a first source / drain metal layer.

[0132] Figure 10A for Figure 4 A partially enlarged schematic diagram of the display substrate after the third conductive layer is formed. Figure 10B for Figure 10A In some examples, such as Figure 10A and Figure 10B As shown, the third conductive layer 23 of a single display island region of the first display region may include at least a plurality of connecting electrodes (eg, including a first connecting electrode 401 to a thirteenth connecting electrode 413 ).

[0133] In some examples, such as Figure 9 、 Figure 10A and Figure 10B As shown, a first pixel circuit in the display island area is used as an example for description. The first connecting electrode 401 can be electrically connected to the first area 310-1 of the first active layer 310 of the first transistor T1 through the first via V1, and can also be electrically connected to the first initial signal line INIT1 through the fifteenth via V15. The second connecting electrode 402 can be electrically connected to the first area 320-1 of the second active layer 320 of the second transistor T2 through the second via V2, and can also be electrically connected to the gate of the third transistor T3 through the seventh via V7. The third connecting electrode 403 can be electrically connected to the first area 340-1 of the fourth active layer 340 of the fourth transistor T4 through the third via V3. The fourth connecting electrode 404 can be electrically connected to the first area 350-1 of the fifth active layer 350 of the fifth transistor T5 through the fourth via V4, and can also be electrically connected to the second capacitor plate 382 of the storage capacitor through the fourteenth via V14. The fifth connection electrode 405 may be electrically connected to the second region 360 - 2 of the sixth active layer 360 of the sixth transistor T6 through the fifth via hole V5 and may also be electrically connected to the second region 370 - 2 of the seventh active layer 370 of the seventh transistor T7 through the sixth via hole V6 .

[0134] In some examples, such as Figure 9 、 Figure 10A and Figure 10B As shown, a display island area is used as an example for description. The sixth connecting electrode 406 can be located on one side of the first connecting electrode 401 in the first direction X. The seventh connecting electrode 407 can be electrically connected to one end of the first initial signal line INIT1 through the sixteenth via hole V16. The eighth connecting electrode 408 can be electrically connected to one end of the third scan line RST1(n) through the eighth via hole V8. The ninth connecting electrode 409 can be electrically connected to the other end of the third scan line RST1(n) through the ninth via hole V9. The tenth connecting electrode 410 can be electrically connected to one end of the first scan line GL(n) through the tenth via hole V10. The eleventh connecting electrode 411 can be electrically connected to the other end of the first scan line GL(n) through the eleventh via hole V11. The twelfth connecting electrode 412 can be electrically connected to one end of the emission control line EML(n) through the twelfth via hole V12. The thirteenth connecting electrode 413 can be electrically connected to the other end of the emission control line EML(n) through the thirteenth via hole V13.

[0135] In some examples, after forming the third conductive layer 23 , the light-transmitting area of ​​the first display region may include: a substrate 100 , and a first insulating layer 101 , a second insulating layer 102 , and a third insulating layer 103 disposed on the substrate 100 .

[0136] At this point, the driving circuit layer is completed. The driving circuit layer of a single display island area in the first display area may include four first pixel circuits arranged in sequence along the first direction X.

[0137] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate 100 having the aforementioned pattern formed thereon, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 104.

[0138] Figure 11 for Figure 4 A partial enlarged schematic diagram of a display substrate after forming a fourth insulating layer. Figure 11 As shown, the fourth insulating layer 104 of a single display island region of the first display region may be provided with a plurality of via holes, for example, including: a twenty-first via hole V21 to a thirty-second via hole V32. The fourth insulating layer 104 within the twenty-first via hole V21 to the thirty-second via hole V32 may be removed to expose the surface of the third conductive layer 23.

[0139] (8) Forming a transparent conductive layer. In some examples, a transparent conductive film is deposited on the substrate 100 having the aforementioned pattern formed thereon, and the transparent conductive film is patterned by a patterning process to form a transparent conductive layer 24.

[0140] Figure 12A for Figure 4 A partially enlarged schematic diagram of a display substrate after a transparent conductive layer is formed. Figure 12B for Figure 12A Schematic diagram of a transparent conductive layer in FIG. In some examples, such as Figure 12A and Figure 12B As shown, the transparent conductive layer 24 of a single display island area in the first display area may include at least: a plurality of connecting electrodes (for example, including: a fourteenth connecting electrode 414 and a fifteenth connecting electrode 415), a plurality of connecting lines (for example, including: a first connecting line 501 to a fourth connecting line 504), a plurality of power connecting lines 512 and a plurality of data lines 511.

[0141] In some examples, such as Figure 11 、 Figure 12A and Figure 12BAs shown, the fourteenth connecting electrode 414 can be electrically connected to the first connecting electrode 401 through the twenty-first via hole V21. By providing multiple fourteenth connecting electrodes 414 in the display island region, the uniformity of the film structure can be ensured. The fifteenth connecting electrode 415 can be electrically connected to the fifth connecting electrode 405 through the twenty-fourth via hole V24, thereby achieving electrical connection with the second region 360-2 of the sixth active layer 360 of the sixth transistor T6.

[0142] In some examples, such as Figure 11 、 Figure 12A and Figure 12B As shown, one end of the first connecting line 501 can be electrically connected to one end of the first initial signal line INIT1 in a display island area through the twenty-sixth via hole V26; the other end of the first connecting line 501 can extend to another display island area through the light-transmitting area, and be electrically connected to one end of the first initial signal line INIT1 in another display island area through the twenty-first via hole V21, thereby realizing the transmission of the first initial signal between adjacent display island areas in the first direction X.

[0143] In some examples, such as Figure 11 、 Figure 12A and Figure 12B As shown, one end of the second connecting line 502 can be electrically connected to the eighth connecting electrode 408 through the twenty-seventh via hole V27 to achieve electrical connection with one end of the third scanning line in a display island area; the other end of the second connecting line 502 can be extended to another display island area through the light-transmitting area, and be electrically connected to the ninth connecting electrode 409 through the twenty-eighth via hole V28 to achieve electrical connection with one end of the third scanning line in the display island area, thereby realizing the transmission of the first reset control signal between adjacent display island areas in the first direction X.

[0144] In some examples, such as Figure 11 、 Figure 12A and Figure 12B As shown, one end of the third connecting line 503 can be electrically connected to the tenth connecting electrode 410 through the twenty-ninth via hole V29 to achieve electrical connection with one end of the first scanning line in a display island area; the other end of the third connecting line 503 can be extended to another display island area through the light-transmitting area, and be electrically connected to the eleventh connecting electrode 411 through the thirtieth via hole V30 to achieve electrical connection with one end of the first scanning line in the display island area, thereby realizing the transmission of the scanning signal between adjacent display island areas in the first direction X.

[0145] In some examples, such as Figure 11 、 Figure 12A and Figure 12BAs shown, one end of the fourth connecting line 504 can be electrically connected to the twelfth connecting electrode 412 through the thirty-first via hole V31 to achieve electrical connection with one end of the light-emitting control line in a display island area; the other end of the fourth connecting line 504 can extend to another display island area through the light-transmitting area, and be electrically connected to the thirteenth connecting electrode 413 through the thirty-second via hole V32 to achieve electrical connection with one end of the light-emitting control line in the display island area, thereby realizing the transmission of the light-emitting control signal between adjacent display island areas in the first direction X.

[0146] In this example, the first signal lines connecting first pixel circuits in adjacent display islands in the first direction X may include: a first connection line 501 to a fourth connection line 504. The first connection line 501 may be a first initial connection line that transmits a first initial signal. The second connection line 502 may be a second scan connection line that transmits a first reset control signal. The third connection line 503 may be a first scan connection line that transmits a scan signal. The fourth connection line 504 may be a light-emitting control line that transmits a light-emitting control signal. In some examples, the first connection line 501 to the fourth connection line 504 may each be a straight line segment extending along the first direction X, i.e., a straight line.

[0147] In some examples, such as Figure 11 、 Figure 12A and Figure 12BAs shown, the data line 511 can be electrically connected to the third connection electrode 403 through the twenty-second via hole V22, thereby electrically connecting to the first region 340-1 of the fourth active layer 340 of the fourth transistor T4 of the first pixel circuit. The data line 511 can extend along the second direction Y. In the light-transmitting region between two adjacent display islands in the second direction Y, the data line 511 can have a zigzag shape. The zigzag paths of the data line electrically connected to the first pixel circuit 11a and the data line electrically connected to the first pixel circuit 11b within a display island can be the same. The zigzag paths of the data line electrically connected to the first pixel circuit 11c and the data line electrically connected to the first pixel circuit 11d can be the same. The zigzag path of the data line electrically connected to the first pixel circuit 11a can be different from the zigzag path of the data line electrically connected to the first pixel circuit 11c. For example, the data line electrically connected to the first pixel circuit 11a can first extend along the second direction Y from one display island to the light-transmitting region, then extend along a third direction F3 intersecting the second direction Y, and finally extend along the second direction Y to another display island. The clockwise angle between the second direction Y and the third direction F3 can be greater than 0 degrees and less than 90 degrees, for example, approximately 30 degrees, 45 degrees, or 60 degrees. The data line electrically connected to the first pixel circuit 11c can first extend from one display island area to the light-transmitting area along the second direction Y, then extend along a fourth direction F4 intersecting the second direction Y, and finally extend along the second direction Y to another display island area. The clockwise angle between the second direction Y and the fourth direction F4 can be greater than 90 degrees and less than 180 degrees, for example, approximately 100 degrees, 120 degrees, or 145 degrees.

[0148] In some examples, such as Figure 11 、 Figure 12A and Figure 12B As shown, one end of the power connection line 512 can be electrically connected to the fourth connection electrode 404 in one display island area through the twenty-third via hole V23, and the other end of the power connection line 512 can extend through the light-transmitting area to another display island area and be electrically connected to the sixth connection electrode 406 through the twenty-fifth via hole V25, thereby realizing the transmission of the first voltage signal between adjacent display island areas in the second direction Y. The power connection line 512 can be in the shape of a zigzag line extending along the second direction Y.

[0149] In this example, the second signal routing lines connecting first pixel circuits in adjacent display islands in the second direction Y may include a data line 511 and a power connection line 512. The power connection line 512 may be located between adjacent data lines 511 in the first direction X. The zigzag directions of the data lines 511 and the power connection lines 512 electrically connected to the same first pixel circuit may be substantially the same. In this example, by configuring the second signal routing lines as zigzag lines, the first signal routing lines may be bypassed to achieve electrical connection between the first pixel circuits in adjacent display islands.

[0150] In some examples, such as Figure 12A As shown, in a display island area, the first pixel circuits 11a, 11b, 11c, and 11d from left to right along the first direction X are respectively the first first pixel circuit, the second first pixel circuit, the third first pixel circuit, and the fourth first pixel circuit. The third first pixel circuit in a display island area in a row of display island areas can be electrically connected to the first first pixel circuit in a display island area in an adjacent column on the right side of the next row via a second signal line, and the fourth first pixel circuit in the display island area can be electrically connected to the second first pixel circuit in a display island area in an adjacent column on the right side of the next row via a second signal line. The first first pixel circuit in a display island area in a row of display island areas can be electrically connected to the third first pixel circuit in a display island area in an adjacent column on the left side of the next row via a second signal line, and the second first pixel circuit in the display island area can be electrically connected to the fourth first pixel circuit in a display island area in an adjacent column on the left side of the next row via a second signal line.

[0151] In some examples, such as Figure 12A As shown, the second signal line electrically connected to the first first pixel circuit and the second signal line electrically connected to the second first pixel circuit in a display island area can be at least partially parallel, and the second signal line electrically connected to the third first pixel circuit and the second signal line electrically connected to the fourth first pixel circuit can be at least partially parallel. The second signal line electrically connected to the first first pixel circuit and the second signal line electrically connected to the fourth first pixel circuit can be roughly symmetrical about the midline of the four first pixel circuits in the first direction X, and the second signal line electrically connected to the second first pixel circuit and the second signal line electrically connected to the third first pixel circuit can be roughly symmetrical about the midline of the four first pixel circuits in the first direction X. Specifically, the data line and the power supply line electrically connected to the first first pixel circuit and the data line and the power supply line electrically connected to the second first pixel circuit in the display island area can be at least partially parallel, and the data line and the power supply line electrically connected to the third first pixel circuit and the data line and the power supply line electrically connected to the fourth first pixel circuit can be at least partially parallel. The data line and power supply line electrically connected to the first first pixel circuit and the data line and power supply line electrically connected to the fourth first pixel circuit can be symmetrically designed, and the data line and power supply line electrically connected to the second first pixel circuit and the data line and power supply line electrically connected to the third first pixel circuit can be symmetrically designed. This facilitates the arrangement of the first signal lines and the second signal lines within the light-transmitting area and avoids mutual interference.

[0152] In some examples, after forming the transparent conductive layer 24, the light-transmitting region of the first display area may include: a substrate 100, and a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, and a transparent conductive layer disposed on the substrate 100. The transparent conductive layer 24 in the light-transmitting region may include: first to fourth connecting lines, a data line, and a power connecting line.

[0153] (9) Forming a fifth insulating layer. In some examples, a fifth insulating film is coated on the substrate 100 on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form the fifth insulating layer 105.

[0154] Figure 13 for Figure 4 A partial enlarged schematic diagram of a display substrate after the fifth insulating layer is formed. Figure 13 As shown, the fifth insulating layer 105 of a single display island region of the first display region may be provided with a plurality of via holes, for example, including: a 41st via hole V41 to a 43rd via hole V43. The fifth insulating layer 105 within the 41st via hole V41 to the 43rd via hole V43 may be removed to expose the surface of the transparent conductive layer 24.

[0155] (10) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate 100 having the aforementioned pattern formed thereon, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer 25. In some examples, the fourth conductive layer 25 may also be referred to as a second source / drain metal layer.

[0156] Figure 14A for Figure 4 A partially enlarged schematic diagram of the display substrate after the fourth conductive layer is formed. Figure 14B for Figure 14A In some examples, such as Figure 14A and Figure 14B As shown, the fourth conductive layer 25 of a single display island region of the first display region may include at least: a plurality of power connection electrodes 601 and a plurality of anode connection electrodes 602 .

[0157] In some examples, such as Figure 13 、 Figure 14A and Figure 14BAs shown, within a display island region, the power connection electrode 601 can be electrically connected to one end of a power connection line 512 through the 41st via hole V41, and can also be electrically connected to one end of another power connection line 512 through the 42nd via hole V42, thereby enabling transmission of a first voltage signal within the display island region. The anode connection electrode 602 can be electrically connected to the 15th connection electrode 415 through the 43rd via hole V43, thereby achieving electrical connection to the second region 360-2 of the sixth active layer 360 of the sixth transistor T6 of the first pixel circuit.

[0158] In some examples, after forming the fourth conductive layer 25, the light-transmitting area of ​​the first display area may include: a substrate 100, and a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a transparent conductive layer 24 and a fifth insulating layer 105 arranged on the substrate 100.

[0159] (11) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate 100 on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form the sixth insulating layer 106.

[0160] Figure 15 for Figure 4 A partial enlarged schematic diagram of a display substrate after the sixth insulating layer is formed in FIG. Figure 15 As shown, the sixth insulating layer 106 of a single display island in the first display region may be provided with a plurality of via holes, such as a fifty-first via hole V51. The sixth insulating layer 106 in the plurality of fifty-first via holes V51 may be removed to expose the surface of the fourth conductive layer 25.

[0161] In some examples, after forming the sixth insulating layer 106, the light-transmitting area of ​​the first display area may include: a substrate 100, and a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a transparent conductive layer 24, a fifth insulating layer 105 and a sixth insulating layer 106 sequentially arranged on the substrate 100.

[0162] (12) Forming an anode layer. In some examples, an anode film is deposited on the substrate 100 having the aforementioned pattern formed thereon, and the anode film is patterned by a patterning process to form an anode layer 301.

[0163] Figure 16A for Figure 4 A partially enlarged schematic diagram of a display substrate after the anode layer is formed. Figure 16B for Figure 14A Schematic diagram of the anode layer. In some examples, such as Figure 16A and Figure 16BAs shown, the anode layer 301 of a single display island area in the first display area may include at least: multiple anodes (for example, including: the first anode 1301 of the first light-emitting element 13a, the second anode 1303 of the first light-emitting element 13b, the third anode 1303 of the first light-emitting element 13c, and the fourth anode 1304 of the first light-emitting element 13d).

[0164] In some examples, such as Figure 15 and Figure 16A As shown, the first anode 1301 can be electrically connected to the anode connection electrode 602 electrically connected to the first pixel circuit 11a through a fifty-first via hole V51. The second anode 1302 can be electrically connected to the anode connection electrode 602 electrically connected to the first pixel circuit 11c through another fifty-first via hole V51. The third anode 1303 can be electrically connected to the anode connection electrode 602 electrically connected to the first pixel circuit 11b through another fifty-first via hole V51. The fourth anode 1304 can be electrically connected to the anode connection electrode 602 electrically connected to the first pixel circuit 11d through another fifty-first via hole V51.

[0165] (13) Forming a pixel definition layer. In some examples, a pixel definition film is coated on the substrate having the aforementioned pattern, and a pixel definition layer (PDL) is formed through masking, exposure, and development processes.

[0166] In some examples, such as Figure 4 As shown, the pixel definition layer 302 of a single display island area in the first display area may form a first pixel opening OP1, a second pixel opening OP2, a third pixel opening OP3, and a fourth pixel opening OP4. The first pixel opening OP1 may expose the surface of the first anode 1301, the second pixel opening OP2 may expose the surface of the second anode 1302, the third pixel opening OP3 may expose the surface of the third anode 1303, and the fourth pixel opening OP4 may expose the surface of the fourth anode 1304.

[0167] (14) Forming an organic light-emitting layer, a cathode layer, and an encapsulation layer. In some examples, organic light-emitting layers can be formed in the plurality of pixel openings formed above, and the organic light-emitting layers are connected to corresponding anodes. Subsequently, a cathode film is deposited and patterned through a patterning process to form a cathode layer. The cathode layer can be electrically connected to the organic light-emitting layer and the second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode layer. The encapsulation layer can include a laminated structure of inorganic material / organic material / inorganic material.

[0168] In some exemplary embodiments, the first to third conductive layers 21 to 23 and the fourth conductive layer 25 may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The transparent conductive layer 24 may be made of a transparent conductive material, such as indium tin oxide (ITO). The first to fourth insulating layers 101 to 104 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The fifth to sixth insulating layers 105 to 106 may be referred to as planar layers and may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer 302 may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0169] In some examples, such as Figure 1 As shown, the second display area A2 may include multiple second pixel circuits 12 and multiple second light-emitting elements 14. At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 14, and the at least one second pixel circuit 12 may be configured to drive the electrically connected at least one second light-emitting element 14 to emit light. For example, the multiple second pixel circuits 12 and the multiple second light-emitting elements 14 may be electrically connected in a one-to-one correspondence. The multiple second light-emitting elements 14 in the second display area A2 may include: a second light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a second light-emitting element emitting a third color light. The arrangement of the multiple second light-emitting elements may be similar to that of the multiple first light-emitting elements and will not be described in detail here. In some examples, the orthographic projection of the light-emitting area of ​​the second light-emitting element on the substrate may overlap with the orthographic projection of the electrically connected second pixel circuit on the substrate. In some examples, adjacent second pixel circuits in the second display area may not be electrically connected via traces of a transparent conductive layer, and a transparent conductive layer may not be provided in the second display area. The remaining film layer structure of the second display area may be similar to that of the first display area and will not be described in detail here.

[0170] The structure of the display substrate and its fabrication process in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or reduced as needed. For example, the fourth conductive layer may not be required. For another example, adjacent power connection lines along the second direction Y may be integrally formed, without the need for electrical connection via power connection electrodes. However, this embodiment is not limited to this.

[0171] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0172] In other examples, a display island region may be provided with two first pixel circuits and two first light-emitting elements. Multiple display island regions may be arranged in multiple rows and columns, and the display island regions in adjacent rows may be aligned in the second direction, and the display island regions in adjacent columns may be aligned in the first direction. The first pixel circuits of adjacent display island regions in the second direction may be electrically connected via a second signal trace, which may be a straight line segment. The first pixel circuits of adjacent display island regions in the first direction may be electrically connected via a first signal trace, which may be a straight line segment. However, this embodiment is not limited to this.

[0173] In some implementations, a single display island area in the first display area can be provided with a first light-emitting element and a first pixel circuit, and the first pixel circuit can be located below the first light-emitting element so that the light-transmitting area is as large as possible. However, when a single first pixel circuit is provided in the display island area, the spacing between the display island areas is small, and the winding space of the first signal line and the second signal line electrically connecting the adjacent first pixel circuits will be limited, resulting in the first signal line and the second signal line being longer and having a smaller line width and line spacing. Since the first signal line and the second signal line are made of transparent conductive material, taking ITO as an example of the transparent conductive material, the square resistance of ITO is relatively large, and the first pixel circuit is electrically connected to the second pixel circuit in the second display area through the first signal line and the second signal line, the load of the longer first signal line and the second signal line will affect the display of the second display area, resulting in poor display. Compared with the solution of setting a first light-emitting element and a first pixel circuit in a single display island area and covering the first pixel circuit with the first light-emitting element, the display substrate provided by this embodiment can increase the space between the display island areas by concentrating multiple first pixel circuits in the display island area, increase the arrangement freedom of the first signal line and the second signal line located in the transparent conductive layer, increase the wiring space of the first signal line and the second signal line, thereby increasing the line width of the first signal line and the second signal line to reduce the resistance of the first signal line and the second signal line, avoid poor display of the display substrate due to the load of the first signal line and the second signal line, and can support a higher refresh rate.

[0174] Furthermore, in a solution where a single display island region is provided with a first light-emitting element and a first pixel circuit, with the first light-emitting element covering the first pixel circuit, there are numerous raised display islands and recessed slits, which can easily exacerbate light diffraction effects in the first display region and degrade image quality. The display substrate provided in this embodiment, by centrally arranging multiple first pixel circuits in the display island region, can reduce the number of islands and slits, increase the size of the light-transmitting area between adjacent display island regions, effectively reduce light diffraction effects, and facilitate smoothing of the edges of the display island regions.

[0175] At least one embodiment of the present disclosure further provides a display device including the display substrate as described above.

[0176] In some examples, the display device may further include: a sensor located on a non-display surface side of the display substrate, and an orthographic projection of the sensor on the display substrate may overlap with the first display area of ​​the display substrate.

[0177] Figure 17 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 17 As shown, this embodiment provides a display device including: a display substrate 91 and a sensor 92 located on a light-emitting side of a light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0178] In some exemplary embodiments, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0179] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display substrate, characterized in that: include: a first display area; The first display area includes: a plurality of display island areas separated from each other, and a light-transmitting area located between adjacent display island areas; The display island region includes: four first pixel circuits and four first light-emitting elements provided on a substrate, the four first pixel circuits being electrically connected to the four first light-emitting elements in a one-to-one correspondence, and the first pixel circuits being configured to drive the first light-emitting elements to emit light; First pixel circuits in adjacent display islands in a first direction are electrically connected via a first signal line, and first pixel circuits in adjacent display islands in a second direction are electrically connected via a second signal line; the first direction intersects the second direction; and the first signal line and the second signal line are made of a transparent conductive material. The four first pixel circuits include a first first pixel circuit, a second first pixel circuit, a third first pixel circuit, and a fourth first pixel circuit arranged in sequence along the first direction; the second signal lines include: a data line and a power connection line for transmitting a first voltage signal; any of the power connection lines is located between adjacent data lines in the first direction; The data line and the power connection line electrically connected to the first first pixel circuit, and the data line and the power connection line electrically connected to the second first pixel circuit are at least partially parallel; the data line and the power connection line electrically connected to the third first pixel circuit, and the data line and the power connection line electrically connected to the fourth first pixel circuit are at least partially parallel; the data line and the power connection line electrically connected to the first first pixel circuit are roughly symmetrical with the data line and the power connection line electrically connected to the fourth first pixel circuit in the first direction. The data line and the power connection line electrically connected to the second first pixel circuit are roughly symmetrical with the data line and the power connection line electrically connected to the third first pixel circuit in the first direction.

2. The display substrate according to claim 1, wherein: At least a portion of the first signal wiring and the second signal wiring is located in the light-transmitting area.

3. The display substrate according to claim 2, wherein: The four first light-emitting elements include: one first light-emitting element emitting first color light, one first light-emitting element emitting second color light, and two first light-emitting elements emitting third color light.

4. The display substrate according to claim 3, wherein: The first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in the same row, the two first light-emitting elements emitting the third color light are arranged in the same row, and the first light-emitting element emitting the first color light, one first light-emitting element emitting the third color light, the first light-emitting element emitting the second color light and another first light-emitting element emitting the third color light are arranged in different columns.

5. The display substrate according to claim 3 or 4, characterized in that: The orthographic projections of the light emitting areas of the two first light emitting elements emitting light of the third color on the substrate do not overlap with the orthographic projections of the electrically connected first pixel circuits on the substrate; The orthographic projection of the light emitting region of the first light emitting element emitting the first color light on the substrate overlaps with the orthographic projection of the electrically connected first pixel circuit on the substrate; The orthographic projection of the light emitting region of the first light emitting element emitting the second color light on the substrate overlaps with the orthographic projection of the electrically connected first pixel circuit on the substrate.

6. The display substrate according to claim 4, wherein: The orthographic projection of the first light-emitting element emitting light of the third color on the substrate overlaps with the orthographic projection of the second signal trace on the substrate.

7. The display substrate according to claim 1, wherein: The multiple display island areas are arranged into multiple rows and columns, a row of display island areas includes multiple display island areas arranged along the first direction, and a column of display island areas includes multiple display island areas arranged along the second direction; two adjacent display island areas in at least one column of display island areas are arranged at least one row apart, and two adjacent display island areas in at least one row of display island areas are arranged at least one column apart.

8. The display substrate according to claim 7, wherein: The third first pixel circuit in the display island area of ​​the kth row and mth column is electrically connected to the first first pixel circuit in the k+1th row and m+1th column through the second signal routing, and the fourth first pixel circuit in the display island area of ​​the kth row and mth column is electrically connected to the second first pixel circuit in the k+1th row and m+1th column through the second signal routing; wherein k and m are integers.

9. The display substrate according to claim 1, wherein: The first signal wiring and the second signal wiring are located on a side of the first pixel circuit away from the substrate, and are located on a side of the first light-emitting element close to the substrate.

10. The display substrate according to claim 1, wherein The first signal wiring and the second signal wiring are in the same layer structure.

11. The display substrate according to claim 1, wherein The first signal line is a straight line segment extending along the first direction, and the second signal line is a broken line segment extending along the second direction.

12. The display substrate according to claim 1, wherein The first signal lines include: a first initial connection line for transmitting a first initial signal, a first scan connection line for transmitting a scan signal, a second scan connection line for transmitting a first reset control signal, and a light-emitting control line for transmitting a light-emitting control signal.

13. The display substrate according to claim 1, wherein The display substrate also includes: a second display area located on at least one side of the first display area; the second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements arranged on the substrate, at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light.

14. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 13.

15. The display device according to claim 14, wherein: The display device further includes a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate overlaps with the first display area of ​​the display substrate.

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