SOI lateral device and manufacturing method

Abstract

The present invention relates to a SOI lateral device structure and manufacturing method, comprising a substrate, a buried oxide layer, a drift region, and an active region. The substrate, the insulating layer, and the drift region on the insulating layer include a vertical conductive structure, and the cross-section of the vertical conductive structure passing through the insulating layer and the silicon on the insulating layer in the vertical direction is in the shape of an elongated strip; the vertical conductive structure also includes a low-dielectric constant dielectric and polycrystalline in the groove wall; and the active region also includes a source region and a drain region. The present invention has a dielectric withstand voltage at the coupling electrode and the buried oxide that increases more as the dielectric constant decreases and the electric field increases, and the breakdown voltage is greater without affecting the specific conductivity. A process method for deep buried layer etching is also provided, which can introduce previously unattainable devices from model establishment into engineering applications through this process.

Description

Technical Field

[0001] The present invention relates to semiconductor process manufacturing, in particular to an SOI lateral device and a deep trench process solution. Background Art

[0002] SOI (Silicon On Insulator) high-voltage integrated circuits are widely used due to their advantages, including high speed, low power consumption, radiation resistance, and ease of isolation. However, as the core component of SOI high-voltage integrated circuits, the low vertical breakdown voltage of SOI lateral devices limits their application in high-voltage power integrated circuits. Numerous researchers, both domestically and internationally, have proposed a series of novel structures to improve the vertical breakdown voltage of SOI lateral devices. However, many devices that enhance the electric field in the insulating layer remain theoretical and technologically unattainable. Summary of the Invention

[0003] Based on this, it is necessary to provide a SOI lateral device with high breakdown voltage and a manufacturing method thereof.

[0004] In order to achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0005] A SOI lateral device, comprising:

[0006] substrate 101;

[0007] A buried oxide layer 102 is provided on the substrate 101;

[0008] A drift region 105 is provided on the buried oxide layer 102;

[0009] The first conductive type well region 111 is located on the right side of the drift region 105.

[0010] The second conductive type well region 110 is located on the left side of the drift region 105.

[0011] A vertical conductive structure 104 is located between the first conductivity type well region 111 and the second conductivity type well region 110 , and extends downward from the drift region 105 to the buried oxide layer 102 ;

[0012] A first low-k dielectric 103 , having a lower dielectric constant than silicon dioxide, is disposed in the buried oxide layer 102 and surrounds the bottom of the vertical conductive structure 104 ;

[0013] a second low-k dielectric 118 disposed on a side of the vertical conductive structure 104 , between the vertical conductive structure 104 and the drift region 105 , and above the first low-k dielectric 103 ;

[0014] All vertical conductive structures 104 are located between the first conductivity type well region 111 and the second conductivity type well region 110 .

[0015] The source region 113 is located in the second conductivity type well region 110;

[0016] The drain region 114 is located in the first conductive type well region 111.

[0017] A field oxide layer 115 is located above the drift region 105;

[0018] a gate 116 disposed above the region between the source region 113 and the drain region 114;

[0019] The vertical conductive structure 104 is located between the gate 116 and the drain region 114 , and the source region 113 , the drain region 114 and the drift region 105 have the first conductivity type;

[0020] a substrate lead-out region 112 having the second conductivity type, located in the second conductivity type well region 110 and disposed on a side of the source region 113 away from the gate 116 ;

[0021] The gate 116 extends from the edge of the source region 113 to the field oxide layer 115 .

[0022] As a preferred embodiment, the drift region 105 is provided with at least one column of the vertical conductive structures 104, each column includes at least two vertical conductive structures, the vertical conductive structures of adjacent columns are staggered, and the column direction and the length direction of the conductive channel are at an angle greater than 0 degrees in the horizontal plane, and the portion of the bottom of each column that is deeply buried in the oxide is spherical or elliptical; the SOI lateral device also includes at least one conductive equipotential bar 117 on the field oxide layer 115, each conductive equipotential bar 117 is electrically connected to a column of vertical conductive structures; each of the conductive equipotential bars extends along the width direction of the conductive channel.

[0023] As a preferred embodiment, the material of the vertical conductive structure includes polysilicon;

[0024] And / or the material of the first low-k dielectric 103 includes silicon oxyfluoride;

[0025] And / or the bottom of the first low-k dielectric 103 is in direct contact with the substrate 101 .

[0026] In the above-mentioned SOI lateral device, the vertical conductive structure-low-K dielectric-drift region forms a capacitor effect similar to that of conductive material-dielectric material-semiconductor, which can not only assist in the depletion of the drift region, but also make the equipotential lines at the bottom of the drift region pressed into the structure below the vertical conductive structure. Since the bottom and side low-K dielectrics are in the area with dense equipotential lines, when the lateral device is in the reverse cutoff region, the electric field in the dielectric can be greatly enhanced, thereby increasing the breakdown voltage.

[0027] Preferably, the material of each of the conductive equipotential strips includes metal or alloy.

[0028] Preferably, the dielectric layer is made of low-K dielectric.

[0029] Preferably, the top of the low-K dielectric is flush with the top of the buried oxide layer.

[0030] Preferably, the first conductivity type is N-type, and the second conductivity type is P-type.

[0031] To achieve the above object, the present invention further provides a method for manufacturing the SOI lateral device, comprising the following steps:

[0032] providing a substrate having an insulating layer and a silicon layer formed thereon;

[0033] depositing a first oxide layer on the substrate;

[0034] depositing a silicon nitride layer on the substrate;

[0035] depositing a second oxide layer on the substrate;

[0036] Photolithographically defining a deep groove area on the silicon layer using a deep groove photomask;

[0037] Etching to the silicon surface using a first etching method;

[0038] etching the deep trench to the insulating layer using a second etching method;

[0039] Using a third etching method to etch a small portion of the insulating layer;

[0040] further etching the insulating layer using a fourth etching method;

[0041] depositing insulating materials;

[0042] Stripping off the silicon nitride layer;

[0043] Filling polysilicon;

[0044] forming an N / P well;

[0045] forming a gate;

[0046] Forming drain-source-gate leads;

[0047] Depositing interlayer dielectric;

[0048] Forming holes and metal.

[0049] As a preferred embodiment, the thickness of the first oxide layer is 0.15-0.4 microns and is grown by furnace tube oxidation;

[0050] and / or the thickness of the silicon nitride is 1-2.5 microns and is deposited using low pressure chemical vapor deposition;

[0051] And / or the thickness of the second oxide layer is 3-5 microns, and is deposited by plasma-assisted chemical vapor deposition.

[0052] As a preferred embodiment, the first etching method is fluorine-based gas plasma etching with strong anisotropy and a slightly large selectivity ratio of the oxide layer and silicon nitride to silicon;

[0053] The second etching method is a plasma etching method with strong anisotropy and relatively large selectivity between silicon and oxide layers;

[0054] The third etching method is plasma etching with a large selectivity ratio between the oxide layer and silicon and strong anisotropy;

[0055] The fourth etching method is a wet etching method with a large selectivity ratio between the oxide layer and silicon and strong isotropy;

[0056] As a preferred embodiment, the deposited insulating material includes a low dielectric constant material and is deposited by low-pressure vapor deposition.

[0057] As a preferred method, dry etching is used to strip off the silicon nitride layer.

[0058] As a preferred method, in-situ doping is used to fill the polysilicon.

[0059] As a preferred embodiment, in the deposited interlayer dielectric:

[0060] The first layer of tetraethyl orthosilicate (TEOS) is deposited using low-pressure chemical vapor deposition;

[0061] Silicon nitride is deposited using atmospheric pressure chemical vapor deposition;

[0062] The second tetraethyl orthosilicate (TEOS) is deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0063] In one embodiment, the bottom and sidewalls of the deep trench are partially filled with an insulating low-K dielectric;

[0064] In one embodiment, the deep trench is filled with polycrystalline;

[0065] In one embodiment, the insulating layer is a buried oxide layer.

[0066] The present invention has the following beneficial effects: the dielectric withstand voltage at the coupling electrode and buried oxide increases significantly as the dielectric constant decreases, resulting in a higher breakdown voltage without affecting the specific conductance. It also provides a process for deep buried layer etching, enabling previously unattainable devices to be introduced into engineering applications from model building. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of the preferred embodiments of the present invention shown in the accompanying drawings. The same reference numerals indicate the same parts throughout the accompanying drawings, and the drawings are not intentionally drawn to scale with actual size, but rather to illustrate the subject matter of the present invention.

[0068] Figure 1 This is a three-dimensional diagram of the SOI lateral device structure of Example 1;

[0069] Figure 2 It is a front view of the SOI lateral device structure of Example 1;

[0070] Figure 3 Schematic diagram of the silicon and silicon-on-insulator substrate of Example 3;

[0071] Figure 4 Schematic diagram of the first oxide layer in Example 3;

[0072] Figure 5 Schematic diagram of the silicon nitride layer in Example 3;

[0073] Figure 6 Schematic diagram of the second oxide layer in Example 3;

[0074] Figure 7 Schematic diagram of the photoresist in Example 3;

[0075] Figure 8 Schematic diagram of photolithography in Example 3;

[0076] Figure 9 This is a schematic diagram after using the first etching method in Example 3;

[0077] Figure 10 Schematic diagram of adhesive removal in Example 3;

[0078] Figure 11 This is a schematic diagram of the second etching method used in Example 3;

[0079] Figure 12 Schematic diagram of the third etching method and the fourth etching method in Example 3;

[0080] Figure 13 Schematic diagram of filling with low dielectric constant medium in Example 3;

[0081] Figure 14 Schematic diagram of denitriding the silicon layer in Example 3;

[0082] Figure 15 Schematic diagram of polysilicon in Example 3;

[0083] Figure 16 This is a schematic diagram after removing the first oxide layer in Example 3;

[0084] Figure 17 Schematic diagram of forming source, drain, gate and metal in Example 3.

[0085] 101 is a substrate, 102 is a buried oxide layer, 103 is a first low dielectric constant medium, 104 is a vertical conductive structure, 105 is a drift region, 106 is a first oxide layer, 107 is a silicon nitride layer, 108 is a second oxide layer, 109 is a photoresist, 110 is a second conductive type well region, 111 is a first conductive type well region, 112 is a substrate lead-out region, 113 is a source region, 114 is a drain region, 115 is a field oxide layer, 116 is a gate, 117 is a conductive equipotential strip, and 118 is a second low dielectric constant medium. DETAILED DESCRIPTION

[0086] The following is a detailed description of a method for manufacturing a buried layer electric field enhancement structure proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0087] Example 1

[0088] Figure 1 is a perspective view of a lateral silicon-on-insulator device in one embodiment. Figure 2 for Figure 1 The cross-sectional view of the silicon-on-insulator lateral device is shown in FIG. Figure 1 and Figure 2 In the embodiment shown, the silicon-on-insulator lateral device is a SOILDMOSFET (silicon-on-insulator laterally diffused metal-oxide-semiconductor field-effect transistor), comprising:

[0089] Substrate 101: The substrate 101 is a P-type silicon substrate.

[0090] A buried oxide layer 102 is provided on the substrate 101;

[0091] A drift region 105 is provided on the buried oxide layer 102;

[0092] The first conductive type well region 111 is located on the right side of the drift region 105.

[0093] The second conductive type well region 110 is located on the left side of the drift region 105.

[0094] A vertical conductive structure 104 is located between the first conductivity type well region 111 and the second conductivity type well region 110 , and extends downward from the drift region 105 to the buried oxide layer 102 ;

[0095] A first low-k dielectric 103 , having a lower dielectric constant than silicon dioxide, is disposed in the buried oxide layer 102 and surrounds the bottom of the vertical conductive structure 104 ;

[0096] A deep trench is defined between the drift region 105 and the buried oxide layer 102. The bottom of the deep trench is filled with a first low-k dielectric 103, which replaces the buried oxide layer material. The sidewalls of the deep trench above the first low-k dielectric 103 are also filled with the first low-k dielectric 103. The remaining space in the deep trench, excluding the first low-k dielectric 103, is filled with conductive material, forming a vertical conductive structure 104 extending from the drift region 105 downward to the buried oxide layer 102. The first low-k dielectric 103 surrounds the bottom of the vertical conductive structure 104.

[0097] In the above-mentioned silicon-on-insulator lateral device, the vertical conductive structure 104-first low-k dielectric 103-drift region 105 forms a capacitor effect similar to that of a conductive material-dielectric material-semiconductor, which can not only assist in the depletion of the drift region 105, but also make the equipotential lines at the bottom of the drift region 105 pressed into the structure below the vertical conductive structure 104. Since the first low-k dielectric 103 that replaces the buried oxide layer material is located at the densest equipotential line, when the lateral device is in the reverse cutoff region, the electric field strength in the dielectric can be greatly enhanced, thereby increasing the breakdown voltage. It is understandable that the dielectric constant K of the first low-k dielectric 103 is at least less than the dielectric constant K of silicon dioxide (i.e., the material of the buried oxide layer 102). In one embodiment of the present application, the dielectric constant K of the first low-k dielectric 103 is less than 3.9.

[0098] a second low-k dielectric 118 disposed on a side of the vertical conductive structure 104 , between the vertical conductive structure 104 and the drift region 105 , and above the first low-k dielectric 103 ;

[0099] The drift region 105 has a first conductivity type, and the gate 116 is located above the region between the source region 113 and the drain region 114 and is located on the gate dielectric layer. The vertical conductive structure 104 is located between the gate 116 and the drain region 114. Each SOIL DMOS can be provided with multiple deep trenches having vertical conductive structures 104 and a first low-k dielectric 103. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0100] All vertical conductive structures 104 are located between the first conductivity type well region 111 and the second conductivity type well region 110 .

[0101] The source region 113 is located in the second conductivity type well region 110;

[0102] The second-conductivity-type well region 110 forms the inversion layer channel, directly affecting the gate threshold voltage and also influencing the drift region depletion. The first-conductivity-type well region 111 serves as the drain-end drift region buffer layer of the silicon-on-insulator lateral device, increasing the device's on-state breakdown voltage during forward operation.

[0103] The drain region 114 is located in the first conductive type well region 111.

[0104] In one embodiment of the present application, the source region 113 and the drain region 114 are N+ regions, and the drift region 105 is an N- region.

[0105] A field oxide layer 115 is located above the drift region 105;

[0106] a gate 116 disposed above the region between the source region 113 and the drain region 114;

[0107] The vertical conductive structure 104 is located between the gate 116 and the drain region 114 , and the source region 113 , the drain region 114 and the drift region 105 have the first conductivity type;

[0108] a substrate lead-out region 112 having the second conductivity type, located in the second conductivity type well region 110 and disposed on a side of the source region 113 away from the gate 116 ;

[0109] The gate 116 extends from the edge of the source region 113 to the field oxide layer 115 .

[0110] The drift region 105 is provided with at least one row of vertical conductive structures 104, each row including at least two vertical conductive structures. The vertical conductive structures of adjacent rows are staggered, and the row direction forms an angle greater than 0 degrees with the length direction of the conductive channel in the horizontal plane. The portion of the bottom of each row that penetrates into the buried oxide is spherical or elliptical. The SOI lateral device also includes at least one conductive equipotential strip 117 on the field oxide layer 115, each conductive equipotential strip 117 electrically connected to a row of vertical conductive structures; each conductive equipotential strip extends along the width direction of the conductive channel. Figure 1 In this embodiment, a plurality of vertical conductive structures 104 are arranged in the drift region 105 to form an array structure. It is understandable that in order to leave enough carrier movement paths for the drift region 105, the vertical conductive structures 104 cannot be connected together, but must be arranged in an array. Figure 1 and Figure 2 In the embodiment shown, the conductive equipotential structure is a plurality of conductive equipotential strips 117 provided on the field oxide layer 115. Each conductive equipotential strip 117 extends along the width direction of the conductive channel, and each conductive equipotential strip 117 passes through the field oxide layer 115 downwardly through the conductive material to electrically connect to at least two vertical conductive structures 104 below.

[0111] The material of the vertical conductive structure includes polysilicon;

[0112] And / or the material of the first low-k dielectric 103 includes silicon oxyfluoride;

[0113] And / or the bottom of the first low-k dielectric 103 is in direct contact with the substrate 101 .

[0114] Example 2

[0115] This embodiment provides a method for manufacturing the SOI lateral device, comprising the following steps:

[0116] providing a substrate having an insulating layer and a silicon layer formed thereon;

[0117] depositing a first oxide layer on the substrate;

[0118] depositing a silicon nitride layer on the substrate;

[0119] depositing a second oxide layer on the substrate;

[0120] Photolithographically defining a deep groove area on the silicon layer using a deep groove photomask;

[0121] Etching to the silicon surface using a first etching method;

[0122] etching the deep trench to the insulating layer using a second etching method;

[0123] Using a third etching method to etch a small portion of the insulating layer;

[0124] further etching the insulating layer using a fourth etching method;

[0125] depositing insulating materials;

[0126] Stripping off the silicon nitride layer;

[0127] Filling polysilicon;

[0128] forming an N / P well;

[0129] forming a gate;

[0130] Forming drain-source-gate leads;

[0131] Depositing interlayer dielectric;

[0132] Forming holes and metal.

[0133] As a preferred embodiment, the thickness of the first oxide layer is 0.15-0.4 microns and is grown by furnace tube oxidation;

[0134] and / or the thickness of the silicon nitride is 1-2.5 microns and is deposited using low pressure chemical vapor deposition;

[0135] And / or the thickness of the second oxide layer is 3-5 microns, and is deposited by plasma-assisted chemical vapor deposition.

[0136] Specifically, the first etching method is fluorine-based gas plasma etching with strong anisotropy and a slightly large selectivity ratio of the oxide layer and silicon nitride to silicon;

[0137] The second etching method is a plasma etching method with strong anisotropy and relatively large selectivity between silicon and oxide layers;

[0138] The third etching method is plasma etching with a large selectivity ratio between the oxide layer and silicon and strong anisotropy;

[0139] The fourth etching method is a wet etching method with a large selectivity ratio between the oxide layer and silicon and strong isotropy;

[0140] As a preferred embodiment, the deposited insulating material includes a low dielectric constant material and is deposited by low-pressure vapor deposition.

[0141] As a preferred method, dry etching is used to strip off the silicon nitride layer.

[0142] As a preferred method, in-situ doping is used to fill the polysilicon.

[0143] As a preferred embodiment, in the deposited interlayer dielectric:

[0144] The first layer of tetraethyl orthosilicate (TEOS) is deposited using low-pressure chemical vapor deposition;

[0145] Silicon nitride is deposited using atmospheric pressure chemical vapor deposition;

[0146] The second tetraethyl orthosilicate (TEOS) is deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0147] The bottom and sidewalls of the deep trench are partially filled with an insulating low-K dielectric;

[0148] The deep groove is filled with polycrystalline;

[0149] The insulating layer is a buried oxide layer.

[0150] Example 3

[0151] This embodiment provides a method for manufacturing the SOI lateral device, comprising the following steps: providing a substrate having a substrate 101, a buried oxide layer 102, and a drift region 105 on the buried oxide layer, such as Figure 3 As shown;

[0152] A first oxide layer 106 is grown on the substrate with a thickness of 0.15-0.4 μm. Figure 4 As shown, due to the requirements for oxide layer quality and improvement of silicon surface defect stress, direct furnace tube oxidation growth is adopted in this step;

[0153] A silicon nitride layer 107 is deposited on the substrate using low pressure chemical vapor deposition with a thickness of 1-2.5 microns. Figure 5 As shown, in this step, low-pressure chemical vapor deposition is used for consideration of silicon nitride shaping and uniformity;

[0154] A second oxide layer 108 is deposited on the substrate using plasma-assisted chemical vapor deposition with a thickness of 3-5 microns. Figure 6 As shown, for this step, atmospheric pressure, low pressure and plasma-assisted chemical vapor deposition can be used for quality requirements;

[0155] For coating, a photoresist 109 with a high resolution and a thickness of about 1 micron is selected. Figure 7 As shown;

[0156] A second conductive type well region 110 is defined on the silicon layer by photolithography using a deep groove photomask, and then developed and inspected. Figure 8 As shown;

[0157] The second conductive type well region 110 is etched to the silicon surface using a first etching method, such as Figure 9 As shown, the selectivity of the oxide layer and silicon nitride to silicon does not need to be too strict, but uniformity and anisotropy must be guaranteed. Fluorine-based gas dry plasma etching is used. By adjusting the oxygen content, a certain selectivity of the oxide layer to silicon can be achieved, and the anisotropy can be controlled by adjusting the number of fluorine atoms and ion energy.

[0158] Degumming, cleaning, such as Figure 10 As shown;

[0159] The second conductive type well region 110 is etched to the buried oxide layer 102 using a second etching method, such as Figure 11 As shown, the selectivity of silicon to oxide layer in this step does not need to be too strict, but uniformity and anisotropy must be ensured. Chlorine or bromine dry plasma etching is used. By adjusting the oxygen or hydrogen content, a certain selectivity of silicon to oxide layer can be met. Chlorine or bromine can ensure anisotropy.

[0160] The third etching method is used to etch the second conductive type well region 110 to a portion of the buried oxide layer 102. The selectivity of the oxide layer to silicon nitride does not need to be too strict, but it must ensure a very high selectivity to silicon, with good uniformity and anisotropy. Fluorine-based gas dry plasma etching is used. By adjusting the hydrogen content, when the hydrogen concentration is greater than 40%, the silicon etching rate is almost 0. Adjusting the oxygen / nitrogen ratio can have a certain selectivity for silicon nitride, and adjusting the number of fluorine atoms and ion energy to control the anisotropy; the fourth etching method is used to continue etching the second conductive type well region 110 to a portion of the buried oxide layer 102, as shown in FIG. Figure 12 As shown, the selectivity of the oxide layer to silicon nitride does not need to be too harsh, but it must ensure a very high selectivity to silicon, good uniformity and isotropy, and adopt a dry isotropic menu mainly using fluorine-based gases;

[0161] Deposit a first low-k dielectric 103, such as Figure 13 As shown, low pressure chemical vapor deposition is used;

[0162] Peel off the silicon nitride layer, e.g. Figure 14 As shown, plasma dry etching using hot phosphoric acid or fluorine-based gas plus oxygen / nitrogen is used;

[0163] Deposit vertical conductive structure 104, such as Figure 15 As shown, in-situ doping is used, followed by chemical mechanical polishing and etching back;

[0164] Remove the oxide layer, such as Figure 16 As shown, dilute hydrofluoric acid buffered with ammonium fluoride was used;

[0165] forming an N / P well;

[0166] forming a gate;

[0167] Forming drain-source-gate leads;

[0168] Depositing interlayer dielectric;

[0169] Forming holes and metal, such as Figure 17 shown.

Claims

1. A SOI lateral device, characterized in that include: a substrate (101); A buried oxide layer (102) is provided on the substrate (101); A drift region (105) is provided on the buried oxide layer (102); The first conductive type well region (111) is located on the right side of the drift region (105). The second conductive type well region (110) is located on the left side inside the drift region (105). A vertical conductive structure (104) is located between the first conductive type well region (111) and the second conductive type well region (110), and extends downward from the drift region (105) to the buried oxide layer (102); A first low-k dielectric (103) having a lower dielectric constant than silicon dioxide, disposed in the buried oxide layer (102) and surrounding the bottom of the vertical conductive structure (104); A second low-dielectric-constant medium (118) is provided on a side of the vertical conductive structure (104), between the vertical conductive structure (104) and the drift region (105), and above the first low-dielectric-constant medium (103); All vertical conductive structures (104) are located between the first conductive type well region (111) and the second conductive type well region (110); A source region (113) located in the second conductivity type well region (110); The drain region (114) is located in the first conductive type well region (111), A field oxide layer (115) is located above the drift region (105); a gate (116) disposed above the region between the source region (113) and the drain region (114); The vertical conductive structure (104) is located between the gate (116) and the drain region (114), and the source region (113), the drain region (114) and the drift region (105) have a first conductivity type; A substrate lead-out region (112) having a second conductivity type, located in the second conductivity type well region (110), and disposed on a side of the source region (113) away from the gate (116); The gate (116) extends from the edge of the source region (113) to the field oxide layer (115); The drift region (105) is provided with at least one column of the vertical conductive structures (104), each column includes at least two vertical conductive structures, the vertical conductive structures of adjacent columns are staggered, and the column direction and the length direction of the conductive channel form an angle greater than 0 degrees on the horizontal plane, and the portion of the bottom of each column that penetrates into the buried oxide is spherical or elliptical; the SOI lateral device also includes at least one conductive equipotential strip (117) on the field oxide layer (115), each conductive equipotential strip (117) is electrically connected to a column of vertical conductive structures; each conductive equipotential strip extends along the width direction of the conductive channel.

2. The SOI lateral device according to claim 1, wherein: The material of the vertical conductive structure includes polysilicon; And / or the material of the first low dielectric constant medium (103) includes silicon oxyfluoride; And / or the bottom of the first low-k dielectric (103) is in direct contact with the substrate (101).

3. A method for manufacturing a lateral SOI device according to any one of claims 1 to 2, characterized in that The following steps are involved: providing a substrate having an insulating layer and a silicon layer formed thereon; depositing a first oxide layer on the substrate; depositing a silicon nitride layer on the substrate; depositing a second oxide layer on the substrate; Photolithographically defining a deep groove area on the silicon layer using a deep groove photomask; Etching to the silicon surface using a first etching method; etching the deep trench to the insulating layer using a second etching method; Using a third etching method to etch a small portion of the insulating layer; further etching the insulating layer using a fourth etching method; depositing insulating materials; Stripping off the silicon nitride layer; Filling polysilicon; forming an N / P well; forming a gate; Forming drain-source-gate leads; Depositing interlayer dielectric; Forming holes and metal.

4. The method for manufacturing a lateral SOI device according to claim 3, wherein: The thickness of the first oxide layer (106) is 0.15-0.4 microns and is grown by furnace oxidation; and / or the thickness of the silicon nitride is 1-2.5 microns and is deposited using low pressure chemical vapor deposition; And / or the thickness of the second oxide layer is 3-5 microns, and is deposited by plasma-assisted chemical vapor deposition.

5. The method for manufacturing a lateral SOI device according to claim 3, wherein: The first etching method is fluorine-based gas plasma etching; The second etching method is chlorine or bromine plasma etching; The third etching method is plasma etching; The fourth etching method is wet etching.

6. The method for manufacturing a lateral SOI device according to claim 3, wherein: The deposited insulating material includes a low dielectric constant material and is deposited by low pressure vapor deposition.

7. The method for manufacturing a lateral SOI device according to claim 3, wherein: The silicon nitride layer is stripped off by dry etching.

8. The method for manufacturing a lateral SOI device according to claim 3, wherein: The polysilicon is filled by in-situ doping.

9. The method for manufacturing a lateral SOI device according to claim 3, wherein: In the deposited interlayer dielectric: The first layer of tetraethyl orthosilicate (TEOS) is deposited using low-pressure chemical vapor deposition; Silicon nitride is deposited using atmospheric pressure chemical vapor deposition; The second tetraethyl orthosilicate (TEOS) is deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

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