Semiconductor device

Abstract

A semiconductor device capable of appropriately discharging a surge charge in a protection circuit that protects a protected circuit is provided. According to one embodiment, a protection circuit in a semiconductor device includes a first transistor and a second transistor having a gate electrically connected to a first node between a first wiring and a second wiring, connected in series between the first and second wirings; a third transistor and a fourth transistor having a gate electrically connected to a second node between the first and second transistors, connected in series between the first and second wirings; and a fifth transistor having a gate electrically connected to a third node between the third and fourth transistors, provided between the second node and the second wiring. The protection circuit further includes a calculation circuit that calculates a first signal received from the second node and outputs a second signal; and a sixth transistor that receives the second signal and outputs a control signal to the calculation circuit.

Description

[0001] Related Applications

[0002] This application has priority based on Japanese Patent Application No. 2021-35519 (Filing date: March 5, 2021). This application includes the entire contents of the base application by reference to the base application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] In a semiconductor device provided with an ESD (electrostatic discharge) protection circuit that protects a protected circuit from static electricity, it is desirable to properly discharge surge charges within the ESD protection circuit. SUMMARY

[0005] The present application provides a semiconductor device that can properly discharge surge charges within a protection circuit that protects a protected circuit.

[0006] According to one embodiment, a semiconductor device includes a protection circuit electrically connected to a first wiring supplied with a first voltage and a second wiring supplied with a second voltage, and a protected circuit electrically connected to the first wiring and the second wiring downstream of the protection circuit and protected by the protection circuit. The protection circuit includes first and second transistors having gates electrically connected to a first node between the first wiring and the second wiring and connected in series between the first wiring and the second wiring, third and fourth transistors having gates electrically connected to a second node between the first and second transistors and connected in series between the first wiring and the second wiring, and a fifth transistor having a gate electrically connected to a third node between the third and fourth transistors and disposed between the second node and the second wiring. The protection circuit further includes an operation circuit that receives a first signal from the second node or from a fourth node disposed between the first wiring and the second wiring downstream of the second node and outputs a second signal obtained by an operation using the first signal, and a sixth transistor electrically connected to a fifth node disposed between the first wiring and the second wiring downstream of the second node, receives the second signal from the operation circuit, and outputs a control signal to the operation circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a circuit diagram showing the configuration of an ESD protection circuit of the first embodiment.

[0008] Figure 2 Fig. 1 is a circuit diagram showing the configuration of an ESD protection circuit according to a first embodiment.

[0009] Figure 3 Figs. 2(a) to 2(f) are timing charts showing operation examples of the ESD protection circuit according to the above comparative example.

[0010] Figure 4 Fig. 3 is a circuit diagram showing the configuration of a semiconductor device according to the first embodiment.

[0011] Figure 5 Figs. 4(a) and 4(b) are graphs for explaining the operation of the ESD protection circuit according to the above comparative example.

[0012] Figure 6 Figs. 5(a) and 5(b) are graphs for explaining the operation of the ESD protection circuit according to the first embodiment.

[0013] Figure 7 Figs. 6(a) and 6(b) are another graphs for explaining the operation of the ESD protection circuit according to the first embodiment.

[0014] Figure 8 Fig. 7 is a circuit diagram showing the configuration of an ESD protection circuit according to a second embodiment.

[0015] Figure 9 Fig. 8 is a circuit diagram showing the configuration of an ESD protection circuit according to a third embodiment.

[0016] Figure 10 Fig. 9 is a circuit diagram showing the configuration of an ESD protection circuit according to a fourth embodiment. DETAILED DESCRIPTION

[0017] Embodiments of the present application will be explained below with reference to the drawings. In the following embodiments, Figures 1-10 In the following embodiments, the same components are denoted by the same reference numerals, and repeated explanation is omitted.

[0018] (First Embodiment)

[0019] Figure 1 Fig. 1 is a circuit diagram showing the configuration of an ESD protection circuit 1 according to a first embodiment.

[0020] The ESD protection circuit 1 according to the present embodiment is provided in a semiconductor device, and is capable of protecting a protected circuit in the semiconductor device from static electricity. The semiconductor device has, for example, a three-dimensional memory as the protected circuit. The ESD protection circuit 1 according to the present embodiment is an RCTMOS circuit.

[0021] The semiconductor device has pads P1, P2 and wirings L1, L2 to which power supply voltages are supplied. The pad P1 is an external connection pad to which a VCCQ voltage is supplied. The pad P2 is an external connection pad to which a VSS voltage is supplied. The wiring L1 is a power supply wiring to which the VCCQ voltage is supplied from the pad P1. The wiring L2 is a power supply wiring to which the VSS voltage is supplied from the pad P2. The ESD protection circuit 1 of the present embodiment is electrically connected to the wirings L1, L2, and the protected circuit of the present embodiment is electrically connected to the wirings L1, L2 downstream of the ESD protection circuit 1. Specific examples of the constitution of the protected circuit will be described later. The VCCQ voltage is an example of the first voltage, and the VSS voltage is an example of the second voltage. The wiring L1 is an example of the first wiring, and the wiring L2 is an example of the second wiring.

[0022] In addition, a VCC voltage can be supplied to the pad P1 instead of the VCCQ voltage. In this case, the VCC voltage is supplied from the pad P1 to the wiring L1. The VCCQ voltage appearing in the following description can be replaced with the VCC voltage.

[0023] The ESD protection circuit 1 of the present embodiment includes the transistors Tr11, Tr21 constituting the inverter 11, the transistors Tr12, Tr22 constituting the inverter 12, the transistors Tr13, Tr23 constituting the inverter 13, the transistors Tr14, Tr24 constituting the inverter 14, the transistors Tr15, Tr25 constituting the inverter 15, the transistors Tr16, Tr26 constituting the inverter 16, and the transistors Tr17, Tr18, Tr27, Tr28 adjacent to the inverter 11. The transistors Tr13, Tr23, Tr14, Tr24, Tr15, Tr25, Tr16, Tr26 are examples of the first, second, third, fourth, seventh, eighth, ninth, and tenth transistors, respectively.

[0024] The ESD protection circuit 1 of the present embodiment further includes the other transistors Tr1, Tr2, Tr3, the resistors R1, R2, R3, R4, R5, R6, the capacitors C1, C2, C3, and the NOR circuit (NOR gate) 21. The transistors Tr1, Tr2, and Tr3 are examples of the fifth, sixth, and eleventh transistors, respectively. The NOR circuit 21 is an example of the operation circuit.

[0025] Figure 1The nodes VRC, V1, V2, V3', V3, V4', V4, V5', V5, V6', V6, and GIN in the ESD protection circuit 1 are also shown. The node V3' is an example of the first node, the nodes V3, V4', V5' are examples of the second node, and the node V4 is an example of the third node. The nodes V5, V6' are examples of the fourth node, the nodes V6, GIN are examples of the fifth node, and the node VRC is an example of the sixth node. In addition, the symbols representing the nodes are also used as symbols representing voltages on the nodes. For example, the voltage on the node V1 is also written as the voltage V1.

[0026] The resistor R1 and the capacitor C1 are connected in series between the wiring L1 and the wiring L2. The resistor R1 is disposed between the wiring L1 and the node VRC. The capacitor C1 is disposed between the node VRC and the wiring L2. The resistor R1 and the capacitor C1 function as a trigger circuit that acts in accordance with a time constant determined by the resistance value of the resistor R1 and the capacitance value of the capacitor C1. The voltage VRC follows the variation in the VCCQ voltage of the pad P1 with a time delay based on the time constant. This trigger circuit is also called an RC timer.

[0027] The gate of the transistor Tr11 and the gate of the transistor Tr21 are electrically connected to the node VRC. The transistors Tr11 and Tr21 are connected in series between the wiring L1 and the wiring L2. The transistor Tr11 is electrically connected to the wiring L1 via the transistors Tr17, Tr18 and is electrically connected to the node V1. The transistor Tr21 is electrically connected to the node V1 and is electrically connected to the wiring L2 via the transistors Tr27, Tr28. The gate of the transistor Tr17 and the gate of the transistor Tr27 are electrically connected to the node VRC. The gate of the transistor Tr18 and the gate of the transistor Tr28 are electrically connected to the node V2. In this embodiment, the transistors Tr11, Tr17, Tr18 are p-type MOSFETs, and the transistors Tr21, Tr27, Tr28 are n-type MOSFETs. The transistors Tr11, Tr21 output the voltage V1 having a logic level that is inverted from the logic level of the voltage VRC. The transistors Tr17, Tr18, Tr27, and Tr28 have a function of lagging the voltage V1 so that the ESD protection circuit 1 stably operates when the VCCQ voltage of the pad P1 varies. The circuit of these transistors Tr11, Tr17, Tr18, Tr21, Tr27, Tr28 is also called a power noise filter circuit (Schmitt trigger).

[0028] The gate of the transistor Tr12 and the gate of the transistor Tr22 are electrically connected to the node V1. The transistor Tr12 and the transistor Tr22 are connected in series between the wiring L1 and the wiring L2. The transistor Tr12 is provided between the wiring L1 and the node V2. The transistor Tr22 is provided between the node V2 and the wiring L2. In this embodiment, the transistor Tr12 is a p-type MOSFET and the transistor Tr22 is an n-type MOSFET. The transistors Tr12 and Tr22 output a voltage V2 having a logic level inverted from that of the voltage V1. The circuit of these transistors Tr12 and Tr22 functions as a buffer circuit which amplifies and inverts the voltage V1.

[0029] The resistor R2 is provided between the node V2 and the node V3'. The capacitor C2 is provided between the node V3' and the wiring L2. The node V3' is located downstream of the node V2. The resistor R2 and the capacitor C2 function as a filter circuit (low-pass filter) which suppresses oscillation of the voltage V2.

[0030] The gate of the transistor Tr13 and the gate of the transistor Tr23 are electrically connected to the node V3'. The transistor Tr13 and the transistor Tr23 are connected in series between the wiring L1 and the wiring L2. The transistor Tr13 is provided between the wiring L1 and the node V3. The transistor Tr23 is provided between the node V3 and the wiring L2. In this embodiment, the transistor Tr13 is a p-type MOSFET and the transistor Tr23 is an n-type MOSFET. The transistors Tr13 and Tr23 output a voltage V3 having a logic level inverted from that of the voltage V3'. The circuit of these transistors Tr13 and Tr23 functions as a buffer circuit which amplifies and inverts the voltage V3'.

[0031] The gate of the transistor Tr14 and the gate of the transistor Tr24 are electrically connected to the node V4'. The node V4' of this embodiment is electrically connected to the node V3 and is at the same potential as the node V3. The transistor Tr14 and the transistor Tr24 are connected in series between the wiring L1 and the wiring L2. The transistor Tr14 is provided between the wiring L1 and the node V4. The transistor Tr24 is provided between the node V4 and the wiring L2. In this embodiment, the transistor Tr14 is a p-type MOSFET and the transistor Tr24 is an n-type MOSFET. The transistors Tr14 and Tr24 output a voltage V4 having a logic level inverted from that of the voltage V4'. The circuit of these transistors Tr14 and Tr24 functions as a buffer circuit which amplifies and inverts the voltage V4'.

[0032] The gate of the transistor Tr1 is electrically connected to the node V4. The transistor Tr1 is electrically connected to the node V3 via the resistor R3, and is electrically connected to the wiring L2. Specifically, the resistor R3 is electrically connected to the wiring between the node V3 and the node V4'. In the present embodiment, the transistor Tr1 is an n-type MOSFET. The circuits of the transistors Tr13, Tr23, Tr14, Tr24, and Tr1 of the present embodiment function as a voltage detection circuit that detects a voltage generated by a surge. Thus, it is possible to determine the presence or absence of a surge.

[0033] The resistor R4 is disposed between the node V4' and the wiring L2. Specifically, the resistor R4 is electrically connected to the wiring between the node V4' and the node V5'.

[0034] The gate of the transistor Tr15 and the gate of the transistor Tr25 are electrically connected to the node V5'. The node V5' of the present embodiment is electrically connected to the nodes V3 and V4', and is at the same potential as the nodes V3 and V4'. The transistors Tr15 and Tr25 are connected in series between the wiring L1 and the wiring L2. The transistor Tr15 is electrically connected to the wiring L1, and is electrically connected to the node V5 via the resistor R5. The transistor Tr25 is electrically connected to the node V5, and is electrically connected to the wiring L2. In the present embodiment, the transistor Tr15 is a p-type MOSFET, and the transistor Tr25 is an n-type MOSFET. The transistors Tr15 and Tr25 output a voltage V5 having a logic level that is inverted from the logic level of the voltage V5'. The circuits of these transistors Tr15 and Tr25 function as a buffer circuit that amplifies and inverts the voltage V5'.

[0035] The resistor R6 is disposed between the node V5 and the node V6'. The capacitor C3 is disposed between the node V6' and the wiring L2. The node V6' is located downstream of the node V5. The resistor R6 and the capacitor C3 function as a filter circuit (low-pass filter) that suppresses oscillation of the voltage V5.

[0036] The gate of the transistor Tr16 and the gate of the transistor Tr26 are electrically connected to the node V6'. The transistor Tr16 and the transistor Tr26 are connected in series between the wiring LI and the wiring L2. The transistor Tr16 is arranged between the wiring LI and the node V6. The transistor Tr26 is arranged between the node V6 and the wiring L6. In the present embodiment, the transistor Tr16 is a p-type MOSFET, and the transistor Tr26 is an n-type MOSFET. The transistors Tr16, Tr26 output the voltage V6 having a logic level inverted from the logic level of the voltage V6'. The circuit of these transistors Tr16, Tr26 functions as a buffer circuit that amplifies and inverts the voltage V6'. The circuit of the transistors Tr15, Tr25, Tr16, Tr26 of the present embodiment functions as a discharge drive circuit that discharges the surge charge in the ESD protection circuit 1 to the transistor Tr3. The transistor Tr2 and the NOR circuit 21 also participate in the operation of the discharge drive circuit.

[0037] The NOR circuit 21 receives the voltage V5' from the node V5' at one input terminal and receives the voltage VRC from the node VRC at the other input terminal. Then, the NOR circuit 21 performs NOR operation of the voltage V5' and the voltage VRC, and outputs the voltage VRC1 obtained by the NOR operation from the output terminal. The voltage V5' is an example of the first signal, the voltage VRC1 is an example of the second signal, and the voltage VRC is an example of the third signal. More detailed circumstances regarding the operation of the NOR circuit 21 will be described later.

[0038] The transistor Tr2 has a control terminal (gate) that receives the voltage VRC1. One of the main terminals (source and drain) of the transistor Tr2 is electrically connected to the node GIN, and the other of the main terminals of the transistor Tr2 is electrically connected to the NOR circuit 21. The node GIN is located between the node V6 and the gate of the transistor Tr3, and is at the same potential as the node V6. The transistor Tr2 is controlled by the voltage VRC1 from the NOR circuit 21, and outputs a control signal S that controls the NOR circuit 21 to the NOR circuit 21. In the present embodiment, the transistor Tr2 is an n-type MOSFET.

[0039] The transistor Tr3 has a gate electrically connected to the node GIN. The transistor Tr3 is arranged between the wiring LI and the wiring L2. When the VCCQ voltage sharply rises, the transistor Tr3 becomes in an on state, and current flows from the wiring LI to the wiring L2 via the transistor Tr3. Thus, it is possible to suppress the influence of sudden change of the VCCQ voltage on the protected circuit. For example, the surge charge generated in the ESD protection circuit 1 is discharged from the wiring LI to the wiring L2 via the transistor Tr3. The transistor Tr3 is also referred to as a discharge transistor. In the present embodiment, the transistor Tr3 is an n-type MOSFET.

[0040] Further details of the ESD protection circuit 1 according to the present embodiment will be described later.

[0041] Figure 2 is a circuit diagram showing the configuration of the ESD protection circuit 1 of a comparative example of the first embodiment.

[0042] The ESD protection circuit 1 of the present comparative example has a configuration in which the NOR circuit 21 of the ESD protection circuit 1 according to the present embodiment is replaced by a NOT circuit (NOT gate, inverter) 22. The NOT circuit 22 receives the voltage VRC from the node VRC at an input terminal. Then, the NOT circuit 22 performs a NOT operation on the voltage VRC and outputs the voltage obtained by the NOT operation from an output terminal. The voltage output from the NOT circuit 22 and the control voltage S output from the transistor Tr2 are supplied to the same node, from which the voltage VRC1' is supplied to the gate of the transistor Tr2.

[0043] Next, the operation of the ESD protection circuit 1 of the present comparative example will be described.

[0044] When the power supply to the ESD protection circuit 1 of the present comparative example is turned on, in order to suppress the through current of the transistor Tr3 due to the rise of the voltage GIN caused by the gate coupling of the transistor Tr3, it is necessary to fix the voltage GIN at the VSS voltage.

[0045] The ESD protection circuit 1 of the present comparative example has two paths as paths for fixing the voltage GIN at the VSS voltage. The first path is a path in which the inverter 16, which operates after being charged via the node VRC, changes the voltage GIN to the VSS voltage. The first path reaches the node GIN from the node VRC via the nodes V1, V2, V3, V4, V5, and V6. The second path is a path in which the transistor Tr2 is turned on via the NOT circuit 22 when the voltage VRC is low, thereby changing the voltage GIN to the VSS voltage. The second path reaches the transistor Tr2 from the node VRC via the NOT circuit 22.

[0046] The ESD protection circuit 1 of the present comparative example changes the voltage GIN to the VSS voltage via the second path immediately after the power supply is turned on. The ESD protection circuit 1 of the present comparative example also disconnects the second path after the voltage GIN is fixed to the VSS voltage via the first path. During the switching from the first path to the second path, no through current is generated in the transistor Tr3.

[0047] Further, when a surge is applied to the ESD protection circuit 1 of the present comparative example, the VCCQ voltage sharply rises due to the surge. Due to this, the logic level of the voltage V4' becomes high (H), and the logic level of the voltage GIN also becomes high. As a result, the surge charge is discharged via the transistor Tr3.

[0048] Figure 3 is a timing chart showing an operation example of the ESD protection circuit 1 of the above-described comparative example.

[0049] Figure 3 An operation example when power is turned on to the ESD protection circuit 1 of the present comparative example is shown. When power is turned on to the ESD protection circuit 1 of the present comparative example, the VCCQ voltage rises to the power supply rated voltage, and the voltage VRC1' also rises accordingly. Thereby, the logic level of the voltage V4' changes from low level (L) to high level, and then the logic level of the voltage V5 changes from high level to low level. On the other hand, the voltage V6 (= voltage GIN) remains low level. In addition, in the ESD protection circuit 1 of the present comparative example, the voltage VRC1' is always higher than the voltage V6. Therefore, the voltage VRC1' is always higher than the voltage V6. Figure 3 In the ESD protection circuit 1 of the present comparative example, since no surge is applied to the ESD protection circuit 1, the current Is flowing through the transistor Tr3 is zero. When the on current flows through the transistor Tr3, the current Is becomes positive.

[0050] Figure 4 is a circuit diagram showing the configuration of the semiconductor device of the first embodiment. In addition, Figure 4 the configuration shown in the above-described comparative example is common to the semiconductor device of the present embodiment and the semiconductor device of the above-described comparative example.

[0051] As shown in Figure 4 , the semiconductor device of the present embodiment has the above-described ESD protection circuit 1 and an internal circuit 2 as an example of the above-described protected circuit. The internal circuit 2 is, for example, a three-dimensional memory. The internal circuit 2 of the present embodiment has an interface circuit 2a, a memory core 2b, and a sequencer 2c as constituent elements of the three-dimensional memory.

[0052] As shown in Figure 4 , the semiconductor device of the present embodiment further has a pad P1, a pad P2, at least one pad P3, a wiring L1, a wiring L2, an inverter INV, a resistor R, and a capacitor C. The pad P3 is an I / O (input / output) pad of the semiconductor device of the present embodiment. The inverter INV has an input terminal electrically connected to the pad P3. The resistor R is electrically connected to a node between the wiring L1, the pad P3, and the inverter INV. The capacitor C is electrically connected to the wiring L1 and the wiring L2 between the ESD protection circuit 1 and the internal circuit 2.

[0053] The interface circuit 2a is interposed between the pads P1 to P3 and other circuits in the internal circuit 2. The interface circuit 2a, for example, sends a command signal, an address signal from the pad P3 to the sequencer 2c, or sends a data signal from the pad P3 to the memory core 2b, or sends a data signal from the memory core 2b to the pad P3. The interface circuit 2a is also electrically connected to the wirings L1, L2. The memory core 2b has a plurality of memory cells. The sequencer 2c controls various actions of the semiconductor device of the present embodiment in accordance with a command signal, an address signal received from the interface circuit 2a.

[0054] Figure 4 The arrow shown indicates a discharge path when a surge is applied to the pad P3. The surge charge at this time is discharged to the wiring L2 through the resistor R, the wiring L1, and the ESD protection circuit 1 (transistor Tr3). Thus, the internal circuit 2 can be protected from static electricity. The semiconductor device of the present embodiment supplies the VCCQ voltage after the surge voltage is reduced by the ESD protection circuit 1 from the wiring L1 to the interface circuit 2a.

[0055] Figure 5 is a graph for explaining the action of the ESD protection circuit 1 of the above-described comparative example.

[0056] Here, the problem point in the case where the ESD test voltage of the ESD protection circuit 1 of the present comparative example is reduced is explained. Figure 5 (a) of shows the change of the VCCQ voltage and the voltage GIN with time in the case where the ESD test voltage is 2000 V. Figure 5 (b) of shows the change of the VCCQ voltage and the voltage GIN with time in the case where the ESD test voltage is 1000 V. The symbol Va indicates a circuit action minimum voltage, the symbol Vb indicates a withstand voltage standard, and the symbol T indicates an RC timer period.

[0057] When the ESD test voltage is changed from 2000 V to 1000 V, the surge current decreases, and the maximum value of the VCCQ voltage at the time of application of a surge decreases. Thus, a discharge action in the vicinity of the circuit action minimum voltage of the ESD protection circuit 1 is expected. However, in the ESD protection circuit 1 of the present comparative example, the voltage GIN at the time of discharge is determined by "VCCQ voltage - I (Tr2) x Ron (Tr2)", and the voltage GIN is lower than the VCCQ voltage. Thus, the discharge margin of the transistor Tr3 decreases. As a result, the discharge based on the transistor Tr3 can become an insufficient state, and a voltage rise due to a residual charge becomes a main cause of violation of the withstand voltage standard. Here, I (Tr2) indicates a current flowing through the transistor Tr2, and Ron (Tr2) indicates an on-resistance of the transistor Tr2.

[0058] In Figure 5In (b), at the time points indicated by arrows A and B, the VCCQ voltage is higher than the withstand voltage standard. At these moments, the voltage rise caused by residual charge leads to a breach of the withstand voltage standard. Just before reaching these moments, the voltage GIN is lower than the minimum operating voltage of the circuit, which is the cause of the residual charge.

[0059] On the other hand, the ESD protection circuit 1 of this embodiment has a NOR circuit 21 instead of a NOT circuit 22, and supplies voltage VRC and voltage V5' to the NOR circuit 21. Figure 1 Therefore, when a surge voltage is applied to ESD protection circuit 1, if voltage V5' becomes high, the gate potential (i.e., voltage VRC1) of transistor Tr2, which pulls voltage GIN low, becomes low. This allows transistor Tr2 to turn off and voltage GIN to rise to VCCQ. (Refer to...) Figure 6 This needs to be explained.

[0060] Figure 6 This is a graph illustrating the operation of the ESD protection circuit 1 in the first embodiment.

[0061] Figure 6 (a) For the ESD protection circuit 1 of the above comparative example, the changes of VCCQ voltage and voltage GIN over time are shown when the ESD test voltage is 1000V. Figure 6 The curve shown in (a) is similar to Figure 5 The curve shown in (b) is the same. Figure 6 (b) For the ESD protection circuit 1 of this embodiment, the changes of VCCQ voltage and voltage GIN over time are shown when the ESD test voltage is 1000V.

[0062] In the above comparative examples ( Figure 6 In (a)), the discharge voltage GIN is lower than the VCCQ voltage. Therefore, before the logic level of the voltage output from NOT circuit 22 is reversed, the gate potential of transistor Tr1 is lower than the threshold voltage of transistor Tr1. As a result, insufficient discharge occurs due to the cutoff of transistor Tr1, and residual charge leads to a violation of the withstand voltage standard.

[0063] On the other hand, in this embodiment ( Figure 6In (b)), the voltage GIN can rise to VCCQ when a surge is applied. This suppresses the possibility of transistor Tr1 being turned off before the logic level of the voltage (VRC1) output from NOR circuit 21 reverses. Therefore, according to this embodiment, insufficient discharge caused by the turn-off of transistor Tr1 can be suppressed, and residual charge leading to a violation of the withstand voltage standard can be suppressed. Furthermore, according to this embodiment, this effect can be achieved without hindering countermeasures against the through current during power-on, and similarly to the comparative example described above, appropriate circuit characteristics of the ESD protection circuit 1 can be achieved during power-on.

[0064] Figure 7 This is another graph used to illustrate the operation of the ESD protection circuit 1 in the first embodiment.

[0065] Figure 7 (a) For the ESD protection circuit 1 of the above comparative example, the changes of VCCQ voltage and voltage GIN over time are shown when the ESD test voltage is 1000V. Figure 7 (b) For the ESD protection circuit 1 of this embodiment, the changes of VCCQ voltage and voltage GIN over time are shown when the ESD test voltage is 1000V. Compared to Figure 6 (a) and Figure 6 In case (b), Figure 7 (a) and Figure 7 (b) shows the changes of VCCQ voltage and voltage GIN over time when the difference between the operation of the ESD protection circuit 1 in the comparative example and the operation of the ESD protection circuit 1 in this embodiment is small.

[0066] In the above comparative examples ( Figure 7 In (a)), the discharge voltage GIN is lower than the VCCQ voltage. Therefore, sometimes the gate potential of transistor Tr1 is lower than the threshold voltage of transistor Tr1 before the logic level of the voltage output from NOT circuit 22 is reversed. In this case, because transistor Tr1 does not discharge, the VCCQ voltage rises due to the inflow of charge. Therefore, as the VCCQ voltage rises, transistor Tr1 discharges the charge. However, in transistor Tr1, insufficient discharge occurs because a sufficient VGS (gate-source voltage) cannot be ensured, resulting in a violation of the withstand voltage standard.

[0067] On the other hand, in this embodiment ( Figure 7 In (b)), the voltage GIN can be raised to VCCQ voltage when a surge is applied. This suppresses situations where the withstand voltage standard is violated due to insufficient discharge.

[0068] As described above, the ESD protection circuit 1 of the present embodiment has the NOR circuit 21 that receives the voltage V5' at one input terminal and receives the VCCQ voltage at the other input terminal, and outputs the voltage VRC1 obtained by the operation of the voltage V5' and the VCCQ voltage to the transistor Tr2. Therefore, according to the present embodiment, the surge charge in the ESD protection circuit 1 can be properly discharged, and it is possible to suppress the case where the residual charge causes the violation of the withstand voltage standard, and the like.

[0069] In addition, such an effect can be achieved by using an operation circuit other than the NOR circuit 21. An example of such an operation circuit is described in the embodiments described later.

[0070] (Second Embodiment)

[0071] Figure 8 is a circuit diagram showing the configuration of the ESD protection circuit 1 of the second embodiment.

[0072] The ESD protection circuit 1 of the present embodiment has a configuration in which the NOR circuit 21 of the first embodiment is replaced by a combination of the NOR circuit 21 and the NOT circuit 22. The combination of the NOR circuit 21 and the NOT circuit 22 of the present embodiment is an example of an operation circuit.

[0073] In the present embodiment, the NOT circuit 22 receives the voltage V6' from the node V6' at the input terminal. Then, the NOT circuit 22 performs the NOT operation of the voltage V6', and outputs the voltage obtained by the NOT operation from the output terminal. The voltage V6' is an example of the first signal, and the voltage output from the NOT circuit 22 is an example of the fourth signal.

[0074] In the present embodiment, the NOR circuit 21 is also caused to receive the voltage output from the NOT circuit 22 at one input terminal, and to receive the voltage VRC from the node VRC at the other input terminal. Then, the NOR circuit 21 performs the NOR operation of the voltage output from the NOT circuit 22 and the voltage VRC, and outputs the voltage VRC2 obtained by the NOR operation from the output terminal. The transistor Tr2 of the present embodiment has a gate that receives the voltage VRC2, is controlled by the voltage VRC2 from the NOR circuit 21, and outputs the control signal S that controls the NOT circuit 22 to the NOT circuit 22. The voltage VRC2 is an example of the second signal, and the voltage VRC is an example of the third signal.

[0075] In the present embodiment, when a surge voltage is applied to the ESD protection circuit 1, if the voltage V6' becomes low, the gate potential of the transistor Tr2 that pulls down the voltage GIN (i.e., the voltage VRC2) becomes low. Due to this, it is possible to turn off the transistor Tr2, and it is possible to raise the voltage GIN to the VCCQ voltage.

[0076] (third embodiment)

[0077] Figure 9 is a circuit diagram showing the configuration of the ESD protection circuit 1 of the third embodiment.

[0078] The ESD protection circuit 1 of the present embodiment has a configuration in which the NOR circuit 21 of the ESD protection circuit 1 of the present embodiment is replaced by a NOT circuit 22. The NOT circuit 22 of the present embodiment is an example of an arithmetic circuit.

[0079] In the present embodiment, the NOT circuit 22 receives the voltage V5' from the node V5' at the input terminal. Then, the NOT circuit 22 performs a NOT operation on the voltage V5', and outputs the voltage VRC3 obtained by the NOT operation from the output terminal. The transistor Tr2 of the present embodiment has a gate that receives the voltage VRC3, is controlled by the voltage VRC3 from the NOT circuit 22, and outputs the control signal S that controls the NOT circuit 22 to the NOT circuit 22. The voltage V5' is an example of a first signal, and the voltage VRC3 is an example of a second signal.

[0080] In the present embodiment, if the voltage V5' becomes high when a surge voltage is applied to the ESD protection circuit 1, the gate potential of the transistor Tr2 that pulls down the voltage GIN (i.e., the voltage VRC3) becomes low. Thereby, the transistor Tr2 can be turned off, and the voltage GIN can be raised to the VCCQ voltage.

[0081] (fourth embodiment)

[0082] Figure 10 is a circuit diagram showing the configuration of the ESD protection circuit 1 of the fourth embodiment.

[0083] The ESD protection circuit 1 of the present embodiment has a capacitor C4 in addition to the configuration elements of the ESD protection circuit 1 of the first embodiment. The capacitor C4 and the resistor R4 are connected in series between the wiring L1 and the wiring L2. The capacitor C4 is disposed between the wiring L1 and the nodes V3, V4', and V5'. The resistor R4 is disposed between the nodes V3, V4', and V5' and the wiring L2. The capacitor C4 and the resistor R4 of the present embodiment function as a filter circuit (high-pass filter) that is electrically connected to the nodes V3, V4', and V5'. The filter circuit is disposed downstream of the inverters 11 to 14 and the transistor Trl, and upstream of the inverters 15 to 16 and the transistors Tr2 to Tr3 between the wiring L1 and the wiring L2.

[0084] In the present embodiment, the NOR circuit 21 receives the voltage V5' from the node V5' at one input terminal and the voltage VRC from the node VRC at the other input terminal. Then, the NOR circuit 21 performs NOR operation of the voltage V5' and the voltage VRC and outputs the voltage VRC4 obtained by the NOR operation from the output terminal. The transistor Tr2 of the present embodiment has a gate that receives the voltage VRC4 and controls the NOR circuit 21 by the voltage VRC4 from the NOR circuit 21 to output the control signal S that controls the NOR circuit 21 to the NOR circuit 21. The voltage V5' is an example of the first signal, the voltage VRC4 is an example of the second signal, and the voltage VRC is an example of the third signal.

[0085] Next, the ESD protection circuit 1 of the first embodiment is compared with the ESD protection circuit 1 of the fourth embodiment.

[0086] In the ESD protection circuit 1 of the first embodiment, Figure 1 ) when the ESD test voltage is changed from 2000 V to 1000 V, the surge current decreases and the gradient of the rise of the VCCQ voltage at the time of application of the surge becomes slow. Therefore, depending on the configuration of the voltage detection circuit within the ESD protection circuit 1, it is possible that the voltage detection circuit cannot follow the gradient of the rise of the VCCQ voltage and the voltage V4' cannot be turned to the high level. As a result, it is possible that an error occurs in the voltage detection at the time of application of the surge and discharge deficiency is caused. Further, it is possible that the VCCQ voltage rises due to residual charge and thus the withstand voltage standard is violated. In addition, since the setting of the detection voltage of the voltage detection circuit is set by balancing the impedances of the charge side and the discharge side, it is easily broken by factors such as PVT, power supply voltage, and the like, and thus it is preferable to secure a margin of operation.

[0087] On the other hand, the ESD protection circuit 1 of the fourth embodiment Figure 10 ) has a high-pass filter including the capacitor C4 and the resistor R4. Thereby, it is possible to pull up the voltage V4' to the high level at the time of application of the surge.

[0088] In the present embodiment, it is preferable to set the cutoff frequency of the high-pass filter to be lower than the operation frequency (power supply rise frequency) of the VCCQ voltage at the time of application of the surge voltage. Thereby, the high-pass filter can contribute to the rise of the VCCQ voltage at the time of application of the surge voltage as a coupling capacitor. Further, with respect to the rise of the VCCQ voltage at the time of turning on the power supply, since the filtering is performed by the high-pass filter, it is possible to prevent the degradation of the function of reducing the through current. In addition, the capacitance value and shape of the capacitor C4 and the resistance value and shape of the resistor R4 can be arbitrarily selected.

[0089] In the first embodiment, the voltage V4' cannot be pulled up to the high level at the time of application of a surge, and it is possible that a violation of the withstand voltage standard occurs due to residual charge accompanying insufficient discharge. On the other hand, according to the fourth embodiment, the voltage V4' can be pulled up to the high level at the time of application of a surge voltage, and it is possible to suppress the occurrence of such a violation of the withstand voltage standard. In addition, in a case where the violation of the withstand voltage standard is not a problem in the first embodiment, by adopting the configuration of the ESD protection circuit 1 of the first embodiment which does not have the capacitor C4, it is possible to reduce the cost equivalent to the capacitor C4.

[0090] In addition, the semiconductor device of the present embodiment can also have a plurality of ESD protection circuits 1 having the configuration shown in FIG. 1 within one semiconductor chip. In this case, the capacitance value and shape of the capacitor C4 and the resistance value and shape of the resistor R4 can be the same in all of the ESD protection circuits 1, or can be different between the ESD protection circuits 1. Figure 10 In addition, the semiconductor device of the present embodiment can also have a plurality of ESD protection circuits 1 having the configuration shown in FIG. 1 within one semiconductor chip. In this case, the capacitance value and shape of the capacitor C4 and the resistance value and shape of the resistor R4 can be the same in all of the ESD protection circuits 1, or can be different between the ESD protection circuits 1.

[0091] In addition, the semiconductor device of the present embodiment can also have a plurality of ESD protection circuits 1 having the configuration shown in FIG. 1 within one semiconductor chip. In this case, the capacitance value and shape of the capacitor C4 and the resistance value and shape of the resistor R4 can be the same in all of the ESD protection circuits 1, or can be different between the ESD protection circuits 1. Figure 8 or Figure 9 In addition, the semiconductor device of the present embodiment can also have a plurality of ESD protection circuits 1 having the configuration shown in FIG. 1 within one semiconductor chip. In this case, the capacitance value and shape of the capacitor C4 and the resistance value and shape of the resistor R4 can be the same in all of the ESD protection circuits 1, or can be different between the ESD protection circuits 1.

[0092] In addition, in the present specification, the ESD test voltage is set to 2000 V and 1000 V, but the value of the ESD test voltage of each embodiment can also be other values. Such values of 2000 V and 1000 V are one example for explaining the operation of the ESD protection circuit 1 of each embodiment. The actual applied voltage is determined, for example, in accordance with the applied voltage specifications determined for each product of the semiconductor device.

[0093] The above-described embodiments are merely examples and are not intended to limit the scope of the application. The novel device described in the present specification can be implemented in various other ways. In addition, with respect to the modes of the device described in the present specification, various omissions, substitutions, and modifications can be made within the scope of the gist of the application. The appended claims and their equivalents are intended to include such modes, modifications, and the like.

[0094] Symbol Explanation

[0095] 1: ESD protection circuit, 2: internal circuit,

[0096] 2a: interface circuit, 2b: memory core, 2c: sequencer,

[0097] 11-16: inverters, 21: NOR circuit, 22: NOT circuit, P1-P3: pads, L1-L2: wires, R1-R6: resistors, C1-C4: capacitors, Tr1-Tr3, Tr11-Tr18, Tr21-Tr28: transistors.

Claims

1. A semiconductor device comprising: a first wiring and a second wiring; a protected circuit electrically connected to the first wiring and the second wiring downstream of the protected circuit, protected by the protected circuit, the protected circuit comprising: a first transistor and a second transistor having a gate electrically connected to a first node between the first wiring and the second wiring, connected in series between the first wiring and the second wiring; a third transistor and a fourth transistor having a gate electrically connected to a second node between the first transistor and the second transistor, connected in series between the first wiring and the second wiring; a fifth transistor having a gate electrically connected to a third node between the third transistor and the fourth transistor, provided between the second node and the second wiring; a calculation circuit receiving a first signal from the second node or from a fourth node provided between the first wiring and the second wiring downstream of the second node, outputting a second signal obtained by calculation using the first signal; and a sixth transistor electrically connected to a fifth node provided between the first wiring and the second wiring downstream of the second node, receiving the second signal from the calculation circuit, outputting a control signal to the calculation circuit. a protection circuit electrically connected to a first wiring supplied with a first voltage and a second wiring supplied with a second voltage; 2. The semiconductor device according to claim 1, wherein the calculation circuit receives a third signal from a sixth node provided between the first wiring and the second wiring upstream of the first node, outputs the second signal obtained by calculation using the first signal and the third signal.

3. The semiconductor device according to claim 2, wherein the calculation circuit includes a NOR circuit outputting the second signal obtained by NOR calculation of the first signal and the third signal.

4. The semiconductor device according to claim 2, wherein the calculation circuit includes: a NOT circuit outputting a fourth signal obtained by NOT calculation of the first signal; and a NOR circuit outputting the second signal obtained by NOR calculation of the fourth signal and the third signal.

5. The semiconductor device according to claim 2, wherein the sixth node is between a resistance electrically connected to the first wiring and a capacitor electrically connected to the second wiring.

6. The semiconductor device according to claim 1, wherein the calculation circuit includes a NOT circuit outputting the second signal obtained by NOT calculation of the first signal.

7. The semiconductor device according to claim 1, wherein the sixth transistor receives the second signal at a gate of the sixth transistor.

8. The semiconductor device according to any one of claims 1 to 6, wherein the protected circuit further comprises a high-pass filter provided between the first wiring and the second wiring, electrically connected to the second node.

9. The semiconductor device according to claim 8, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The high-pass filter is provided downstream of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor between the first wiring and the second wiring.

10. The semiconductor device according to claim 8, wherein The high-pass filter includes a capacitor and a resistor connected in series between the first wiring and the second wiring.

11. The semiconductor device according to any one of claims 1 to 6, wherein The protection circuit further includes: a seventh transistor and an eighth transistor having a gate electrically connected to the second node, connected in series between the first wiring and the second wiring, and a ninth transistor and a tenth transistor electrically connected to the fourth node between the seventh transistor and the eighth transistor, connected in series between the first wiring and the second wiring, the sixth transistor is electrically connected to the fifth node between the ninth transistor and the tenth transistor.

12. The semiconductor device according to any one of claims 1 to 6, wherein The protection circuit further includes an eleventh transistor having a gate electrically connected to the fifth node, provided between the first wiring and the second wiring.

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