A switching converter

Abstract

The application relates to the field of power supply circuits and discloses a switching converter. Compared with the prior art, the application adds an absorption capacitor and a MOS tube in series and then connects the absorption capacitor and the MOS tube in parallel at both ends of a power tube Q2 of the switching converter. The application controls the MOS tube to control the charging and discharging time of the absorption capacitor, so that the positive stress peak and the negative stress peak generated by the power tube Q1 and the power tube Q2 are reduced when the power tube Q1 is turned off, thereby avoiding the problems of device selection difficulty and poor EMI; and the application is beneficial to improving the turn-off speed of the power tube Q1 and reducing the turn-off loss in the application environment with large output current.

Description

Technical Field

[0001] This invention relates to the field of power supply circuits, and particularly to switching converters used in ZVS control. Background Technology

[0002] ZVS (Zero Voltage Switching) BUCK converters are the main trend in the development of switching converters due to their advantages such as low switching losses, high efficiency, and good EMI performance.

[0003] Please refer to Figure 1 Chinese patent application CN202011039117.2 discloses a multimode soft-switching converter and its control method. The switching converter includes a synchronous rectifier circuit and a controller. The controller, based on the load and switching frequency, controls the conduction and cutoff of power transistors Q1 and Q2 in the synchronous rectifier control circuit, enabling the synchronous rectifier circuit to operate in frequency conversion mode, quasi-resonant frequency limiting mode, and frequency reduction mode. The controller determines whether the frequency conversion mode and quasi-resonant frequency limiting mode should include a reverse phase based on the relationship between the input and output voltages. Ultimately, this achieves zero-voltage turn-on of the synchronous rectifier circuit across the entire load range and the entire input voltage range, i.e., a soft-switching effect, thereby improving the switching converter's operating frequency, power density, and efficiency, while reducing size and cost.

[0004] The multimode soft-switching converter and its control method proposed in this patent are mainly based on the ZVS technology of synchronous rectified BUCK converters. By raising the midpoint voltage Vs of the switching converter to near the input voltage Vin before power transistor Q1 is turned on, and then turning on power transistor Q1, ZVS of power transistor Q1 is achieved. Furthermore, since this control method is mainly implemented by detecting whether the inductor current L crosses zero, the switching BUCK converter operates near the critical mode, and its power transistor Q2 can naturally achieve ZVS turn-on and approximately ZCS (zero-current turn-off).

[0005] However, the aforementioned multimode soft-switching converter and its control method have the following drawbacks: before the power transistor Q1 is turned off, the maximum current iQ1 flowing through the power transistor Q1 is... max >2Io (Io represents the output current of the soft-switching converter mentioned above). In order to reduce turn-off losses, the turn-off speed of power transistor Q1 needs to be fast enough. However, because the turn-off speed of power transistor Q1 is fast, power transistors Q1 and Q2 generate very large positive stress peaks and negative stress peaks, respectively, which leads to difficulties in device selection and poor EMI. Summary of the Invention

[0006] In view of this, the technical problem to be solved by the present invention is to propose a switching converter that can reduce the positive and negative stress spikes generated by power transistors Q1 and Q2 at the moment of power transistor Q1 turn-off in existing synchronous rectifier BCUK converters under application environments with large output current. This improves the applicability, device reliability, and EMI performance of the switching converter and reduces the difficulty of device selection. At the same time, while ensuring the reduction of power transistor stress, it can effectively reduce the impact of absorption capacitors on the efficiency of the switching converter.

[0007] The inventive concept of this application is as follows: A snubber capacitor and a switching transistor (MOS transistor) are connected in series, and then connected in parallel across the drain and source terminals of the power transistor Q2 in a switching converter. During the on-time of power transistor Q2, before power transistor Q1 is turned on, the switching transistor is turned on, and the snubber capacitor is applied to the switching converter. When power transistor Q2 is turned off, the equivalent output capacitance across the drain and source terminals of power transistor Q2 is the sum of the parasitic capacitance and the snubber capacitor. Since the inductor current reverses when power transistor Q2 is turned off, the reverse current in the inductor charges the parasitic capacitance and the snubber capacitor of power transistor Q2 at the instant of turn-off (the capacitance of the snubber capacitor is much larger than that of the parasitic capacitance), and the drain voltage of power transistor Q2 begins to rise. When the drain voltage of power transistor Q2 rises to near the output voltage of the switching converter, the switching transistor is turned off. At this time, the equivalent output capacitance across power transistor Q2 decreases from the sum of the parasitic capacitance and the snubber capacitor to equal the capacitance of the parasitic capacitance. As the equivalent output capacitance of power transistor Q2 decreases, the slope of the drain voltage rise of power transistor Q2 increases, and the drain voltage continues to rise until it reaches near the input voltage, at which point power transistor Q1 turns on, achieving zero-voltage turn-on of power transistor Q1.

[0008] When power transistor Q1 is turned off, since the inductor current of the switching converter cannot change abruptly, the drain voltage of power transistor Q2 begins to decrease. At this time, the equivalent output capacitance across power transistor Q2 is C. OSS2 (The value of the parasitic capacitance) decreases rapidly. When the drain voltage drops below the absorption capacitor voltage, the body diode of the switching transistor conducts. At this time, the equivalent output capacitance C across the power transistor Q2 is... OSS2 The sum of the absorption capacitor and the voltage across the transistor. By turning on the transistor while its body diode is conducting, zero-voltage turn-on can be achieved, reducing turn-on losses. Because the equivalent capacitance of power transistor Q2 increases, the slope of its drain voltage drop becomes slower. Since capacitor voltage cannot change abruptly, this effectively absorbs the positive and negative stress spikes generated by power transistors Q1 and Q2 when Q1 is turned off, thus resolving EMI issues.

[0009] Furthermore, when the load is relatively light, the switching converter operates in frequency-limited mode. In this state, the maximum current flowing through power transistor Q1 before it is turned off is small, and stress issues are not prominent. To reduce the impact on efficiency in this state, the switching transistor has no drive input and does not operate.

[0010] Based on this inventive concept, the present invention provides the following technical solution:

[0011] A switching converter includes power transistors Q1 and Q2, an inductor, and a capacitor. Power transistors Q1 and Q2 each have a first terminal and a second terminal. The first terminal of power transistor Q1 is connected to the positive terminal of a power supply. The second terminal of power transistor Q1 is connected to both one end of the inductor and the first terminal of power transistor Q2. The other end of the inductor is connected to one end of the capacitor, and the second terminal of power transistor Q2 is connected to the other end of the capacitor.

[0012] The switching converter also includes an active snubber circuit connected in parallel with the first and second terminals of the power transistor Q2. The active snubber circuit includes a snubber capacitor and a switching transistor with a body diode. The snubber capacitor and the switching transistor are connected in series. The snubber capacitor is used to absorb the voltage stress generated when the power transistor Q1 is turned off when the switching transistor is turned on.

[0013] After the power transistor Q1 is turned off, when the voltage at the first terminal of the power transistor Q2 is lower than the voltage of the absorption capacitor and when the body diode of the switching transistor is turned on, the switching transistor is controlled to be turned on.

[0014] When the output load current of the switching converter is less than a certain value, and the switching converter is operating in frequency limiting mode, the switching transistor remains off. The frequency limiting mode is one of the following operating modes:

[0015] The first working mode is: after the power transistor Q1 is turned off, the power transistor Q2 is not turned on. When the drain voltage of the power transistor Q2 resonates to the trough, the working mode of turning on the power transistor Q2 is then activated.

[0016] The second operating mode is as follows: after the power transistor Q1 is turned off, the power transistor Q2 is not turned on. When the drain voltage of the power transistor Q2 resonates to the peak, the power transistor Q1 is turned on again.

[0017] Preferably, power transistors Q1, Q2 and the switching transistor are all MOSFETs, the first terminals of power transistors Q1 and Q2 are the drain terminals, and the second terminals of power transistors Q1 and Q2 are the source terminals.

[0018] One end of the snubber capacitor is connected to both the source of the power transistor Q1 and one end of the inductor. The other end of the snubber capacitor is connected to the drain of the switching transistor. The source of the switching transistor is connected to the other end of the capacitor, and the source of the switching transistor is used to connect to the negative terminal of the power supply.

[0019] Preferably, power transistors Q1, Q2 and the switching transistor are MOSFETs, with the first terminals of power transistors Q1 and Q2 being the drain terminals and the second terminals of power transistors Q1 and Q2 being the source terminals.

[0020] The drain of the switching transistor is connected to both the source of the power transistor Q1 and one end of the inductor. One end of the snubber capacitor is connected to the source of the switching transistor, and the other end of the snubber capacitor is connected to the other end of the capacitor. The other end of the snubber capacitor is also used to connect to the negative terminal of the power supply.

[0021] Preferably, the absorption capacitor is a collection of multiple capacitors connected in series or in parallel, and the switching transistor is a collection of multiple switching transistors connected in series or in parallel.

[0022] Preferably, when the switching transistor is turned off, the drain voltage Vs of the power transistor Q2 satisfies the following relationship: Vin>Vs>0V, where Vin is the voltage of the power supply.

[0023] Preferably, when the switching transistor is turned off, the drain voltage Vs of the power transistor Q2 satisfies the following relationship: Vs = V out V out This is the output voltage of the switching converter.

[0024] Preferably, the switching transistor is an NMOS transistor.

[0025] Preferably, during one switching cycle, after the power transistor Q2 is turned off, the switching transistor is controlled to remain on before the inter-electrode voltage between the first and second terminals of the power transistor Q2 rises to a certain voltage value.

[0026] Preferably, the voltage value is greater than 0 and less than the voltage of the power supply.

[0027] The working principle of this invention will be analyzed in conjunction with specific embodiments, and will not be elaborated here. The beneficial effects of this invention are as follows:

[0028] (1) The voltage stored in the absorption capacitor is controlled by controlling the turn-off of the switching transistor. During the decrease of the midpoint voltage of the BUCK converter (i.e., the voltage at the connection point between the source and drain of power transistor Q1 and power transistor Q2), when the midpoint voltage is lower than the voltage of the absorption capacitor, the body diode of the switching transistor conducts, putting the absorption capacitor into the circuit. At this moment, the switching transistor is turned on, achieving zero-voltage turn-on of the switching transistor. Utilizing the principle that the capacitor voltage cannot change abruptly, the positive and negative stress spikes generated in the switching converter when power transistor Q1 is turned off can be effectively reduced, thus solving the EMI problem.

[0029] (2) The present invention controls the charging voltage of the absorption capacitor by controlling the switching transistor to turn off, avoiding the absorption capacitor being engaged throughout the process, which can effectively reduce the inductor negative current loss and power transistor Q1 turn-off loss caused by the absorption capacitor.

[0030] (3) When the load is relatively light, the switching converter operates in frequency-limited mode. In this state, the maximum current flowing through the power transistor Q1 before it is turned off is small, and the stress problem is not prominent. To reduce the efficiency impact in this state, the switching transistor has no drive input and does not operate. This effectively avoids the impact of the absorption capacitor on efficiency. Attached Figure Description

[0031] Figure 1 Schematic diagram of an existing switching converter;

[0032] Figure 2 Schematic diagram of the switching converter of the first embodiment of the present invention;

[0033] Figure 3 for Figure 2 Control timing and waveforms;

[0034] Figure 4 A schematic diagram of the switching converter according to the second embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0036] First Embodiment

[0037] Figure 2 This is a schematic diagram of a switching converter according to a first embodiment of the present invention. In this embodiment, the switching converter is a synchronous rectified BCUK converter, which includes power transistors Q1 and Q2, inductor L, and capacitor C. out In addition to the active absorption circuit, in this embodiment, power transistors Q1 and Q2 are MOSFETs. The drain of power transistor Q1 is connected to the positive terminal of the power supply, and the source of power transistor Q1 is connected to both one end of an inductor and the drain of power transistor Q2. The other end of the inductor is connected to capacitor C. out At one end, the source of power transistor Q2 is connected to capacitor C. out At the other end, an active absorption circuit is connected in parallel with the drain and source of power transistor Q2. It includes an absorption capacitor Cr and a MOSFET Q3 connected in series. Specifically, one end of the absorption capacitor Cr is connected to both the source of power transistor Q1 and one end of inductor L, while the other end of the absorption capacitor Cr is connected to the drain of MOSFET Q3. The source of MOSFET Q3 is simultaneously connected to the negative input power supply and capacitor C. out The other end is the negative of the power supply output, and the absorption capacitor is used to absorb the voltage stress generated when the power transistor Q1 is turned off.

[0038] Figure 3 This document presents the control timing and waveforms of the switching converter of this invention. Now, in conjunction with... Figure 3 The seven stages of each cycle (from time t0 to time t7, denoted as T) are explained as follows:

[0039] During the T0-T1 phase: At the initial moment To, the inductor current iL = 0A. At this time, power transistor Q2 continues to conduct, and the drive voltage Vgs2 of power transistor Q2 remains high until moment T1, when power transistor Q2 is turned off, and the drive voltage Vgs2 of power transistor Q2 becomes low. During the T0-T1 phase, MOSFET Q3 remains on, and the drive voltage Vgs3 remains high. The absorption capacitor Cr is connected in parallel with the parasitic capacitance Coss2 of power transistor Q2.

[0040] During the T1-T2 phase: At the initial moment T1, the inductor current iL reaches its negative maximum value, at which point power transistor Q2 is turned off, and the drive voltage Vgs2 of power transistor Q2 becomes low. During the T1-T2 phase, MOSFET Q3 remains on, and the absorption capacitor Cr is connected in parallel with the parasitic capacitance Coss2 of power transistor Q2, increasing the equivalent output capacitance of power transistor Q2. During this phase, the drain voltage Vs of power transistor Q2 rises relatively slowly until moment T2, when the drain voltage Vs rises to near the output voltage Vout, at which point MOSFET Q3 is turned off (when MOSFET Q3 is turned off, the drain voltage Vs must satisfy: Vin > Vs > 0V, the drain voltage Vs is determined based on the actual debugging results), and the drive voltage Vgs3 of MOSFET Q3 becomes low. The equivalent output capacitance of power transistor Q2 decreases to be the same as the parasitic capacitance Coss2.

[0041] During the T2-T3 phase: the equivalent output capacitance of power transistor Q2 decreases to be the same as the parasitic capacitance Coss2, and the drain voltage Vs rises at a steeper slope, climbing rapidly until it reaches near the input voltage Vin of the power supply. At time T3, power transistor Q1 turns on, achieving zero-voltage turn-on for power transistor Q1.

[0042] T3-T4 stage: At time T3, power transistor Q1 is turned on, and the driving voltage Vgs1 of power transistor Q1 becomes high level, which lasts until time T4.

[0043] T4-T5 stage: At time T4, power transistor Q1 is turned off, and its drive voltage Vgs1 becomes low. Since the current in inductor L cannot change abruptly, the drain voltage Vs of power transistor Q2 begins to drop rapidly. At this time, the equivalent output capacitance of power transistor Q2 is Coss2.

[0044] During the T5-T6 phase: At time T5, the drain voltage Vs of power transistor Q2 is less than the voltage of the absorption capacitor Cr. At this time, the body diode of MOSFET Q3 is turned on. The absorption capacitor Cr is connected in parallel with the parasitic capacitance Coss2 of power transistor Q2, increasing the equivalent output capacitance of power transistor Q2. Therefore, the rate of decrease of the drain voltage Vs of power transistor Q2 slows down. Since capacitor voltage cannot change abruptly, the stress generated by power transistors Q1 and Q2 can be effectively absorbed at this moment. That is, the positive stress peak generated by power transistor Q1 and the corresponding negative stress peak generated by power transistor Q2 when power transistor Q1 is turned off are greatly reduced, thereby reducing system stress and EMI problems, while having a relatively small impact on system losses. Because the body diode of MOSFET Q3 turns on first at time T5, and then MOSFET Q3 turns on, MOSFET Q3 is turned on with zero voltage.

[0045] During the T6-T7 phase: At time T6, the drain voltage Vs of power transistor Q2 drops to 0V, the body diode of power transistor Q2 turns on, and then power transistor Q2 turns on. Therefore, power transistor Q2 is turned on with zero voltage.

[0046] Thus, one cycle of the first embodiment of the present invention has ended.

[0047] Note that the driving waveform of MOSFET Q3 is not limited to that described in the first embodiment. During stages T2-T5, MOSFET Q3 is not conducting. During stages T0-T1 and T5-T7, whether MOSFET Q3 conducts is not restricted. During stages T1-T2, MOSFET Q3 must conduct. During stages T5-T6, whether MOSFET Q3 conducts depends on the stress absorption effect.

[0048] Second Embodiment

[0049] Figure 4 This is a schematic diagram of the synchronous rectifier BCUK converter according to the second embodiment of the present invention. Figure 1 The difference lies in the connection relationship between the absorption capacitor Cr and the MOSFET Q3. Specifically, the drain of the MOSFET Q3 is connected to both the source of the power transistor Q1 and one end of the inductor L. One end of the absorption capacitor Cr is connected to the source of the MOSFET Q3, and the other end of the absorption capacitor Cr is connected to both the negative power input, the other end of the capacitor Cout, and the negative terminal of the power supply.

[0050] The second embodiment operates on the same principle as the first embodiment, and will not be described again here. The control timing and waveform of the synchronous rectifier BCU converter in the second embodiment are the same as those in the first embodiment.

[0051] Note: During stages T2-T5, MOSFET Q3 must not be turned on. During stages T0-T1 and T5-T7, there is no restriction on whether MOSFET Q3 is turned on. However, during stages T1-T2, MOSFET Q3 must be turned on. During stages T5-T6, whether MOSFET Q3 is turned on depends on the stress absorption effect.

[0052] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be considered as limitations on the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims. For those skilled in the art, several improvements and modifications can be made without departing from the spirit and scope of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A switching converter, comprising a power transistor Q1, a power transistor Q2, an inductor, and a capacitor, wherein the power transistor Q1 and the power transistor Q2 each have a first terminal and a second terminal, the first terminal of the power transistor Q1 is connected to the positive terminal of a power supply, the second terminal of the power transistor Q1 is connected to both one end of the inductor and the first terminal of the power transistor Q2, the other end of the inductor is connected to one end of the capacitor, and the second terminal of the power transistor Q2 is connected to the other end of the capacitor, characterized in that... The switching converter also includes an active absorption circuit connected in parallel with the first and second terminals of the power transistor Q2. The active absorption circuit includes an absorption capacitor and a switching transistor with a body diode. The absorption capacitor and the switching transistor are connected in series. The absorption capacitor is used to absorb the voltage stress generated when the power transistor Q1 is turned off when the switching transistor is turned on. After the power transistor Q1 is turned off, when the voltage at the first terminal of the power transistor Q2 is lower than the voltage of the absorption capacitor and when the body diode of the switching transistor is turned on, the switching transistor is controlled to be turned on. When the output load current of the switching converter is less than a certain value, and the switching converter is operating in frequency limiting mode, the switching transistor remains off. The frequency limiting mode is one of the following operating modes: The first working mode is: after the power transistor Q1 is turned off, the power transistor Q2 is not turned on. When the drain voltage of the power transistor Q2 resonates to the trough, the working mode of turning on the power transistor Q2 is then activated. The second operating mode is as follows: after the power transistor Q1 is turned off, the power transistor Q2 is not turned on. When the drain voltage of the power transistor Q2 resonates to the peak, the power transistor Q1 is turned on again.

2. The switching converter of claim 1, wherein: The power transistor Q1, the power transistor Q2 and the switching transistor are all MOSFETs. The first terminals of the power transistors Q1 and Q2 are the drain terminals and the second terminals of the power transistors Q1 and Q2 are the source terminals. One end of the absorption capacitor is connected to both the source of the power transistor Q1 and one end of the inductor. The other end of the absorption capacitor is connected to the drain of the switching transistor. The source of the switching transistor is connected to the other end of the capacitor, and the source of the switching transistor is used to connect to the negative terminal of the power supply.

3. The switching converter of claim 1, wherein: The power transistor Q1, the power transistor Q2 and the switching transistor are MOSFETs. The first terminals of the power transistors Q1 and Q2 are the drain terminals, and the second terminals of the power transistors Q1 and Q2 are the source terminals. The drain of the switching transistor is connected to both the source of the power transistor Q1 and one end of the inductor. One end of the absorption capacitor is connected to the source of the switching transistor, and the other end of the absorption capacitor is connected to the other end of the capacitor. The other end of the absorption capacitor is also used to connect to the negative terminal of the power supply.

4. The switching converter of claim 2 or 3, characterized in that: The absorption capacitor is a collection of multiple capacitors connected in series or in parallel, and the switching transistor is a collection of multiple switching transistors connected in series or in parallel.

5. The switching converter of claim 2 or 3, wherein: When the switching transistor is turned off, the drain voltage Vs of the power transistor Q2 satisfies the following relationship: Vin>Vs>0V, where Vin is the voltage of the power supply.

6. The switching converter of claim 5, wherein: When the switch tube is off, the drain voltage Vs of the power tube Q2 satisfies the following relationship: Vs=V out , wherein V out is the output voltage of the switch converter.

7. The switching converter of claim 2 or 3, wherein: The switching transistor is an NMOS transistor.

8. The control method of the switching converter according to claim 1, characterized in that: During one switching cycle, after the power transistor Q2 is turned off, the switching transistor is controlled to remain on until the inter-electrode voltage between the first and second terminals of the power transistor Q2 rises to a certain voltage value.

9. The control method of the switching converter according to claim 8, characterized in that: The voltage value is greater than 0 and less than the voltage of the power supply.

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