A low temperature coefficient oscillator circuit

Abstract

The embodiment of the specification provides a low-temperature drift coefficient oscillator circuit, comprising: a first charge-discharge capacitor CL and a second charge-discharge capacitor CR connected in parallel at a first input end of a latch circuit, current input ends of first and second current steering switches are connected to a current output end of a bias current generation circuit, the current input ends of the first and second current steering switches are connected to the first and second input ends of the latch circuit respectively, controlled input ends of the first and second current steering switches are connected to output ends of a second buffer and a first buffer respectively, input ends of the first and second buffers are connected to first and second output ends of the latch respectively, and output ends of the first and second buffers are used for outputting complementary first and second square wave signals CKB and CK. The on-chip oscillator is realized by using a standard CMOS process, and the production cost is reduced.

Description

TECHNICAL FIELD

[0001] The present specification relates to the field of analog integrated circuits, and in particular to a low temperature drift oscillator circuit. BACKGROUND

[0002] Oscillators are an essential module in many electronic systems, ranging from clock generation circuits in microprocessors to carrier synthesis in wireless communication systems. The most commonly used oscillator is the quartz crystal oscillator, which has the characteristics of stable performance, small process deviation and low temperature coefficient. Since the quartz crystal oscillator uses a quartz crystal, it cannot be compatible with standard CMOS technology, which will increase the production cost.

[0003] Therefore, it is necessary to provide a low temperature drift oscillator circuit for replacing the off-chip quartz crystal oscillator with an on-chip oscillator implemented by using standard CMOS technology to reduce production cost. SUMMARY

[0004] One of the embodiments of the present specification provides a low temperature drift oscillator circuit, comprising: a latch circuit, a bias current generation circuit, a first current steering switch, a second current steering switch, a first charging capacitor CL and a second charging capacitor CR, the first charging capacitor CL is connected in parallel to the first input terminal of the latch circuit, the second charging capacitor CR is connected in parallel to the second input terminal of the latch circuit, the current input terminals of the first current steering switch and the second current steering switch are connected to the current output terminal of the bias current generation circuit, the current input terminals of the first current steering switch and the second current steering switch are connected to the first input terminal and the second input terminal of the latch circuit respectively, the controlled input terminals of the first current steering switch and the second current steering switch are connected to the output terminals of the second buffer and the first buffer respectively, the input terminals of the first buffer and the second buffer are connected to the first output terminal and the second output terminal of the latch respectively, and the output terminals of the first buffer and the second buffer are also used to output the complementary first square wave signal CKB and the second square wave signal CK.

[0005] In some embodiments, the latch circuit comprises a first NMOS transistor M0, a second NMOS transistor M1, a first PMOS transistor M2, a second PMOS transistor M3, a first inverter I0 and a second inverter I1; a gate of the first NMOS transistor M0 and a gate of the second NMOS transistor M1 constitute two complementary input terminals INL and INR of the latch circuit, a drain of the first NMOS transistor M0 and a drain of the second NMOS transistor M1 constitute two complementary output terminals X0 and X1 of the latch circuit, a source of the first NMOS transistor M0 and a source of the second NMOS transistor M1 are both grounded; a source of the first PMOS transistor M2 and a source of the second PMOS transistor M3 are both connected to a power supply VDD, a gate of the second PMOS transistor M3 is connected to a drain X0 of the first PMOS transistor M2, a gate of the first PMOS transistor M2 is connected to a drain X1 of the second PMOS transistor M3, a drain of the first NMOS transistor M0 is electrically connected to the drain X0 of the first PMOS transistor M2, and a drain of the second NMOS transistor M1 is electrically connected to the drain X1 of the second PMOS transistor M3.

[0006] In some embodiments, the first current steering switch comprises a fourth PMOS transistor M7 and a fourth NMOS transistor M6, a source of the fourth PMOS transistor M7 is electrically connected to a current output terminal of the bias current generation circuit, a gate of the fourth PMOS transistor M7 and a gate of the fourth NMOS transistor M6 are both electrically connected to an output terminal of a second CMOS buffer I2, a drain of the fourth PMOS transistor M7 and a drain of the fourth NMOS transistor M6 are electrically connected, a node INL at which the drain of the fourth PMOS transistor M7 and the drain of the fourth NMOS transistor M6 are connected is electrically connected to a gate of the first NMOS transistor M0, one plate of the first charging capacitor CL is electrically connected to the node INL, and the other plate of the first charging capacitor CL is grounded.

[0007] In some embodiments, the second current steering switch comprises a third NMOS transistor M4 and a third PMOS transistor M5, a source of the third PMOS transistor M5 is electrically connected with a current output terminal of the bias current generating circuit, a gate of the third PMOS transistor M5 and a gate of the third NMOS transistor M4 are both electrically connected with an output terminal of the first CMOS buffer I3, a drain of the third PMOS transistor M5 is electrically connected with a drain of the third NMOS transistor M4, a junction INR of the drain of the third PMOS transistor M5 and the drain of the third NMOS transistor M4 is electrically connected with a gate of the second NMOS transistor M1, one plate of the second charging capacitor CR is electrically connected with the junction INR, and the other plate of the second charging capacitor CR is grounded.

[0008] In some embodiments, the bias current generating circuit comprises a fifth PMOS transistor M8, a sixth PMOS transistor M9, a fifth NMOS transistor M10, a first resistor R0, a current source i0 and an operational amplifier AMP, a gate of the fifth NMOS transistor M10 is connected with a drain of the fifth NMOS transistor M10, the drain of the fifth NMOS transistor M10 is electrically connected with the current source i0, a source of the fifth NMOS transistor M10 is grounded, a source of the fifth PMOS transistor M8 and a source of the sixth PMOS transistor M9 are both electrically connected with a power supply VDD, a drain of the sixth PMOS transistor M9 is grounded through the first resistor R0, an inverting terminal of the operational amplifier AMP is electrically connected with the drain of the fifth NMOS transistor M10, a non-inverting terminal of the operational amplifier AMP is electrically connected with the drain of the sixth PMOS transistor M9, and a drain of the fifth PMOS transistor M8 outputs a bias current i ref for charging the first charging capacitor CL or the second charging capacitor CR. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present specification will be further explained in the way of example embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limitative, in these embodiments, the same numbers represent the same structures, wherein:

[0010] Figure 1 is a circuit schematic diagram of a low temperature coefficient oscillator circuit according to some embodiments of the present specification;

[0011] Figure 2 is a schematic diagram of waveforms of three key junctions in an oscillator circuit according to some embodiments of the present specification;

[0012] Figure 3is a circuit schematic diagram of a latch circuit according to some embodiments of the present specification;

[0013] Figure 4 is a circuit schematic diagram of a current source according to some embodiments of the present specification;

[0014] Figure 5 is a circuit schematic diagram of a current source according to some embodiments of the present specification;

[0015] Figure 6 is a circuit schematic diagram of a latch circuit according to some embodiments of the present specification;

[0016] Figure 7 is a circuit schematic diagram of a low temperature coefficient oscillator circuit according to some embodiments of the present specification;

[0017] Figure 8 is a circuit schematic diagram of a latch circuit according to some embodiments of the present specification. DETAILED DESCRIPTION

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some examples or embodiments of the present specification, and for those skilled in the art, the present specification can also be applied to other similar scenarios without creative labor, unless it is obvious from the language environment or otherwise stated. The same reference numerals in the drawings represent the same structure or operation unless it is obvious from the language environment or otherwise stated.

[0019] It should be understood that the "system", "device", "unit" and / or "module" used herein is a method for distinguishing different components, elements, parts, sections or assemblies at different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions.

[0020] As shown in the specification and claims, unless the context clearly indicates otherwise, "one", "a", "an" and / or "the" do not refer to the singular, but can also include the plural. Generally speaking, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.

[0021] Flowcharts are used in this specification to illustrate the operations performed by the system according to embodiments of this specification. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0022] A low-temperature drift coefficient oscillator circuit may include a latch circuit, a bias current generating circuit, a first current-directed switch, a second current-directed switch, a first charging capacitor CL, and a second charging capacitor CR. The first charging capacitor CL is connected in parallel to the first input terminal of the latch circuit, and the second charging capacitor CR is connected in parallel to the second input terminal of the latch circuit. The current input terminals of both the first and second current-directed switches are connected to the current output terminal of the bias current generating circuit. The current input terminals of the first and second current-directed switches are respectively connected to the first and second input terminals of the latch circuit. The controlled input terminals of the first and second current-directed switches are respectively connected to the output terminals of the second and first buffers. The input terminals of the first and second buffers are respectively connected to the first and second output terminals of the latch. The output terminals of the first and second buffers are also used to output complementary first square wave signals CK and CKB.

[0023] Figure 1 This is a circuit diagram of a low-temperature drift coefficient oscillator circuit according to some embodiments of this specification.

[0024] like Figure 1 As shown, in some embodiments, the latch circuit includes a first NMOS transistor M0, a second NMOS transistor M1, a first PMOS transistor M2, a second PMOS transistor M3, a first inverter I0, and a second inverter I1. The gates of the first NMOS transistor M0 and the second NMOS transistor M1 form two complementary input terminals (i.e., input terminal INL and input terminal INR) of the latch circuit, and the drains of the first NMOS transistor M0 and the second NMOS transistor M1 form two complementary output terminals (i.e., output terminal X0 and output terminal X1) of the latch circuit. The sources of the first NMOS transistor M0 and the second NMOS transistor M1 are both grounded. The source of the first PMOS transistor M2 and the source of the second PMOS transistor M3 are both connected to the power supply VDD. The gate of the second PMOS transistor M3 is connected to the drain X0 of the first PMOS transistor M2. The gate of the first PMOS transistor M2 is connected to the drain X1 of the second PMOS transistor M3. The drain of the first NMOS transistor M0 is electrically connected to the drain X0 of the first PMOS transistor M2. The drain of the second NMOS transistor M1 is electrically connected to the drain X1 of the second PMOS transistor M3.

[0025] It can be appreciated that the latch circuit described in the present application is not limited to a certain specific form, such as Figure 6 indicated, in other embodiments, the circuit structure of the latch circuit can also be other circuit structures, such as Figure 1 indicated circuit structure. Figure 6

[0026] As shown in Figure 1 indicated, in some embodiments, a low temperature coefficient oscillator circuit can further include a first CMOS buffer I2 and a second CMOS buffer I3, an input end of the first CMOS buffer I2 is electrically connected with a drain X1 of the second PMOS transistor M3, an output end (i.e. outputting a first square wave signal CKB) of the first CMOS buffer I2 is electrically connected with the first current steering switch as a first output end, an input end of the second CMOS buffer I3 is electrically connected with a drain X0 of the first PMOS transistor M2, an output end (i.e. outputting a second square wave signal CK) of the second CMOS buffer I3 is electrically connected with the second current steering switch as a second output end.

[0027] As shown in Figure 1 indicated, the first current steering switch includes a fourth PMOS transistor M7 and a fourth NMOS transistor M6, a source of the fourth PMOS transistor M7 is electrically connected with a current output end of the bias current generating circuit, a gate of the fourth PMOS transistor M7 and a gate of the fourth NMOS transistor M6 are both electrically connected with the output end of the second CMOS buffer I2, a drain of the fourth PMOS transistor M7 is electrically connected with a drain of the fourth NMOS transistor M6, a junction INL of the drain of the fourth PMOS transistor M7 and the drain of the fourth NMOS transistor M6 is electrically connected with a gate of the first NMOS transistor M0, one of the plates of the first charging capacitor CL is electrically connected with the junction INL, and the other plate of the first charging capacitor CL is grounded.

[0028] As shown in Figure 1 indicated, the second current steering switch includes a third NMOS transistor M4 and a third PMOS transistor M5, a source of the third PMOS transistor M5 is electrically connected with the current output end of the bias current generating circuit, a gate of the third PMOS transistor M5 and a gate of the third NMOS transistor M4 are both electrically connected with the output end of the first CMOS buffer I3, a drain of the third PMOS transistor M5 is electrically connected with a drain of the third NMOS transistor M4, a junction INR of the drain of the third PMOS transistor M5 and the drain of the third NMOS transistor M4 is electrically connected with a gate of the second NMOS transistor M1, one of the plates of the second charging capacitor CR is electrically connected with the junction INR, and the other plate of the second charging capacitor CR is grounded.

[0029] ​It can be understood that, after the low-temperature drift coefficient oscillator circuit is powered on, assuming that the initial levels of the two input terminals INL and INR of the latch circuit are 0 and 1 respectively, then the levels of the two output ports X0 and X1 of the latch circuit are 1 and 0 respectively, and the levels of the corresponding nodes CK and CKB are 1 and 0 respectively, so that the fourth PMOS transistor M7 in the first current steering switch and the third NMOS transistor M4 in the second current steering switch are turned on, so that the node INR is kept at a level of 0, and the bias current i ref The fourth PMOS transistor M7 charges the first charging capacitor CL, and the voltage across the first charging capacitor CL linearly rises over time until the latch circuit changes state (that is, the level of X0 flips from 1 to 0, and the level of X1 flips from 0 to 1), and the voltage VT of the node INL at this moment is defined as the flip threshold voltage of the latch circuit, so i ref *t = C*VT, where C is the capacitance of the first charging capacitor CL, and t is the bias current i ref The time for charging the first charging capacitor CL.

[0030] Since the level of the two outputs X0 of the latch circuit flips from 1 to 0, and the level of X1 flips from 0 to 1, the level of the second square wave signal CK flips to 0, and the level of the first square wave signal CKB flips to 1, so the fourth NMOS transistor M6 in the first current steering switch and the third PMOS transistor M5 in the second current steering switch are turned on, thereby discharging the charge on the first charging capacitor CL, so that the voltage of the node INL drops rapidly to zero volts, and at the same time, the bias current i ref Again starts to charge the second charging capacitor CR through the third PMOS transistor M5, and the voltage across the second charging capacitor CR linearly rises over time until the latch circuit is triggered to change state again (that is, the level of X0 flips from 0 to 1, and the level of X1 flips from 1 to 0), and due to the symmetry of the latch circuit, the voltage of the node INR at this moment must also be VT, and similarly i ref *t = C*VT, where C is the capacitance of the second charging capacitor CR, and t is the bias current i ref The time for charging the second charging capacitor CR. The latch circuit switches states in this way, outputting complementary first and second square wave signals CKB and CK. Figure 2 The waveforms of the three key nodes in the oscillator circuit (i.e., the first square wave signal CK, the second square wave signal CKB, and the node INR) are given, and from the figure it can be seen that the period T of the first square wave signal CK output square wave signal is T = 2*t = 2*(C*VT) / i ref .

[0031] To obtain the flip threshold voltage VT of the latch circuit, the latch circuit can be simplified as Figure 3 the structure shown in FIG. 1 (where Cpar0 and Cparl are the parasitic capacitances at the output nodes X0 and Xl, respectively), and the input terminal INR is connected to the power supply voltage VDD, and the input terminal INL is connected to a test voltage source Vtest with an initial voltage of zero volt. After the power supply is turned on, the voltage at node X0 of the latch circuit is VDD, and the voltage at node Xl is zero volt. The value of the test voltage source Vtest is gradually increased, and the voltage at node X0 is observed. When the voltage at node X0 drops to VTP (VTP is the threshold voltage of the PMOS (i.e., the first NMOS transistor M0)), the corresponding value of the test voltage source Vtest is the required VT. The state in which the voltage at node X0 drops to VTP is the critical state of the flip of the latch circuit. At this time, the current flowing through the first PMOS transistor M2 (the first PMOS transistor M2 is in the linear region) is equal to the current flowing through the first NMOS transistor M0 (the first NMOS transistor M0 is in the saturation region). If the voltage at the node continues to drop, the second PMOS transistor M3 will be turned on, so that the second PMOS transistor M3 enters the fast flip. According to the I-V characteristics of the MOS transistor:

[0032]

[0033] where i P is the drain current of the first PMOS transistor M2, μ P is the mobility of holes in the first PMOS transistor M2, C ox is the gate capacitance per unit area of the first PMOS transistor M2, is the ratio of the channel width to the channel length of the first PMOS transistor M2, i n is the drain current of the first NMOS transistor M0, μ n is the mobility of holes in the first NMOS transistor M0, is the ratio of the channel width to the channel length of the first NMOS transistor M0, and VTN is the threshold voltage of the first NMOS transistor M0.

[0034] Neglecting the second-order effects of the MOS transistor, let i P = i n , and the VT can be obtained as follows:

[0035]

[0036] It can be understood that, assuming the bias current generation circuit is a constant current source, the first term on the right side of the above equation has a positive temperature coefficient, while the threshold voltage VTN or VTP has a negative temperature coefficient. The temperature coefficient of VT can be adjusted to approach zero by adjusting the size of the PMOS and NMOS in the latch circuit, and the period T of the square wave signal output by the oscillator is analyzed as T = 2 · t = 2 · (C · VT) / i ref If the capacitance C and the constant current source i ref are both temperature independent, a temperature independent square wave signal can be obtained, but there are two difficulties in implementation: first, it is difficult to implement a temperature independent current source; second, it is difficult to ensure that the temperature coefficient of VT always maintains around the desired value under process variation. Therefore, the present specification provides a low temperature drift coefficient oscillator circuit that can output a temperature independent square wave signal based on the output of the bias current generation circuit, which is a current proportional to temperature.

[0037] As Figure 1 shown, in some embodiments, the bias current generation circuit includes a fifth PMOS transistor M8, a sixth PMOS transistor M9, a fifth NMOS transistor M10, a first resistor R0, a current source i0, and an operational amplifier AMP. The gate of the fifth NMOS transistor M10 is connected to the drain of the fifth NMOS transistor M10, the drain of the fifth NMOS transistor M10 is electrically connected to the current source i0, the source of the fifth NMOS transistor M10 is grounded, the source of the fifth PMOS transistor M8 and the source of the sixth PMOS transistor M9 are both electrically connected to the power supply VDD, the drain of the sixth PMOS transistor M9 is grounded through the first resistor R0, the non-inverting terminal of the operational amplifier AMP is electrically connected to the drain of the fifth NMOS transistor M10, the inverting terminal of the operational amplifier AMP is electrically connected to the drain of the sixth PMOS transistor M9, and the drain of the fifth PMOS transistor M8 outputs a bias current iref for charging the first charging capacitor CL or the second charging capacitor CR.

[0038] In some embodiments, the current source i0 can be any relatively stable current source. The so-called relative stability refers to that the fluctuation range of the current source itself is within ±30%.

[0039] In some embodiments, the current source i0 includes a bandgap reference circuit. The structure of the bandgap reference circuit can be as Figure 4 shown. The bandgap reference circuit can be used to output a current i PTAT proportional to temperature. In some embodiments, the current source i0 can also include other circuit structures, for example, the circuit as Figure 5 shown.

[0040] It can be understood that when the fifth PMOS transistor M8 and the sixth PMOS transistor M9 have the same size, the current i flowing out of the drain of the fifth PMOS transistor M8 is D8 = VGS / R0, wherein VGS is the gate-source voltage of the fifth NMOS transistor M10. The gate voltage of the fifth NMOS transistor M10 can be obtained by the following formula:

[0041]

[0042] wherein, is the ratio of the channel width to the channel length of the fifth NMOS transistor M10.

[0043] then, i D8 is:

[0044]

[0045] with i D8 replaced by i ref in the period expression of the oscillator output square wave signal, and after rearrangement, we have:

[0046]

[0047] Generally, the temperature coefficient of the capacitor can be ignored, and the resistance can adopt a P-type polysilicon resistance with a very low temperature coefficient. As can be seen from the above period expression of the oscillator output square wave signal, as long as the first NMOS transistor M0 and the second NMOS transistor M1 in the latch circuit and the fifth NMOS transistor M10 in the bias current generation circuit are well matched, and the channel current of the fifth NMOS transistor M10 has a positive temperature coefficient, the oscillator can output a square wave signal independent of temperature. Since the process-related parameter VTN in the above period expression cancels out, and the weakly related terms under the square root also cancel out to some extent, the temperature coefficient of the oscillator output square wave period is not sensitive to the process.

[0048] It can be understood that a low-temperature drift coefficient oscillator circuit as shown in Figure 7 is also within the scope of protection, which is a dual circuit of the low-temperature drift coefficient oscillator circuit as shown in Figure 1 . The so-called dual circuit refers to replacing all PMOS in the original circuit with NMOS, replacing all NMOS in the original circuit with PMOS, replacing all NAND gates in the original circuit with NOR gates, replacing VSS in the original circuit with VDD, and replacing VDD in the original circuit with VSS. In some embodiments, the latch circuit of the low-temperature drift coefficient oscillator circuit as shown in Figure 7 may also have a circuit structure as shown in Figure 7 , or other circuit structures, for example, the circuit structure as shown in Figure 8 .

[0049] The foregoing detailed description has set forth various embodiments of the application via the use of specific terminology. As such, it is to be understood that whenever a particular embodiment is described, that embodiment is intended to serve as a representative example, and is not intended to limit the scope of the disclosure. As described, modifications, improvements and variations of the specific examples described herein can occur to those skilled in the art. Such modifications, improvements and variations are intended to be within the spirit and scope of the examples described herein, and are intended to be encompassed by the claims.

[0050] Also, the use of "a" or "an" to describe elements of the disclosure is not intended to be construed to mean there is only one of these elements. Similarly, the conjunctive use of "comprising" or "containing" to describe the elements of the disclosure is not intended to be construed to mean that these elements are the only elements required to implement the disclosure. The conjunctive use of "comprising" or "containing" is intended to mean that the elements listed after such conjunctive use are included and can be present in the disclosure, but not excluding the presence of other elements that are not specifically listed.

[0051] In addition, the order of presentation of the treatment elements and sequences, the use of numerical terms, or the use of other designations in the description of the disclosure is not intended to limit the order of the processes and methods of the disclosure. Although the above disclosure discusses some presently preferred embodiments of the application by way of various examples, it is to be understood that such disclosure of details is not intended to limit the scope of the claims to the sole disclosed embodiments, but rather that the claims are intended to cover all modifications and equivalent combinations of features thereof that are within the spirit and scope of the disclosure. For example, although the system components described above can be implemented by hardware devices, they can also be implemented by software solutions only, such as installing the described system on an existing server or mobile device.

[0052] Similarly, it is to be noted that the description of the examples of the disclosure in the foregoing description can sometimes use relative terms, such as "one embodiment", "one example", or "some examples" to describe various features. However, the use of these terms does not mean that the features described in one example are required in one or more other examples. In other words, although features are described in the context of certain examples, the features of each example can be combined with features of other examples, even though not explicitly described or shown in the course of the description. In addition, the use of the term "example" or "exemplary" is intended to indicate that the feature so described is an example of a particular feature. No inference should be drawn from the use of the term "example" or "exemplary" that a feature so described is preferred over other features described herein.

[0053] Each patent, patent application, patent publication, and other material cited in this specification is hereby incorporated by reference in its entirety herein for the teachings relevant to the sentence and / or paragraph in which the reference is presented. Document histories, to the extent not inconsistent with the pertinent U.S. patent application file history, are also incorporated by reference herein. To the extent that material incorporated by reference contradicts or contradicts any portion of this specification, including definition, the portion of the material incorporated by reference prevails. Note, however, that in the event of inconsistencies between any such material and the present specification, including definitions, the present specification, including definitions, will control.

[0054] Finally, it should be understood that the embodiments described herein are merely exemplary of the principles of the present description. Other embodiments can be devised without departing from the scope of the present description. Accordingly, the embodiments described herein are not intended to limit the scope of the present description, but rather are intended to be exemplary thereof.

Claims

1. A low temperature coefficient oscillator circuit, characterized by, The latch circuit, the bias current generating circuit, the first current steering switch, the second current steering switch, the first charging capacitor CL and the second charging capacitor CR, the first charging capacitor CL is connected in parallel to the first input terminal of the latch circuit, the second charging capacitor CR is connected in parallel to the second input terminal of the latch circuit, the current input terminals of the first current steering switch and the second current steering switch are connected to the current output terminal of the bias current generating circuit, the current input terminals of the first current steering switch and the second current steering switch are connected to the first input terminal and the second input terminal of the latch circuit respectively, the controlled input terminals of the first current steering switch and the second current steering switch are connected to the output terminals of the second buffer and the first buffer respectively, the input terminals of the first buffer and the second buffer are connected to the first output terminal and the second output terminal of the latch respectively, and the output terminals of the first buffer and the second buffer are used for outputting the complementary first square wave signal CKB and the second square wave signal CK. The latch circuit comprises a first NMOS transistor M0, a second NMOS transistor M1, a first PMOS transistor M2, a second PMOS transistor M3, a first inverter I0 and a second inverter I1. The gate of the first NMOS transistor M0 and the gate of the second NMOS transistor M1 constitute two complementary input terminals INL and INR of the latch circuit, the drain of the first NMOS transistor M0 and the drain of the second NMOS transistor M1 constitute two complementary output terminals X0 and X1 of the latch circuit, and the source of the first NMOS transistor M0 and the source of the second NMOS transistor M1 are grounded. The source of the first PMOS transistor M2 and the source of the second PMOS transistor M3 are connected to a power supply VDD, the gate of the second PMOS transistor M3 is connected to the drain X0 of the first PMOS transistor M2, the gate of the first PMOS transistor M2 is connected to the drain X1 of the second PMOS transistor M3, the drain of the first NMOS transistor M0 is electrically connected to the drain X0 of the first PMOS transistor M2, and the drain of the second NMOS transistor M1 is electrically connected to the drain X1 of the second PMOS transistor M3. ​ 2. The low temperature coefficient oscillator circuit of claim 1, wherein, The first current steering switch comprises a fourth PMOS transistor M7 and a fourth NMOS transistor M6, the source of the fourth PMOS transistor M7 is electrically connected with the current output end of the bias current generating circuit, the gate of the fourth PMOS transistor M7 and the gate of the fourth NMOS transistor M6 are both electrically connected with the output end of the second CMOS buffer I2, the drain of the fourth PMOS transistor M7 is electrically connected with the drain of the fourth NMOS transistor M6, the joint point INL of the drain of the fourth PMOS transistor M7 and the drain of the fourth NMOS transistor M6 is electrically connected with the gate of the first NMOS transistor M0, one of the plates of the first charging capacitor CL is electrically connected with the joint point INL, and the other plate of the first charging capacitor CL is grounded.

3. The low temperature coefficient oscillator circuit of claim 1, wherein, The second current steering switch comprises a third NMOS transistor M4 and a third PMOS transistor M5, the source of the third PMOS transistor M5 is electrically connected with the current output end of the bias current generating circuit, the gate of the third PMOS transistor M5 and the gate of the third NMOS transistor M4 are both electrically connected with the output end of the first CMOS buffer I3, the drain of the third PMOS transistor M5 is electrically connected with the drain of the third NMOS transistor M4, the joint point INR of the drain of the third PMOS transistor M5 and the drain of the third NMOS transistor M4 is electrically connected with the gate of the second NMOS transistor M1, one of the plates of the second charging capacitor CR is electrically connected with the joint point INR, and the other plate of the second charging capacitor CR is grounded.

4. A low temperature coefficient oscillator circuit as claimed in any one of claims 1 to 3, characterized in that The bias current generating circuit comprises a fifth PMOS transistor M8, a sixth PMOS transistor M9, a fifth NMOS transistor M10, a first resistor R0, a current source i0 and an operational amplifier AMP. The gate of the fifth NMOS transistor M10 is connected with the drain of the fifth NMOS transistor M10, the drain of the fifth NMOS transistor M10 is electrically connected with the current source i0, the source of the fifth NMOS transistor M10 is grounded, the source of the fifth PMOS transistor M8 and the source of the sixth PMOS transistor M9 are electrically connected with the power supply VDD, the drain of the sixth PMOS transistor M9 is grounded through the first resistor R0, the inverting input terminal of the operational amplifier AMP is electrically connected with the drain of the fifth NMOS transistor M10, the non-inverting input terminal of the operational amplifier AMP is electrically connected with the drain of the sixth PMOS transistor M9, the drain of the fifth PMOS transistor M8 outputs the bias current i ref for charging the first charging capacitor CL or the second charging capacitor CR.

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