Image sensing device

Abstract

An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supply circuit coupled between the output terminal and the high voltage terminal and configured to provide, based on the control voltage, a precharge current to the output terminal that is configured to be adaptively adjusted according to the voltage level of the pixel signal.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to semiconductor design technologies, and more particularly, to image sensing devices. Background Art

[0002] An image sensing device is a device that uses the light-responsive characteristics of a semiconductor to capture an image. Image sensing devices are generally classified into charge-coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. Recently, CMOS image sensing devices have been widely used because they allow both analog control circuits and digital control circuits to be directly implemented on a single integrated circuit (IC).

[0003] The paper “A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps” discloses a reference-shared in-pixel differential common-source amplifier (RSDA) (hereinafter referred to as “in-pixel amplifier”). The in-pixel amplifier can achieve a high conversion gain when reading out pixel signals, but there is a concern that such a design may reduce the readout speed. Summary of the Invention

[0004] Various embodiments of the present disclosure relate to an image sensing device capable of reducing the load on a readout line of a pixel signal in a structure where an in-pixel amplifier is connected to the readout line.

[0005] In addition, various embodiments of the present disclosure relate to an image sensing device and an operation method of the image sensing device capable of minimizing the stabilization time of a pixel signal output through a readout line of the pixel signal in a structure where an in-pixel amplifier is connected to the readout line.

[0006] According to an embodiment, an image sensing device may include: a control circuit connected between an output terminal of a pixel signal and a high voltage terminal and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supply circuit connected between the output terminal and the high voltage terminal and configured to provide a precharge current configured to be adaptively adjusted according to the voltage level of the pixel signal to the output terminal based on the control voltage.

[0007] According to an embodiment, an image sensing device may include: a reference circuit coupled between a high voltage terminal and a control node and configured to provide a reference voltage to the control node based on a reference control signal; a sensing circuit coupled between the control node and an output terminal of a pixel signal and configured to sense a slope of the pixel signal based on the reference control signal and a boost control signal, wherein the sensing circuit is configured to provide a control voltage to the control node according to the sensed slope; a subtraction circuit coupled between the high voltage terminal and a low voltage terminal and configured to generate a subtraction current corresponding to the reference voltage; and a current supply circuit coupled between the output terminal and the high voltage terminal and configured to provide a precharge current applied with the subtraction current to the output terminal based on the control voltage and the subtraction current.

[0008] According to an embodiment, an image sensing device may include: a reference pixel; a target pixel; an amplifier commonly coupled to the reference pixel and the target pixel and configured to output a pixel signal of the target pixel through an output terminal during a readout period of a target row time; and a precharger configured to provide a precharge current configured to be adaptively adjusted according to a voltage level of the pixel signal to the output terminal during an initial time of the readout period.

[0009] According to an embodiment, an image sensing device may include: a reference pixel; a target pixel including a floating diffusion node; and a reset transistor element configured to reset a potential of the floating diffusion node during a reset period of a target row time; an amplifier commonly coupled to the reference pixel and the target pixel and configured to output a target pixel signal of the target pixel through an output terminal during a readout period of the target row time; and a switch circuit configured to decouple the reset transistor element from the output terminal during at least the readout period.

[0010] The switch circuit may be configured to couple the reset transistor element to the output terminal during at least the reset period.

[0011] The switch circuit may include a first switch and a second switch connected in series between the output terminal and the reset transistor element, the first switch may be configured to be turned off based on a line decoupling signal during at least the readout period of the target row time, and the second switch may be configured to be short-circuited based on a row change signal during the target row time.

[0012] The reference pixel may include a pixel disposed in a row adjacent to a row in which the target pixel is disposed.

[0013] According to an embodiment, an image sensing device may include: a plurality of pixels, each including a floating diffusion node and a reset transistor element configured to reset the potential of the floating diffusion node; an amplifier configured to sequentially output a plurality of pixel signals of the plurality of pixels through an output terminal; and a switching circuit configured to connect a first pixel among the plurality of pixels to the amplifier as a reference pixel and connect a second pixel among the plurality of pixels to the amplifier as a target pixel for each target row time, wherein the switching circuit includes a first switch configured to disconnect the output terminal from the reset transistor element included in the target pixel during other row times of the target row time except for the initial row time.

[0014] The first switch may be configured to connect the reset transistor element to the output terminal during the initial row time.

[0015] The reset transistor element may be configured to reset the potential of the floating diffusion node during a reset period of the target row time, and the initial row time includes the reset period.

[0016] The target pixel may be configured to generate a target pixel signal during a readout period of the target row time, and the other row times include the readout period.

[0017] The switching circuit may further include a second switch serially connected to the first switch between the output terminal and the reset transistor element. The first switch may be configured to disconnect based on a line disconnection signal during other row times of the target row time, and the second switch may be configured to be short-circuited based on a row change signal during the target row time.

[0018] The first pixel may be disposed in a first row adjacent to a second row in which the second pixel is disposed.

[0019] According to an embodiment, an image sensing device may include: a reference pixel; a target pixel that is electrically disconnected from an output terminal of a target pixel signal during a transfer time, charges accumulated in a photodiode are transferred to a floating diffusion node during the transfer time, and the target pixel is configured to output a target pixel signal through the output terminal during a readout period after the transfer time; an amplifier connected to the reference pixel and the target pixel and configured to amplify the target pixel signal during the readout period; and a disabling circuit configured to disable the amplifier during the transfer time.

[0020] The disabling circuit may be connected between a high-voltage terminal and the amplifier and may be configured to electrically disconnect the high-voltage terminal from the amplifier during the transfer time.

[0021] The image sensing device may further include a compensation circuit configured to supply a compensation current to a common node to which a current source included in an amplifier is coupled during a transfer time.

[0022] The compensation circuit may include: a first switch coupled between a high voltage terminal and a coupling node and configured to operate based on a first control signal having a fixed voltage level; and a second switch coupled between the coupling node and the common node and configured to operate based on a second control signal activated during the transfer time.

[0023] The image sensing device may further include an interrupt circuit configured to electrically disconnect the common node from a current source included in an amplifier during the transfer time.

[0024] The reference pixel may include a pixel disposed in a row adjacent to a row in which a target pixel is disposed.

[0025] According to an embodiment, the image sensing device may include: a plurality of pixels; an amplifier configured to sequentially amplify a plurality of pixel signals output from the plurality of pixels; a switch circuit configured to couple a first pixel among the plurality of pixels to the amplifier as a reference pixel and a second pixel among the plurality of pixels to the amplifier as a target pixel during respective row times; and a disabling circuit configured to disable the amplifier during a part of the respective row time.

[0026] The part of the respective row time may include a transfer time for transferring charge accumulated in a photodiode of the target pixel to a floating diffusion node of the target pixel.

[0027] The disabling circuit may be coupled between a high voltage terminal and the amplifier and configured to electrically disconnect the high voltage terminal from the amplifier during the part of the respective row time.

[0028] The image sensing device may further include a compensation circuit configured to supply a compensation current to a common node to which a current source included in an amplifier is coupled during the part of the respective row time.

[0029] The compensation circuit may include: a first switch coupled between a high voltage terminal and a coupling node and configured to operate based on a first control signal having a fixed voltage level; and a second switch coupled between the coupling node and the common node and configured to operate based on a second control signal activated during a part of the respective row time.

[0030] The image sensing device may further include an interrupt circuit configured to electrically disconnect the common node from a current source included in an amplifier during the part of the respective row time.

[0031] The first pixel may be set in a first row adjacent to a second row in which the second pixel is set.

[0032] According to an embodiment, an operation method of an image sensing device may include the steps of: maintaining a voltage level of an output terminal of a target pixel at a reset level of the target pixel during a transfer time, and transferring charges accumulated in a photodiode to a floating diffusion node during the transfer time; and amplifying the voltage level of the output terminal from the reset level to a target level corresponding to the target pixel during a readout period after the transfer time.

[0033] During the readout period, an amplifier connected to the output terminal may be configured to be disabled, and the target pixel may be configured to be electrically disconnected from the output terminal.

[0034] During the readout period, a current generated from a current source included in the amplifier may be configured to be compensated.

[0035] During the readout period, the current source included in the amplifier may be configured to be electrically disconnected from a common node to which the target pixel and a reference pixel are connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a block diagram illustrating an image sensing device according to a first embodiment.

[0037] Figure 2 illustrates Figure 1 an example of a circuit diagram of a pixel array and an amplification region shown.

[0038] Figure 3 illustrates Figure 2 an equivalent circuit diagram of the (n-1)th pixel, the nth pixel, an in-pixel amplifier, and third and fifth switches shown.

[0039] Figure 4 illustrates Figure 1 a timing diagram of an operation of the image sensing device shown.

[0040] Figure 5 is a block diagram illustrating an image sensing device according to a second embodiment.

[0041] Figure 6 illustrates Figure 5 an example of a circuit diagram of a pixel array and an amplification region shown.

[0042] Figure 7 illustrates Figure 6 an equivalent circuit diagram of the (n-1)th pixel, the nth pixel, an in-pixel amplifier, a disabling circuit, and a compensation circuit shown.

[0043] Figure 8Is an illustration Figure 5 A circuit diagram of another example of the pixel array and the enlarged area shown.

[0044] Figure 9 Is an illustration Figure 8 An equivalent circuit diagram of the (n-1)th pixel, the nth pixel, the in-pixel amplifier, the disable circuit, and the interrupt circuit shown.

[0045] Figure 10 Is an illustration Figure 5 A timing diagram of an example of the operation of the image sensing device shown.

[0046] Figure 11 Is an illustration Figure 5 A timing diagram of another example of the operation of the image sensing device shown.

[0047] Figure 12 Is a block diagram of an image sensing device according to the third embodiment.

[0048] Figure 13 Is an illustration Figure 12 A circuit diagram of an example of the pixel array and the enlarged area shown.

[0049] Figure 14 Is an illustration Figure 13 An equivalent circuit diagram of the (n-1)th pixel, the nth pixel, the in-pixel amplifier, and the pre-charger shown.

[0050] Figure 15 Is an illustration Figure 13 And Figure 14 A circuit diagram of an example of the pre-charger shown.

[0051] Figure 16 Is an illustration Figure 13 And Figure 14 A circuit diagram of another example of the pre-charger shown.

[0052] Figure 17 Is an illustration Figure 12 A timing diagram of the operation of the image sensing device shown.

[0053] Figure 18 Is another illustration Figure 17 A timing diagram of the operation of the image sensing device shown. Detailed implementation

[0054] Each embodiment is described below with reference to the drawings in order to describe the present disclosure in detail so that those of ordinary skill in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0055] It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element can be directly connected to or coupled to the other element, or electrically connected to or coupled to the other element with one or more elements interposed therebetween. Additionally, it should also be understood that unless otherwise stated, when used in this specification, the terms "comprising", "including", "having", and "containing" do not exclude the presence of one or more other elements, but may further include or have one or more other elements. Throughout the description of the specification, some components are described in the singular form, but the present disclosure is not limited thereto, and it will be understood that these components can be formed in the plural form.

[0056] Figure 1 is a block diagram illustrating an image sensing device 100 according to a first embodiment.

[0057] Referring to Figure 1 , the image sensing device 100 may include a timing controller 110, a row decoder 120, a pixel array 130, an amplification region 140, a signal conversion region 150, and a column decoder 160.

[0058] The timing controller 110 may control the overall operation of the image sensing device 100. The timing controller 110 is also referred to as a timing generator.

[0059] The row decoder 120 may control the pixel array 130 for each row. For example, the row decoder 120 may generate a first row control signal for controlling the pixels arranged in the first row of the pixel array 130, and generate a y-th row control signal for controlling the pixels arranged in the y-th row of the pixel array 130. Herein, "y" is a natural number greater than 2.

[0060] The pixel array 130 may include pixels arranged at the intersections of a plurality of rows and a plurality of columns. The pixels may generate pixel signals for each row under the control of the row decoder 120.

[0061] The amplification region 140 may amplify the gain of the pixel signals. For example, the amplification region 140 may couple a random first pixel in the pixels as a target pixel, couple a random second pixel in the pixels as a reference pixel, and amplify the gain of the pixel signal read out from the target pixel. The amplification region 140 may include a plurality of in-pixel amplifiers and a plurality of switch circuits corresponding to the plurality of columns of the pixel array 130 (refer to Figure 2 and Figure 3 ).

[0062] The signal conversion region 150 may convert the analog-type pixel signals into digital-type signals. For example, the signal conversion region 150 may include a plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of the pixel array 130.

[0063] The column decoder 160 may control each column of the signal conversion regions 150. For example, the column decoder 160 may control the plurality of ADCs in sequence.

[0064] Figure 2 is an illustration Figure 1 A circuit diagram showing an example of the pixel array 130 and the amplification region 140 shown. For ease of description, in Figure 2 A circuit diagram corresponding to a part of the pixel array 130 and a part of the amplification region 140 is illustrated. This part of the pixel array 130 may include pixels corresponding to any one of the plurality of columns, and this part of the amplification region 140 may include a pixel amplifier 141 and a switch circuit 143 corresponding to that any one column.

[0065] The pixel array 130 may include pixels arranged in a column direction. Hereinafter, the pixel PXn arranged in the nth row among the pixels is referred to as the nth pixel, and the pixel PXn-1 arranged in the (n-1)th row among the pixels is referred to as the (n-1)th pixel. In this article, "n" is a natural number greater than 2. When the nth pixel PXn is a target pixel, the (n-1)th pixel PXn-1 may be a reference pixel. In other words, the target pixel and the reference pixel may be normal pixels arranged adjacent to each other in the column direction.

[0066] The nth pixel PXn may include an nth photodiode PDn, an nth transfer element TTn, an nth floating diffusion node FDn, an nth reset gate-controlled transistor element RTn (hereinafter referred to as a reset transistor element), an nth driving element DTn, and an nth selection element STn.

[0067] The nth photodiode PDn may be connected between a low voltage terminal (for example, a ground voltage terminal) and the nth transfer element TTn. For example, the nth photodiode PDn may generate charge corresponding to incident light during the nth integration time.

[0068] The nth transfer element TTn may be connected between the nth photodiode PDn and the nth floating diffusion node FDn. The nth transfer element TTn may selectively connect the nth photodiode PDn to the nth floating diffusion node FDn based on the nth transfer control signal TXn. For example, the nth transfer element TTn may transfer the charge of the nth photodiode PDn to the nth floating diffusion node FDn during the nth transfer time Cn of the nth row time nth_RT.

[0069] The nth floating diffusion node FDn may be connected to an nth capacitor CCn. The nth capacitor CCn may store the charge generated by the nth photodiode PDn. For example, the nth capacitor CCn may be a parasitic capacitor.

[0070] The n-th reset transistor element RTn can be connected between the fifth line L4 and the n-th floating diffusion node FDn. The n-th reset transistor element RTn can selectively connect the fifth line L4 to the n-th floating diffusion node FDn based on the n-th reset control signal Rxn. For example, the n-th reset transistor element RTn can electrically connect the fifth line L4 to the n-th floating diffusion node FDn during the n-th reset time (i.e., reset period) An of the n-th row time nth_RT. During the reset time An, the voltage level at the floating diffusion node FDn is returned (reset) to a reference level so that a subsequent charge transfer from the n-th photodiode PDn to the n-th floating diffusion node FDn during the subsequent n-th transfer time Cn can be measured with respect to the reference level.

[0071] The n-th driving element DTn can be connected between the first line L0 and the n-th selection element STn. The n-th driving element DTn can generate an n-th pixel signal corresponding to the voltage loaded on the n-th floating diffusion node FDn.

[0072] The n-th selection element STn can be connected between the n-th driving element DTn and the third line L2. The n-th selection element STn can output the n-th pixel signal to the third line L2 based on the n-th selection control signal SXn. For example, the n-th selection element STn can output the n-th reset signal as the n-th pixel signal during the n-th reset readout time (i.e., reset readout period) Bn of the n-th row time nth_RT, and output the n-th data signal as the n-th pixel signal during the n-th data readout time (i.e., data readout period) Dn of the n-th row time nth_RT.

[0073] The n-th transfer control signal TXn, the n-th reset control signal RXn, and the n-th selection control signal SXn can be the n-th row control signals generated by the row decoder 120.

[0074] The (n - 1)-th pixel PXn-1 can include the (n - 1)-th photodiode PDn-1, the (n - 1)-th transfer element TTn-1, the (n - 1)-th floating diffusion node FDn-1, the (n - 1)-th reset transistor element RTn-1, the (n - 1)-th driving element DTn-1, and the (n - 1)-th selection element STn-1.

[0075] The (n - 1)-th photodiode PDn-1 can be connected between a low voltage terminal (e.g., a ground voltage terminal) and the (n - 1)-th transfer element TTn-1. For example, the (n - 1)-th photodiode PDn-1 can generate charge corresponding to incident light during the (n - 1)-th integration time.

[0076] The (n - 1)th transfer element TTn-1 can be connected between the (n - 1)th photodiode PD-1 and the (n - 1)th floating diffusion node FDn-1. The (n - 1)th transfer element TTn-1 can selectively connect the (n - 1)th photodiode PDn-1 to the (n - 1)th floating diffusion node FDn-1 based on the (n - 1)th transfer control signal TXn-1. For example, the (n - 1)th transfer element TTn-1 can transfer the charge of the (n - 1)th photodiode PDn-1 to the (n - 1)th floating diffusion node FDn-1 during the (n - 1)th transfer time of the (n - 1)th row time (n - 1)th_RT.

[0077] The (n - 1)th floating diffusion node FDn-1 can be connected to the (n - 1)th capacitor CCn-1. The (n - 1)th capacitor CCn-1 can store the charge generated by the (n - 1)th photodiode PDn-1. For example, the (n - 1)th capacitor CCn-1 can be a parasitic capacitor.

[0078] The (n - 1)th reset transistor element RTn-1 can be connected between the fourth line L3 and the (n - 1)th floating diffusion node FDn-1. The (n - 1)th reset transistor element RTn-1 can selectively connect the fourth line L3 to the (n - 1)th floating diffusion node FDn-1 based on the (n - 1)th reset control signal RXn-1. For example, the (n - 1)th reset transistor element RTn-1 can electrically connect the fourth line L3 to the (n - 1)th floating diffusion node FDn-1 during the (n - 1)th reset time of the (n - 1)th row time (n - 1)th_RT. Additionally, the (n - 1)th reset transistor element RTn-1 can electrically connect the fourth line L3 to the (n - 1)th floating diffusion node FDn-1 during the nth reset time An of the nth row time nth_RT.

[0079] The (n - 1)th driving element DTn-1 can be connected between the first line L0 and the (n - 1)th selection element STn-1. The (n - 1)th driving element DTn-1 can generate the (n - 1)th pixel signal corresponding to the voltage loaded on the (n - 1)th floating diffusion node FDn-1.

[0080] The (n - 1)-th selection element STn-1 can be coupled between the (n - 1)-th driving element DTn-1 and the second line L1. The (n - 1)-th selection element STn-1 can output the (n - 1)-th pixel signal to the second line L1 based on the (n - 1)-th selection control signal SXn-1. For example, the (n - 1)-th selection element STn-1 can output the (n - 1)-th reset signal as the (n - 1)-th pixel signal during the (n - 1)-th reset readout time of the (n - 1)-th row time (n - 1)th_RT, and output the (n - 1)-th data signal as the (n - 1)-th pixel signal during the (n - 1)-th data readout time of the (n - 1)-th row time (n - 1)th_RT. Additionally, the (n - 1)-th selection element STn-1 can electrically couple the (n - 1)-th driving element DTn-1 to the second line L1 during the n-th row time nth_RT.

[0081] The (n - 1)-th transfer control signal TXn-1, the (n - 1)-th reset control signal RXn-1, and the (n - 1)-th selection control signal SXn-1 can be the (n - 1)-th row control signals generated by the row decoder 120.

[0082] The amplification region 140 can include an in-pixel amplifier 141 and a switch circuit 143.

[0083] The in-pixel amplifier 141 can sequentially output the (n - 1)-th pixel signal and the n-th pixel signal. For example, the in-pixel amplifier 141 can amplify the gain of the (n - 1)-th pixel signal during the (n - 1)-th row time (n - 1)th_RT, and amplify the gain of the n-th pixel signal during the n-th row time nth_RT. Since the in-pixel amplifier 141 corresponds to the reference-shared in-pixel differential common-source amplifier (RSDA) disclosed in the paper “A 0.50ermsNoise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-PixelDifferential Amplifier at 8.3Mpixel 35fps”, its detailed description is omitted.

[0084] The switch circuit 143 can include a first switch S0 to a tenth switch S9. The first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 can be controlled (closed or opened) based on a row change signal RC during a target row time (such as the n-th row time nth_RT), and the fifth switch S4 and the sixth switch S5 can be controlled based on a line decoupling signal LC. The row change signal RC and the line decoupling signal LC can be generated by Figure 1The timing controller 110 shown generates. Since the first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 respectively correspond to the switches shown in the paper "A0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-PixelDifferential Amplifier at 8.3Mpixel 35fps", their detailed descriptions are omitted. However, the first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 are illustrated according to the RSDA mode disclosed in the paper. Figure 5 .8.2 The switches shown correspond, so their detailed descriptions are omitted. However, the first switch S0 to the fourth switch S3 and the seventh switch S6 to the tenth switch S9 are illustrated according to the RSDA mode disclosed in the paper.

[0085] The fifth switch S4 can be connected between the third switch S2 and the third line L2. For example, the fifth switch S4 can electrically connect the third switch S2 to the third line L2 during the nth reset time An of the nth row time nth_RT, and disconnect the third switch S2 from the third line L2 during the other row times Bn, Cn, and Dn of the nth row time nth_RT.

[0086] The sixth switch S5 can be connected between the fourth switch S3 and the second line L1. For example, the sixth switch S5 can electrically connect the fourth switch S3 to the second line L1 during the (n - 1)th reset time of the (n - 1)th row time (n - 1)th_RT, and disconnect the fourth switch S3 from the second line L1 during the other row times of the (n - 1)th row time (n - 1)th_RT.

[0087] Figure 3 is an illustration Figure 2 The equivalent circuit diagram of the (n - 1)th pixel PXn-1, the nth pixel PXn, the in-pixel amplifier 141, and the third switch S2 and the fifth switch S4 shown. Figure 3 Illustrates the case where the nth pixel PXn is connected to the output terminal VOUT of the in-pixel amplifier 141.

[0088] Refer to Figure 3, although the third switch S2 may be shorted during the nth row time nth_RT, the fifth switch S4 may be shorted during the initial row time of the nth row time nth_RT, the initial row time including the nth reset time An, and the fifth switch S4 may be turned off during other row times of the nth row time nth_RT, the other row times including some or all of the nth reset read time Bn, the nth transfer time Cn, and the nth data read time Dn. During other row times, only the third line L2 may be connected to the output terminal VOUT of the in-pixel amplifier 141. Therefore, during other row times, among the load caused by the first parasitic capacitor PC1 of the third line L2 and the load caused by the second parasitic capacitor PC2 of the fifth line L4, since the fifth switch S4 is turned off, only the load caused by the first parasitic capacitor PC1 of the third line L2 may be reflected to the output terminal VOUT of the in-pixel amplifier 141. In other words, during other row times, the output terminal VOUT of the in-pixel amplifier 141 is not affected by the load caused by the second parasitic capacitor PC2 of the fifth line L4. Therefore, the stabilization time of the pixel signal of the nth pixel PXn read out through the output terminal VOUT may be reduced, and thus the readout speed of the pixel signal may be increased.

[0089] Hereinafter, with reference to Figure 4 the operation of the image sensing device 100 according to the first embodiment having the above configuration will be described.

[0090] Figure 4 is an illustration Figure 1 a timing diagram showing the operation of the image sensing device 100 shown. The case where the nth pixel PXn is the target pixel will be representatively described below.

[0091] With reference to Figure 4 , during the nth row time nth_RT, the (n - 1)th pixel PXn - 1 may be connected to the in-pixel amplifier 141 as a reference pixel through the switch circuit 143, and the nth pixel PXn may be connected to the in-pixel amplifier 141 as a target pixel through the switch circuit 143. During the nth row time nth_RT, the (n - 1)th selection element STn - 1 may be turned on based on the (n - 1)th selection control signal SXn - 1, and the nth selection element STn may be turned on based on the nth selection control signal SXn.

[0092] During the nth initial row time (i.e., the nth reset time An) of the nth row time nth_RT, the (n - 1)th reset transistor element RTn-1 can be turned on based on the (n - 1)th reset control signal RXn-1, and the nth reset transistor element RTn can be turned on based on the nth reset control signal RXn. Additionally, during the nth initial row time (i.e., the nth reset time An), the fifth switch S4 included in the switch circuit 143 can be short-circuited based on the line disconnection signal LC. Thus, a negative feedback loop can be formed between the nth floating diffusion node FDn and the output terminal VOUT, and an offset can be stored in the nth floating diffusion node FDn. The offset can refer to the mismatch between the (n - 1)th pixel PXn-1 and the nth pixel PXn. As a reference, the offset can be canceled through a correlated double sampling (CDS) operation.

[0093] During other row times of the nth row time nth_RT (i.e., the nth reset read time Bn, the nth transfer time Cn, and the nth data read time Dn), the fifth switch S4 can be turned off based on the line disconnection signal LC. In this case, the line disconnection signal LC can transition from a high logic level to a low logic level during an initial period of the nth reset read time Bn. The turned-off fifth switch S4 minimizes non-ideal effects of charges that are inadvertently injected into the nth floating diffusion node FDn, for example, according to switch operations.

[0094] During other row times, since the fifth switch S4 is turned off during other times, the output terminal VOUT of the in-pixel amplifier 141 is not affected by the load caused by the second parasitic capacitor PC2 of the fifth line L4 among the load caused by the first parasitic capacitor PC1 of the third line L2 and the load caused by the second parasitic capacitor PC2 of the fifth line L4. In particular, during the nth data read time Dn, since the reset transistor element RTn is disconnected from the output terminal VOUT when the fifth switch S4 of the switch circuit 143 is turned off, the output terminal VOUT of the in-pixel amplifier 141 is not affected by the load caused by the second parasitic capacitor PC2 of the fifth line L4.

[0095] Therefore, the stabilization time of the pixel signal of the nth pixel PXn read out through the output terminal VOUT can be reduced, and thus the readout speed of the pixel signal can be increased.

[0096] According to the first embodiment, there is an advantage of minimizing the load reflected to the output terminal during a period (the period at least includes the data read time) of reading the pixel signal.

[0097] Figure 5 FIG. is a block diagram illustrating an image sensing device 200 according to a second embodiment.

[0098] Reference Figure 5 , the image sensing device 200 may include a timing controller 210, a row decoder 220, a pixel array 230, an amplification region 240, a signal conversion region 250, and a column decoder 260.

[0099] The timing controller 210 may control the overall operation of the image sensing device 200. The timing controller 210 is also referred to as a timing generator.

[0100] The row decoder 220 may control the pixel array 230 for each row. For example, the row decoder 220 may generate a first row control signal for controlling the pixels arranged in the first row of the pixel array 230, and generate a y-th row control signal for controlling the pixels arranged in the y-th row of the pixel array 230. Herein, "y" is a natural number greater than 2.

[0101] The pixel array 230 may include pixels arranged at the intersections of a plurality of rows and a plurality of columns. The pixels may generate pixel signals for each row under the control of the row decoder 220.

[0102] The amplification region 240 may amplify the gain of the pixel signal. For example, the amplification region 240 may access a random first pixel in the pixels as a target pixel, access a random second pixel in the pixels as a reference pixel, and amplify the gain of the pixel signal read out from the target pixel. The amplification region 240 may include a plurality of in-pixel amplifiers and a plurality of switch circuits corresponding to the plurality of columns of the pixel array 230 (reference Figure 7 or Figure 9 ).

[0103] The signal conversion region 250 may convert an analog-type pixel signal into a digital-type signal. For example, the signal conversion region 250 may include a plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of the pixel array 230.

[0104] The column decoder 260 may control the signal conversion region 250 for each column. For example, the column decoder 260 may sequentially control the plurality of ADCs.

[0105] Figure 6 is an illustration Figure 5 The circuit diagram of an example of the pixel array 230 and the amplification region 240 shown. For ease of description, in Figure 6 the circuit diagram corresponding to a part of the pixel array 230 and a part of the amplification region 240 is shown. This part of the pixel array 230 may include pixels corresponding to any one of the plurality of columns, and this part of the amplification region 240 may include an in-pixel amplifier 241, a disabling circuit 245, a compensation circuit 247, and a switch circuit 243 corresponding to this any one column.

[0106] The pixel array 230 may include pixels arranged in a column direction. Hereinafter, among the pixels, the pixel PXn arranged in the n-th row is referred to as the n-th pixel, and the pixel PXn-1 arranged in the (n-1)-th row among the pixels is referred to as the (n-1)-th pixel. In this document, "n" is a natural number greater than 2. When the n-th pixel PXn is a target pixel, the (n-1)-th pixel PXn-1 may be a reference pixel. In other words, the target pixel and the reference pixel may be normal pixels arranged adjacent to each other in the column direction.

[0107] The n-th pixel PXn may include an n-th photodiode PDn, an n-th transfer element TTn, an n-th floating diffusion node FDn, an n-th reset transistor element RTn, an n-th driving element DTn, and an n-th selection element STn.

[0108] The n-th photodiode PDn may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the n-th transfer element TTn. For example, the n-th photodiode PDn may generate charges corresponding to incident light during the n-th integration time.

[0109] The n-th transfer element TTn may be coupled between the n-th photodiode PDn and the n-th floating diffusion node FDn. The n-th transfer element TTn may selectively couple the n-th photodiode PDn to the n-th floating diffusion node FDn based on the n-th transfer control signal TXn. For example, the n-th transfer element TTn may transfer the charges of the n-th photodiode PDn to the n-th floating diffusion node FDn during the n-th transfer time Cn of the n-th row time nth_RT.

[0110] The n-th floating diffusion node FDn may be coupled to an n-th capacitor CCn. The n-th capacitor CCn may store the charges generated by the n-th photodiode PDn. For example, the n-th capacitor CCn may be a parasitic capacitor.

[0111] The n-th reset transistor element RTn may be coupled between the fifth line L4 and the n-th floating diffusion node FDn. The n-th reset transistor element RTn may selectively couple the fifth line L4 to the n-th floating diffusion node FDn based on the n-th reset control signal RXn. For example, the n-th reset transistor element RTn may electrically couple the fifth line L4 to the n-th floating diffusion node FDn during the n-th reset time An of the n-th row time nth_RT.

[0112] The n-th driving element DTn may be coupled between the first line L0 and the n-th selection element STn. The n-th driving element DTn may generate an n-th pixel signal corresponding to the voltage applied to the n-th floating diffusion node FDn.

[0113] The n-th selection element STn can be coupled between the n-th driving element DTn and the third line L2. The n-th selection element STn can output the n-th pixel signal to the third line L2 based on the n-th selection control signal SXn. For example, the n-th selection element STn can output the n-th reset signal as the n-th pixel signal during the n-th reset readout time Bn of the n-th row time nth_RT, and output the n-th data signal as the n-th pixel signal during the n-th data readout time Dn of the n-th row time nth_RT.

[0114] The n-th transfer control signal TXn, the n-th reset control signal RXn, and the n-th selection control signal SXn can be the n-th row control signals generated by the row decoder 220.

[0115] The (n - 1)-th pixel PXn-1 can include the (n - 1)-th photodiode PDn-1, the (n - 1)-th transfer element TTn-1, the (n - 1)-th floating diffusion node FDn-1, the (n - 1)-th reset transistor element RTn-1, the (n - 1)-th driving element DTn-1, and the (n - 1)-th selection element STn-1.

[0116] The (n - 1)-th photodiode PDn-1 can be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the (n - 1)-th transfer element TTn-1. For example, the (n - 1)-th photodiode PDn-1 can generate charges corresponding to incident light during the (n - 1)-th integration time.

[0117] The (n - 1)-th transfer element TTn-1 can be coupled between the (n - 1)-th photodiode PDn-1 and the (n - 1)-th floating diffusion node FDn-1. The (n - 1)-th transfer element TTn-1 can selectively couple the (n - 1)-th photodiode PDn-1 to the (n - 1)-th floating diffusion node FDn-1 based on the (n - 1)-th transfer control signal TXn-1. For example, the (n - 1)-th transfer element TTn-1 can transfer the charges of the (n - 1)-th photodiode PDn-1 to the (n - 1)-th floating diffusion node FDn-1 during the (n - 1)-th transfer time of the (n - 1)-th row time.

[0118] The (n - 1)-th floating diffusion node FDn-1 can be coupled to the (n - 1)-th capacitor CCn-1. The (n - 1)-th capacitor CCn-1 can store the charges generated by the (n - 1)-th photodiode PDn-1. For example, the (n - 1)-th capacitor CCn-1 can be a parasitic capacitor.

[0119] The (n - 1)-th reset transistor element RTn-1 can be connected between the fourth line L3 and the (n - 1)-th floating diffusion node FDn-1. The (n - 1)-th reset transistor element RTn-1 can selectively connect the fourth line L3 to the (n - 1)-th floating diffusion node FDn-1 based on the (n - 1)-th reset control signal RXn-1. For example, the (n - 1)-th reset transistor element RTn-1 can electrically connect the fourth line L3 to the (n - 1)-th floating diffusion node FDn-1 during the (n - 1)-th reset time of the (n - 1)-th row time. Additionally, the (n - 1)-th reset transistor element RTn-1 can electrically connect the fourth line L3 to the (n - 1)-th floating diffusion node FDn-1 during the n-th reset time An of the n-th row time nth_RT.

[0120] The (n - 1)-th driving element DTn-1 can be connected between the first line L0 and the (n - 1)-th selection element STn-1. The (n - 1)-th driving element DTn-1 can generate the (n - 1)-th pixel signal corresponding to the voltage loaded on the (n - 1)-th floating diffusion node FDn-1.

[0121] The (n - 1)-th selection element STn-1 can be connected between the (n - 1)-th driving element DTn-1 and the second line L1. The (n - 1)-th selection element STn-1 can output the (n - 1)-th pixel signal to the second line L1 based on the (n - 1)-th selection control signal SXn-1. For example, the (n - 1)-th selection element STn-1 can output the (n - 1)-th reset signal as the (n - 1)-th pixel signal during the (n - 1)-th reset readout time of the (n - 1)-th row time, and output the (n - 1)-th data signal as the (n - 1)-th pixel signal during the (n - 1)-th data readout time of the (n - 1)-th row time. Additionally, the (n - 1)-th selection element STn-1 can electrically connect the (n - 1)-th driving element DTn-1 to the second line L1 during the n-th row time nth_RT.

[0122] The (n - 1)-th transfer control signal TXn-1, the (n - 1)-th reset control signal RXn-1, and the (n - 1)-th selection control signal SXn-1 can be the (n - 1)-th row control signals generated by the row decoder 220.

[0123] The amplification region 240 can include an in-pixel amplifier 241, a disabling circuit 245, a compensation circuit 247, and a switching circuit 243.

[0124] The in-pixel amplifier 241 can sequentially output the (n-1)th pixel signal and the nth pixel signal. For example, the in-pixel amplifier 241 can amplify the gain of the (n-1)th pixel signal during the (n-1)th row time, and amplify the gain of the nth pixel signal during the nth row time nth_RT. Since the in-pixel amplifier 241 corresponds to the reference-shared in-pixel differential common-source amplifier (RSDA) disclosed in the paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted.

[0125] The disabling circuit 245 can disable the in-pixel amplifier 241 for each transfer time. For example, the disabling circuit 245 can disable the in-pixel amplifier 241 during the (n-1)th transfer time, and disable the in-pixel amplifier 241 during the nth transfer time Cn. The disabling circuit 245 will be described in more detail below.

[0126] The compensation circuit 247 can supply a compensation current to the common node CN for each transfer time. The compensation circuit 247 will be described in more detail below.

[0127] The switch circuit 243 can include a first switch S0 to an eighth switch S7. The first switch S0 to the eighth switch S7 can be controlled based on the row change signal RC. The row change signal RC can be generated by the timing controller 210. Since the first switch S0 to the eighth switch S7 corresponds to the switches shown in Figure 5 .8.2 in the paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted. However, the switch circuit 243 is illustrated according to the RSDA mode disclosed in the paper.

[0128] Figure 7 is illustrated Figure 6 The equivalent circuit diagrams of the (n-1)th pixel PXn-1, the nth pixel PXn, the in-pixel amplifier 241, the disabling circuit 245, and the compensation circuit 247 shown. Figure 7 It is illustrated that the nth pixel PXn is connected to the output terminal VOUT of the in-pixel amplifier 241.

[0129] Refer to Figure 7, the (n - 1)th pixel PXn-1 can be connected between either of the two output terminals of the in-pixel amplifier 241 and the common node CN of the in-pixel amplifier 241. When the (n - 1)th pixel PXn-1 is used as a reference pixel, the (n - 1)th reset transistor element RTn-1 included in the (n - 1)th pixel PXn-1 can be connected to the high-voltage terminal VRX for reset.

[0130] The nth pixel PXn can be connected between the other output terminal VOUT of the two output terminals and the common node CN. When the nth pixel PXn is used as a target pixel, the nth reset transistor element RTn included in the nth pixel PXn can be connected to the output terminal VOUT.

[0131] The disable circuit 245 can be connected between the high-voltage terminal and the in-pixel amplifier 241. The disable circuit 245 can electrically disconnect the high-voltage terminal from the in-pixel amplifier 241 during the nth transfer time Cn. For example, the disable circuit 245 can include a PMOS transistor. The PMOS transistor can have a gate terminal for receiving a disable signal SXB activated for each transfer time and source and drain terminals connected between the high-voltage terminal and the in-pixel amplifier 241. The disable signal SXB can be generated by the timing controller 210.

[0132] The compensation circuit 247 can be connected between the high-voltage terminal and the common node CN. The compensation circuit 247 can prevent power fluctuations caused by the disable circuit 245 for each transfer time. For example, the compensation circuit 247 can include a first switch S11 and a second switch S12.

[0133] The first switch S11 can be connected between the high-voltage terminal and the connection node CPN. The first switch S11 can operate based on a first control signal FS having a fixed voltage level. For example, the first control signal FS can have a high voltage provided from the high-voltage terminal VRX for reset. For example, the first switch S11 can include an NMOS transistor. The NMOS transistor can have a gate terminal for receiving the first control signal FS and source and drain terminals connected between the high-voltage terminal and the connection node CPN.

[0134] The second switch S12 can be connected between the connection node CPN and the common node CN. The second switch S12 can operate based on the disable signal SXB. For example, the second switch S12 can include an NMOS transistor. The NMOS transistor can have a gate terminal for receiving the disable signal SXB and source and drain terminals connected between the connection node CPN and the common node CN.

[0135] Figure 8 is illustrativeFigure 5 Another example circuit diagram of the pixel array 230 and the enlarged area 240 shown. In Figure 8 A circuit diagram corresponding to a part of the pixel array 230 and a part of the enlarged area 240 is illustrated. This part of the pixel array 230 may include pixels corresponding to any one of a plurality of columns, and this part of the enlarged area 240 may include a pixel amplifier 241, a disabling circuit 245, an interrupt circuit 249, and a switching circuit 243 corresponding to the any one column. Hereinafter, only the interrupt circuit 249, which is a configuration different from that of Figure 6 will be described.

[0136] The interrupt circuit 249 may disconnect the common node CN from the current source for each transfer time. Refer to Figure 9 for a more detailed description of the interrupt circuit 249.

[0137] Figure 9 is an equivalent circuit diagram illustrating the (n - 1)th pixel PXn - 1, the nth pixel PXn, the pixel amplifier 241, the disabling circuit 245, and the interrupt circuit 249 shown in Figure 8 . Figure 9 Illustrates the case where the nth pixel PXn is connected to the output terminal VOUT of the pixel amplifier 241. Hereinafter, only the interrupt circuit 249, which is a configuration different from that of Figure 7 will be described.

[0138] Refer to Figure 9 , the interrupt circuit 249 may be connected between the common node CN and the current source 249a, and the common node CN and the current source 249a are included in the pixel amplifier 241. The interrupt circuit 249 may prevent fluctuations of the common node CN caused by the disabling circuit 245 for each transfer time. For example, the interrupt circuit 249 may include an NMOS transistor. The NMOS transistor may have a gate terminal for receiving an interrupt control signal SXX and source and drain terminals connected between the common node CN and the current source 249a. The interrupt control signal SXX may be generated by the timing controller 210.

[0139] Hereinafter, refer to Figure 10 and Figure 11 to describe the operation of the image sensing device 200 according to the second embodiment having the above configuration.

[0140] Figure 10 is a timing diagram illustrating an example of the operation of the image sensing device 200 shown in Figure 5 . For ease of description, the case where the nth pixel PXn is the target pixel is representatively described.

[0141] Refer to Figure 10, during the nth row time nth_RT, the (n - 1)th pixel PXn-1 can be connected to the in-pixel amplifier 241 through the switch circuit 243 as a reference pixel, and the nth pixel PXn can be connected to the in-pixel amplifier 241 through the switch circuit 243 as a target pixel. During the nth row time nth_RT, the (n - 1)th selection element STn-1 can be turned on based on the (n - 1)th selection control signal SXn-1, and during one or more times of each row processing signal including the reset time An, the reset readout time Bn, the transfer time Cn, and the data readout time Dn, the nth selection element STn can be turned on based on the nth selection control signal SXn.

[0142] The nth row time nth_RT can include the nth reset time An, the nth reset readout time Bn, the nth transfer time Cn, and the nth data readout time Dn.

[0143] During the nth reset time An, the nth pixel PXn can store an offset in the nth floating diffusion node FDn based on the nth reset control signal RXn.

[0144] During the nth reset readout time Bn, the nth pixel PXn can generate a pixel signal corresponding to the reset level according to the voltage loaded on the nth floating diffusion node FDn.

[0145] During the nth transfer time Cn, the nth pixel PXn can transfer the charge accumulated in the nth photodiode PDn to the nth floating diffusion node FDn based on the nth transfer control signal TXn. At this time, the disabling circuit 245 can disable the in-pixel amplifier 241 based on the disabling signal SXB. For example, the disabling circuit 245 can disconnect the high-voltage terminal from the in-pixel amplifier 241 during the nth transfer time Cn. The compensation circuit 247 can provide a compensation current to the common node CN during the nth transfer time Cn, thereby preventing the power fluctuation of the current source from being affected when the power (i.e., high voltage) supplied to the in-pixel amplifier 241 is cut off. The nth pixel PXn can be disconnected from the output terminal VOUT based on the nth selection control signal SXn. Therefore, during the nth transfer time Cn, the voltage level of the output terminal VOUT can be maintained at the reset level. For example, the voltage level of the output terminal VOUT can be maintained at the reset level by the parasitic capacitor connected to the output terminal VOUT.

[0146] During the n-th data readout time Dn, the n-th pixel PXn may generate a pixel signal corresponding to a target level (i.e., the data level of the pixel signal) according to the voltage applied to the n-th floating diffusion node FDn. At this time, the voltage level of the output terminal VOUT from which the pixel signal is output may increase (or be amplified) from the reset level to the target level, thereby minimizing the settling time for the pixel signal to reach the target level. In other words, during the n-th data readout time Dn, since the operating range or swing range of the voltage level of the output terminal VOUT (refer to the dashed line for VOUT in Figure 10 can be reduced to the effective output range (refer to the solid line for VOUT in Figure 10 ), the settling time can be minimized.

[0147] Figure 11 is an example Figure 5 A timing diagram showing another example of the operation of the image sensing device 200 shown. The case where the n-th pixel PXn is the target pixel is representatively described.

[0148] Refer to Figure 11 , during the n-th row time nth_RT, the (n - 1)-th pixel PXn-1 may be connected to the in-pixel amplifier 241 as a reference pixel through the switch circuit 243, and the n-th pixel PXn may be connected to the in-pixel amplifier 241 as a target pixel through the switch circuit 243. During the n-th row time nth_RT, the (n - 1)-th selection element STn-1 may be turned on based on the (n - 1)-th selection control signal SXn-1, and the n-th selection element STn may be turned on based on the n-th selection control signal SXn.

[0149] The n-th row time nth_RT may include the n-th reset time An, the n-th reset readout time Bn, the n-th transfer time Cn, and the n-th data readout time Dn.

[0150] During the n-th reset time An, the n-th pixel PXn may store an offset in the n-th floating diffusion node FDn based on the n-th reset control signal RXn.

[0151] During the n-th reset readout time Bn, the n-th pixel PXn may generate a pixel signal corresponding to the reset level according to the voltage applied to the n-th floating diffusion node FDn.

[0152] During the n-th transfer time Cn, the n-th pixel PXn can transfer the charge accumulated in the n-th photodiode PDn to the n-th floating diffusion node FDn based on the n-th transfer control signal TXn. At this time, the disabling circuit 245 can disable the in-pixel amplifier 241 based on the disabling signal SXB. For example, the disabling circuit 245 can disconnect the high-voltage terminal from the in-pixel amplifier 241 during the n-th transfer time Cn. During the n-th transfer time Cn, the interrupting circuit 249 can disconnect the common node CN from the current source 249a based on the interrupt control signal SXX, thereby protecting the current source 249a from being affected by the fluctuations of the common node CN that occur when the power (i.e., high voltage) supplied to the in-pixel amplifier 241 is cut off. The n-th pixel PXn can be disconnected from the output terminal VOUT based on the n-th selection control signal SXn. Therefore, during the n-th transfer time Cn, the voltage level of the output terminal VOUT can be maintained at the reset level. For example, the voltage level of the output terminal VOUT can be kept at the reset level by the parasitic capacitor connected to the output terminal VOUT.

[0153] During the n-th data readout time Dn, the n-th pixel PXn can generate a pixel signal corresponding to the target level (i.e., the data level of the pixel signal) according to the voltage applied to the n-th floating diffusion node FDn. At this time, the voltage level of the output terminal VOUT from which the pixel signal is output can be raised (or amplified) from the reset level to the target level, thereby minimizing the settling time for the pixel signal to reach the target level. In other words, during the n-th data readout time Dn, since the operating range or swing range of the voltage level of the output terminal VOUT (refer to the dashed line for VOUT in Figure 11 can be reduced to the effective output range (refer to the solid line for VOUT in Figure 11 ), the settling time can be minimized.

[0154] According to the second embodiment, when reading out the pixel signal, the settling time for the pixel signal to reach the target level can be minimized.

[0155] Figure 12 FIG. is a block diagram illustrating an image sensing device 300 according to the third embodiment.

[0156] Referring to Figure 12 , the image sensing device 300 can include a timing controller 310, a row decoder 320, a pixel array 330, an amplification region 340, a signal conversion region 350, and a column decoder 360.

[0157] The timing controller 310 can control the overall operation of the image sensing device 300. The timing controller 310 is also referred to as a timing generator.

[0158] The row decoder 320 may control the pixel array 330 for each row. For example, the row decoder 320 may generate a first row control signal for controlling pixels arranged in the first row of the pixel array 330, and generate a y-th row control signal for controlling pixels arranged in the y-th row of the pixel array 330. Herein, "y" is a natural number greater than 2.

[0159] The pixel array 330 may include pixels arranged at intersections of a plurality of rows and a plurality of columns. The pixels may generate pixel signals for each row under the control of the row decoder 320.

[0160] The amplification region 340 may amplify the gain of the pixel signal. For example, the amplification region 340 may access a random first pixel in the pixel as a target pixel, access a random second pixel in the pixel as a reference pixel, and amplify the gain of the pixel signal read out from the target pixel. The amplification region 340 may include a plurality of in-pixel amplifiers, a plurality of switch circuits, and a plurality of pre-chargers corresponding to the plurality of columns of the pixel array 330 (refer to Figure 13 ).

[0161] The signal conversion region 350 may convert an analog-type pixel signal into a digital-type signal. For example, the signal conversion region 350 may include a plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of the pixel array 330.

[0162] The column decoder 360 may control the signal conversion region 350 for each column. For example, the column decoder 360 may sequentially control the plurality of ADCs.

[0163] Figure 13 is an example Figure 12 The circuit diagram of an example of the pixel array 330 and the amplification region 340 shown. For ease of description, in Figure 13 a circuit diagram corresponding to a part of the pixel array 330 and a part of the amplification region 340 is shown. This part of the pixel array 330 may include pixels corresponding to any one of the plurality of columns, and this part of the amplification region 340 may include an in-pixel amplifier 341 and a switch circuit 343 corresponding to the any one column.

[0164] The pixel array 330 may include pixels arranged in a column direction. Hereinafter, among the pixels, the pixel PXn arranged in the n-th row is referred to as the n-th pixel, and the pixel PXn-1 arranged in the (n-1)-th row among the pixels is referred to as the (n-1)-th pixel. Herein, "n" is a natural number greater than 2. When the n-th pixel PXn is the target pixel, the (n-1)-th pixel PXn-1 may be the reference pixel. In other words, the target pixel and the reference pixel may be normal pixels arranged adjacent to each other in the column direction.

[0165] The nth pixel Pxn may include an nth photodiode PDn, an nth transfer element TTn, an nth floating diffusion node FDn, an nth reset transistor element RTn, an nth driving element DTn, and an nth selection element STn.

[0166] The nth photodiode PDn may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the nth transfer element TTn. For example, the nth photodiode PDn may generate charge corresponding to incident light during the nth integration time.

[0167] The nth transfer element TTn may be coupled between the nth photodiode PDn and the nth floating diffusion node FDn. The nth transfer element TTn may selectively couple the nth photodiode PDn to the nth floating diffusion node FDn based on an nth transfer control signal TXn. For example, the nth transfer element TTn may transfer the charge of the nth photodiode PDn to the nth floating diffusion node FDn during an nth transfer time Cn of the nth row time nth_RT.

[0168] The nth floating diffusion node FDn may be coupled to an nth capacitor CCn. The nth capacitor CCn may store the charge generated by the nth photodiode PDn. For example, the nth capacitor CCn may be a parasitic capacitor.

[0169] The nth reset transistor element RTn may be coupled between a fifth line L4 and the nth floating diffusion node FDn. The nth reset transistor element RTn may selectively couple the fifth line L4 to the nth floating diffusion node FDn based on an nth reset control signal Rxn. For example, the nth reset transistor element RTn may electrically couple the fifth line L4 to the nth floating diffusion node FDn during an nth reset time An of the nth row time nth_RT.

[0170] The nth driving element DTn may be coupled between a first line L0 and the nth selection element STn. The nth driving element DTn may generate an nth pixel signal corresponding to the voltage applied to the nth floating diffusion node FDn.

[0171] The nth selection element STn may be coupled between the nth driving element DTn and a third line L2. The nth selection element STn may output the nth pixel signal to the third line L2 based on an nth selection control signal SXn. For example, the nth selection element STn may output an nth reset signal as the nth pixel signal during an nth reset readout time Bn of the nth row time nth_RT, and output an nth data signal as the nth pixel signal during an nth data readout time Dn of the nth row time nth_RT.

[0172] The n-th transfer control signal TXn, the n-th reset control signal RXn, and the n-th selection control signal SXn may be the n-th row control signal generated by the row decoder 320.

[0173] The (n - 1)-th pixel PXn-1 may include the (n - 1)-th photodiode PDn-1, the (n - 1)-th transfer element TTn-1, the (n - 1)-th floating diffusion node FDn-1, the (n - 1)-th reset transistor element RTn-1, the (n - 1)-th driving element DTn-1, and the (n - 1)-th selection element STn-1.

[0174] The (n - 1)-th photodiode PDn-1 may be coupled between a low voltage terminal (e.g., a ground voltage terminal) and the (n - 1)-th transfer element TTn-1. For example, the (n - 1)-th photodiode PDn-1 may generate charge corresponding to incident light during the (n - 1)-th integration time.

[0175] The (n - 1)-th transfer element TTn-1 may be coupled between the (n - 1)-th photodiode PDn-1 and the (n - 1)-th floating diffusion node FDn-1. The (n - 1)-th transfer element TTn-1 may selectively couple the (n - 1)-th photodiode PDn-1 to the (n - 1)-th floating diffusion node FDn-1 based on the (n - 1)-th transfer control signal TXn-1. For example, the (n - 1)-th transfer element TTn-1 may transfer the charge of the (n - 1)-th photodiode PD-1 to the (n - 1)-th floating diffusion node FDn-1 during the (n - 1)-th transfer time of the (n - 1)-th row time (n - 1)th_RT.

[0176] The (n - 1)-th floating diffusion node FDn-1 may be coupled to the (n - 1)-th capacitor CCn-1. The (n - 1)-th capacitor CCn-1 may store the charge generated by the (n - 1)-th photodiode PD-1. For example, the (n - 1)-th capacitor CCn-1 may be a parasitic capacitor.

[0177] The (n - 1)th reset transistor element RTn-1 can be coupled between the fourth line L3 and the (n - 1)th floating diffusion node FDn-1. The (n - 1)th reset transistor element RTn-1 can selectively couple the fourth line L3 to the (n - 1)th floating diffusion node FDn-1 based on the (n - 1)th reset control signal RXn-1. For example, the (n - 1)th reset transistor element RTn-1 can electrically couple the fourth line L3 to the (n - 1)th floating diffusion node FDn-1 during the (n - 1)th reset time of the (n - 1)th row time (n - 1)th_RT. Additionally, the (n - 1)th reset transistor element RTn-1 can electrically couple the fourth line L3 to the (n - 1)th floating diffusion node FDn-1 during the nth reset time An of the nth row time nth_RT.

[0178] The (n - 1)th driving element DTn-1 can be coupled between the first line L0 and the (n - 1)th selection element STn-1. The (n - 1)th driving element DTn-1 can generate the (n - 1)th pixel signal corresponding to the voltage loaded on the (n - 1)th floating diffusion node FDn-1.

[0179] The (n - 1)th selection element STn-1 can be coupled between the (n - 1)th driving element DTn-1 and the second line L1. The (n - 1)th selection element STn-1 can output the (n - 1)th pixel signal to the second line L1 based on the (n - 1)th selection control signal SXn-1. For example, the (n - 1)th selection element STn-1 can output the (n - 1)th reset signal as the (n - 1)th pixel signal during the (n - 1)th reset readout time of the (n - 1)th row time (n - 1)th_RT, and output the (n - 1)th data signal as the (n - 1)th pixel signal during the (n - 1)th data readout time of the (n - 1)th row time (n - 1)th_RT. Additionally, the (n - 1)th selection element STn-1 can electrically couple the (n - 1)th driving element DTn-1 to the second line L1 during the nth row time nth_RT.

[0180] The (n - 1)th transfer control signal TXn-1, the (n - 1)th reset control signal RXn-1, and the (n - 1)th selection control signal SXn-1 can be the (n - 1)th row control signals generated by the row decoder 320.

[0181] The amplification region 340 can include an in-pixel amplifier 341, a switching circuit 343, and a pre-charger 345.

[0182] The in-pixel amplifier 341 can sequentially output the (n - 1)th pixel signal and the nth pixel signal through the output terminal VOUT. For example, the in-pixel amplifier 341 can amplify the gain of the (n - 1)th pixel signal during the (n - 1)th row time (n - 1)th_RT, and amplify the gain of the nth pixel signal during the nth row time nth_RT. Since the in-pixel amplifier 341 corresponds to the reference-shared in-pixel differential common-source amplifier (RSDA) disclosed in the paper "A0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted.

[0183] The switch circuit 343 can include the first switch S0 to the eighth switch S7. The first switch S0 to the eighth switch S7 can be controlled based on the row change signal RC. The row change signal RC can be generated by the timing controller 310. Since the first switch S0 to the eighth switch S7 corresponds to the switches shown in Figure 5 .8.2 of the paper "A 0.50erms Noise 1.45μm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps", its detailed description is omitted. However, the switch circuit 343 is shown according to the RSDA mode disclosed in the paper.

[0184] The pre-charger 345 can be connected to the output terminal VOUT of the in-pixel amplifier 341. The pre-charger 345 will be described in more detail below.

[0185] Figure 14 is an illustration Figure 13 The equivalent circuit diagrams of the (n - 1)th pixel PXn-1, the nth pixel PXn, the in-pixel amplifier 341, and the pre-charger 345 shown. Figure 14 An example shows the case where the nth pixel PXn is connected to the output terminal VOUT of the in-pixel amplifier 341.

[0186] Referring to Figure 14 , the in-pixel amplifier 341 can output the pixel signal of the nth pixel PXn through the output terminal VOUT by using the (n - 1)th pixel PXn-1.

[0187] The pre-charger 345 can supply a pre-charge current IP to the output terminal VOUT according to the voltage level of the pixel signal of the n-th pixel PXn read out through the output terminal VOUT. For example, the pre-charger 345 can supply a pre-charge current IP adaptively adjusted according to the slope of the pixel signal (i.e., the change amount of the voltage level of the pixel signal) to the output terminal VOUT during the initial time of the n-th data read time Dn, where a larger pre-charge current is used to compensate for a steeper slope.

[0188] Figure 15 is an illustration Figure 13 and Figure 14 The circuit diagram of an example of the pre-charger 345 shown.

[0189] Referring to Figure 15 , the pre-charger 345 can include a control circuit 345A and a current supply circuit 345B.

[0190] The control circuit 345A can be connected between the output terminal VOUT and the high voltage terminal. The control circuit 345A can generate a control voltage corresponding to the voltage level of the pixel signal of the n-th pixel PXn. For example, the control circuit 345A can include a sensing circuit 3451 and a reference circuit 3453.

[0191] The sensing circuit 3451 can be connected between the output terminal VOUT and the control node AA. The sensing circuit 3451 can sense the slope of the pixel signal of the n-th pixel PXn based on the control signal ROB, and supply a control voltage to the control node AA according to the sensing result. For example, the sensing circuit 3451 can include a first switch SS0 and an AC coupler ACC. The first switch SS0 can be connected to the output terminal VOUT and the first node. The first switch SS0 can operate based on the control signal ROB. For example, the first switch SS0 can be short-circuited during the n-th reset time An and the initial time. The control signal ROB can be a signal obtained by performing an OR operation on the reference control signal RXX and the boost control signal BST. The reference control signal RXX and the boost control signal BST can be generated by the timing controller 310. The AC coupler ACC can be connected between the first node and the control node AA. The AC coupler ACC can generate a control voltage whose voltage level changes corresponding to the slope of the pixel signal of the n-th pixel PXn through the control node AA.

[0192] The reference circuit 3453 can provide a reference voltage to the control node AA based on the reference control signal RXX. That is, the reference circuit 3453 can initialize the control node AA to the reference voltage during the nth reset time An. For example, the reference circuit 3453 can include a second switch SS1, a current-voltage converter NM0, a third switch SS2, and a current source CS. The second switch SS1 can be coupled between the control node AA and the second node. The second switch SS1 can operate based on the reference control signal RXX. For example, the second switch SS1 can be shorted during the nth reset time An. The current-voltage converter NM0 can be coupled between the second node and the third node. The current-voltage converter NM0 can convert the reference current generated by the current source CS into a reference voltage. The third switch SS2 can be coupled between the third node and the fourth node. The third switch SS2 can operate based on the reference control signal RXX. For example, the third switch SS2 can be shorted during the nth reset time An. The current source CS can be coupled between the fourth node and the high voltage terminal. The current source CS can generate a reference current.

[0193] The current supply circuit 345B can be coupled between the output terminal VOUT and the high voltage terminal. The current supply circuit 345B can provide a precharge current IP adaptively adjusted according to the voltage level of the pixel signal of the nth pixel PXn to the output terminal VOUT based on the control voltage applied through the control node AA (for example, a higher voltage level results in a larger precharge current). For example, the current supply circuit 345B can include a first voltage-current converter NM1, a fourth switch SS3, a first current mirror PM0 and PM1, and a driver PM2. The first voltage-current converter NM1 can be coupled between the low voltage terminal and the fifth node. The first voltage-current converter NM1 can convert the control voltage into a control current IS. The fourth switch SS3 can be coupled between the fifth node and the sixth node. The fourth switch SS3 can operate based on the boost control signal BST. For example, the fourth switch SS3 can be shorted during the initial time of the nth data readout time Dn. The first current mirror PM0 and PM1 can be coupled between the sixth node, the output terminal VOUT, and the high voltage terminal. The first current mirror PM0 and PM1 can generate a precharge current IP corresponding to the control current IS. The driver PM2 can be coupled between the high voltage terminal and the common gate node of the first current mirror PM0 and PM1. The driver PM2 can be controlled based on the boost control signal BST. For example, the driver PM2 can disable the first current mirror PM0 and PM1 during other times of the nth row time nth_RT except for the initialization time of the nth data readout time Dn.

[0194] Figure 16 is illustrative Figure 13 andFigure 14 Another example circuit diagram of the pre-charger 345 shown.

[0195] Referring to Figure 16 , the pre-charger 345 may include a control circuit 345A, a current supply circuit 345B, and a subtraction circuit 345C.

[0196] Since the control circuit 345A and the current supply circuit 345B are the same as those described in Figure 15 , their detailed descriptions are omitted. In Figure 16 , a subtraction current IR can be applied to the pre-charge current IP generated by the current supply circuit 345B. That is, the pre-charge current IP can be the current obtained by subtracting the subtraction current IR from the control current IS (IP = IS - IR).

[0197] The subtraction circuit 345C can be connected between the high voltage terminal and the low voltage terminal. The subtraction circuit 345C can be connected between the second node of the reference circuit 3453 and the sixth node of the current supply circuit 345B. The subtraction circuit 345C can receive a reference voltage through the second node and generate a subtraction current IR corresponding to the reference voltage or reference current through the sixth node. For example, the subtraction circuit 345C may include a fifth switch SS4, a capacitor CC, a second voltage-current converter NM2, a sixth switch SS5, and second current mirrors PM3 and PM4.

[0198] The fifth switch SS4 can be connected between the second node and the seventh node. The fifth switch SS4 can operate based on a reference control signal RXX. For example, the fifth switch SS4 can be short-circuited during the nth reset time An.

[0199] The capacitor CC can be connected between the seventh node and the low voltage terminal. The capacitor CC can store the reference voltage.

[0200] The second voltage-current converter NM2 can be connected between the seventh node, the low voltage terminal, and the eighth node. The second voltage-current converter NM2 can generate a stored current corresponding to the reference voltage stored in the capacitor CC through the eighth node.

[0201] The sixth switch SS5 can be connected between the eighth node and the ninth node. The sixth switch SS5 can operate based on a boost control signal BST. For example, the sixth switch SS5 can be short-circuited during the initial time of the nth data readout time Dn.

[0202] The second current mirrors PM3 and PM4 can be connected between the ninth node, the high voltage terminal, and the sixth node of the current supply circuit 345B. The second current mirrors PM3 and PM4 can generate a subtraction current IR corresponding to the stored current through the sixth node.

[0203] In the following, with reference to Figure 17 and Figure 18 the operation of the image sensing device 300 according to the third embodiment having the above configuration will be described.

[0204] Figure 17 is an example Figure 12 a timing chart illustrating the operation of the image sensing device shown. The case where the nth pixel PXn is the target pixel is representatively described.

[0205] With reference to Figure 17 , during the nth row time nth_RT, the (n - 1)th pixel PXn-1 can be connected to the in-pixel amplifier 341 as a reference pixel through the switch circuit 343, and the nth pixel PXn can be connected to the in-pixel amplifier 341 as a target pixel through the switch circuit 343. During the nth row time nth_RT, the (n - 1)th selection element STn-1 can be turned on based on the (n - 1)th selection control signal SXn-1, and the nth selection element STn can be turned on based on the nth selection control signal SXn.

[0206] During the nth reset time An of the nth row time nth_RT, the (n - 1)th reset transistor element RTn-1 can be turned on based on the (n - 1)th reset control signal RXn-1, and the nth reset transistor element RTn can be turned on based on the nth reset control signal RXn. Accordingly, a negative feedback loop can be formed between the nth floating diffusion node FDn and the output terminal VOUT, and an offset can be stored in the nth floating diffusion node FDn. The offset may refer to the mismatch between the (n - 1)th pixel PXn-1 and the nth pixel PXn. As a reference, the offset can be canceled through a correlated double sampling (CDS) operation.

[0207] Meanwhile, during the nth reset time An, the first switch SS0 included in the sensing circuit 3451 and the second switch SS1 and the third switch SS2 included in the reference circuit 3453 can be short-circuited by the reference control signal RXX. Accordingly, the control voltage of the control node AA can be initialized to a voltage level corresponding to the reference voltage generated by the reference circuit 3453.

[0208] During the nth reset readout time Bn, the in-pixel amplifier 341 can output a reset signal corresponding to the offset as the pixel signal of the nth pixel PXn.

[0209] During the nth transfer time Cn, the nth pixel PXn can transfer the charge accumulated in the nth photodiode PDn to the nth floating diffusion node FDn based on the nth transfer control signal TXn.

[0210] During the n-th data readout time Dn, the in-pixel amplifier 341 may output a data signal corresponding to the charge as a pixel signal of the n-th pixel PXn. At this time, during the initial time of the n-th data readout time Dn, the pre-charger 345 may supply a pre-charge current IP adaptively adjusted according to the voltage level of the pixel signal of the n-th pixel PXn to the output terminal VOUT (for example, a higher voltage level results in a larger pre-charge current). Therefore, the stabilization time of the pixel signal of the n-th pixel PXn output through the output terminal VOUT can be reduced, and thus the readout time of the pixel signal can be shortened.

[0211] When the subtraction circuit 345C is included in the pre-charger 345, a subtraction current IR may be applied to the pre-charge current IP. That is, the pre-charger 345 may generate a current obtained by subtracting the subtraction current IR from the control current IS as the pre-charge current IP (IP = IS - IR). Therefore, when the pixel signal of the n-th pixel PXn is output through the output terminal VOUT, an overshoot that appears in the pixel signal can be prevented. As the pixel signal has a lower voltage level, due to the pre-charge current IP, the pixel signal is more affected by the reference voltage of the reference circuit 3453. Therefore, when the pixel signal has a lower voltage level, an overshoot with a larger level may appear in the pixel signal due to the pre-charge current IP, but the pre-charge current IP can be generated by subtracting the subtraction current IR corresponding to the reference voltage from the control current IS, thereby preventing the overshoot.

[0212] Figure 18 is another illustration Figure 17 The timing diagram of the operation of the image sensing device 300 shown.

[0213] Referring to Figure 18 , as described above, the pre-charger 345 may generate a pre-charge current IP adaptively adjusted according to the voltage level of the pixel signal of the n-th pixel PXn. For example, as the slope of the pixel signal is smaller (i.e., as the change amount of the voltage level of the pixel signal decreases), the pre-charger 345 may generate a pre-charge current IP with a lower level, and as the slope of the pixel signal is steeper (i.e., as the change amount of the voltage level of the pixel signal increases), the pre-charger 345 may generate a pre-charge current IP with a higher level.

[0214] According to the third embodiment, there is an advantage of boosting the readout line (i.e., the output terminal) of the pixel signal adaptively according to the voltage level of the pixel signal.

[0215] According to an embodiment of the present disclosure, in a structure where the in-pixel amplifier is connected to the readout line, the load of the readout line of the pixel signal can be reduced, and thus the readout speed of the pixel signal can be improved.

[0216] In addition, according to an embodiment of the present disclosure, the stabilization time of the pixel signal output through the readout line of the pixel signal can be minimized in a structure where the in-pixel amplifier is connected to the readout line, and thus the readout speed of the pixel signal can be increased.

[0217] Although the present disclosure has been shown and described with respect to specific embodiments, the disclosed embodiments are provided for description and are not intended to be limiting. In addition, it should be noted that, as will be recognized by those skilled in the art from the present disclosure, the present disclosure can be implemented in various ways by substitutions, changes, and modifications that fall within the scope of the appended claims.

[0218] In addition, the methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device (e.g., control circuit 345A (described above)). The computer, processor, controller, or other signal processing device can be those described herein or elements other than the elements described herein. Since the algorithms (or operations of the computer, processor, controller, or other signal processing device) underlying these methods have been described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0219] When implemented at least partially in software form, the controller, processor, device, module, unit, multiplexer, generator, logic, interface, decoder, driver, and other signal generation and signal processing functions (such as control circuit 345A (described above)) can include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0220] Cross-reference to related applications

[0221] This application claims the priority of Korean Patent Application No. 10-2021-0028903, filed on Mar. 4, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, the image sensing device comprises: a control circuit, the control circuit being connected between an output terminal of a pixel signal and a high voltage terminal, and generating a control voltage, the voltage level of the control voltage changing corresponding to the slope of the pixel signal; and a current supply circuit, the current supply circuit being connected between the output terminal and the high voltage terminal, and providing a pre-charge current adaptively adjusted according to the slope of the pixel signal to the output terminal based on the control voltage.

2. The image sensing device according to claim 1, wherein, the control circuit comprises: a reference circuit, the reference circuit providing a reference voltage to a control node based on a reference control signal; and a sensing circuit, the sensing circuit being connected between the output terminal and the control node, and sensing the slope of the pixel signal based on the reference control signal and a boost control signal, wherein, the sensing circuit provides the control voltage to the control node according to the sensed slope.

3. The image sensing device according to claim 2, wherein, the sensing circuit comprises: a first switch, the first switch being connected to the output terminal and a first node, and operating based on the reference control signal and the boost control signal; and an AC coupler, the AC coupler being connected between the first node and the control node, and generating the control voltage through the control node, wherein the voltage level of the control voltage changes corresponding to the slope of the pixel signal.

4. The image sensing device according to claim 2, wherein, the reference circuit comprises: a second switch, the second switch being connected between the control node and a second node, and operating based on the reference control signal; a current-voltage converter, the current-voltage converter being connected between the second node and a third node; a third switch, the third switch being connected between the third node and a fourth node, and operating based on the reference control signal; and a current source, the current source being connected between the fourth node and the high voltage terminal, and generating a reference current corresponding to the reference voltage.

5. The image sensing device according to claim 1, wherein, the current supply circuit comprises: a voltage-current converter, the voltage-current converter being connected between a low voltage terminal and a fifth node, and generating a control current corresponding to the control voltage; a fourth switch, the fourth switch being connected between the fifth node and a sixth node, and operating based on a boost control signal; a current mirror, the current mirror being connected between the sixth node, the output terminal and the high voltage terminal, and generating the pre-charge current corresponding to the control current; and a driver, the driver being connected between the high voltage terminal and a common gate node of the current mirror, and being controlled based on the boost control signal.

6. An image sensing device, the image sensing device comprises: A reference circuit, the reference circuit being connected between a high voltage terminal and a control node, and providing a reference voltage to the control node based on a reference control signal; A sensing circuit, the sensing circuit being connected between the control node and an output terminal of a pixel signal, and sensing a slope of the pixel signal based on the reference control signal and a boost control signal, wherein the sensing circuit provides a control voltage to the control node according to the sensed slope; A subtraction circuit, the subtraction circuit being connected between the high voltage terminal and a low voltage terminal, and generating a subtraction current corresponding to the reference voltage; and A current supply circuit, the current supply circuit being connected between the output terminal and the high voltage terminal, and providing a precharge current applied with the subtraction current to the output terminal based on the control voltage and the subtraction current.

7. The image sensing device according to claim 6, wherein, the current supply circuit generates a control current corresponding to the control voltage, and generates the precharge current by subtracting the subtraction current from the control current.

8. The image sensing device according to claim 6, wherein, the precharge current is adaptively adjusted according to a voltage level of the pixel signal.

9. The image sensing device according to claim 6, wherein, the sensing circuit includes: a first switch, the first switch being connected to the output terminal and a first node, and operating based on the reference control signal and the boost control signal; and an AC coupler, the AC coupler being connected between the first node and the control node, and generating the control voltage, wherein a voltage level of the control voltage changes corresponding to the slope of the pixel signal.

10. The image sensing device according to claim 6, wherein, the reference circuit includes: a second switch, the second switch being connected between the control node and a second node, and operating based on the reference control signal; a current-voltage converter, the current-voltage converter being connected between the second node and a third node; a third switch, the third switch being connected between the third node and a fourth node, and operating based on the reference control signal; and a current source, the current source being connected between the fourth node and the high voltage terminal, and generating a reference current corresponding to the reference voltage.

11. The image sensing device according to claim 6, wherein, the current supply circuit includes: a first voltage-current converter, the first voltage-current converter being connected between the low voltage terminal and a fifth node, and generating a control current corresponding to the control voltage; a fourth switch, the fourth switch being connected between the fifth node and a sixth node, and operating based on the boost control signal; a first current mirror, the first current mirror being connected between the sixth node, the output terminal and the high voltage terminal, and generating the precharge current corresponding to the control current; and A driver, which is coupled between the high-voltage terminal and the common gate node of the first current mirror and is controlled based on the boost control signal.

12. The image sensing device according to claim 6, wherein, the subtraction circuit includes: a fifth switch, which is coupled between the reference circuit and the seventh node and operates based on the reference control signal; a capacitor, which is coupled between the seventh node and the low-voltage terminal and stores the reference voltage; a second voltage-current converter, which is coupled between the seventh node, the low-voltage terminal and the eighth node and generates a stored current corresponding to the reference voltage stored in the capacitor through the eighth node; a sixth switch, which is coupled between the eighth node and the ninth node and operates based on the boost control signal; and a second current mirror, which is coupled between the ninth node, the high-voltage terminal and the current supply circuit and provides a subtraction current corresponding to the stored current to the current supply circuit.

13. An image sensing device, which includes: a reference pixel; a target pixel; an amplifier, which is commonly coupled to the reference pixel and the target pixel and outputs the pixel signal of the target pixel through an output terminal during a readout period of a target row time; and a pre-charger, which provides a pre-charge current adaptively adjusted according to a control voltage to the output terminal during an initial time of the readout period, and the voltage level of the control voltage changes corresponding to the slope of the pixel signal.

14. The image sensing device according to claim 13, wherein, the pre-charger includes: a control circuit, which is coupled between the output terminal and the high-voltage terminal and generates a control voltage corresponding to the voltage level of the pixel signal; and a current supply circuit, which is coupled between the output terminal and the high-voltage terminal and provides the pre-charge current adaptively adjusted according to the voltage level of the pixel signal to the output terminal based on the control voltage.

15. The image sensing device according to claim 14, wherein, the control circuit includes: a reference circuit, which provides a reference voltage to a control node based on a reference control signal; and a sensing circuit, which is coupled between the output terminal and the control node and senses the slope of the pixel signal based on the reference control signal and the boost control signal, and provides the control voltage to the control node according to the sensed slope.

16. The image sensing device according to claim 15, wherein, the sensing circuit includes: a first switch, which is coupled to the output terminal and a first node and operates based on the reference control signal and the boost control signal; and An AC coupler is coupled between the first node and the control node, and generates the control voltage through the control node, wherein the voltage level of the control voltage changes corresponding to the slope of the pixel signal.

17. The image sensing device according to claim 15, wherein, the reference circuit includes: a second switch coupled between the control node and a second node and operating based on the reference control signal; a current-voltage converter coupled between the second node and a third node; a third switch coupled between the third node and a fourth node and operating based on the reference control signal; and a current source coupled between the fourth node and the high voltage terminal and generating a reference current corresponding to the reference voltage.

18. The image sensing device according to claim 14, wherein, the current supply circuit includes: a first voltage-current converter coupled between a low voltage terminal and a fifth node and generating a control current corresponding to the control voltage; a fourth switch coupled between the fifth node and a sixth node and operating based on a boost control signal; a first current mirror coupled between the sixth node, the output terminal and the high voltage terminal and generating the pre-charge current corresponding to the control current; and a driver coupled between the high voltage terminal and the common gate node of the first current mirror and controlled based on the boost control signal.

19. The image sensing device according to claim 15, the image sensing device further includes: a subtraction circuit coupled between the high voltage terminal and the low voltage terminal and generating a subtraction current corresponding to the reference voltage; wherein the current supply circuit generates the pre-charge current to which the subtraction current is applied.

20. The image sensing device according to claim 19, wherein, the subtraction circuit includes: a fifth switch coupled between the reference circuit and a seventh node and operating based on the reference control signal; a capacitor coupled between the seventh node and the low voltage terminal and storing the reference voltage; a second voltage-current converter coupled between the seventh node, the low voltage terminal and an eighth node and generating a stored current corresponding to the reference voltage stored in the capacitor through the eighth node; a sixth switch coupled between the eighth node and a ninth node and operating based on the boost control signal; and a second current mirror coupled between the ninth node, the high voltage terminal and the current supply circuit and providing a subtraction current corresponding to the stored current to the current supply circuit.

Images