Systems and methods for defect inspection in charged particle systems using voltage comparison

Abstract

A system and method are provided for defect inspection using voltage comparison in a charged particle system. Some embodiments of the system and method include: positioning a stage at a first position such that a first beam of a plurality of beams can scan a first surface region of a wafer at a first time to generate a first image associated with the first surface region; positioning the stage at a second position such that a second beam of the plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region; and comparing the first image with the second image to detect whether a defect is identified in the first surface region of the wafer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Application 62 / 950,786, filed December 19, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of using voltage comparison in charged particle beam systems to inspect wafers for defects. Background Technology

[0004] In the manufacturing process of integrated circuits (ICs), incomplete or finished circuit components are inspected to ensure they are manufactured according to the design and free of defects. Inspection systems using optical microscopes typically have a resolution as low as a few hundred nanometers; and this resolution is limited by the wavelength of light. As the physical size of IC components continues to shrink to less than 100 nanometers or even less than 10 nanometers, there is a need for inspection systems with higher resolution than those using optical microscopes.

[0005] Achieving charged particle (e.g., electron) beam microscopy with resolutions as low as less than one nanometer, such as scanning electron microscopy (SEM) or transmission electron microscopy (TEM), serves as a practical tool for inspecting IC components with feature sizes smaller than 100 nanometers. Using SEM, electrons from a single primary electron beam or multiple primary electron beams can be focused onto a location of interest on the wafer to be inspected. The primary electrons interact with the wafer and may be backscattered or may cause the wafer to emit secondary electrons. The intensity of the electron beam, including backscattered and secondary electrons, can vary based on the properties of the wafer's internal and external structures, thus indicating the presence of defects in the wafer. Summary of the Invention

[0006] Embodiments consistent with this disclosure include systems and methods for inspecting wafers using voltage comparison in a charged particle beam system. The system includes a controller comprising circuitry configured to: move a stage at a first speed to a first position such that a first beam of a plurality of beams scans a first surface region of the wafer at a first time interval to generate a first image associated with the first surface region; move the stage at a second speed to a second position such that a second beam of the plurality of beams scans the first surface region at a second time interval to generate a second image associated with the first surface region; detect defects in the first surface region of the wafer based on a comparison of the first and second images; and adjust the time difference between the first and second times intervals by adjusting the speed of the stage, wherein the time difference is greater than zero, and wherein the speed of the stage is greater than zero during the detection period.

[0007] The method for inspection includes: moving a stage to a first position at a first speed such that a first beam of a plurality of beams can scan a first surface region of a wafer at a first time to generate a first image associated with the first surface region; moving the stage to a second position at a second speed such that a second beam of a plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region; detecting defects in the first surface region of the wafer based on a comparison of the first image and the second image; and adjusting the time difference between the first time and the second time by adjusting the speed of the stage, wherein the time difference is greater than zero, and wherein the speed of the stage is greater than zero during the inspection.

[0008] A non-transitory computer-readable medium stores an instruction set executable by at least one processor of a computing device to cause the computing device to perform a method for inspecting a wafer, the method comprising: moving a stage at a first speed to a first position such that a first beam of a plurality of beams can scan a first surface region of the wafer at a first time to generate a first image associated with the first surface region; moving the stage at a second speed to a second position such that a second beam of the plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region; detecting defects in the first surface region of the wafer based on a comparison of the first image and the second image; and adjusting the time difference between the first time and the second time by adjusting the speed of the stage, wherein the time difference is greater than zero, and wherein the speed of the stage is greater than zero during the inspection.

[0009] Additional objects and advantages of the disclosed embodiments will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments. The objects and advantages of the disclosed embodiments may be realized and obtained by the elements and combinations set forth in the claims.

[0010] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and do not limit the disclosed embodiments as claimed. Attached Figure Description

[0011] Figure 1 This is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure.

[0012] Figure 2 This is a schematic diagram illustrating an exemplary multi-beam electronic tool consistent with embodiments of the present disclosure, which may be... Figure 1 It is part of an exemplary EBI system.

[0013] Figure 3This is an exemplary graph showing the yield of secondary electrons relative to the landing energy of primary electrons, consistent with embodiments of this disclosure.

[0014] Figure 4 This is a schematic diagram illustrating the voltage comparison response of a chip consistent with an embodiment of the present disclosure.

[0015] Figure 5 This is an illustration of an exemplary voltage comparison image over a time series, consistent with embodiments of this disclosure.

[0016] Figure 6 This is an illustration of an exemplary voltage comparison image relating to changes in surface potential over a time series, consistent with embodiments of this disclosure.

[0017] Figure 7 This is an illustration of an exemplary multi-beam configuration of a primary sub-beam consistent with embodiments of this disclosure.

[0018] Figure 8 This is an illustration of a multi-beam scanning region on a wafer in a time sequence, consistent with embodiments of this disclosure.

[0019] Figure 9A This is an illustration of a multi-beam scanning region on a wafer in a time sequence, consistent with embodiments of this disclosure.

[0020] Figure 9B This is an illustration of a multi-beam interlaced scanning pattern consistent with embodiments of this disclosure.

[0021] Figure 10 This is a diagram of beam current on a wafer consistent with embodiments of this disclosure.

[0022] Figure 11 This is a flowchart illustrating an exemplary wafer inspection method consistent with embodiments of this disclosure. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise stated, the same numerals in different drawings denote the same or similar elements. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatuses and methods consistent with aspects of the invention as described in the appended claims.

[0024] Electronic devices consist of circuits formed on silicon wafers called substrates. Many circuits can be formed together on the same silicon wafer and are called integrated circuits or ICs. The size of these circuits has been reduced significantly so that more circuits can be assembled on the substrate. For example, the IC chip in a smartphone can be as small as a thumbnail but can include more than 2 billion transistors, each less than 1 / 1000th the size of a human hair.

[0025] Manufacturing these tiny ICs is a complex, time-consuming, and expensive process, typically involving hundreds of individual steps. Even an error in one step can result in a defective IC that is unusable. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process, that is, to improve the overall yield of the process.

[0026] A component of improving yield is monitoring the chip manufacturing process to ensure it produces a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structure during its formation. This can be done using a scanning electron microscope (SEM). SEMs are used to image these extremely small structures, essentially taking "photographs" of them. The images can be used to determine if the structure is formed correctly and in the correct location. If defects are found, the process can be adjusted to make them less likely to recur.

[0027] SEM (Sequencing Electron Microscopy) can obtain images of a wafer that show the internal device structure beneath the area of ​​the wafer being inspected. A single-beam SEM inspection tool can obtain a single image of a wafer area and compare the obtained image with a reference image showing a corresponding device structure without any defects. Differences detected from the image comparison may indicate the presence of defects in the wafer.

[0028] However, single-beam SEM inspection tools are limited. Because the electrical characteristics of a device structure can change over time, capturing a single image at any given point in time may be useless for identifying defects in some devices. That is, some defects may appear in images within a short period of time due to subtle differences from a reference device or due to current sensitivity. For example, due to the time-dependent behavior of some devices, an image captured by a single beam on the first occasion may show differences from a reference image, while another image captured by a single beam on the second occasion may not show any differences from the reference image. Therefore, single-beam SEM inspection tools may not reliably identify defects in the structure of some devices.

[0029] Some single-beam SEM inspection tools can acquire multiple images of the same area of ​​a wafer. Each of these multiple images can be acquired at different times. By comparing multiple images of the same area of ​​the wafer, single-beam SEM inspection tools can identify defects in the wafer. However, acquiring multiple images using single-beam SEM inspection tools also suffers from limitations. In this type of inspection, the time span between each image frame is fixed and long. Due to the long time span between frames (e.g., due to the low rate of image capture), this type of inspection may still fail to capture images of defects (e.g., it may fail to detect changes in electrical properties caused by defects).

[0030] Some embodiments disclosed herein provide systems and methods for addressing some or all of these disadvantages by using multi-beam inspection tools to obtain multiple images of the same region of a wafer more quickly and with controlled timing between images, and to compare multiple images (e.g., Figure 5 Voltage comparison images 534 and 536 are used to identify defects in the wafer. The disclosed embodiments provide systems and methods that can use multiple beams to scan areas of a wafer to generate multiple images of the wafer area, thereby allowing for wafer defect detection and higher production yields.

[0031] Figure 1 A schematic diagram of an exemplary EBI system 100 consistent with embodiments of this disclosure is illustrated. Figure 1 As shown, the EBI system 100 includes a main cavity 10, a load-locking cavity 20, an electron beam tool 40, and a device front-end module (EFEM) 30. The electron beam tool 40 is located within the main cavity 10. Although the specification and drawings relate to electron beams, it should be understood that the embodiments are not intended to limit this disclosure to specific charged particles.

[0032] EFEM 30 includes a first loading port 30a and a second loading port 30b. EFEM 30 may include additional loading ports. The first loading port 30a and the second loading port 30b may, for example, receive a front-opening wafer transfer cassette (FOUP) containing wafers (e.g., semiconductor wafers or wafers made of other materials) or samples to be inspected (wafers and samples are collectively referred to as “wafers”). One or more robotic arms (not shown) in EFEM 30 transport the wafers to the load-locking cavity 20.

[0033] The load-locked chamber 20 can be connected to a load-locked vacuum pump system (not shown), which removes gas molecules from the load-locked chamber 20 to achieve a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) transport the wafer from the load-locked chamber 20 to the main chamber 10. The main chamber 10 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules from the main chamber 10 to achieve a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by an electron beam tool 40. The electron beam tool 40 may include a multi-beam electron inspection tool.

[0034] The controller 50 is electrically connected to the electronic beam tool 40. The controller 50 may be a computer configured to perform various controls of the EBI system 100. Although the controller 50 is... Figure 1 The structure shown is separate from the main cavity 10, load locking cavity 20, and EFEM 30; however, it should be understood that the controller 50 may be part of this structure. Although this disclosure provides an example of a main cavity 10 for housing an electron beam inspection tool, it should be noted that aspects of this disclosure are, in their broadest sense, not limited to the chamber housing an electron beam inspection tool. Rather, it should be understood that the above principles can also be applied to other tools operating under a second pressure.

[0035] Figure 2 The illustration shows an exemplary multi-beam electron beam tool 40 (also referred to herein as apparatus 40) consistent with embodiments of the present invention and can be configured for use in EBI system 100 ( Figure 1 A schematic diagram of the image processing system 290 used in the ).

[0036] The electron beam tool 40 includes an electron source 202, a bore 204, a condenser lens 206, a primary electron beam 210 emitted from the electron source 202, a source conversion unit 212, multiple sub-beams 214, 216, and 218 of the primary electron beam 210, a primary projection optics system 220, a motorized wafer stage 280, a wafer holder 282, multiple secondary electron beams 236, 238, and 240, a secondary optics system 242, and an electronic inspection device 244. The primary projection optics system 220 may include a beam splitter 222, a deflection scanning unit 226, and an objective lens 228. The electronic inspection device 244 may include inspection sub-regions 246, 248, and 250.

[0037] The electronic source 202, the gun hole 204, the condenser lens 206, the source conversion unit 212, the beam splitter 222, the deflection scanning unit 226, and the objective lens 228 can be aligned with the main optical axis 260 of the device 40. The secondary optical system 242 and the electronic detection device 244 can be aligned with the secondary optical axis 252 of the device 40.

[0038] Electron source 202 may include a cathode, extractor, or anode, wherein primary electrons may be emitted from the cathode and extracted or accelerated to form a primary electron beam 210 with a cross (virtual or real) 208. The primary electron beam 210 can be visualized as being emitted from the cross 208. A bore 204 may block peripheral electrons of the primary electron beam 210 to reduce the Coulomb effect. The Coulomb effect may lead to an increase in the size of the detection point.

[0039] Source conversion unit 212 may include an imaging element array and a beam-limiting aperture array. The imaging element array may include an array of micro-deflectors or microlenses. The imaging element array can form multiple parallel images (virtual or real) at an intersection 208 with multiple sub-beams 214, 216, and 218 of the primary electron beam 210. The beam-limiting aperture array can limit the multiple sub-beams 214, 216, and 218. Although Figure 2 Three sub-bundles 214, 216, and 218 are shown, but embodiments of this disclosure are not limited thereto. For example, in some embodiments, the apparatus 40 may be configured to generate a first number of sub-bundles. In some embodiments, the first number of sub-bundles may be in the range of 1 to 1000. In some embodiments, the first number of sub-bundles may be in the range of 200 to 500. In an exemplary embodiment, the apparatus 40 may generate 400 sub-bundles.

[0040] The condenser lens 206 can focus the primary electron beam 210. The currents of the sub-beams 214, 216, and 218 downstream of the source conversion unit 212 can be changed by adjusting the focusing capability of the condenser lens 206 or by changing the radial dimensions of the corresponding beam-limiting apertures within the beam-limiting aperture array. The objective lens 228 can focus the sub-beams 214, 216, and 218 onto the wafer 230 for imaging, and can form multiple detection points 270, 272, and 274 on the surface of the wafer 230.

[0041] Beam splitter 222 can be a Wien filter-type beam splitter that generates electrostatic and magnetic dipole fields. In some embodiments, if applied, the force exerted by the electrostatic dipole field on the electrons of sub-beams 214, 216, and 218 on the electrons can be equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the electrons. Sub-beams 214, 216, and 218 can therefore pass directly through beam splitter 222 with zero deflection. However, the total dispersion of sub-beams 214, 216, and 218 generated by beam splitter 222 can also be non-zero. Beam splitter 222 can separate secondary electron beams 236, 238, and 240 from sub-beams 214, 216, and 218 and guide secondary electron beams 236, 238, and 240 toward secondary optical system 242.

[0042] The deflection scanning unit 226 can deflect sub-beams 214, 216, and 218 to scan detection points 270, 272, and 274 over the surface region of wafer 230. In response to the incident of sub-beams 214, 216, and 218 at detection points 270, 272, and 274, secondary electron beams 236, 238, and 240 can be emitted from wafer 230. The secondary electron beams 236, 238, and 240 can include electrons with an energy distribution including secondary electrons (energy ≤ 50 eV) and backscattered electrons (energy between 50 eV and the landing energy of sub-beams 214, 216, and 218). The secondary optical system 242 can focus the secondary electron beams 236, 238, and 240 onto detection sub-regions 246, 248, and 250 of the electron detection device 244. The detection sub-regions 246, 248 and 250 can be configured to detect the corresponding secondary electron beams 236, 238 and 240 and generate corresponding signals (e.g., voltage, current, etc.), which are used to reconstruct an image of the surface region of the wafer 230.

[0043] The generated signals can represent the intensity of the secondary electron beams 236, 238, and 240, and can be provided to an image processing system 290 that communicates with the electronic detection device 244, the main projection optics system 220, and the motorized wafer stage 280. The movement speed of the motorized stage 280 can be adjusted to adjust the time interval between successive beam scans of a region on the wafer 230. Because different materials on the wafer 230 have different resistivity-capacitance characteristics, the time interval may need to be adjusted, thus exhibiting different sensitivities to imaging timing. In some embodiments, the controller 50 can enable the motorized stage 280 to continuously move the wafer 230 at a constant speed in one direction. In other embodiments, the controller 50 can enable the motorized stage 280 to change the movement speed of the wafer 230 over time depending on the steps of the scanning process. Continuous movement of the stage 280 can be consistent with positioning the stage 280 at various locations so that different beams can scan specific surface areas of the wafer 230 at different times.

[0044] The intensities of the secondary electron beams 236, 238, and 240 can vary depending on the external or internal structure of the wafer 230, and thus can indicate whether the wafer 230 contains defects. Furthermore, as discussed above, sub-beams 214, 216, and 218 can be projected onto different locations on the top surface of the wafer 230, or onto different sides of the wafer 230 at specific locations, to generate secondary electron beams 236, 238, and 240 of varying intensities. Therefore, by mapping the intensities of the secondary electron beams 236, 238, and 240 to regions of the wafer 230, the image processing system 290 can reconstruct an image reflecting characteristics of the internal or external structure of the wafer 230.

[0045] In some embodiments, the image processing system 290 may include an image acquirer 292, a storage device 294, and a controller 296. The image acquirer 292 may include one or more processors. For example, the image acquirer 292 may include a computer, server, mainframe, terminal, personal computer, any kind of mobile computing device, or a combination thereof. The image acquirer 292 may be communicatively coupled to the electronic inspection device 244 of the electron beam tool 40 via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, the Internet, wireless network, wireless radio, or a combination thereof. In some embodiments, the image acquirer 292 may receive signals from the electronic inspection device 244 and may construct an image. The image acquirer 292 may thus acquire an image of the wafer 230. The image acquirer 292 may also perform various post-processing functions, such as generating contours, overlaying indicators on the acquired image, etc. The image acquirer 292 may be configured to perform adjustments to the brightness and contrast of the acquired image. In some embodiments, storage device 294 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer-readable storage, etc. Storage device 294 may be coupled to image acquirer 292 and can be used to save scanned raw image data as raw images and post-processed images. Image acquirer 292 and storage device 294 may be connected to controller 296. In some embodiments, image acquirer 292, storage device 294, and controller 296 may be integrated together into a single control unit.

[0046] In some embodiments, the image acquirer 292 may acquire one or more images of the wafer based on imaging signals received from the electronic inspection device 244. The imaging signals may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image comprising multiple imaging regions. The single image may be stored in the storage device 294. The single image may be an original image that can be divided into multiple regions. Each region may include an imaging region containing features of the wafer 230. The acquired images may include multiple images of a single imaging region of the wafer 230 sampled multiple times over a time series. The multiple images may be stored in the storage device 294. In some embodiments, the image processing system 290 may be configured to perform image processing steps using multiple images of the same location on the wafer 230.

[0047] In some embodiments, the image processing system 290 may include measurement circuitry (e.g., an analog-to-digital converter) to obtain the distribution of detected secondary electrons. Electron distribution data collected during the detection time window, combined with corresponding scan path data of sub-beams 214, 216, and 218 incident on the wafer surface, can be used to reconstruct an image of the wafer structure to be inspected. The reconstructed image can be used to reveal various features of the internal or external structure of the wafer 230, and thus can be used to reveal any defects that may be present in the wafer.

[0048] Figure 3 An exemplary graph consistent with embodiments of this disclosure is illustrated, showing the yield of secondary electrons relative to the landing energy of the primary electron sub-beam. The graph illustrates multiple sub-beams of the primary electron beam (e.g., Figure 2 The landing energy of the primary electron beam 210 and its multiple sub-beams 214, 216 and 218) versus the secondary electron beam (e.g., Figure 2 The relationship between the yields of the secondary electron beams (236, 238, and 240) is shown. Yield indicates the number of secondary electrons generated in response to the influence of primary electrons. For example, a yield greater than 1.0 indicates that more secondary electrons can be generated than the number of primary electrons that have landed on the wafer. Similarly, a yield less than 1.0 indicates that fewer secondary electrons can be generated in response to the influence of primary electrons.

[0049] like Figure 3 As shown in the diagram, when the landing energy of primary electrons is in the range of E1 to E2, more electrons may leave the wafer surface than land on it, which can result in a positive potential at the wafer surface. In some embodiments, defect inspection can be performed within the aforementioned landing energy range, which is referred to as "positive mode." This is because the inspection equipment (e.g., Figure 2 The detection device 244 may receive fewer secondary electrons (see [reference]). Figure 4 ), electron beam tools (e.g., Figure 2 The multi-beam electron beam tool 40 can generate darker voltage contrast images of device structures with more positive surface potentials.

[0050] When the landing energy is below E1 or above E2, fewer electrons may leave the wafer surface, resulting in a negative potential at the wafer surface. In some embodiments, defect inspection can be performed within this landing energy range, which is referred to as "negative mode." Electron beam tools (e.g., Figure 2 A multi-beam electron beam tool 40 can generate brighter voltage contrast images of device structures with more negative surface potentials, and detection devices (e.g., Figure 2 The detection device 244 may receive a large number of secondary electrons (see [reference]). Figure 4 ).

[0051] In some embodiments, the landing energy of the primary electron beam can be controlled by the total bias voltage between the electron source and the wafer.

[0052] Figure 4 The illustration shows a schematic diagram of the voltage contrast response of a wafer consistent with embodiments of the present disclosure. In some embodiments, a voltage contrast method using a charged particle inspection system can be used to detect physical and electrical defects in a wafer (e.g., resistive short circuits and open circuits, defects in deep trench capacitors, back-end process (BEOL) defects, etc.). Defect detection using voltage contrast imaging can utilize a pre-scanning process (i.e., charging, overflow, neutralization, or preparation process) in which charged particles are applied to the wafer (e.g., Figure 2 The area of ​​the chip 230 is to be inspected before the inspection is carried out.

[0053] In some embodiments, by using multiple sub-beams of the primary electron beam (e.g., Figure 2 The primary electron beam 210 contains multiple sub-beams 214, 216, and 218) that irradiate a wafer, and the wafer's voltage contrast response to the irradiation is measured. The electron beam tool (e.g., Figure 2 The multi-beam electron beam tool 40 can be used to inspect wafers (e.g., Figure 2 Defects in the internal or external structure of the wafer 230. In some embodiments, the wafer may include a test device region 420 developed on a substrate 410. In some embodiments, the test device region 420 may include a plurality of device structures 430 and 440 separated by an insulating material 450. For example, device structure 430 is connected to the substrate 410. Conversely, device structure 440 is separated from the substrate 410 by an insulating material 450 such that a thin insulating structure 470 (e.g., a thin oxide) exists between device structure 440 and substrate 410.

[0054] Electron beam tools can use multiple sub-beams of a primary electron beam (e.g., Figure 2 The primary electron beam 210 contains multiple sub-beams 214, 216, and 218 that scan the surface of the test device region 420, thereby generating secondary electrons from the surface of the test device region 420 (e.g., ...). Figure 2 The secondary electrons 236, 238, and 240). As explained above, when the landing energy of the primary electron is between E1 and E2 (i.e., Figure 3 When the yield is greater than 1.0, there may be more electrons leaving the wafer surface than landing on the surface, resulting in a positive potential at the wafer surface.

[0055] like Figure 4As shown, a positive potential can accumulate at the surface of the wafer. For example, after an electron beam tool scans the test device region 420 (e.g., during a pre-scan process), because device structure 440 is not connected to an electrical ground in substrate 410, device structure 440 can retain more positive charge, resulting in a positive potential at the surface of device structure 440. Conversely, because the positive charge may be neutralized by electrons supplied by the connection to substrate 410, the application of primary electrons with the same landing energy (i.e., the same yield) to device structure 430 may result in less positive charge remaining in device structure 430.

[0056] Electron beam tools (e.g., Figure 2 The image processing system of the multi-beam electronic beam tool 40 (e.g., Figure 2 The image processing system 290 can generate voltage contrast images 435 and 445 corresponding to device structures 430 and 440, respectively. For example, device structure 430 is short-circuited to ground and may not retain any accumulated positive charge. Therefore, when the primary electron beam lands on the surface of the wafer during inspection, device structure 430 may repel more secondary electrons, resulting in a brighter voltage contrast image. Conversely, because device structure 440 is not connected to the substrate 410 or any other ground, device structure 440 may retain an accumulation of positive charge. This accumulation of positive charge may cause device structure 440 to repel fewer secondary electrons during inspection, resulting in a darker voltage contrast image.

[0057] Electron beam tools (e.g., Figure 2 A multi-beam electron beam retrieval tool (40) can pre-scan the surface of a wafer by supplying electrons to build up a potential on the wafer surface. After pre-scanning the wafer, the electron beam retrieval tool can obtain images of multiple dies within the wafer. Because the dies can include the same device structure, defects can be detected by comparing the differences in voltage contrast images from multiple dies. For example, if the voltage contrast level of one image differs from the voltage contrast levels of other images, the die corresponding to that different voltage contrast level may have a defect, where a mismatch exists in the image. The assumption that the pre-scanning is applied to the wafer is that the surface potential built up on the wafer surface during the pre-scanning will be retained during inspection and remain above the detection threshold of the electron beam retrieval tool.

[0058] However, due to electrical breakdown or tunneling effects, the accumulated surface potential level may change during inspection, making defects undetectable. For example, when a high voltage is applied to a high-resistivity thin device structure (e.g., a thin oxide) such as insulator structure 470, leakage current may flow through the high-resistivity structure, preventing it from functioning as a perfect insulator. This can affect circuit functionality and lead to device defects. Similar leakage current effects can also occur in structures with improperly formed materials or high-resistivity metal layers, such as tungsten plugs and cobalt silicide (e.g., CoSi, CoSi2, Co2Si, Co3Si, etc.) layers between the source or drain regions of a field-effect transistor (FET).

[0059] A defective etching process can leave a thin oxide layer, resulting in an undesirable resistance blockage (e.g., an open circuit) between two structures intended for electrical connection (e.g., device structure 440 and substrate 410). For example, device structures 430 and 440 may be designed to contact substrate 410 and function identically, but due to manufacturing errors, an insulator structure 470 may be present in device structure 440. In this case, the insulator structure 470 may represent a defect that makes it susceptible to breakdown.

[0060] If the insulator 470 is sufficiently thick (e.g., greater than 10 nm), the positive charge accumulated in the device structure 440 may not leak through the insulator structure 470, and the electron beam tool may be able to detect defects by acquiring a single voltage contrast image 445 during inspection and comparing it with a reference voltage contrast image 435. However, if the insulator 470 is thin (e.g., less than 10 nm), the positive charge accumulated in the device structure 440 may decrease over time due to leakage current. As the device structure 440 loses positive charge over time due to leakage current, the voltage contrast level in the device structure 440 may also change from dark to bright over time. Depending on when the electron beam tool captures the image, the electron beam tool may fail to detect any defects from the image because the device structure 440 has a voltage contrast level below the threshold of the detection device. For example, if a single-beam electron beam tool is used to inspect a wafer after the device structure 440 has lost positive charge due to leakage, the single-beam electron beam tool can capture a voltage comparison image 447 that shows no difference from the voltage comparison image 435 (i.e., no difference from a defect-free device structure).

[0061] Multi-beam electron beam tools (e.g., Figure 2 An electron beam tool 40 can be used to detect device defects susceptible to changes in charge accumulated on a wafer over time. For example, a multi-beam electron tool can use multiple sub-beams of a primary electron beam (e.g., Figure 2The primary electron beam 210 comprises multiple sub-beams 214, 216, and 218 to continuously scan the wafer (e.g., Figure 2 The region of the chip 230 including device structure 440. The controller (e.g., Figure 1 The controller 50 may include circuitry for adjusting the holding wafer (e.g., during inspection) Figure 2 The mobile platform of the chip 230 (e.g., Figure 2 The speed of the motorized wafer stage 280 is adjusted to allow for adjustment of the time between each beam scan targeting any given area of ​​the wafer. The circuitry can position the stage at a first location such that a first beam of a plurality of beams can scan a first surface region of the wafer at a first time to generate a first image associated with the first surface region. The circuitry can continuously move the motorized stage to position it at a second location such that a second beam of a plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region. For more information on continuous scanning using a multi-beam apparatus, see U.S. Patent Application No. 62 / 850,461, filed May 20, 2019, entitled “System and Method for Scanning a Sample Using Multi-Beam Inspection Apparatus,” the disclosure of which is incorporated herein by reference in its entirety. It should be noted that positioning the stage at a particular location such that the beams can scan a particular location on the wafer (where the beams land on the wafer) while the stage is in that particular location may or may not include a stationary stage. For example, in continuous scanning mode, when the stage is positioned such that a specific location on the wafer is aligned with a specific beam, the stage can be temporarily positioned only as the stage continuously moves the wafer.

[0062] The circuitry can repeat the above process for the total number of beams used by the multi-beam electronic tool (e.g., 1,000 sub-beams) or any subset of the beams. For example, a 1,000-sub-beam system can consist of a 10 x 100 beam array, where all 10 beams in each of the 100 rows are aligned on a row that overlaps with 10 beams. The circuitry can position the stage to scan 100 locations on the wafer, where each of the 100 locations is scanned by 10 beams in a row that overlaps with that location, such that each location is scanned consecutively by each of the 10 beams in the row that overlaps with that location. Although a particular location in this example is scanned by beams aligned in a row, the beams do not need to be aligned. For example, because the beams can be deflected by beam deflectors so that misaligned beams consecutively scan the same location on the wafer, misaligned beams can scan the same location. In some embodiments, the multi-beam electronic beam tool can be configured such that different or overlapping areas of the wafer can be scanned simultaneously. In this example, the first surface region may include device structure 440. The circuitry can construct voltage contrast images of the generated images based on detection data obtained from the detector. The circuitry can then compare the voltage contrast level of each voltage contrast image of the first surface region with any other voltage contrast level of the voltage contrast images, and with the voltage contrast level of a reference voltage contrast image, to detect differences between the voltage contrast levels (i.e., detect defects in the first surface region of the wafer). The above process can be applied to any of the multiple surface regions on the wafer.

[0063] For example, regarding structure 440, the first beam can generate a voltage contrast image 445, the second beam can generate a voltage contrast image 446, and the third beam can generate a voltage contrast image 447. Advantageously, a multi-beam electronic beam tool can generate multiple images of device structure 440 over one or more time series and compare those images with each other to enable the detection of defects in device structure 440. Furthermore, the controller includes circuitry for adjusting the speed of the motorized stage or the time interval between consecutive scans of any particular location on the wafer by each of the multiple beams. Detectors (e.g., Figure 2 The detection device 244 can be configured to: detect multiple secondary charged particles (e.g., ...) associated with multiple sub-beams of the primary electron beam impacting the first surface region. Figure 2 The detection of the secondary electron beams (236, 238, and 240) generates detection data.

[0064] Furthermore, in some embodiments, the circuitry can position the stage of the electron beam tool at a pre-scan position before positioning it at the first position, allowing a high-current beam to charge the first surface region during the pre-scan time prior to the first time by supplying electrons to build a potential on the wafer surface. Charging can occur until device breakdown occurs. After charging the wafer, the electron beam tool can generate an image of the first surface region. In some embodiments, the first, second, and several other sub-beams can be low-current beams. In other embodiments, the electron beam tool can gradually charge the wafer using low-energy primary electrons without inducing a breakdown effect during the charging phase. In other embodiments, the detection tool can sample and generate voltage contrast images simultaneously with the charging process, allowing instantaneous voltage contrast changes to be obtained during charging.

[0065] Those skilled in the art will understand that the bright and dark appearance of an image can be altered or reversed depending on the actual processing of the test structure or the setting of the electron beam tool.

[0066] Figure 5 An exemplary voltage comparison image over a time series, consistent with embodiments of the present disclosure, is illustrated. In some embodiments, the wafer inspection process may include a pre-scan phase 501 and an inspection phase 503. During the pre-scan phase 501, an electron beam tool (e.g., Figure 2 A multi-beam electron beam tool 40 applies electrons to the surface of a wafer to build up a potential on the wafer surface. As explained above, an EBI system (e.g., Figure 1 The EBI system 100 can use one or more high-current beams during pre-scanning to charge the surface regions of the wafer and construct voltage contrast images of the surface regions. During inspection phase 503, in some embodiments, the EBI system can use multiple beams in a continuous scan mode over one or more time series to construct multiple voltage contrast images of the surface regions of the wafer. As described above, the holding position of the wafer (e.g., ...) can be adjusted throughout the continuous scan. Figure 2 The mobile platform of the chip 230 (e.g., Figure 2 The speed of the motorized stage 280 is adjusted so that the length of each time series can be different. The EBI system can detect changes in the potential on the wafer over time by comparing multiple voltage contrast images of the same surface area of ​​the wafer at different times, which can indicate the presence of device defects.

[0067] like Figure 5 As shown, the voltage contrast image can be constructed by an EBI system. For example, a motorized stage can position the wafer so that the primary electron beam (e.g., Figure 2 The first sub-beam of the primary electron beam (210) can be generated at time T.pre1 The surface area of ​​the pre-scanned wafer. The motorized stage can continuously move the wafer so that the second sub-beam of the primary electron beam can be scanned at time T. pre2 The same surface area of ​​the pre-scanned wafer. In T pre1 and T pre2 The potential of the surface region may not be high enough to show any detectable voltage contrast area, as shown in voltage contrast images 510 and 512 constructed using the first and second sub-beams, respectively. The motorized stage can be continuously moved through the end of the pre-scan stage 501 to position the wafer so that the third sub-beam of the primary electron beam can be positioned at time T. pre3 The surface area of ​​the pre-scanned wafer. A voltage contrast image 514 can be constructed using a third sub-beam. As shown in the voltage contrast image 514, dark voltage contrast (DVC) regions 560a, 562a, and 564a may appear at the end of the pre-scan stage 501.

[0068] In other embodiments, the electron beam tool may skip the pre-scanning phase 501 and begin the inspection process in inspection phase 503 for detecting wafer defects. In such an embodiment, once the inspection process is initiated, the electron beam tool can begin continuous scanning. Because a high-current beam is not used to charge the wafer surface in this embodiment, the scanning during inspection phase 503 can be used to gradually build up charge on the wafer surface during inspection.

[0069] The motorized stage can move continuously so that after the pre-scanning phase 501, the fourth, fifth, sixth, seventh, eighth, or more sub-beams of the primary electron beam can scan the same pre-charged surface region of the wafer at times t1, t2, t3, t4, and t5, respectively. Figure 5 As shown, the electron beam tool can use fourth, fifth, sixth, seventh, and eighth sub-beams to construct voltage contrast images 530, 532, 534, 536, and 538, respectively. Although this example illustrates the use of eight or more sub-beams, it should be understood that fewer than eight sub-beams can be used. For example, it can be understood that a single sub-beam can capture multiple images of a surface area.

[0070] At time t l Voltage contrast image 530 shows three DVC regions 560a, 562a, and 564a present on the surface region of the wafer. DVC regions 560a, 562a, and 564a can represent the surface potential accumulated in the device structure of the surface region after pre-scanning. At times t2 and t3, voltage contrast images 532 and 534 show DVC regions 560a, 562a, and 564a, which can indicate that the accumulated positive charge remains in the device structure, and from time T... pre3 There is no change from t1.

[0071] At times t4 and t5, voltage contrast images 536 and 538 show that the DVC region 562a disappears while the DVC regions 560a and 564a remain, indicating that the corresponding device structure for the DVC region 562a may have lost the accumulated positive charge due to leakage current, resulting in the surface potential of the DVC region 562a dropping to an undetectable level (i.e., breakdown effect). For example, the positive charge accumulated at the corresponding device structure of the DVC region 562a may be neutralized due to device breakdown thin device structure defects (e.g., see Figure 4 the insulator structure 470).

[0072] The electron beam tool can adjust the time interval (e.g., the time span between t1 and t2) so that the sub-beams of the primary electron beam can scan the surface area of the wafer more or less frequently. For example, the time interval can be as short as 5 ns to obtain signal differences from subtle voltage contrast defects, thereby improving the sensitivity of voltage contrast wafer inspection. Advantageously, the electron beam tool can compare voltage contrast images 510, 512, 514, 530, 532, 534, 536, 538 or more images of the same surface area of the wafer to detect changes in the DVC region over time and identify device structure defects.

[0073] Although Figure 5 illustrates three pre-scan voltage contrast images and five inspection voltage contrast images obtained from the electron beam tool, it should be understood that any number of images can be used to detect device structure defects in the wafer. Additionally, although Figure 5 the voltage contrast images shown in

[0074] Figure 6 illustrate a detection mechanism using dark voltage contrast, it should be understood that bright voltage contrast can also be used when the electron beam tool is operating in the negative mode. For example, in some embodiments, since the electron beam tool is operating in the positive mode (e.g., E1 < landing energy < E2), the wafer can have a positive surface potential. In other embodiments, since the electron beam tool is operating in the negative mode (e.g., landing energy < E1 or landing energy > E2), the wafer can have a negative potential. Figure 4The device structure 440 is used. The potential at the surface of the wafer can be gradually increased from time zero to potential 610, until at t break1 Breakdown occurs because the potential levels at times t1, t2, t3, and t4 are higher than those of the detector (e.g., ...). Figure 2 The threshold voltage 615 of the detection device 244 means that the three DVC regions 640, 642, and 644 can appear in the voltage comparison images 630, 632, 634, and 636. When at time t... break1 When breakdown occurs, the potential may drop to approximately zero. As a result, the potential falls below the threshold voltage 615 at time t5, causing the DVC region 642 to disappear in the voltage contrast image 638. Advantageously, an electron beam tool can identify defects in the wafer by comparing the voltage contrast image 638 with voltage contrast images 630, 632, 634, and 636.

[0075] Figure 7 An exemplary multi-beam configuration of a primary sub-beam consistent with embodiments of this disclosure is illustrated. Figure 7 As shown, the primary sub-beams of a 3×3 multi-beam array generating nine detection points 701, 702, ..., 709 can be arranged in a 3×3 matrix configuration. The 3×3 multi-beam array can be used in inspection systems that can operate in continuous scanning mode (e.g., Figure 1 In the EBI system 100). Similar to earlier embodiments, the controller (e.g., Figure 1 The controller 50) may include a mechanism for adjusting the holding wafer (e.g., Figure 2 The mobile platform of the chip 230 (e.g., Figure 2The circuitry relates to the speed of the motorized wafer stage 280. For example, the wafer can move at a speed K in the y-direction while different regions of the wafer are simultaneously scanned by probe points 701-709 in a 3×3 array. The speed of the motorized stage can be adjusted throughout the continuous scanning process so that the time between each beam scan of any region on the wafer can be different. In some embodiments, the primary sub-beams of the 3×3 array can be rotated by an angle relative to the wafer movement direction, for example, so that the beam scan does not overlap with any pixels due to the offset of the beam scan in the X-dimensional. In some embodiments, probe points 701-709 can scan the wafer in a direction perpendicular to the wafer movement direction. For example, probe points 701-709 can scan in the x-direction as illustrated by arrows 721-729 while the wafer moves in the y-direction. In some embodiments, probe points 701-709 can scan the wafer in a direction parallel to the wafer movement direction. For example, probe points 701-709 can move in the y-direction as illustrated by arrows 731-733 while the wafer also moves in the y-direction. In such an embodiment, the scan width of the primary sub-beam can be unrestricted by the configuration of the primary sub-beam (e.g., pitch or rotation angle).

[0076] In some embodiments, the scanning direction of probe points 701-709 is parallel to the wafer movement direction. In such embodiments, each probe point scans multiple scan portions positioned along the wafer movement direction. For example, the first row of scan portions (e.g., Figure 8 Surface area 810; Figure 9A Row A can be scanned by primary sub-beams corresponding to detector points 701, 702, and 703. Similarly, the second row scan portion (e.g., Figure 9A Row B can be scanned by the primary sub-beams corresponding to detector points 704, 705, and 706, and the third row scan portion (e.g., Figure 9A The C-row can be scanned by primary sub-beams corresponding to probe points 707, 708, and 709. It should be understood that any other scanning method can be used to scan each scanned portion. For example, in some embodiments, probe points 701-703 can be scanned and backtracked in opposite directions (e.g., scanned from right to left and backtracked from left to right).

[0077] In some embodiments, some scanned portions (e.g., Figure 8 The surface region 810 can be generated by the same set of beams (e.g., Figure 8 Sub-bundles 802, 804, and 806 are scanned continuously. These regions can be scanned two or more times by one or more sub-bundles. For example, in continuous scan mode, the region in the first row ( Figure 9ASpecific locations within wafer region 913 (row A) can be continuously scanned by probe points 701, 702, and 703. The controller (e.g., Figure 1 The controller 50; Figure 2 The controller 296 can collect scan data, including multiple scan data from each overlapping region, and process the scan data to generate a continuous image of the wafer for inspection.

[0078] In some embodiments, the scanning and repositioning steps can occur simultaneously with continuous wafer movement. In such embodiments, the movement of the probe point can be adjusted to accommodate the continuous movement of the wafer. For example, since the wafer is also moving in the same direction, the scan path can be lengthened. Because the wafer is moving in the opposite direction to the tracing direction (e.g., by the time probe point 701 traverses to the left, the wafer may have already been moved further to the right), the tracing path can be shortened.

[0079] As described with respect to earlier embodiments, in some embodiments, the controller can control the movement of the primary sub-beam and the motorized stage so that the primary sub-beam can repeat the movement pattern. By controlling the speed of scanning, backtracking, repositioning, and the movement of the motorized stage, the probe point can continuously repeat various movement patterns.

[0080] Although Figure 7 The illustration shows a primary sub-bundle with nine detector points 701-709 arranged in a 3×3 matrix. However, it should be understood that the principles disclosed herein can be applied to any number and arrangement of primary sub-bundles, such as primary sub-bundles arranged in a 3×2, 4×4, 5×5, 3×5, 8×5, 20×20 or any size matrix configuration.

[0081] Figure 8 The illustration depicts a multi-beam scanning region on a wafer in a time series, consistent with embodiments of this disclosure. Multi-beam electron beam tools (e.g., Figure 2 The multi-beam electron beam tool 40 can use multiple sub-beams of the primary electron beam (e.g., multiple sub-beams 214, 216, and 218 of the primary electron beam 210) to inspect wafers (e.g., ...). Figure 2 Defects in the chip 230. For example, multiple sub-bundles may include a first sub-bundle 802, a second sub-bundle 804, and a third sub-bundle 806. A motorized stage (e.g., Figure 2 The motorized stage 280 can position the wafers such that sub-bundles 802, 804, and 806 are aligned in a row. During inspection, the controller (e.g., Figure 1The controller 50 may include circuitry for adjusting the speed of the motorized stage holding the wafer so that the wafer can move continuously, so that the surface area 810 of the wafer can be scanned once or multiple times by sub-beam 802 at t1, by sub-beam 804 at t2, and by sub-beam 806 at t3, and therefore the times t1, t2, or t3 can be different. Figure 8 This example is represented as a vertical slice, starting from the bottom, where sub-beam 802 scans a specific location on surface region 810 at time t1, sub-beam 804 scans the same specific location at time t2, and sub-beam 806 scans the same specific location at time t3. As explained above, the electron beam tool can construct voltage contrast images of surface region 810 corresponding to each sub-beam 802, 804, and 806. Advantageously, the electron beam tool can identify defects in surface region 810 by comparing the voltage contrast images corresponding to each of sub-beams 802, 804, and 806. While this example illustrates at least one sub-beam of sub-beams 802, 804, and 806 at the depicted interval from time t1 to time t... 11 The wafer is scanned, but it should be understood that the time interval can be adjusted by changing the speed of the motorized stage throughout the continuous scanning process, so that the frequency of the sub-beam scanning wafer is higher or lower than the required frequency. Figure 8 The frequencies described in the text. For example, it should be understood that a single sub-beam can capture multiple images of a surface area.

[0082] Figure 9A The illustration shows a multi-beam scanning region on wafer 900 in a time series, consistent with embodiments of this disclosure. Similar to... Figure 8 Multi-beam electronic beam tools (e.g., Figure 2 The multi-beam electron beam tool 40 can use multiple sub-beams of the primary electron beam (e.g., multiple sub-beams 214, 216, and 218 of the primary electron beam 210) in a continuous scan mode to inspect a wafer (e.g., ...). Figure 2 Defects in wafer 230. For example, multiple sub-beams may include a 3×3 beam configuration, wherein the first row A includes sub-beams 902a, 904a, and 906a, the second row B includes sub-beams 902b, 904b, and 906b, and the third row C includes sub-beams 902c, 904c, and 906c. Row A may include wafer regions 911-915, row B may include wafer regions 921-925, and row C may include wafer regions 931-935.

[0083] In some embodiments, a multi-beam electron beam tool can construct one or more voltage contrast images for each of the wafer regions 911-915, 921-925, and 931-935. For example, in continuous scan mode, wafer region 913 can be scanned by sub-beam 902a at time t1, by sub-beam 904a at time t2, and by sub-beam 906a at time t3. Similarly, wafer region 923 can be scanned by sub-beam 902b at time t1, by sub-beam 904b at time t2, and by sub-beam 906b at time t3. Likewise, wafer region 933 can be scanned by sub-beam 902c at time t1, by sub-beam 904c at time t2, and by sub-beam 906c at time t3. As explained above, the electron beam tool can construct a voltage contrast image corresponding to each wafer region in sub-bundles 902a-902c, 904a-904c, and 906a-906c. Advantageously, the electron beam tool can identify defects in one or more wafer regions 911-915, 921-925, and 931-935 by comparing the voltage contrast images corresponding to each sub-bundle. The controller (e.g., Figure 1 The controller 50 may include circuitry for adjusting the motorized stage holding the wafer during inspection (e.g., Figure 2 The speed of the motorized chip stage 280 is adjusted so that times t1, t2, or t3 can be different. Although Figure 9A Lines are provided to represent beam scans offset in the vertical dimension (e.g., sub-beams 902a, 904a, 906a), but this is for illustrative purposes only, and the beams may not be offset in the vertical dimension and may scan the same position on the wafer continuously.

[0084] As explained above, if an electron beam tool can use multiple beams to scan each row multiple times consecutively, images can be generated more frequently. After using multiple beams to scan all areas multiple times consecutively, the image processing system (e.g., Figure 2 The image processing system 290 can reconstruct images by reassembling the scan data generated during each scan. As a result, the electron beam tool using this embodiment can better detect time-related defects in the structure of fast charging or discharging devices.

[0085] although Figure 9A The diagram illustrates a 3×3 beam configuration, but it should be understood that other beam configurations may be used during inspections.

[0086] Figure 9B The illustration shows a multi-beam interlaced scanning pattern 900B consistent with embodiments of this disclosure. Primary sub-beams (e.g., Figure 2Sub-bundles 214, 216, and 218 can be configured to scan the wafer using interlaced scanning patterns in a continuous scan mode (e.g., Figure 2 (Chip 230). For example... Figure 9B As shown, the electron beam tool can control the primary sub-beam so that detector points 910A, 910B, 910C, and 910D can move along scan lines 1-20. For example, detector points 910A and 910B can move along scan lines 1-18, and detector points 910C and 910D can move along scan lines 3-20. These scan lines are substantially parallel to each other. In this configuration, detector points 910A-910D can be moved according to the motion stage holding the wafer (e.g., ...). Figure 2 The motorized stage 280 moves continuously and simultaneously between different scan lines at a speed that allows adjustment of the time between each beam scan for any given area of ​​the wafer.

[0087] Figure 9B The right side shows an exemplary movement trajectory of the probe point relative to an absolute reference frame. The trajectory can be divided into four phases. In phase 1, the probe point follows the movement of the wafer and scans along a first direction. In phase 2, the probe point moves against the direction of wafer movement to reach the starting point of a second scan line. In phase 3, the probe point follows the movement of the wafer and scans along a second direction. In phase 4, the probe point moves against the direction of wafer movement to reach the starting point of a third scan line. These four phases are repeated during interlaced scanning. As explained above, any area of ​​the wafer can be scanned multiple times by any one of the probe points 910A, 910B, 910C, or 910D. For more information on continuous scanning using a multi-beam device, see U.S. Patent Application No. 62 / 850,461. Figure 11 .

[0088] Although Figure 9B The illustration shows a primary sub-bundle with four detector points 910A-910D arranged in a 2×2 matrix. However, it should be understood that the principles disclosed herein can be applied to any number and arrangement of primary sub-bundles, such as primary sub-bundles arranged in a 3×2, 4×4, 5×5, 3×5, 8×5, 20×20 or any size matrix configuration.

[0089] Figure 10 The illustration depicts a beam current on a wafer 1001 consistent with an embodiment of this disclosure. Some materials on wafer 1001 may require multi-beam electronic beam-setting tools (e.g., Figure 2A multi-beam electron beam tool 40 is used to pre-scan at least one area of ​​wafer 1001 to detect defects in those areas. Depending on the material on wafer 1001, the electron beam tool can adjust the current of each sub-beam of the primary electron beam (e.g., primary electron beam 210). The current of each beam can be adjusted directly or indirectly by, for example, adjusting the depth of focus of the beam. For example, sub-beams 1002 and 1004 can be configured as high-current beams for pre-scanning at least one area of ​​wafer 1001, while sub-beams 1003, 1005, and 1006 can be configured as low-current beams for inspecting the same area of ​​wafer 1001. A motorized stage (e.g., holding wafer 1001) is used to hold wafer 1001. Figure 2 The motorized wafer stage 280 can move continuously in direction 1020 during inspection, such that each of the sub-beams 1002-1006 can continuously scan one or more common areas of the wafer 1001. The controller may include circuitry for adjusting the speed of the motorized stage holding the wafer during inspection, such that the time of each beam scan for any given area of ​​the wafer can be adjusted.

[0090] Advantageously, the electron beam tool can identify defects in one or more regions of wafer 1001 by comparing voltage contrast images corresponding to each sub-beam. Although this example illustrates the use of five sub-beams, it should be understood that more or fewer sub-beams may be used. For example, it should be understood that a single sub-beam can capture multiple images of a surface region.

[0091] Figure 11 A flowchart illustrating an exemplary method 1100 for wafer inspection, consistent with embodiments of this disclosure, is shown. Method 1100 can be performed by an EBI system (e.g., Figure 1 The EBI system 100 is executed. The EBI system may include an electron beam tool (e.g., [missing information]) that performs one or more steps of method 1500. Figure 2 Multi-beam electronic beam tool 40).

[0092] In step 1101, a controller (e.g., Figure 1 The EBI system of the controller 50 may include a system for adjusting the holding wafer ( Figure 2 The mobile platform of the chip 230 (e.g., Figure 2 The circuitry for the speed of the motorized stage 280 is configured to position the wafer by continuously moving it to a pre-scan position before positioning the stage at a first position, thereby enabling a high-current beam (e.g., Figure 10 The high-current sub-beam 1002) can be pre-scanned before the first time (e.g., Figure 5In the pre-scan phase 501, a first surface region of the wafer is charged. Charging can occur until device breakdown occurs. After charging the wafer, the EBI system can generate an image of the first surface region. In some embodiments, the EBI system can sample and generate a voltage contrast image while charging is in progress, so that transient voltage contrast changes can be obtained during charging. It should be noted that positioning the wafer at the pre-scan position so that the beam can charge the first surface region of the wafer (where the beam lands) while the stage is in the pre-scan position may or may not include stopping the stage. For example, in continuous scan mode, when the stage is positioned such that the beam is aligned with the first surface region, the stage may only be positioned temporarily as the stage continuously moves the wafer.

[0093] In step 1103, the EBI system may adjust the speed of the motorized stage holding the wafer to continuously move the wafer to a first position, or the motorized stage may be positioned at the first position during modes other than continuous scanning, such that the first beam of a plurality of beams (e.g., Figure 9A Sub-bundle 902a; Figure 10 The low-current sub-beam 1005 is able to scan the first surface region of the wafer in the first instant (e.g., Figure 9A Region 913), to generate a first image associated with the first surface region (e.g., region ... Figure 5 Image 530). The EBI system can be based on the detector (e.g., image 530). Figure 2 The detection data obtained by the detection device 244 is used to construct a voltage contrast image of the generated image. An example of a mode other than continuous scanning is a step-scan mode, in which the motorized stage positions the wafer at a first position, then scans the field of view while the wafer is in the first position, then the motorized stage positions the wafer at a second position, and then scans a new field of view while the wafer is in the second position.

[0094] In step 1105, the EBI system may adjust the speed of the motorized stage holding the wafer to continuously move the wafer to the second position, or the motorized stage may be positioned at the second position during modes other than continuous scanning, such that the second beam of multiple beams (e.g., Figure 9A Sub-bundle 904a; Figure 10 The low-current sub-beam 1006 is able to scan the first surface region of the wafer in the second time (e.g., Figure 9A Region 913), to generate a second image associated with the first surface region (e.g., region ... Figure 5 Image 536). The EBI system can construct a voltage contrast image of the generated image based on the detection data obtained from the detector.

[0095] In step 1107, the EBI system can compare the voltage contrast level of each voltage contrast image of the first surface region with any other voltage contrast level of the voltage contrast images to detect differences between the voltage contrast levels for the purpose of identifying any defects in the first surface region of the wafer. Method 1100 can be applied to any of the multiple surface regions on the wafer. Advantageously, the EBI system can identify defects in one or more surface regions of the wafer by comparing voltage contrast images corresponding to each sub-bundle in the sub-bundle.

[0096] In any of the above steps, the controller can adjust the speed of the motorized stage holding the wafer, thereby adjusting the time for each scan of any given area of ​​the wafer.

[0097] The embodiments may be further described using the following terms:

[0098] 1. A charged particle multi-beam system for generating multiple beams for inspecting a wafer positioned on a stage, the system comprising:

[0099] The controller includes circuitry configured to:

[0100] The stage is positioned at a first position so that the first beam of the plurality of beams can scan the first surface area of ​​the wafer at a first time to generate a first image associated with the first surface area.

[0101] The stage is positioned at a second location such that the second beam of the plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region; and

[0102] The first image is compared with the second image so that it is possible to detect whether a defect is identified in the first surface region of the wafer.

[0103] 2. The system according to Clause 1, wherein the wafer includes a plurality of surface regions.

[0104] 3. The system according to any one of Clauses 1-2, wherein the first image and the second image indicate voltage contrast levels.

[0105] 4. The system according to Clause 3, wherein the controller includes circuitry for detecting a difference between the voltage contrast levels of the first image and the voltage contrast levels of the second image.

[0106] 5. The system according to any one of Clauses 1-4, wherein the controller includes circuitry for adjusting the time interval between the first time and the second time.

[0107] 6. The system according to Clause 5, wherein adjusting the time interval between the first time and the second time includes adjusting the speed of the stage.

[0108] 7. The system according to any one of clauses 1-6 further includes:

[0109] A detector, communicatively coupled to a controller, is configured to generate detection data based on the detection of multiple secondary charged particles associated with a first and second beams impacting a first surface region.

[0110] 8. The system according to any one of Clauses 1-7, wherein:

[0111] The controller includes circuitry configured to:

[0112] The stage is positioned at a third position so that the third beam of the plurality of beams can scan the first surface region at a third time to generate a third image associated with the first surface region; and

[0113] The third image is compared with the first or second image to enable the detection of whether a defect is identified in the first surface region of the wafer.

[0114] 9. The system according to Clause 8, wherein the controller includes circuitry for adjusting the time interval between each of the first time, the second time, and the third time.

[0115] 10. The system according to Clause 9, wherein adjusting the time interval between each of the first time, the second time, and the third time includes adjusting the speed of the stage.

[0116] 11. The system according to any one of clauses 8-10, wherein the third image indicates the voltage contrast level.

[0117] 12. The system according to Clause 11, wherein the controller includes circuitry configured to detect differences between voltage contrast levels of a first image, a second image, and a third image.

[0118] 13. The system according to any one of clauses 7-12, wherein:

[0119] The detector is configured to generate detection data based on the detection of multiple secondary charged particles associated with the first, second, and third beams that impact the first surface region.

[0120] 14. The system according to any one of clauses 8-13, wherein the first beam, the second beam and the third beam are low-current beams.

[0121] 15. The system according to any one of clauses 8-14, wherein the first beam has a first current, and the second and third beams have a second current different from the first current.

[0122] 16. The system according to any one of clauses 8-14, wherein the first beam and the second beam have a first current, and the third beam has a second current different from the first current.

[0123] 17. The system according to any one of clauses 1-16, wherein the controller comprises being configured to:

[0124] Before positioning the stage at the first position, the stage is positioned at the pre-scan position so that the high-current beam can charge the first surface region during the pre-scan time prior to the first time.

[0125] 18. The system as described in Clause 17, wherein a device malfunction occurs during charging.

[0126] 19. The system according to any one of Clauses 1-18, wherein the defect includes an electrical defect associated with leakage current.

[0127] 20. The system according to any one of clauses 11 and 12, wherein the controller includes circuitry configured to: construct a first voltage comparison image, a second voltage comparison image, and a third voltage comparison image corresponding to the first image, the second image, and the third image based on detection data generated by the detector.

[0128] 21. The system according to any one of clauses 1-7, wherein:

[0129] The controller includes circuitry configured to:

[0130] The stage is positioned at a first position so that the third beam among the multiple beams can scan the second surface region of the wafer at a first time to generate a third image associated with the second surface region.

[0131] The stage is positioned at a second position so that the fourth beam of the plurality of beams can scan the second surface region of the wafer at a second time to generate a fourth image associated with the second surface region; and

[0132] The third image is compared with the fourth image to enable the detection of whether a defect is identified in the second surface region of the wafer.

[0133] 22. The system according to Clause 21, wherein the third and fourth images indicate voltage contrast levels.

[0134] 23. The system according to Clause 22, wherein the controller includes circuitry configured to detect a difference between the voltage contrast level of the third image and the voltage contrast level of the fourth image.

[0135] 24. The system according to any one of clauses 21-23, wherein:

[0136] The detector is configured to generate detection data based on the detection of multiple secondary charged particles associated with the third and fourth beams that impact the second surface region.

[0137] 25. The system according to Clause 24, wherein the controller includes circuitry configured to construct a third voltage comparison image and a fourth voltage comparison image corresponding to the third image and the fourth image based on detection data generated by the detector.

[0138] 26. The system according to any one of clauses 1-25, wherein positioning the stage at a first position and a second position involves continuous movement of the stage.

[0139] 27. The system according to any one of clauses 1-26, wherein the beam current of each of the plurality of beams is constant during inspection.

[0140] 28. A method for generating multiple beams for inspecting a wafer positioned on a stage, the method comprising:

[0141] The stage is positioned at a first position so that the first beam of the plurality of beams can scan the first surface area of ​​the wafer at a first time to generate a first image associated with the first surface area.

[0142] The stage is positioned at a second location such that the second beam of the plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region; and

[0143] The first image is compared with the second image so that it is possible to detect whether a defect is identified in the first surface region of the wafer.

[0144] 29. The method according to Clause 28, wherein the wafer includes a plurality of surface regions.

[0145] 30. The method according to any one of clauses 28-29, wherein the first image and the second image indicate voltage contrast levels.

[0146] 31. The method according to Clause 30 includes detecting a difference between the voltage contrast level of the first image and the voltage contrast level of the second image.

[0147] 32. The method according to any one of Clauses 28-31, including adjusting the time interval between the first time and the second time.

[0148] 33. The method according to Clause 32, wherein adjusting the time interval between the first time and the second time includes adjusting the speed of the stage.

[0149] 34. The method according to any one of clauses 28-33, comprising:

[0150] A detector, communicatively coupled to the controller, is configured to generate detection data based on the detection of multiple secondary charged particles associated with a first and a second beam impacting the first surface region.

[0151] 35. The method according to any one of clauses 28-34, comprising:

[0152] The stage is positioned at a third position so that the third beam of the plurality of beams can scan the first surface region at a third time to generate a third image associated with the first surface region; and

[0153] The third image is compared with the first or second image to enable the detection of whether a defect is identified in the first surface region of the wafer.

[0154] 36. The method described in Clause 35 includes adjusting the time interval between each of the first time, the second time, and the third time.

[0155] 37. The method according to Clause 36, wherein adjusting the time interval between each of the first time, the second time, and the third time includes adjusting the speed of the stage.

[0156] 38. The method according to any one of clauses 35-37, wherein the third image indicates the voltage contrast level.

[0157] 39. The method according to Clause 38 includes detecting the difference between the voltage contrast levels of a first image, a second image, and a third image.

[0158] 40. The method according to any one of clauses 35-39, wherein:

[0159] The detector is configured to generate detection data based on the detection of multiple secondary charged particles associated with the first, second, and third beams that impact the first surface region.

[0160] 41. The method according to any one of clauses 35-40, wherein the first beam, the second beam, and the third beam are low-current beams.

[0161] 42. The method according to any one of clauses 35-41, wherein the first beam has a first current, and the second and third beams have a second current different from the first current.

[0162] 43. The method according to any one of clauses 35-41, wherein the first beam and the second beam have a first current, and the third beam has a second current different from the first current.

[0163] 44. The method according to any one of clauses 28-43, comprising:

[0164] Before positioning the stage at the first position, the stage is positioned at the pre-scan position so that the high-current beam can charge the first surface region during the pre-scan time prior to the first time.

[0165] 45. The method according to Clause 44, wherein a device malfunction occurs during charging.

[0166] 46. ​​The method according to any one of Clauses 28-45, wherein the defect includes an electrical defect associated with leakage current.

[0167] 47. The method according to any one of clauses 40-43, comprising constructing a first voltage comparison image, a second voltage comparison image, and a third voltage comparison image corresponding to the first image, the second image, and the third image based on detection data generated by the detector.

[0168] 48. The method according to any one of clauses 28-34, comprising:

[0169] The stage is positioned at a first position so that the third beam of the plurality of beams can scan the second surface region of the wafer at a first time to generate a third image associated with the second surface region.

[0170] The stage is positioned at a second position so that the fourth beam of the plurality of beams can scan the second surface region of the wafer at a second time to generate a fourth image associated with the second surface region; and

[0171] The third image is compared with the fourth image to enable the detection of whether a defect is identified in the second surface region of the wafer.

[0172] 49. The method according to Clause 48, wherein the third and fourth images indicate voltage contrast levels.

[0173] 50. The method according to Clause 49 includes detecting the difference between the voltage contrast level of the third image and the voltage contrast level of the fourth image.

[0174] 51. The method according to any one of clauses 48-50, wherein:

[0175] The detector is configured to generate detection data based on the detection of multiple secondary charged particles associated with the third and fourth beams that impact the second surface region.

[0176] 52. The method according to Clause 51 includes constructing a third voltage contrast image and a fourth voltage contrast image corresponding to the third image and the fourth image based on detection data generated by the detector.

[0177] 53. The method according to any one of clauses 28-52, wherein positioning the stage at a first position and a second position involves continuous movement of the stage.

[0178] 54. The method according to any one of clauses 28-53, wherein the beam current of each of the plurality of beams is constant during inspection.

[0179] 55. A non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computing device to cause the computing device to perform a method for generating a plurality of beams for inspecting a wafer positioned on a stage, the method comprising:

[0180] The stage is positioned at a first position so that the first beam of the plurality of beams can scan the first surface area of ​​the wafer at a first time to generate a first image associated with the first surface area.

[0181] The stage is positioned at a second location such that the second beam of the plurality of beams can scan the first surface region at a second time to generate a second image associated with the first surface region; and

[0182] The first image is compared with the second image so that it is possible to detect whether a defect is identified in the first surface region of the wafer.

[0183] 56. The non-transitory computer-readable medium according to Clause 55, wherein the first image and the second image indicate voltage contrast levels.

[0184] 57. A non-transitory computer-readable medium as described in Clause 56, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0185] The difference between the voltage contrast level of the first image and the voltage contrast level of the second image is detected.

[0186] 58. A non-transitory computer-readable medium according to any one of clauses 55-57, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0187] Adjust the time interval between the first and second times.

[0188] 59. The non-transitory computer-readable medium as described in Clause 58, wherein adjusting the time interval between the first time and the second time includes adjusting the speed of the stage.

[0189] 60. A non-transitory computer-readable medium according to any one of clauses 55-59, comprising:

[0190] A detector, communicatively coupled to the controller, is configured to generate detection data based on the detection of multiple secondary charged particles associated with a first and a second beam impacting the first surface region.

[0191] 61. A non-transitory computer-readable medium according to any one of clauses 55-60, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0192] The stage is positioned at a third position so that the third beam of the plurality of beams can scan the first surface region at a third time to generate a third image associated with the first surface region; and

[0193] The third image is compared with the first or second image to enable the detection of whether a defect is identified in the first surface region of the wafer.

[0194] 62. A non-transitory computer-readable medium as described in Clause 61, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0195] Adjust the time interval between each of the first, second, and third times.

[0196] 63. The non-transitory computer-readable medium as described in Clause 62, wherein adjusting the time interval between each of the first time, the second time, and the third time includes adjusting the speed of the stage.

[0197] 64. A non-transitory computer-readable medium according to any one of clauses 61-63, wherein the third image indicates a voltage contrast level.

[0198] 65. A non-transitory computer-readable medium according to any one of clauses 61-64, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0199] The differences in voltage contrast levels between the first image, the second image, and the third image are detected.

[0200] 66. A non-transitory computer-readable medium according to any one of clauses 61-65, wherein:

[0201] The detector is configured to generate detection data based on the detection of multiple secondary charged particles associated with the first, second, and third beams that impact the first surface region.

[0202] 67. A non-transitory computer-readable medium according to any one of clauses 61-66, wherein the first beam, the second beam, and the third beam are low-current beams.

[0203] 68. A non-transitory computer-readable medium according to any one of clauses 61-67, wherein the first beam has a first current, and the second and third beams have a second current different from the first current.

[0204] 69. A non-transitory computer-readable medium according to any one of clauses 61-67, wherein the first beam and the second beam have a first current, and the third beam has a second current different from the first current.

[0205] 70. A non-transitory computer-readable medium according to any one of clauses 55-69, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0206] Before positioning the stage at the first position, the stage is positioned at the pre-scan position so that the high-current beam can charge the first surface region during the pre-scan time prior to the first time.

[0207] 71. The non-transitory computer-readable medium as described in Clause 70, wherein a device failure occurs during charging.

[0208] 72. A nontransitory computer-readable medium according to any one of Clauses 55-71, wherein the defect includes an electrical defect associated with leakage current.

[0209] 73. A non-transitory computer-readable medium as described in Clause 66, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0210] A first voltage comparison image, a second voltage comparison image, and a third voltage comparison image are constructed based on the detection data generated by the detector, corresponding to the first image, the second image, and the third image.

[0211] 74. A non-transitory computer-readable medium according to any one of clauses 55-60, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0212] The stage is positioned at a first position so that the third beam of the plurality of beams can scan the second surface region of the wafer at a first time to generate a third image associated with the second surface region.

[0213] The stage is positioned at a second position so that the fourth beam of the plurality of beams can scan the second surface region of the wafer at a second time to generate a fourth image associated with the second surface region; and

[0214] The third image is compared with the fourth image to enable the detection of whether a defect is identified in the second surface region of the wafer.

[0215] 75. The non-transitory computer-readable medium according to Clause 74, wherein the third image indicates a voltage contrast level and the fourth image indicates a voltage contrast level.

[0216] 76. A non-transitory computer-readable medium as described in Clause 75, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0217] The difference between the voltage contrast levels of the third image and the fourth image is detected.

[0218] 77. A non-transitory computer-readable medium according to any one of clauses 74-76, wherein:

[0219] The detector is configured to generate detection data based on the detection of multiple secondary charged particles associated with the third and fourth beams that impact the second surface region.

[0220] 78. A non-transitory computer-readable medium as described in Clause 77, wherein a set of instructions executable by at least one processor of a computing device causes the computing device to further perform:

[0221] A third voltage comparison image and a fourth voltage comparison image corresponding to the third image and the fourth image are constructed based on the detection data generated by the detector.

[0222] 79. A non-transitory computer-readable medium according to any one of clauses 55-78, wherein positioning the stage at a first position and a second position involves continuous movement of the stage.

[0223] 80. A non-transitory computer-readable medium according to any one of clauses 55-79, wherein the beam current of each of a plurality of beams is constant during inspection.

[0224] 81. A method for inspecting a wafer, the method comprising:

[0225] The time between each scan of pixels on the wafer is adjusted by adjusting the speed of the stage carrying the wafer; and

[0226] Multiple beams are used to scan pixels, with each scan involving different beams of the multiple beams scanning the pixels occurring at different times.

[0227] 82. The method described pursuant to Clause 81 further includes:

[0228] Adjusting the beam current of one of a plurality of beams, wherein scanning of a pixel involves scanning the pixel with the plurality of beam currents.

[0229] 83. The method according to Clause 82, wherein the beam current of each of the plurality of beams remains constant during scanning.

[0230] A non-transitory computer-readable medium consistent with the embodiments in this disclosure may be provided, which stores information for a controller (e.g., Figure 1 Instructions to the processor of the controller 50 are used to control the aforementioned wafer inspection, such as positioning the stage relative to multiple beams, timing the positioning, imaging the wafer area, and determining differences between voltage contrast images. For example, based on the material on the wafer to be inspected, the controller can use circuitry to adjust the current of the sub-beams or the speed of the motorized stage. Common forms of non-transient media include floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, compact disc read-only memory (CD-ROM), any other optical data storage media, any physical media with a perforated pattern, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), FLASH-EPROM or any other flash memory, non-volatile random access memory (NVRAM), cache, registers, any other memory chip or cassette tape and its networked version.

[0231] As used herein, unless expressly stated otherwise, the term "or" covers all possible combinations, unless it is impractical. For example, if a component is stated to include A or B, then unless expressly stated otherwise or it is impractical, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless expressly stated otherwise or it is impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0232] It should be understood that the embodiments of this disclosure are not limited to the exact structures described above and illustrated in the accompanying drawings, and various modifications and changes can be made without departing from its scope. This disclosure has been described in conjunction with various embodiments, and other embodiments of the invention will be apparent to those skilled in the art upon consideration of the specification disclosed herein and the practice of the invention. The specification and examples are intended to be illustrative only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. A charged particle multi-beam system for generating multiple beams for inspecting a wafer positioned on a stage, the system comprising: The controller includes circuitry configured to: The stage is positioned at a first position so that the first beam of the plurality of beams can scan the first surface area of ​​the wafer at a first time to generate a first voltage comparison image associated with the first surface area. The stage is positioned at a second position so that the second beam of the plurality of beams can scan the first surface region at a second time to generate a second voltage comparison image associated with the first surface region. as well as The first voltage comparison image is compared with the second voltage comparison image to enable detection of whether a defect is identified in the first surface region of the wafer.

2. The system of claim 1, wherein the wafer comprises a plurality of surface regions.

3. The system of claim 1, wherein the first voltage comparison image and the second voltage comparison image indicate voltage comparison levels.

4. The system of claim 3, wherein the controller includes circuitry for detecting a difference between the voltage contrast level of the first voltage contrast image and the voltage contrast level of the second voltage contrast image.

5. The system of claim 1, wherein the controller includes circuitry for adjusting the time interval between the first time and the second time.

6. The system of claim 5, wherein adjusting the time interval between the first time and the second time includes adjusting the speed of the stage.

7. The system according to claim 1, further comprising: A detector, communicatively coupled to the controller, is configured to generate detection data based on the detection of a plurality of secondary charged particles associated with the first and second beams impacting the first surface region.

8. The system according to claim 7, wherein: The controller includes a circuit configured to: The stage is positioned at a third position so that the third beam of the plurality of beams can scan the first surface region at a third time to generate a third voltage comparison image associated with the first surface region. as well as The third voltage comparison image is compared with the first voltage comparison image or the second voltage comparison image to enable detection of whether a defect is identified in the first surface region of the wafer.

9. The system of claim 8, wherein the controller includes circuitry for adjusting the time interval between each of the first time, the second time, and the third time.

10. The system of claim 9, wherein adjusting the time interval between each of the first time, the second time, and the third time includes adjusting the speed of the stage.

11. The system of claim 8, wherein each of the first voltage comparison image, the second voltage comparison image, and the third voltage comparison image indicates a voltage comparison level.

12. The system of claim 11, wherein the controller includes circuitry configured to detect a difference between the voltage contrast level of the first voltage contrast image, the voltage contrast level of the second voltage contrast image, and the voltage contrast level of the third voltage contrast image.

13. The system according to claim 8, wherein: The detector is configured to generate detection data based on the detection of a plurality of secondary charged particles associated with the first, second, and third beams impacting the first surface region.

14. The system of claim 8, wherein the first beam, the second beam and the third beam are low-current beams.

15. A non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computing device to cause the computing device to perform a method for generating a plurality of beams for inspecting a wafer positioned on a stage, the method comprising: The stage is positioned at a first position so that the first beam of the plurality of beams can scan the first surface area of ​​the wafer at a first time to generate a first voltage comparison image associated with the first surface area. The stage is positioned at a second position so that the second beam of the plurality of beams can scan the first surface region at a second time to generate a second voltage comparison image associated with the first surface region. as well as The first voltage comparison image is compared with the second voltage comparison image to enable detection of whether a defect is identified in the first surface region of the wafer.

Images