Semiconductor chip package and assembly method

Abstract

A semiconductor device substrate assembly may include a first substrate comprising a first insulating plate and a first patterned metal layer disposed on the first insulating plate, wherein the first insulating plate comprises a first material and a first thickness. The assembly may include a second substrate comprising a second insulating plate and a second patterned metal layer disposed on the second insulating plate, wherein the second insulating plate comprises a first material and a first thickness. The assembly may also include a third substrate disposed between the first and second substrates, the third substrate comprising a third insulating plate and a third patterned metal layer disposed on the third insulating plate, wherein the third insulating plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness is different from the first material and the first thickness, respectively.

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 966,951, filed on January 28, 2020, entitled “Semiconductor Chip Package and Method of Assembly,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to the field of semiconductor devices, and in particular, to packages for power semiconductor chips. Background Art

[0004] Current power semiconductor modules, including insulated gate bipolar transistor (IGBT) or diode power modules (e.g., 3.3 kV, 4.5 kV, or 6.5 kV; 1500 A or 1200 A), can include multiple substrates similar to each other, such as two, four, or six substrates. Each substrate holds the IGBT and diode chips, along with wires and resistors, as well as busbars, which serve as power connections to the power semiconductor module. The substrates, in turn, can be secured to a baseplate to form a substrate assembly arranged on a common support structure (e.g., aluminum silicon carbide).

[0005] The power semiconductor substrate can include a sandwich of two metal sheets (e.g., Cu or Al), one of which is patterned as a patterned metal layer and bonded to a ceramic disposed between the patterned metal sheets. The substrate (e.g., Al2O3, AlN, or Si3N4) is carefully selected, taking into account various requirements, including: 1.) a high degree of electrical insulation from the top side to the bottom side is required (typically a minimum of 6 kV or 10.2 kV for high-power modules), 2.) a high vertical thermal conductivity is required, especially under the semiconductor chips for the best possible cooling; 3.) reliable mechanical stability is required during manufacturing, assembly, and operation, especially during the busbar attachment process, for example, to be more robust to the mechanical stresses of the busbar attachment process; 4.) high lateral conductivity of the top metal layer is required to minimize resistance and corresponding conduction losses, as well as good lateral heat dissipation; 5.) to ensure good manufacturing yield and device quality, the substrate needs to be fully electrically tested before assembly; 6.) the cost of materials, processes, and scrap needs to be kept reasonably low; and 7.) the design must be symmetrical to some extent to ensure symmetrical impedance for each group of chips.

[0006] Typical methods for attaching busbars (typically made of nickel-plated copper or pure copper) to substrates include brazing, ultrasonic welding or laser welding or Ag sintering. In the case of brazing, the joint itself may not have sufficient mechanical strength. Therefore, extra effort is required to keep the busbars in place (e.g., potting the module with epoxy resin). This approach not only requires additional process steps, but also leads to further problems of long-term reliability and additional weight. Recently developed ultrasonic welding or laser welding can provide very strong connections that do not require subsequent epoxy resin potting. Therefore, in principle, it is expected to use these subsequent processes. Before a robust welding process can be successfully implemented, there are still several problems, including particle generation during the welding process, a limited process window due to the risk of damaging the ceramic substrate, and limited accessibility of the welding tool.

[0007] The present embodiment is provided in view of the above circumstances. Summary of the Invention

[0008] The present invention discloses a semiconductor device substrate assembly and package, and related methods. In one embodiment, the semiconductor device substrate assembly may include a first substrate, the first substrate including: a first insulating plate; and a first patterned metal layer disposed on the first insulating plate, wherein the first insulating plate includes a first material and a first thickness. The semiconductor device substrate assembly may include a second substrate, the second substrate including: a second insulating plate; and a second patterned metal layer disposed on the second insulating plate, wherein the second insulating plate includes the first material and the first thickness. The semiconductor device substrate assembly may also include a third substrate disposed between the first substrate and the second substrate, the third substrate including: a third insulating plate; and a third patterned metal layer disposed on the third insulating plate, wherein the third insulating plate includes a second material and a second thickness, wherein at least one of the second material and the second thickness is different from the first material and the first thickness, respectively.

[0009] In another embodiment, a semiconductor device package may include a first substrate, wherein the first substrate includes a first insulating plate; a first patterned metal layer disposed on the first insulating plate; and a first group of semiconductor dies disposed on the first patterned metal layer. The semiconductor device package may also include a second substrate, wherein the second substrate includes a second insulating plate; a second patterned metal layer disposed on the second insulating plate; and a second group of semiconductor dies disposed on the second patterned metal layer. The semiconductor device package may also include a third substrate disposed between the first and second substrates, wherein the third substrate includes a third insulating plate; a third patterned metal layer disposed on the third insulating plate; and a group of busbars connected to the third patterned metal layer.

[0010] In another embodiment, a method for forming a semiconductor package is provided. The method may include attaching a first substrate to a baseplate, the first substrate including a first insulating material and a first patterned metal layer. The method may include attaching a second substrate to the baseplate, the second substrate including a first insulator material and a second patterned metal layer, and attaching a third substrate to the baseplate between the first and second substrates, the third substrate including a second insulator material different from the first material and also including a third patterned metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A shows a top view of a semiconductor device package according to various embodiments of the present disclosure;

[0012] Figure 1B Shown Figure 1A a top perspective view of a semiconductor device package;

[0013] Figure 2 Some embodiments of the present disclosure are shown Figure 1A A variation of the embodiment;

[0014] Figure 3A shows a top view of a semiconductor device package architecture according to an embodiment of the present disclosure;

[0015] Figure 3B A top view illustrating another semiconductor device package according to other embodiments of the present disclosure; and

[0016] Figure 4 A process flow according to an embodiment of the present disclosure is depicted. DETAILED DESCRIPTION

[0017] The present embodiments will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments are shown. These embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and fully convey its scope to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

[0018] In the following description and / or claims, the terms "on," "overlying," "disposed on," and "above" may be used in the following description and claims. "On," "overlying," "disposed on," and "above" may be used to indicate that two or more elements are in direct physical contact with each other. Additionally, the terms "on," "overlying," "disposed on," and "above" may indicate that two or more elements are not in direct contact with each other. For example, "above" may mean that one element is above another element, but not in contact with each other, and that there may be another one or more elements between the two elements. Additionally, although the scope of the claimed subject matter is not limited in this respect, the term "and / or" may mean "and," "or," "exclusive-or," "one," "some, but not all," "neither," and / or "both."

[0019] In various embodiments, semiconductor device packaging and assembly techniques are provided for power semiconductor devices.

[0020] Steering Figure 1A , showing a top view of a semiconductor device package 100 according to various embodiments of the present disclosure. Figure 1B A top perspective view of a variation of a semiconductor device package 100 is shown. The semiconductor device package 100 includes a first substrate 102, a second substrate 104, and a third substrate 106 arranged on a base plate 101. The base plate 101 can be a known material used for power semiconductor device packaging, including a ceramic material such as aluminum silicon carbide. The embodiments are not limited herein. In the configuration of FIG. 1 , according to some embodiments, the first substrate 102 and the second substrate 104 can be similar or identical, being the same or similar in terms of materials, components, architecture, and dimensions. As described below, the third substrate 106 can be substantially different from the first substrate 102 and the second substrate 104.

[0021] As an example, the first substrate 102 may include a first insulating plate 112 and a first patterned metal layer 122 disposed on the first insulating plate 112. In various non-limiting embodiments, the first insulating plate 112 may be formed of a known ceramic material, such as aluminum oxide, silicon nitride, or aluminum nitride. In certain embodiments, the first insulating plate 112 may be formed of aluminum nitride, silicon nitride, or a similar material, having a thickness of, for example, 1 mm, 0.6 mm, or a similar thickness. Thus, the first insulating plate 112 may provide a highly thermally conductive path to the substrate 101. As shown, the first patterned metal layer 122 may be patterned into different areas. It should be noted that the patterned metal layer may be formed of a thin sheet, such as a copper sheet. Although not shown, the first substrate 102 may include a metal sheet on a side opposite to the side supporting the first patterned metal layer 122, thereby forming a stack of insulating plates sandwiched between two metal sheets, as in known device packages.

[0022] The semiconductor device package 100 may include a first set of semiconductor dies, shown as semiconductor dies 132, disposed on the first patterned metal layer 122. The semiconductor dies 132 may represent a set of power devices, including diodes, IGBTs, and the like.

[0023] Similar to the first substrate 102, the second substrate 104 may include a second insulating plate 114 and a second patterned metal layer 124 disposed on the second insulating plate 114. In various non-limiting embodiments, the second insulating plate 114 may be formed of a known ceramic material, such as aluminum oxide, silicon nitride, or aluminum nitride. In certain embodiments, the second insulating plate 114 may be formed of aluminum nitride, having a thickness of, for example, 1 mm, 0.5 mm, or the like. Thus, the second insulating plate 114 may provide a highly thermally conductive path to the substrate 101. As shown, the second patterned metal layer 124 may be patterned into different regions. It should be noted that the second patterned metal layer 124 may be formed of a thin sheet, such as a copper sheet. Although not shown, the second substrate 104 may include a metal sheet on the side opposite to the side supporting the second patterned metal layer 124, thereby forming a stack of insulating plates sandwiched between two metal sheets, as in known device packages.

[0024] Likewise, semiconductor device package 100 may include a second set of semiconductor dies, shown as semiconductor dies 134, disposed on second patterned metal layer 124. Semiconductor dies 134 may represent a set of power devices, including diodes, IGBTs, and the like.

[0025] As in known power semiconductor device packages, the first substrate 102 and the second substrate 104 can be configured to be the same, including the thickness of the first insulating plate 112 and the second insulating plate 114. However, in some embodiments, the thickness of the second insulating plate 114 does not need to match the thickness of the first insulating plate. In embodiments where the semiconductor die 132 and the semiconductor die 134 are power semiconductor chips, in order to generate large currents, the first insulating plate 112 and the second insulating plate 114 can be designed to dissipate excess heat, where high thermal conductivity and low thickness are desired. Therefore, in certain embodiments, the first insulating plate 112 and the second insulating plate 114 can each be formed of aluminum nitride, silicon nitride, or a similar material, having a thickness of, for example, 1 mm, such as 0.6 mm, or other suitable thickness.

[0026] like Figure 1A and Figure 1BAs shown, the semiconductor device package 100 may further include a third substrate 106 disposed between the first substrate 102 and the second substrate 104. The third substrate 106 may include a third insulating plate 116 and a third patterned metal layer 126 disposed on the third insulating plate 116. As shown, the third patterned metal layer 126 may be formed in different sections. Therefore, the third patterned metal layer 126 may be formed of multiple patterned structures to accommodate a busbar assembly disposed thereon.

[0027] like Figure 1A and Figure 1B As shown, the semiconductor device package 100 may further include a bus bar assembly connected to the third patterned metal layer 126 in a plurality of different sections. The bus bar assembly is shown as bus bar 140, where bus bar 140 may be formed of a relatively thick metal, such as copper, and may extend above the plane of the substrate 101, as shown.

[0028] It should be noted that while the first insulating plate 112 and the second insulating plate 114 can be made of a first material (such as silicon nitride), the third insulating plate 116 can be made of a second material (such as aluminum nitride or aluminum oxide). In addition, according to various embodiments, the thickness of the third insulating plate 116 can be different from the thickness of the first insulating plate 112 and the second insulating plate 114. For example, the third insulating plate 116 can be formed of a thicker insulating material than the first insulating plate and the second insulating plate. The selection of the material and thickness of the third insulating plate 116 can take into account the process of attaching the busbar 140 to the third patterned metal layer 126 on the third insulating plate 116. A more efficient attachment process (such as ultrasonic welding) may require a relatively larger thickness and a relatively tougher material for the third insulating plate 116.

[0029] The semiconductor device package 100 may also include a first set of electrical connectors (shown as connectors 128) that electrically connect the third patterned metal layer 126 to the first patterned metal layer 122, and a second set of connectors (shown as connectors 129) that electrically connect the third patterned metal layer 126 to the second patterned metal layer 124. Thus, the semiconductor device package 100 provides an assembly for electrically and thermally managing a group of semiconductor dies, wherein the semiconductor dies are supported on a pair of insulating substrates that are separate from a third substrate that supports a busbar. Advantageously, this arrangement facilitates the ability to tailor the area of ​​the insulating substrate used for thermal management of the semiconductor dies from the area where the busbars are electrically coupled to the semiconductor dies, as described below.

[0030] Special Turn Figure 1BAs shown in the perspective view, the busbar 140 (which has a relatively larger thickness than the connector 128 and the connector 129) can be better attached to the third patterned metal layer 126 by ultrasonic welding or other welding processes, which provides a more stable connection than required for the connector 128 and the connector 129 without damaging the substrate ceramic (such as the third insulating plate 116). At the same time, the substrate ceramics (see the first insulating plate 112 and the second insulating plate 114) can be independently selected so that they provide the optimal characteristics of electrical isolation and high thermal conductivity required by the power semiconductor chipset. As an example, the connector 128 can be attached to the first patterned metal layer 122 and the third patterned metal layer 126 by a brazing process. The connector 129 can also be attached to the second patterned metal layer 124 and the third patterned metal layer 126 by a brazing process. Since the busbar 140 is attached to the third substrate 106, rather than to the substrate including the semiconductor die, such as the first substrate 102 or the second substrate 104, Figure 1A and Figure 1B The arrangement provides several advantages. Because the third insulating plate 116 can be made of a tougher and thicker material than the first and second insulating plates 112 and 114, in addition to the flexibility of selecting a more robust attachment process, this architecture allows the busbar 140 attachment process to avoid interfering with or damaging the less tough, thinner substrates, namely, the first and second substrates 102 and 104.

[0031] Turning now to Table 1, a set of exemplary operations for assembling a semiconductor device package according to some embodiments of the present disclosure is shown. As shown, prior to assembly, the semiconductor die can be subjected to a set of tests. In a DCB operation, a pair of copper sheets can be fixed to a ceramic substrate, such as aluminum oxide, aluminum nitride, or silicon nitride. These sheets can be patterned to form a patterned metal layer suitable for forming a semiconductor die substrate, which refers to a substrate that supports the semiconductor die. Separately, the copper sheets can be attached to a "busbar substrate" for supporting busbars, separate from the semiconductor die substrate. It should be noted that, as described above, the ceramic of the busbar substrate can be different in thickness and material from the semiconductor die substrate. Separately, the busbars can be stamped, formed, and annealed into a predetermined shape.

[0032] According to this embodiment, during assembly, the semiconductor die substrate can be assembled separately from the busbar substrate. According to known techniques, the semiconductor die (chip) can be soldered to the corresponding semiconductor die substrate. According to this embodiment, as described above, the semiconductor die substrate can be selected as an insulator material with a thickness and material optimized for electrical isolation and thermal conductivity. X-ray analysis can be performed to detect defects, followed by wire bonding to the terminals of the semiconductor die, and electrical testing of the circuit after the semiconductor die is fixed and wired to the semiconductor die substrate (e.g., the first substrate 102 and the second substrate 104 as described above).

[0033] To assemble the busbar substrate, ultrasonic welding can be used to attach the busbars to a patterned metal layer, which is secured to an insulating plate, such as aluminum oxide or aluminum nitride. As described above, the insulating plate used for the busbar substrate can be formed of a stronger material and can be thicker than the semiconductor die substrate. Therefore, due to the greater robustness of the busbar substrate, ultrasonic welding operations can be performed with high throughput.

[0034] Advantageously, according to some embodiments, ultrasonic welding for busbar attachment can be performed separately from module assembly and remote from the semiconductor chip, thus preventing particle contamination of the semiconductor chip during the welding process and enabling inspection or testing of the busbar attachment external to the module.

[0035] To complete the assembly, the various semiconductor substrates and busbar substrates are fixed to the base plate, for example by soldering. The arrangement of the various substrates can be as follows: Figure 1A As shown, the busbar substrate (third substrate 106) is disposed between opposing semiconductor die substrates (first substrate 102 and second substrate 104).

[0036] Next, electrical connectors (clamps) (see connectors 128 and 129) can be soldered between the semiconductor substrate and the busbar substrate. In particular, the connectors are soldered to the patterned metal layers (see first substrate 102 and second substrate 104) provided on the respective semiconductor substrates. The soldering operation establishes an electrical connection between the semiconductor chip provided on the semiconductor die substrate and components external to the semiconductor device package via the patterned metal layer on the busbar substrate and the busbar soldered to the patterned metal layer.

[0037] Alternatively, in further embodiments, these connections between the semiconductor substrate and the busbar substrate can be established by wire bonding or other means, with ultrasonic bonding of the busbar being performed last. In these further embodiments, the material of the semiconductor substrate can still be different from that of the busbar substrate, thereby providing a more flexible approach.

[0038] Subsequently, assembly can be performed according to known procedures, including gluing the plastic cover to the base plate, filling with gel, adding plastic inserts and screws, and performing final testing.

[0039]

[0040]

[0041] Form I

[0042] Go to Figure 2, a top view of a variation of semiconductor device package 100 is shown, which is shown as semiconductor device package 200. In this case, semiconductor device package 200 can include the above-described components of semiconductor device package 100, wherein similar components are labeled the same. It should be noted that wiring 204 is shown to illustrate an exemplary conductor pattern connecting semiconductor die 132 to first patterned metal layer 122 and connecting semiconductor die 134 to second patterned metal layer 124.

[0043] Although the above embodiments have described a semiconductor device package having two opposing semiconductor die substrates, in other embodiments, the semiconductor device package may include four semiconductor die substrates, six semiconductor die substrates, etc. In these additional embodiments, as described above, a busbar substrate is separately disposed between the opposing semiconductor substrates to support a busbar that is directly soldered to the busbar substrates. Figure 3A One such embodiment is depicted in which a semiconductor device package 144 includes two pairs of semiconductor die substrates, each pair separated by a busbar substrate (shown as third substrate 106 ), all of which are secured to a baseplate 101 , where the illustrated substrates have been described above.

[0044] In another embodiment of the present disclosure, multiple pairs of substrates may be coupled to one central substrate that holds the busbars. Figure 3B A semiconductor device substrate assembly 150 is depicted in accordance with an additional embodiment of the present disclosure, wherein a pair of substrates containing semiconductor power chips are connected to a central busbar substrate 156. Substrates 102A and 102B disposed on one side of the central busbar substrate 156 can be substantially identical to the first substrate 102 described above. Substrates 104A and 104B disposed on a second side of the central busbar substrate 156 can be substantially identical to the second substrate 104 described above, and in some embodiments can be identical to substrates 102A and 104A. In this configuration, for a given number of substrates and a given number of semiconductor chips, the number of components is reduced, and the use of interconnects between separate busbar substrates can be avoided. In particular, gate connections can be run on the central busbar substrate 156, as well as emitter and collector sense connections. This configuration avoids any need for wire bonding after soldering, thus enabling busbar soldering to be performed before the substrates are soldered to the baseplate.

[0045] According to additional embodiments of the present disclosure, the thickness of the patterned metal layer (e.g., copper layer) provided on the semiconductor chip substrate may be different from the thickness of the patterned metal layer provided on the busbar substrate. It should be noted that using relatively thick copper may facilitate busbar attachment while increasing the difficulty of patterning fine patterns in the patterned metal layer structure on the semiconductor chip substrate.

[0046] Alternatively, increasing the copper thickness beneath the semiconductor die can provide better thermal performance and lateral conductivity, while maintaining the copper thickness beneath the busbar allows soldering parameters to remain the same. In either case, the separation of the busbar substrate from the semiconductor substrate allows for independent selection of the patterned copper metal layer thickness, allowing for optimization of other aspects of the substrate-device assembly. Figure 4 A process flow 400 is depicted according to an embodiment of the present disclosure. At block 402, a first substrate is secured to a baseplate, wherein the first substrate includes a first insulating plate, a first patterned metal layer disposed on the first insulating plate, and a first set of semiconductor dies disposed on the first patterned metal layer.

[0047] At block 404, a second substrate separated from the first substrate is secured to the base plate, wherein the second substrate includes a second insulating plate, a second patterned metal layer disposed on the second insulating plate, and a second group of semiconductor dies disposed on the second patterned metal layer. In various embodiments, the first substrate can be similar to or the same type of substrate as the second substrate. As an example, the first insulating plate and the second insulating plate can have the same dimensions and can be formed from the same material. The first patterned metal layer can have the same shape and overall dimensions as the first patterned metal layer, can be formed from the same material, etc. The first group of semiconductor dies is identical to the second group of semiconductor dies in that the individual dies are identical for each group and are arranged identically.

[0048] In block 406, a third substrate is secured to the base plate and positioned between the first and second substrates, and includes a third insulating plate. In some embodiments, the third substrate may have a different thickness, a different material composition, or both, than the first and second insulating plates. In other embodiments, the third insulating plate may have the same thickness as the first and second insulating plates. As an example, the first and second insulating plates may be formed of a thin electrical insulator with high thermal conductivity, such as silicon nitride, while the third insulating plate is formed of a thicker plate made of aluminum oxide or aluminum nitride. The embodiments are not limited herein. Thus, the assembly of the substrates allows for the formation of busbars directly on the third substrate in a robust soldering process without interfering with the first and second substrates.

[0049] It should be noted that in different embodiments, the operations of blocks 402 , 404 , and 406 may be performed in any order, and generally different substrates may be secured to the baseplate “simultaneously” in the same general operation.

[0050] In another variation of the process flow, the substrate material is the same for all substrates.In the process flow, busbars may be attached to the busbar substrate (third substrate) before the substrates are brazed to the base plate.

[0051] Although the present embodiment has been disclosed with reference to certain embodiments, many modifications, variations, and changes may be made to the described embodiments without departing from the field and scope of the present disclosure as defined in the appended claims. Therefore, the present embodiment is not limited to the embodiments described, but may have the full scope defined by the language of the appended claims and their equivalents.

Claims

1. A semiconductor device substrate assembly, comprising: A first substrate, the first substrate comprising: a first insulating plate; a first patterned metal layer disposed on the first insulating plate, wherein the first insulating plate comprises a first material and a first thickness; and a first group of semiconductor dies disposed on the first patterned metal layer; A second substrate, the second substrate comprising: a second insulating plate; a second patterned metal layer disposed on the second insulating plate, wherein the second insulating plate comprises the first material and has a first thickness; and a second group of semiconductor dies disposed on the second patterned metal layer; and A third substrate is provided between the first substrate and the second substrate, comprising: a third insulating plate; and a third patterned metal layer disposed on the third insulating plate, wherein the third insulating plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness is different from the first material and the first thickness, respectively, the third patterned metal layer comprising a plurality of patterned structures to accommodate a busbar assembly disposed thereon, wherein gate connections for the first group of semiconductor dies and / or for the second group of semiconductor dies extend over the third patterned metal layer.

2. The semiconductor device substrate assembly according to claim 1, wherein the first insulating plate and the second insulating plate include a first insulator material having a first thermal conductivity, and the third insulating plate includes a second insulator material having a second thermal conductivity less than the first thermal conductivity, while having a more robust mechanical property against the mechanical stress of the busbar attachment process. 3 . The semiconductor device substrate assembly of claim 2 , wherein the first insulator material comprises silicon nitride or aluminum nitride, and the second insulator material comprises aluminum nitride or aluminum oxide.

4. The semiconductor device substrate assembly according to claim 1, wherein: The second thickness is greater than the first thickness.

5. The semiconductor device substrate assembly according to claim 1, wherein: The first patterned metal layer and the second patterned metal layer include a first layer thickness, and wherein the third patterned metal layer includes a second layer thickness different from the first layer thickness.

6. The semiconductor device substrate assembly according to claim 1, further comprising a base plate, wherein The first substrate, the second substrate and the third substrate are disposed on the base plate.

7. The semiconductor device substrate assembly according to claim 1, further comprising: a fourth substrate disposed adjacent to the first substrate on the first side of the third substrate; as well as A fifth substrate is disposed adjacent to the second substrate on the second side of the third substrate.

8. A semiconductor device package, comprising: A first substrate, the first substrate comprising: a first insulating plate; and a first patterned metal layer, the first patterned metal layer being disposed on the first insulating plate; and a first group of semiconductor dies disposed on the first patterned metal layer; A second substrate, the second substrate comprising: a second insulating plate; a second patterned metal layer, the second patterned metal layer being disposed on the second insulating plate; and a second group of semiconductor dies disposed on the second patterned metal layer; A third substrate is provided between the first substrate and the second substrate, comprising: a third insulating plate; and a third patterned metal layer, the third patterned metal layer being disposed on the third insulating plate; and A set of busbars is connected to the third patterned metal layer, wherein gate connections for the first group of semiconductor dies and / or for the second group of semiconductor dies extend on the third patterned metal layer. 9 . The semiconductor device package of claim 8 , the first and second insulating plates comprising a first insulator material having a first thickness, and the third insulating plate comprising a second insulator material having a second thickness greater than the first thickness. 10 . The semiconductor device package of claim 9 , the first insulator material comprising silicon nitride, aluminum nitride, or aluminum oxide, and the second insulator material comprising aluminum nitride or aluminum oxide.

11. The semiconductor device package according to claim 8, wherein The first and second groups of semiconductor dies comprise a group of power semiconductor devices. 12 . The semiconductor device package according to claim 8 , further comprising a base plate, wherein the first substrate, the second substrate, and the third substrate are disposed on the base plate. 13 . The semiconductor device package of claim 9 , the first insulator material comprising silicon nitride or aluminum nitride, and the second insulator material comprising aluminum nitride or aluminum oxide. 14 . The semiconductor device package of claim 8 , the first and second insulating plates comprising a first insulator material having a first thermal conductivity, and the third insulating plate comprising a second insulator material having a second thermal conductivity that is less than the first thermal conductivity.

15. A method of forming a semiconductor package, comprising: fixing a first substrate on the base plate, wherein the first substrate comprises a first insulator material and a first patterned metal layer; fixing a second substrate on the base plate, the second substrate comprising the first insulator material and a second patterned metal layer; and A third substrate is fixed on the base plate between the first substrate and the second substrate, the third substrate comprising a second insulator material different from the first insulator material and further comprising a third patterned metal layer, the third substrate further comprising a set of bus bars connected to the third patterned metal layer; securing a first plurality of semiconductor chips on the first patterned metal layer; securing a second plurality of semiconductor chips on the second patterned metal layer; as well as A set of gate connections for the first plurality of semiconductor chips and / or for the second plurality of semiconductor chips extends on the third patterned metal layer.

16. The method according to claim 15, further comprising: A bus bar is connected to the third patterned metal layer.

17. The method according to claim 16, wherein Connecting a bus bar to the third patterned metal layer includes soldering the bus bar to the third patterned metal layer before securing the third substrate to the baseplate.

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