Display device

Abstract

A display device is provided. The display device includes: a first voltage wiring extending in a first direction; a data line spaced apart from the first voltage wiring and extending in the first direction; a scan line extending in a second direction; a sensing line spaced apart from the scan line and extending in a second direction different from the first direction; a first inner bank and a second inner bank arranged on the first voltage wiring and the data line, extending in the first direction, and spaced apart from each other while facing each other; a first electrode arranged on the first inner bank and extending in the first direction; a second electrode arranged on the second inner bank and extending in the first direction; and a plurality of light emitting elements arranged between the first electrode and the second electrode.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] Display devices have become increasingly important with the development of multimedia, and therefore, various types of display devices such as organic light emitting displays and liquid crystal displays are being used.

[0003] The display device includes a display panel (such as an organic light emitting display panel or a liquid crystal display panel) as a device for displaying an image of the display device. Among them, the light emitting display panel may include a light emitting element such as a light emitting diode (LED). For example, the LED may be an organic light emitting diode (OLED) using an organic material as a fluorescent material, or may be an inorganic LED using an inorganic material as a fluorescent material.

[0004] Inorganic LEDs using inorganic semiconductors as fluorescent materials are durable even in high temperature environments and have higher blue light efficiency than OLEDs. In addition, a transfer method using dielectrophoresis (DEP) has been developed for the manufacturing process that has been pointed out as a limitation of conventional inorganic LEDs. Therefore, research on inorganic LEDs with better durability and efficiency than OLEDs is ongoing. Summary of the invention

[0005] Technical issues

[0006] The present invention aims to provide a display device including an inorganic light-emitting element.

[0007] The invention also aims to provide a display device in which a light emitting area and a non-light emitting area are separated so that a circuit element and a display element do not overlap each other.

[0008] It should be noted that the disclosed aspects are not limited thereto, and other aspects not mentioned here will be apparent to those of ordinary skill in the art through the following description.

[0009] Technical Solution

[0010] According to a disclosed embodiment, a display device includes: a first voltage wiring, extending in a first direction; a data line, spaced apart from the first voltage wiring and extending in the first direction; a scan line, extending in a second direction different from the first direction; a sensing line, spaced apart from the scan line and extending in the second direction; a first internal embankment and a second internal embankment, arranged on the first voltage wiring and the data line, extending in the first direction, and arranged to be spaced apart from and facing each other; a first electrode, arranged on the first internal embankment and extending in the first direction; a second electrode, arranged on the second internal embankment and extending in the first direction; and a plurality of light-emitting elements, arranged between the first electrode and the second electrode, wherein each of the plurality of light-emitting elements includes a semiconductor core and an insulating film surrounding at least a portion of an outer surface of the semiconductor core, the semiconductor core including a light-emitting layer.

[0011] The display device may further include: a reference voltage wiring spaced apart from the data line in the second direction and extending in the first direction; and a reference voltage distribution line spaced apart from the sensing line in the first direction and extending in the second direction, wherein the reference voltage distribution line may be electrically connected to the reference voltage wiring.

[0012] The data line may be disposed between the first voltage wiring and the reference voltage wiring, and the sensing line may be disposed between the scan line and the reference voltage distribution line.

[0013] The display device may further include a second voltage wiring extending in the first direction and disposed to be spaced apart from the reference voltage wiring, wherein the first electrode may be electrically connected to the first voltage wiring through the driving transistor, and the second electrode may be electrically connected to the second voltage wiring.

[0014] The second voltage wiring may further include a portion extending in the second direction, and the portion of the second voltage wiring extending in the second direction may partially overlap the second electrode in a plan view.

[0015] The first inner bank may partially overlap the first voltage wiring in a plan view, and the second inner bank may be disposed not to overlap the data line in a thickness direction.

[0016] The display device may also include an outer dam arranged to extend in the first direction and the second direction to surround an area in which the first inner dam and the second inner dam are arranged, wherein the first voltage wiring may extend in the first direction between the second inner dam and the outer dam, and the data line may overlap with a portion of the outer dam extending in the first direction in a thickness direction.

[0017] The display device may also include a shielding electrode having at least a portion overlapping the first electrode and arranged to surround an area in which the light-emitting element is arranged, wherein the shielding electrode may be arranged to cover a portion of the first electrode and each of the first internal dams relative to the outside of the area in which the plurality of light-emitting elements are arranged.

[0018] The display device may further include: a third internal embankment, which is arranged to be separated from the first internal embankment and faces the first internal embankment; and a repair electrode, which is arranged on the third internal embankment, wherein the light-emitting element may further include a first light-emitting element arranged between the first electrode and the second electrode and a second light-emitting element arranged between the first electrode and the repair electrode.

[0019] The semiconductor core of the light emitting element may include a first semiconductor layer, a second semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and the insulating film may be disposed to surround at least an outer surface of the light emitting layer.

[0020] The display device may further include: a first contact electrode disposed on the first electrode and electrically connected to the first electrode and one end of the light emitting element; and a second contact electrode disposed on the second electrode and electrically connected to the second electrode and the other end of the light emitting element.

[0021] According to the disclosed embodiment, the display device includes: a first substrate; a semiconductor layer, which is arranged on the first substrate and includes a first active layer of a driving transistor; a first gate insulating layer, which is arranged on the first substrate and the semiconductor layer; a first gate conductive layer, which is arranged on the first gate insulating layer and includes a first gate electrode of the driving transistor; a first interlayer insulating layer, which is arranged on the first gate conductive layer; a first data conductive layer, which is arranged on the first interlayer insulating layer and includes source / drain electrodes and a first voltage wiring of the driving transistor; a first protective layer, which is arranged on the first data conductive layer; a first planarizing layer, which is arranged on the first protective layer; a first internal embankment and a second internal embankment, which are arranged on the first planarizing layer and are spaced apart from each other and face each other; a first electrode and a second electrode, which are respectively arranged on the first internal embankment and the second internal embankment; and a light-emitting element, which is arranged between the first electrode and the second electrode, wherein the light-emitting element includes a semiconductor core and an insulating film surrounding at least a portion of an outer surface of the semiconductor core, and the semiconductor core includes a light-emitting layer.

[0022] The first electrode may be electrically connected to the source / drain electrodes of the driving transistor through an electrode contact hole penetrating the first protection layer and the first planarization layer.

[0023] The first gate conductive layer may further include a second voltage wiring, and the second electrode may be electrically connected to the second voltage wiring.

[0024] The first data conductive layer may further include a second voltage wiring, and the second electrode may be electrically connected to the second voltage wiring.

[0025] The first data conductive layer may further include a conductive pattern contacting the second voltage wiring through a first wiring contact hole passing through the first interlayer insulating layer, and the second electrode may contact the conductive pattern through a second wiring contact hole passing through the first protective layer and the first planarizing layer.

[0026] The display device may further include: a first contact electrode disposed on the first electrode and electrically connected to the first electrode and one end of the light emitting element; and a second contact electrode disposed on the second electrode and electrically connected to the second electrode and the other end of the light emitting element.

[0027] The display device may further include: a thin film encapsulation structure disposed on the first contact electrode and the second contact electrode; and a color filter layer disposed on the thin film encapsulation structure.

[0028] The display device may further include a color control layer disposed between the color filter layer and the thin film encapsulation structure.

[0029] The display device may further include an outer bank disposed on the first planarization layer and spaced apart from each of the first inner bank and the second inner bank, wherein a height of the outer bank may be greater than a height of each of the first inner bank and the second inner bank.

[0030] The display device may further include a reflective layer disposed on one surface of the outer bank.

[0031] The display device may further include: a buffer layer disposed between the first substrate and the semiconductor layer; and a light blocking layer disposed between the buffer layer and the first substrate and configured to partially overlap the first active layer.

[0032] According to the disclosed embodiment, the display device includes: a first substrate, in which a light-emitting area and a non-light-emitting area are defined; a semiconductor layer, arranged in the non-light-emitting area of ​​the first substrate, and including a first active layer of a driving transistor; a first gate conductive layer, arranged in the non-light-emitting area, and including a first gate electrode arranged to be stacked with the first active layer; a first voltage wiring, arranged in the non-light-emitting area and the light-emitting area, and extending in a first direction; a first internal embankment and a second internal embankment, arranged in the light-emitting area, extending in the first direction, and spaced apart from each other in a second direction; a first electrode, including at least a portion arranged on the first internal embankment, and including a portion extending in the first direction; a second electrode, including at least a portion arranged on the second internal embankment, and including a portion extending in the first direction; and a plurality of light-emitting elements, arranged between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, wherein each of the plurality of light-emitting elements includes a semiconductor core and an insulating film surrounding at least a portion of an outer surface of the semiconductor core, the semiconductor core including the light-emitting layer.

[0033] The display device may further include: a scan line disposed in the non-light emitting region and extending in the second direction; and a sensing line extending in the second direction and spaced apart from the scan line.

[0034] The display device may further include: a reference voltage wiring disposed in the non-luminescent region and the luminescent region and extending in the first direction; and a reference voltage distribution line disposed in the non-luminescent region, extending in the second direction and electrically connected to the reference voltage wiring.

[0035] The first electrode may include a first electrode trunk portion extending in the second direction and a first electrode branch portion branching from the first electrode trunk portion along the first direction, and the second electrode may include a second electrode trunk portion extending in the second direction and a second electrode branch portion branching from the second electrode trunk portion along the first direction.

[0036] The display device may further include: a first contact electrode disposed on the first electrode branch portion and electrically connected to the first electrode and one end of the light-emitting element; and a second contact electrode disposed on the second electrode branch portion and electrically connected to the second electrode and the other end of the light-emitting element.

[0037] The display device may further include an outer bank disposed to cover the non-light emitting area and surround the light emitting area, wherein a height of the outer bank may be greater than a height of each of the first inner bank and the second inner bank.

[0038] Details of other embodiments are included in the detailed description and accompanying drawings.

[0039] Beneficial Effects

[0040] The display device according to one embodiment includes a plurality of light emitting elements disposed in a region in which an inner bank is formed, and thus may have a top emission structure in which light emitted from the light emitting elements is reflected from a side surface of the inner bank.

[0041] Furthermore, according to the embodiment, in the display device, the light emitting region in which the light emitting element is disposed does not overlap with the non-light emitting region in which the circuit element is disposed, so that the display device can have a bottom emission structure.

[0042] It should be noted that the objects of the invention are not limited to the above objects, and other objects of the invention will be apparent to those skilled in the art through the following description.

[0043] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0045] Figure 2 yes Figure 1 Schematic cross-sectional view of a display device.

[0046] Figure 3 is a plan view of a first display substrate according to an embodiment.

[0047] Figure 4 is a schematic diagram showing wirings included in a first display substrate according to an embodiment.

[0048] Figure 5 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0049] Figure 6 is a schematic plan view showing one pixel of a display device according to an embodiment.

[0050] Figure 7 is a schematic plan view of a circuit element layer included in one sub-pixel of a display device according to one embodiment.

[0051] Figure 8 is a schematic plan view of a display element layer included in one pixel of a display device according to one embodiment.

[0052] Fig. 9 It is along Figure 7 and Figure 8 Cross-sectional views taken along line Qa-Qa', line Qb-Qb' and line Qc-Qc'.

[0053] Fig.10It is along Figure 7 and Figure 8 A cross-sectional view taken along line Q1-Q1'.

[0054] Fig.11 is a schematic diagram of a light emitting element according to an embodiment.

[0055] Fig.12 is a schematic cross-sectional view of a display device according to an embodiment.

[0056] Fig.13 is a partial cross-sectional view of a first display substrate according to another embodiment.

[0057] Fig.14 is a schematic cross-sectional view showing one sub-pixel of a display device according to still another embodiment.

[0058] Fig.15 It is along Fig.14 A cross-sectional view taken along line Q2-Q2' and line Q3-Q3'.

[0059] Fig.16 is a schematic plan view of a display element layer included in one sub-pixel of a display device according to still another embodiment.

[0060] Fig.17 It is along Fig.16 A cross-sectional view taken along line Q4-Q4'.

[0061] Figures 18 to 20 is a schematic plan view of a display element layer included in one sub-pixel of a display device according to still another embodiment.

[0062] Fig.21 is a schematic plan view showing one sub-pixel of a display device according to still another embodiment.

[0063] Fig. 22 It is along Fig.21 A cross-sectional view taken along line Q5-Q5' and line Q6-Q6'.

[0064] Fig.23 is a schematic cross-sectional view of a display device according to yet another embodiment.

[0065] Fig.24 is a schematic cross-sectional view of a display device according to yet another embodiment.

[0066] Fig.25 is a schematic cross-sectional view of a portion of a display device according to an embodiment in which an inactive region is located.

[0067] Fig.26 and Fig. 27is a schematic cross-sectional view of a portion of a display device according to another embodiment in which an inactive area is located. DETAILED DESCRIPTION

[0068] The invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. However, the invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0069] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals refer to the same components throughout the specification.

[0070] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the invention. Similarly, the second element may also be referred to as the first element.

[0071] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0072] Figure 1 is a schematic perspective view of a display device according to an embodiment. Figure 2 yes Figure 1 Schematic cross-sectional view of a display device.

[0073] Reference Figure 1 and Figure 2 , the display device 1 can be applied to various electronic devices, such as small or medium-sized electronic devices including tablet personal computers (PCs), smart phones, car navigation units, cameras, center information displays (CIDs) provided in vehicles, wristwatch-type electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, etc., and medium or large-sized electronic devices including televisions, external billboards, monitors, PCs, notebook computers, etc. However, it is obvious that these are provided as embodiments and can be used in other electronic devices within the scope of the invention.

[0074] In some embodiments, the display device 1 may have a rectangular shape in a plan view. The display device 1 may include two first sides extending in one direction and two second sides extending in another direction intersecting the one direction. The corner of the display device 1 where the first side meets the second side may have a right angle, but is not limited thereto, and may have a curved surface. In some embodiments, the first side may be shorter than the second side, but the present invention is not limited thereto. The planar shape of the display device 1 is not limited to the shape shown, but a circular shape or other shapes may be applied as the planar shape.

[0075] The display device 1 may include a display area DPA in which an image is displayed and a non-display area NDA in which no image is displayed. In some embodiments, the non-display area NDA may be located around the display area DPA and may surround the display area DPA.

[0076] In one embodiment, the display device 1 may include a first display substrate 10 and a second display substrate 50 opposite to the first display substrate 10, and may further include a sealing portion 70 configured to bond the first display substrate 10 to the second display substrate 50 and a filler 90 filled between the first display substrate 10 and the second display substrate 50.

[0077] The first display substrate 10 may include elements and circuits for displaying an image, for example, a pixel circuit such as a switching element, a pixel defining film (described below) configured to define a light emitting area and a non-light emitting area in the display area DPA, and a self-luminous element. In an embodiment, the self-luminous element may include at least one of an organic light emitting diode (LED), a quantum dot LED, an inorganic material-based micro-LED (e.g., a micro-LED), and an inorganic material-based nano-LED (e.g., a nano-LED).

[0078] The second display substrate 50 may be located above the first display substrate 10, and may be opposite to the first display substrate 10. The second display substrate 50 may include a color conversion pattern that converts a color of incident light.

[0079] In some embodiments, the color conversion pattern may include at least one of a color filter and a color control layer. A description thereof will be provided below.

[0080] The sealing portion 70 may be located between the first display substrate 10 and the second display substrate 50 in the non-display area NDA. The sealing portion 70 may be disposed along the edge of each of the first display substrate 10 and the second display substrate 50 in the non-display area NDA and surround the display area DPA in a plan view. The first display substrate 10 and the second display substrate 50 may be coupled to each other through the sealing portion 70. In some embodiments, the sealing portion 70 may be made of an organic material. As an example, the sealing portion 70 may be made of an epoxy resin, but the invention is not limited thereto.

[0081] The filler 90 may be located in a space surrounded by the sealing portion 70 between the first display substrate 10 and the second display substrate 50. The space between the first display substrate 10 and the second display substrate 50 may be filled with the filler 90. The filler 90 may be made of a material capable of transmitting light. In some embodiments, the filler 90 may be made of an organic material. As an example, the filler 90 may be made of a silicon-based organic material, an epoxy-based organic material, etc., but the invention is not limited thereto. In addition, the filler 90 may be omitted in some cases.

[0082] Figure 3 is a plan view of a first display substrate according to an embodiment.

[0083] Reference Figure 3 , the first display substrate 10 may include an active area AA and an inactive area DS. The active area AA is an area where a picture can be displayed, and the inactive area DS is an area where no picture is displayed. The active area AA may substantially occupy the center of the first display substrate 10 .

[0084] The first display substrate 10 may have a shape such as a rectangular shape with long horizontal sides, a rectangular shape with long vertical sides, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, a circular shape, etc. The shape of the active area AA of the first display substrate 10 may also be similar to the overall shape of the first display substrate 10. Figure 3 , the first display substrate 10 and the active area AA having a rectangular shape having a lateral side length are shown. However, the present invention is not limited thereto, and the shape of the first display substrate 10 may be variously modified.

[0085] The active area AA of the first display substrate 10 may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix form. The shape of each of the pixels PX may be a rectangular shape or a square shape in a plan view, but the invention is not limited thereto, and the shape may be a rhombus shape in which each side thereof is inclined relative to one direction. The pixels PX may be arranged alternately in a stripe type or a PenTile type. In addition, each of the pixels PX may include one or more light-emitting elements that emit light within a specific wavelength range, thereby displaying a specific color.

[0086] The inactive area DS may be disposed around the active area AA. The inactive area DS may completely or partially surround the active area AA. The active area AA has a rectangular shape, and the inactive area DS may be disposed adjacent to four sides of the active area AA. The inactive area DS may form a frame of the first display substrate 10. In the inactive area DS, a wiring or circuit driver included in the first display substrate 10 may be disposed, or an external device may be installed.

[0087] Figure 4 is a schematic diagram showing wirings included in a first display substrate according to an embodiment.

[0088] Reference Figure 4 , the first display substrate 10 may include a plurality of wirings. The plurality of wirings may include a scan line SCL, a sensing line SSL, a data line DTL, a reference voltage wiring RVL, a first voltage wiring VDL, a second voltage wiring VSL, etc. In addition, although not shown in the drawings, the first display substrate 10 may further include other wirings disposed therein.

[0089] The scan line SCL and the sensing line SSL may extend in the first direction DR1. The scan line SCL and the sensing line SSL may be connected to a scan driver SDR. The scan driver SDR may include a driving circuit. The scan driver SDR may be disposed at one side of the active area AA in the first direction DR1, but the invention is not limited thereto. The scan driver SDR may be connected to a signal connection wiring CWL, and at least one end of the signal connection wiring CWL may form a pad (or "pad") WPD_CW in the inactive area DS to be connected to an external device.

[0090] Meanwhile, in the specification, the term "connection" may mean that one component is connected to another component by physical contact, and one component is connected to the other component by another component. In addition, it is understood that one component and another component are integrated into one component, and a part of the integrated component is connected to another part of the integrated component. In addition, the connection between one component and another component may be interpreted as including an electrical connection through another component in addition to a connection through direct contact.

[0091] The data line DTL and the reference voltage wiring RVL may extend in a second direction DR2 intersecting the first direction DR1. In addition, the reference voltage wiring RVL may further include a portion branching from a portion extending in the second direction DR2 along the first direction DR1. Each of the first voltage wiring VDL and the second voltage wiring VSL may also include a portion extending in the second direction DR2 and a portion connected to the portion and extending in the first direction DR1. The first voltage wiring VDL and the second voltage wiring VSL may have a mesh structure, but the invention is not limited thereto. In addition, although not shown in the drawings, each of the pixels PX of the first display substrate 10 may be connected to at least one data line DTL, the reference voltage wiring RVL, the first voltage wiring VDL, and the second voltage wiring VSL.

[0092] The data line DTL, the reference voltage wiring RVL, the first voltage wiring VDL, and the second voltage wiring VSL may be electrically connected to one or more wiring pads WPD. Each wiring pad WPD may be arranged in the invalid area DS. In one embodiment, the wiring pad WPD_DT (hereinafter referred to as "data pad") of the data line DTL may be arranged in the pad area PDA located on one side of the active area AA in the second direction DR2, and the wiring pad WPD_RV (hereinafter referred to as "reference voltage pad") of the reference voltage wiring RVL, the wiring pad WPD_VDD (hereinafter referred to as "first power pad") of the first voltage wiring VDL, and the wiring pad WPD_VSS (hereinafter referred to as "second power pad") of the second voltage wiring VSL may be arranged in the pad area PDA located on the other side of the active area AA in the second direction DR2. As another example, the data pad WPD_DT, the reference voltage pad WPD_RV, the first power pad WPD_VDD, and the second power pad WPD_VSS may all be arranged in the same area (e.g., the invalid area DS located on the upper side of the active area AA). An external device may be mounted on the wiring pad WPD. The external device may be mounted on the wiring pad WPD through an anisotropic conductive film, ultrasonic bonding, or the like.

[0093] Each pixel PX of the first display substrate 10 includes a pixel driving circuit. The above wiring can apply a driving signal to each pixel driving circuit while passing through or around each pixel PX. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors of each pixel driving circuit may be modified differently. Hereinafter, the pixel driving circuit will be described by adopting an example in which the pixel driving circuit has a 3T1C structure including 3 transistors and 1 capacitor, but the invention is not limited thereto, and various other modified structures of the pixel PX (such as a 2T1C structure, a 7T1C structure, and a 6T1C structure) may be applied.

[0094] Figure 5 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0095] Reference Figure 5 In addition to the light emitting diode EL, each pixel PX or sub-pixel PXn (see Figure 6 ) also includes three transistors DRT, SCT and SST and a storage capacitor Cst.

[0096] The light emitting diode EL emits light according to the current supplied by the driving transistor DRT. The light emitting diode EL includes a first electrode, a second electrode, and a light emitting element 300 (see FIG. 1 ) disposed between the first electrode and the second electrode. Fig.11 ). Due to the electrical signals transmitted from the first electrode and the second electrode, the light emitting element 300 can emit light of a specific wavelength range. A detailed description thereof will be provided below.

[0097] One end of the light-emitting diode EL can be connected to the first source / drain electrode of the driving transistor DRT, and the other end thereof can be connected to the second voltage wiring VSL, through which a low potential voltage (second power voltage VSS) lower than the high potential voltage (first power voltage VDD) of the first voltage wiring VDL is supplied.

[0098] The driving transistor DRT adjusts the current flowing from the first voltage wiring VDL through which the first power voltage VDD is supplied to the light emitting diode EL according to the voltage difference between the gate electrode and the source electrode thereof. The gate electrode of the driving transistor DRT may be connected to the first source / drain electrode of the scanning transistor SCT, the first source / drain electrode of the driving transistor DRT may be connected to the first electrode of the light emitting diode EL, and the second source / drain electrode of the driving transistor DRT may be connected to the first voltage wiring VDL through which the first power voltage VDD is applied.

[0099] The scanning transistor SCT is turned on by the scanning signal of the scanning line SCL so that the data line DTL is connected to the gate electrode of the driving transistor DRT. The gate electrode of the scanning transistor SCT can be connected to the scanning line SCL, the first source / drain electrode of the scanning transistor SCT can be connected to the gate electrode of the driving transistor DRT, and the second source / drain electrode of the scanning transistor SCT can be connected to the data line DTL.

[0100] The sensing transistor SST is turned on by the sensing signal of the sensing line SSL so that the reference voltage wiring RVL is connected to the first source / drain electrode of the driving transistor DRT. The sensing transistor SST may include a gate electrode connected to the sensing line SSL, a first source / drain electrode connected to the reference voltage wiring RVL, and a second source / drain electrode connected to the first source / drain electrode of the driving transistor DRT.

[0101] In one embodiment, in each of the transistors DRT, SCT, and SST, the first source / drain electrode may be a source electrode and the second source / drain electrode may be a drain electrode, but the invention is not limited thereto and interchange of the above description may be possible.

[0102] The storage capacitor Cst is formed between the gate electrode and the first source / drain electrode of the driving transistor DRT. The storage capacitor Cst stores a voltage corresponding to a voltage difference between the gate voltage of the driving transistor DRT and the first source / drain voltage.

[0103] Each of the transistors DRT, SCT, and SST may be formed as a thin film transistor. Figure 5 In the present invention, each of the transistors DRT, SCT and SST has been described as being formed as an n-type metal oxide semiconductor field effect transistor (MOSFET), but the invention is not limited thereto. That is, each of the transistors DRT, SCT and SST may be formed as a p-type MOSFET, or some of them may be formed as n-type MOSFETs and others of them may be formed as p-type MOSFETs.

[0104] Hereinafter, the structure of one pixel PX of the first display substrate 10 according to one embodiment will be described in detail with further reference to other drawings.

[0105] Figure 6 is a schematic plan view showing one pixel of a display device according to an embodiment. Figure 7 is a schematic plan view of a circuit element layer included in one sub-pixel of a display device according to one embodiment. Figure 8 is a schematic plan view of a display element layer included in one pixel of a display device according to one embodiment. Fig. 9 It is along Figure 7 and Figure 8Cross-sectional views taken along line Qa-Qa', line Qb-Qb' and line Qc-Qc'. Fig.10 It is along Figure 7 and Figure 8 A cross-sectional view taken along line Q1-Q1'.

[0106] exist Figure 6 In the figure, the circuit elements and display elements provided in each sub-pixel PXn are partially omitted and shown. Figure 6 The regions "R", "G" and "B" in Figure 7 1 shows a circuit element layer of a sub-pixel (eg, the third sub-pixel PX3), Figure 8 A display element layer included in one pixel PX is shown. Fig. 9 and Fig.10 FIG. 1 shows a partial cross-section of the circuit element layer and the display element layer of the sub-pixel PXn. Figures 6 to 8 Both sides of the first direction DR1 may be respectively referred to as a left side and a right side, and both sides of the second direction DR2 may be respectively referred to as an upper side and a lower side.

[0107] Reference Figures 6 to 10 , each of the pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. The first color may be blue, the second color may be green, and the third color may be red. However, the invention is not limited thereto, and the sub-pixels PXn may emit light having the same color. In addition, Figure 6 In the figure, the pixel PX is shown to include three sub-pixels PXn, but is not limited thereto and may include a greater number of sub-pixels PXn.

[0108] Each of the sub-pixels PXn of the first display substrate 10 may include an area defined as a light emitting area EMA. The first sub-pixel PX1 may include a first light emitting area EMA1, the second sub-pixel PX2 may include a second light emitting area EMA2, and the third sub-pixel PX3 may include a third light emitting area EMA3. The light emitting area EMA may be defined as an area in which the light emitting element 300 included in the first display substrate 10 is disposed to emit light within a specific wavelength range. Light emitted from the light emitting layer 330 of the light emitting element 300 may be emitted to both end surfaces and side surfaces of the light emitting element 300. The light emitting area EMA may include an area in which the light emitting element 300 is disposed, and may include an area adjacent to the light emitting element 300 and through which light emitted from the light emitting element 300 is emitted.

[0109] The invention is not limited thereto, and the light emitting area EMA may also include an area in which light emitted from the light emitting element 300 is reflected or refracted due to another member and emitted. A plurality of light emitting elements 300 may be provided in each sub-pixel PXn, and an area in which the light emitting element 300 is provided and an area adjacent to the area may form the light emitting area EMA.

[0110] Although not shown in the drawings, each of the sub-pixels PXn of the first display substrate 10 may include a non-light emitting region defined as a region other than the light emitting region EMA. The non-light emitting region may be a region where the light emitting element 300 is not disposed and where light emitted from the light emitting element 300 does not reach and thus does not emit light.

[0111] In the first display substrate according to one embodiment, each pixel PX or sub-pixel PXn may include a circuit element layer and a display element layer. The display element layer may be a layer in which the first electrode 210, the second electrode 220, and the light emitting element 300 are disposed, and the circuit element layer may be a layer in which a pixel circuit element for driving the light emitting element 300 and a plurality of wirings are disposed. For example, in addition to the driving transistor DRT, the scanning transistor SCT, the sensing transistor SST, and the storage capacitor Cst, the circuit element layer may also include a scanning line SCL, a sensing line SSL, a data line DTL, a reference voltage wiring RVL, a first voltage wiring VDL, a second voltage wiring VSL, etc.

[0112] Specifically, the first display substrate 10 may include a first substrate 101, and the circuit element layer and the display element layer may be disposed on the first substrate 101. The first substrate 101 may be made of an insulating material such as glass, quartz, polymer resin, etc. In addition, the first substrate 101 may be a rigid substrate, but may also be a flexible substrate that is bendable, foldable, rollable, etc.

[0113] The light blocking layer BML may be disposed on the first substrate 101. The light blocking layer BML may be disposed to overlap a portion of the first active layer DRT_ACT of the driving transistor DRT, which will be described below. The light blocking layer BML may include a material that blocks light, thereby preventing light from being incident on the first active layer DRT_ACT. As an example, the light blocking layer BML may be made of an opaque metal material that blocks light transmission. However, the invention is not limited thereto, and in some cases, the light blocking layer BML may be omitted, or may be disposed in a larger number to overlap with the active layers of other transistors.

[0114] The buffer layer 102 is disposed on the first substrate 101 and the light blocking layer BML. The buffer layer 102 may be completely disposed on the first substrate 101. The buffer layer 102 may be formed on the first substrate 101 to protect the transistor of the pixel PX from moisture penetrating through the first substrate 101 susceptible to moisture penetration, and may perform a surface planarization function. The buffer layer 102 may be formed as a plurality of inorganic layers alternately stacked. For example, the buffer layer 102 may be composed of silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer and a silicon oxynitride (SiON) layer are alternately stacked in a multilayer.

[0115] The semiconductor layer is disposed on the buffer layer 102. The semiconductor layer may form an active layer of each of the transistors. The semiconductor layer may include a first active layer DRT_ACT of the drive transistor DRT, a second active layer SCT_ACT of the scan transistor SCT, and a third active layer SST_ACT of the sensing transistor SST. Each of the active layers may be arranged to partially overlap with the gate electrode of the first gate conductive layer, which will be described below. In the accompanying drawings, the first active layer DRT_ACT and the third active layer SST_ACT may be arranged on the lower side relative to the center of each sub-pixel PXn, and the second active layer SCT_ACT may be arranged on the upper side relative to the center of each sub-pixel PXn. In addition, the first active layer DRT_ACT and the third active layer SST_ACT may be integrally formed as a semiconductor layer, and the drive transistor DRT and the sensing transistor SST may be electrically connected to each other.

[0116] In addition, the semiconductor layer may further include a first semiconductor pattern SP1. The first semiconductor pattern SP1 may be connected to a gate electrode of a sensing transistor SST and a sensing line SSL, which will be described below.

[0117] Meanwhile, in an embodiment, the semiconductor layer may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, and the like. When the semiconductor layer includes polycrystalline silicon, each of the active layers may include a doped region and a channel region. For example, the first active layer DRT_ACT may include a first doped region DRT_ACTa, a second doped region DRT_ACTb, and a first channel region DRT_ACTc. Each doped region may be a region doped with impurities, and the channel region may be disposed between the doped regions. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of crystallization methods may include a rapid thermal annealing (RTA) method, a solid phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method, and the like, but the invention is not limited thereto. As another example, the semiconductor layer may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, and the like.

[0118] However, the semiconductor layer is not necessarily limited to the above description. In an embodiment, the semiconductor layer may also include an oxide semiconductor. In this case, each doped region may be a conductor region. In an embodiment, when the semiconductor layer includes an oxide semiconductor, the oxide semiconductor may be an oxide semiconductor containing indium (In). In some embodiments, the oxide semiconductor may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. However, the invention is not limited thereto.

[0119] The first gate insulating layer 103 is provided on the semiconductor layer and the buffer layer 102. The first gate insulating layer 103 may be used as a gate insulating film of each of the transistors. The first gate insulating layer 103 may be formed to include a silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) or is formed into a stacked structure of inorganic layers.

[0120] The first gate conductive layer is disposed on the first gate insulating layer 103. The first gate conductive layer may include a gate electrode of each of the transistors, a scan line SCL, a sensing line SSL, a second voltage wiring VSL, a reference voltage distribution line RVT, and a first capacitor electrode CSE1 of the storage capacitor Cst.

[0121] The gate electrode of each of the transistors may be arranged to partially overlap with the corresponding active layer. For example, the first gate electrode DRT_G of the driving transistor DRT may overlap with a portion of the first active layer DRT_ACT, the second gate electrode SCT_G of the scanning transistor SCT may overlap with a portion of the second active layer SCT_ACT, and the third gate electrode SST_G of the sensing transistor SST may overlap with a portion of the third active layer SST_ACT. The first gate electrode DRT_G may be connected to the first capacitor electrode CSE1 to form a single pattern. The second gate electrode SCT_G may be electrically connected to the scanning line SCL, and the third gate electrode SST_G may be electrically connected to the sensing line SSL through the first semiconductor pattern SP1.

[0122] The scan line SCL may extend in the first direction DR1 and may be disposed to exceed a boundary of an adjacent sub-pixel PXn. The scan line SCL may be disposed at an upper side relative to a center of the sub-pixel PXn. The scan line SCL may be electrically connected to the second gate electrode SCT_G through a conductive pattern of a first data conductive layer to be described below, and may transmit a scan signal to the scan transistor SCT.

[0123] The sensing line SSL may extend in the first direction DR1 and may be disposed beyond the boundary of the adjacent sub-pixel PXn. The sensing line SSL may be disposed at the lower side in the second direction DR2 relative to the center of the sub-pixel PXn. The sensing line SSL may be electrically connected to the third gate electrode SST_G through the first semiconductor pattern SP1 and may transmit a sensing signal to the sensing transistor SST.

[0124] The reference voltage distribution line RVT may be disposed at a lower side of the sensing line SSL and may extend in the first direction DR1. The reference voltage distribution line RVT may be disposed to extend from the first sub-pixel PX1 to the third sub-pixel PX3, and each pixel PX (i.e., three sub-pixels PXn) may share one reference voltage distribution line RVT. The reference voltage distribution line RVT may be electrically connected to a reference voltage wiring RVL and a first source / drain electrode of a sensing transistor SST of each sub-pixel PXn, which will be described below. The reference voltage distribution line RVT may transmit a reference voltage applied from the reference voltage wiring RVL to the sensing transistor SST.

[0125] The second voltage wiring VSL may extend in the second direction DR2, and may be set to exceed the boundary of the sub-pixel PXn adjacent in the second direction DR2. One second voltage wiring VSL may be set in each pixel PX, that is, one second voltage wiring VSL is set for every three sub-pixels PXn. For example, the second voltage wiring VSL may be set on the right side of the third sub-pixel PX3 to extend in the second direction DR2, and may not be set in the first sub-pixel PX1 and the second sub-pixel PX2. As described above, the second voltage wiring VSL may be electrically connected to the wiring pad WPD so that the second power voltage VSS may be connected to the second voltage wiring VSL. The second voltage wiring VSL may be electrically connected to the second electrode 220 to be described below, so that the second power voltage VSS may be applied to the light emitting element 300.

[0126] However, the invention is not limited thereto. In some embodiments, the second voltage wiring VSL may further include a portion extending in the first direction DR1. The second electrode 220 of each sub-pixel PXn may be electrically connected to the portion of the second voltage wiring VSL extending in the first direction DR1. In addition, the second voltage wiring VSL does not have to be disposed in the first gate conductive layer, but may be disposed in the first data conductive layer, which will be described below.

[0127] The first capacitor electrode CSE1 of the storage capacitor Cst is disposed between the scan line SCL and the sensing line SSL. The first capacitor electrode CSE1 of the storage capacitor Cst may be electrically connected to the first gate electrode DRT_G and the first source / drain electrode SCT_SD1 of the scan transistor SCT. In addition, as will be described below, in a plan view, the first capacitor electrode CSE1 may be located between the first voltage wiring VDL and the data line DTL.

[0128] The first source / drain electrode SCT_SD1 of the scan transistor SCT may contact the second active layer SCT_ACT through the fifth contact hole CT5 in a region overlapping one side of the second active layer SCT_ACT. The scan transistor SCT may be connected to the first capacitor electrode CSE1 of the storage capacitor Cst. For example, the first source / drain electrode SCT_SD1 of the scan transistor SCT may be integrated with the first capacitor electrode CSE1 of the storage capacitor Cst.

[0129] The first gate conductive layer may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys thereof. However, the present invention is not limited thereto.

[0130] The first interlayer insulating layer 105 is disposed on the first gate conductive layer. The first interlayer insulating layer 105 may be used as an insulating film between the first gate conductive layer and other layers disposed thereon. The first interlayer insulating layer 105 may be formed to include a silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiON) or is formed into a stacked structure of inorganic layers.

[0131] Meanwhile, although not shown in the drawings, more insulating layers and conductive layers may be disposed on the first gate conductive layer and the first interlayer insulating layer 105. At least a portion of the conductive layer may be disposed to overlap the first gate conductive layer with the insulating layer interposed therebetween.

[0132] The first data conductive layer is disposed on the first interlayer insulating layer 105. The first data conductive layer may include a data line DTL, a first voltage wiring VDL, a reference voltage wiring RVL, a source / drain electrode of each of transistors, a plurality of conductive patterns SDP1 and VCP, and a second capacitor electrode CSE2 of a storage capacitor Cst.

[0133] The data line DTL may extend in the second direction DR2 and may be disposed to exceed a boundary of an adjacent sub-pixel PXn. The data line DTL may be disposed on the right side relative to the center of the sub-pixel PXn. The data line DTL may contact one side of the second active layer SCT_ACT through a fourth contact hole CT4. A portion of the data line DTL may be a second source / drain electrode of the scan transistor SCT, and a data signal applied to the data line DTL may be transmitted to the scan transistor SCT.

[0134] The first voltage wiring VDL may extend in the second direction DR2 and may be disposed beyond the boundary of the adjacent sub-pixel PXn. The first voltage wiring VDL may be disposed on the left side relative to the center of the sub-pixel PXn. The first voltage wiring VDL may contact one side of the first active layer DRT_ACT through the first contact hole CT1. That is, a portion of the first voltage wiring VDL may be connected to the first source / drain electrode DRT_SD1 (see FIG. 1 ) of the driving transistor DRT. Fig. 9 ), the first power voltage VDD applied to the first voltage wiring VDL can be transmitted to the driving transistor DRT.

[0135] The first voltage wiring VDL and the data line DTL may be disposed in each subpixel PXn. The first voltage wiring VDL and the data line DTL may be disposed at the left and right sides with respect to the center of each subpixel PXn, respectively, and may be disposed to extend in the second direction DR2.

[0136] The reference voltage wiring RVL may extend in the second direction DR2 and may be arranged to exceed the boundary of the sub-pixels PXn adjacent in the second direction DR2. One reference voltage wiring RVL may be arranged in each pixel PX, that is, one reference voltage wiring RVL may be arranged for every three sub-pixels PXn. For example, the reference voltage wiring RVL may be arranged on the right side of the data line DTL in the third sub-pixel PX3, and may not be arranged in the first sub-pixel PX1 and the second sub-pixel PX2. The reference voltage wiring RVL may be electrically connected to the above-mentioned reference voltage distribution line RVT. The reference voltage wiring RVL may be electrically connected to the reference voltage distribution line RVT through the tenth contact hole CT10. The reference voltage applied through the reference voltage wiring RVL may be transmitted to the sensing transistor SST of each sub-pixel PXn through the reference voltage distribution line RVT.

[0137] The second capacitor electrode CSE2 of the storage capacitor Cst is disposed between the first voltage wiring VDL and the data line DTL. The second capacitor electrode CSE2 of the storage capacitor Cst may be disposed to overlap the first capacitor electrode CSE1, and a storage capacitor may be formed between the second capacitor electrode CSE2 and the first capacitor electrode CSE1 (see Fig.10That is, in one embodiment, each of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be located between the first voltage wiring VDL and the data line DTL in a plan view. The second capacitor electrode CSE2 of the storage capacitor Cst may be connected to the second source / drain electrode DRT_SD (or Fig. 9 ”DRT_SD2” in ). For example, the second capacitor electrode CSE2 of the storage capacitor Cst can be integrated with the second source / drain electrode DRT_SD2 of the driving transistor DRT. The second source / drain electrode DRT_SD2 of the driving transistor DRT can contact a portion of the first active layer DRT_ACT through the second contact hole CT2, and can contact a portion of the light blocking layer BML through the third contact hole CT3. In addition, the second source / drain electrode DRT_SD2 of the driving transistor DRT can also contact one side of the third active layer SST_ACT through the eighth contact hole CT8, and the one side can constitute the source / drain electrode of the sensing transistor SST.

[0138] The first source / drain electrode SST_SD of the sensing transistor SST may contact the other side of the third active layer SST_ACT and the reference voltage distribution line RVT. The first source / drain electrode SST_SD of the sensing transistor SST may contact the third active layer SST_ACT through the seventh contact hole CT7 and may contact the reference voltage distribution line RVT through the tenth contact hole CT10.

[0139] The first conductive pattern SDP1 and the second conductive pattern VCP of the first data conductive layer may be connected to a portion of the first gate conductive layer. The first conductive pattern SDP1 may be connected to the scan line SCL and the second gate electrode SCT_G, and a scan signal applied from the scan line SCL may be transmitted to the scan transistor SCT. The first conductive pattern SDP1 may contact the scan line SCL and the second gate electrode SCT_G of the scan transistor SCT through a sixth contact hole CT6 passing through the first interlayer insulating layer 105. The second gate electrode SCT_G may be electrically connected to the scan line SCL through the first conductive pattern SDP1, and the scan signal may be transmitted to the scan transistor SCT.

[0140] The second conductive pattern VCP may be disposed to overlap with the second voltage wiring VSL. The second conductive pattern VCP may contact the second voltage wiring VSL through the first wiring contact hole CTS1 passing through the first interlayer insulating layer 105. In addition, the second conductive pattern VCP may contact the second electrode 220 through the second wiring contact hole CTS2, which will be described below. The second electrode 220 may be electrically connected to the second voltage wiring VSL through the second conductive pattern VCP.

[0141] The first data conductive layer may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. However, the present invention is not limited thereto.

[0142] The first protective layer 107 is disposed on the first data conductive layer. The first protective layer 107 may be disposed to cover the first data conductive layer and may perform a function of protecting the first data conductive layer. The first protective layer 107 may be formed to include a silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) or is formed into a stacked structure of inorganic layers.

[0143] The first planarization layer 109 is disposed on the first protective layer 107. The first planarization layer 109 may include an organic insulating material (e.g., an organic material such as polyimide (PI)) and may perform a surface planarization function. However, the invention is not limited thereto. A greater number of conductive layers may be disposed between the first planarization layer 109 and the first protective layer 107.

[0144] A display element layer including inner banks 410 and 420, multiple electrodes 210 and 220, outer banks 450, multiple contact electrodes 261 and 262, and light emitting elements 300 is disposed on the first planarization layer 109. In addition, multiple insulating layers IL1, IL2, and IL3 may be further disposed on the first planarization layer 109.

[0145] The inner banks 410 and 420 are disposed directly on the first planarization layer 109. The inner banks 410 and 420 may include a first inner bank 410 and a second inner bank 420 disposed adjacent to a central portion of each pixel PX or sub-pixel PXn.

[0146] The first inner bank 410 and the second inner bank 420 may be arranged to be spaced apart from each other and face each other in the first direction DR1. In addition, the first inner bank 410 and the second inner bank 420 may extend in the second direction DR2, and may be separated and terminated at the boundary between the sub-pixels PXn so as not to extend to another sub-pixel PXn adjacent in the second direction DR2. The first inner bank 410 and the second inner bank 420 may be arranged in each sub-pixel PXn to form a pattern in the entire area of ​​the active area AA. By arranging the inner banks 410 and 420 to be spaced apart from each other and face each other, an area in which the light emitting element 300 is arranged may be formed between the inner banks 410 and 420. In the accompanying drawings, two first inner banks 410 and one second inner bank 420 arranged between the two first inner banks 410 are shown, but the invention is not limited thereto. In some cases, a greater number of inner banks 410 and 420 may be further arranged according to the number of electrodes 210 and 220.

[0147] According to one embodiment, in a plan view, the first inner bank 410 and the second inner bank 420 may be located between the first voltage wiring VDL and the data line DTL. As will be described below, the outer bank 450 may be provided at the boundary of each of the sub-pixels PXn, the first voltage wiring VDL and the data line DTL may be provided in each sub-pixel PXn and may partially overlap with the outer bank 450 in the thickness direction. The first inner bank 410 and the second inner bank 420 may each be provided to be spaced apart from the outer bank 450 and may be located between the first voltage wiring VDL and the data line DTL. That is, the first voltage wiring VDL may extend in the second direction DR2 between the second inner bank 420 and the outer bank 450 adjacent to the second inner bank 420 in a plan view, and in some cases, the first voltage wiring VDL may overlap with the first inner bank 410 in the thickness direction. The data line DTL may extend in the second direction DR2 between the first inner bank 410 and the outer bank 450 adjacent to the first inner bank 410 in a plan view, and in some cases, the data line DTL may overlap with the first inner bank 410 in a thickness direction. As used herein, the term "thickness direction" may refer to a vertical direction in a cross section, or a direction in which a plurality of layers are overlapped. Components overlapped in the thickness direction may mean that at least a portion of the components are arranged to overlap each other in a plan view. In other words, the first voltage wiring VDL and the data line DTL may be arranged to overlap with the first inner bank 410 and the second inner bank 420 in a plan view, respectively, but the invention is not limited thereto.

[0148] In addition, in some embodiments, at least a portion of the first inner bank 410 may overlap with the first voltage wiring VDL in the thickness direction, and the second inner bank 420 may not overlap with the data line DTL in the thickness direction. On the other hand, the data line DTL may overlap with a portion of the outer bank 450 extending in the second direction DR2 in the thickness direction, and the first voltage wiring VSL may not overlap with a portion of the outer bank 450 extending in the second direction DR2 in the thickness direction. However, the invention is not limited thereto.

[0149] Each of the first inner bank 410 and the second inner bank 420 may have a predetermined width, and may have a structure in which at least a portion thereof protrudes relative to the upper surface of the first planarization layer 109. Each of the first inner bank 410 and the second inner bank 420 may have the same width, and the protruding portion thereof may have an inclined side surface, and light emitted from the light emitting element 300 disposed between the first inner bank 410 and the second inner bank 420 may travel toward the inclined side surfaces of the inner banks 410 and 420. As will be described below, the electrodes 210 and 220 disposed on the inner banks 410 and 420, respectively, may include a material having a high reflectivity, and light emitted from the light emitting element 300 may be reflected from the electrodes 210 and 220 disposed on the side surfaces of the inner banks 410 and 420 to be emitted in an upward direction relative to the first substrate 101. That is, the inner banks 410 and 420 may provide a region in which the light emitting element 300 is disposed, and at the same time may function as a reflective partition wall that reflects light emitted from the light emitting element 300 upward. In an embodiment, the inner banks 410 and 420 may include an organic insulating material such as polyimide (PI), but the invention is not limited thereto.

[0150] The plurality of electrodes 210 and 220 are disposed on the inner banks 410 and 420 and the first planarization layer 109. The plurality of electrodes 210 and 220 may include a first electrode 210 disposed on the first inner bank 410 and a second electrode 220 disposed on the second inner bank 420.

[0151] The first electrode 210 and the second electrode 220 may include electrode stem portions 210S and 220S extending in the first direction DR1 and one or more electrode branch portions 210B and 220B branched from the electrode stem portions 210S and 220S in the second direction DR2 , respectively.

[0152] Specifically, the first electrode 210 may include a first electrode trunk portion 210S disposed to extend in the first direction DR1 and one or more first electrode branch portions 210B branched from the first electrode trunk portion 210S to extend in the second direction DR2. Both ends of the first electrode trunk portion 210S of any one subpixel PXn may be spaced apart from each other and terminated between the subpixels PXn, and substantially placed on the same straight line with the first electrode trunk portion 210S of the adjacent subpixel PXn (e.g., which is adjacent in the first direction DR1) in the same row. Since both ends of each of the first electrode trunk portions 210S disposed in each subpixel PXn are spaced apart from each other, an electrical signal may be independently transmitted to each of the first electrode branch portions 210B.

[0153] The first electrode branch portion 210B branches from at least a portion of the first electrode stem portion 210S and is disposed to extend in the second direction DR2. The first electrode branch portion 210B may terminate in a state of being spaced apart from the second electrode stem portion 220S disposed to face the first electrode stem portion 210S.

[0154] The first electrode 210 may be electrically connected to the driving transistor DRT. For example, the first electrode 210 may be in contact with the second source / drain electrode DRT_SD2 through an electrode contact hole CTD, which is formed at a portion overlapping the first electrode trunk portion 210S and passes through the first planarization layer 109 to expose a portion of the upper surface of the second source / drain electrode DRT_SD2 of the driving transistor DRT. However, the invention is not limited thereto. In some embodiments, a greater number of conductive layers may be provided between the first planarization layer 109 and the first data conductive layer, and the first electrode 210 may be electrically connected to the driving transistor DRT through the conductive layer.

[0155] The second electrode 220 may include a second electrode trunk portion 220S disposed to extend in the first direction DR1 and one or more second electrode branch portions 220B branched from the second electrode trunk portion 220S to extend in the second direction DR2. The second electrode trunk portion 220S may be disposed to be spaced apart from and face the first electrode trunk portion 210S in the second direction DR2, and the second electrode branch portion 220B may be disposed to be spaced apart from and face one or more first electrode branch portions 210B in the first direction DR1. As an example, the second electrode branch portion 220B may be disposed between two first electrode branch portions 210B, and both sides of the second electrode branch portion 220B may be spaced apart from and face the first electrode branch portions 210B, respectively.

[0156] Unlike the first electrode trunk portion 210S, the second electrode trunk portion 220S may be disposed to extend in the first direction DR1 to cross each of the subpixels PXn. The second electrode branch portion 220B may branch from the second electrode trunk portion 220S in the second direction DR2 and terminate in a state of being spaced apart from the first electrode trunk portion 210S. A plurality of light emitting elements 300 may be disposed between the second electrode branch portion 220B and the first electrode branch portion 210B.

[0157] The second electrode 220 may be electrically connected to the second voltage wiring VSL. For example, the second electrode 220 may contact the second conductive pattern VCP through a second wiring contact hole CTS2, which is formed between the third sub-pixel PX3 and the sub-pixel PXn adjacent to the first direction DR1 and passes through the first planarization layer 109 to expose a portion of the upper surface of the second conductive pattern VCP. The second electrode 220 may be electrically connected to the second voltage wiring VSL through the second conductive pattern VCP. However, the invention is not limited thereto. When the second voltage wiring VSL is disposed in the first data conductive layer, the second conductive pattern VCP may be omitted, and the second electrode 220 may directly contact the second voltage wiring VSL.

[0158] In the drawings, it is shown that two first electrode branch portions 210B and one second electrode branch portion 220B are arranged in one sub-pixel PXn, and the first electrode 210 is arranged in a shape surrounding the outer surface of the second electrode branch portion 220B. However, the invention is not limited thereto. A greater or lesser number of electrode branch portions 210B and 220B may be arranged in each sub-pixel PXn. In this case, the first electrode branch portion 210B and the second electrode branch portion 220B may be alternately arranged spaced apart from each other.

[0159] At the same time, each of the first electrode 210 and the second electrode 220 may not necessarily have a shape extending in one direction, but may have various shapes. For example, the first electrode 210 and the second electrode 220 may each have a partially bent or folded shape, and one of the first electrode 210 and the second electrode 220 may also be arranged to surround the other electrode. As long as at least a portion of the first electrode 210 and at least a portion of the second electrode 220 are spaced apart from each other and face each other to form a region where the light emitting element 300 is to be arranged between the first electrode 210 and the second electrode 220, the arrangement structure and shape of the first electrode 210 and the second electrode 220 are not particularly limited.

[0160] The plurality of electrodes 210 and 220 may be electrically connected to the light emitting element 300, and may receive a predetermined voltage to allow the light emitting element 300 to emit light. For example, the plurality of electrodes 210 and 220 may be electrically connected to the light emitting element 300 through contact electrodes 261 and 262 to be described below, and an electrical signal applied to the electrodes 210 and 220 may be transmitted to the light emitting element 300 through the contact electrodes 261 and 262.

[0161] In an embodiment, the first electrode 210 may be a pixel electrode separated for each sub-pixel PXn, and the second electrode 220 may be a common electrode commonly connected along each sub-pixel PXn. One of the first electrode 210 and the second electrode 220 may be an anode of the light-emitting element 300, and the other may be a cathode of the light-emitting element 300. However, the invention is not limited thereto, and the above description may be interchangeable.

[0162] In addition, each of the electrodes 210 and 220 may be used to form an electric field in the sub-pixel PXn, thereby aligning the light emitting element 300. The light emitting element 300 may be disposed between the first electrode 210 and the second electrode 220 by applying an alignment signal to the first electrode 210 and the second electrode 220 through a process of forming an electric field between the first electrode 210 and the second electrode 220. The light emitting element 300 may be ejected onto the first electrode 210 and the second electrode 220 in a state dispersed in ink by an inkjet printing process, and may be aligned between the first electrode 210 and the second electrode 220 by applying an alignment signal between the first electrode 210 and the second electrode 220 through a method of applying a dielectrophoretic force to the light emitting element 300.

[0163] The first electrode 210 and the second electrode 220 may be disposed on the first inner bank 410 and the second inner bank 420, respectively, and may be spaced apart from each other and face each other in the first direction DR1. A plurality of light emitting elements 300 may be disposed between the first inner bank 410 and the second inner bank 420, and at least one end of each of the light emitting elements 300 may be electrically connected to the first electrode 210 and the second electrode 220. The first electrode 210 and the second electrode 220 disposed on the first inner bank 410 and the second inner bank 420 may be a portion of the first electrode branch portion 210B and a portion of the second electrode branch portion 220B, respectively.

[0164] In some embodiments, the first electrode 210 and the second electrode 220 may be formed to have a width greater than that of the first inner bank 410 and the second inner bank 420, respectively. For example, the first electrode 210 and the second electrode 220 may be disposed to cover the outer surfaces of the first inner bank 410 and the second inner bank 420, respectively. The first electrode 210 and the second electrode 220 may be disposed on the side surfaces of the first inner bank 410 and the second inner bank 420, respectively, and the separation distance between the first electrode 210 and the second electrode 220 may be smaller than the separation distance between the first inner bank 410 and the second inner bank 420. In addition, at least a partial area of ​​each of the first electrode 210 and the second electrode 220 may be directly disposed on the first planarization layer 109.

[0165] Each of the electrodes 210 and 220 may include a transparent conductive material. As an example, each of the electrodes 210 and 220 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., but the invention is not limited thereto. In some embodiments, each of the electrodes 210 and 220 may include a conductive material having a high reflectivity. For example, each of the electrodes 210 and 220 may include a metal such as silver (Ag), copper (Cu), aluminum (Al), etc. as a material having a high reflectivity. In this case, each of the electrodes 210 and 220 may reflect light emitted from the light emitting element 300 and traveling to the side surfaces of the first inner bank 410 and the second inner bank 420 in an upward direction relative to each sub-pixel PXn.

[0166] The invention is not limited thereto, and each of the electrodes 210 and 220 may be formed in a structure in which one or more layers of a transparent conductive material and a metal layer having high reflectivity are stacked, or may be formed as a single layer including a transparent conductive material and a metal layer. In an embodiment, each of the electrodes 210 and 220 may have a stacked structure of ITO / Ag / ITO / IZO, or may be an alloy including Al, Ni, lanthanum (La), etc.

[0167] The first insulating layer IL1 is disposed on the first planarization layer 109, the first electrode 210, and the second electrode 220. The first insulating layer IL1 may be disposed on a side opposite to the region between the inner banks 410 and 420 with respect to the inner banks 410 and 420, except for the region between the electrodes 210 and 220 or between the inner banks 410 and 420 which are spaced apart from each other. For example, the first insulating layer IL1 may be entirely disposed on the first electrode 210 and the second electrode 220 and the first planarization layer 109, and may be disposed to expose a portion of the upper surface of each of the first electrode 210 and the second electrode 220. An opening (not shown) partially exposing the first electrode 210 and the second electrode 220 may be formed in the first insulating layer IL1, and the first insulating layer IL1 may be disposed to cover only one side and the other side of each of the first electrode 210 and the second electrode 220. Some portions of the portions of the first electrode 210 and the second electrode 220 respectively disposed on the inner banks 410 and 420 may be partially exposed due to the opening.

[0168] The first insulating layer IL1 may protect the first electrode 210 and the second electrode 220, and at the same time insulate the first electrode 210 from the second electrode 220. In addition, the first insulating layer IL1 may prevent the light emitting element 300 disposed on the first insulating layer IL1 from being damaged by direct contact with other members. However, the shape and structure of the first insulating layer IL1 are not limited thereto.

[0169] In some embodiments, a step difference may be formed on a portion of the upper surface of the first insulating layer IL1 between the first electrode 210 and the second electrode 220. In some embodiments, the first insulating layer IL1 may include an inorganic insulating material, and a portion of the upper surface of the first insulating layer IL1 disposed to partially cover the first electrode 210 and the second electrode 220 may be stepped due to the electrodes 210 and 220 disposed below the first insulating layer IL1. Therefore, an empty space may be formed between the light emitting element 300 (the light emitting element 300 is disposed on the first insulating layer IL1 between the first electrode 210 and the second electrode 220) and the upper surface of the first insulating layer IL1. The empty space may be filled with a material forming the second insulating layer IL2, which will be described below.

[0170] However, the invention is not limited thereto. The first insulating layer IL1 may be formed so that a portion thereof disposed between the first electrode 210 and the second electrode 220 has a flat upper surface. The upper surface extends in one direction toward the first electrode 210 and the second electrode 220, and the first insulating layer IL1 may also be disposed in a region where the electrodes 210 and 220 overlap the inclined side surfaces of the first inner bank 410 and the second inner bank 420, respectively. The contact electrodes 261 and 262 to be described below may contact the exposed regions of the first electrode 210 and the second electrode 220, and may smoothly contact the end of the light emitting element 300 on the flat upper surface of the first insulating layer IL1.

[0171] The outer bank 450 may be disposed on the first insulating layer IL1. The outer bank 450 may be disposed at a boundary between each of the sub-pixels PXn. The outer bank 450 may be disposed to extend in the first direction DR1 and the second direction DR2 to surround the inner banks 410 and 420 and some of the electrodes 210 and 220 and an area in which the light emitting element 300 is disposed between the inner banks 410 and 420 and between the electrodes 210 and 220. The outer bank 450 may form a grid pattern on the entire surface of the active area AA of the first display substrate 10.

[0172] The external bank 450 may be disposed at a boundary between each of the sub-pixels PXn, and may partially overlap with a wiring disposed in each sub-pixel PXn or pixel PX in a thickness direction. In an embodiment, the external bank 450 may overlap with a data line DTL disposed in each sub-pixel PXn in a plan view in a thickness direction, and some of the external bank 450 may overlap with a reference voltage wiring RVL disposed in each pixel PX in a thickness direction. A portion of the external bank 450 extending in the second direction DR2 may partially overlap with a wiring extending in the second direction DR2 while being disposed at a boundary of a sub-pixel PXn adjacent in the first direction DR1. In addition, even a wiring extending in the first direction DR1 (e.g., a scan line SCL and a sense line SSL) may be disposed to overlap with a portion of the external bank 450 extending in the second direction DR2 in a thickness direction. However, the scan line SCL and the sense line SSL may be disposed not to overlap with a portion of the external bank 450 extending in the first direction DR1 in a thickness direction.

[0173] According to one embodiment, the height of the outer bank 450 may be greater than the height of each of the inner banks 410 and 420. Unlike the inner banks 410 and 420, the outer bank 450 may divide adjacent sub-pixels PXn and simultaneously prevent ink from overflowing to adjacent sub-pixels PXn in an inkjet printing process for setting the light-emitting element 300 during the manufacturing process of the first display substrate 10. That is, the outer bank 450 may separate inks in different sub-pixels PXn in which different light-emitting elements 300 are dispersed from each other to prevent the inks from mixing with each other. Similar to the inner banks 410 and 420, the outer bank 450 may include polyimide (PI), but the invention is not limited thereto.

[0174] The light emitting element 300 may be disposed in a region formed between the first electrode 210 and the second electrode 220 or in a region formed between the first inner bank 410 and the second inner bank 420. One end of the light emitting element 300 may be electrically connected to the first electrode 210, and the other end thereof may be electrically connected to the second electrode 220. The light emitting element 300 may be electrically connected to the first electrode 210 and the second electrode 220 through the contact electrodes 261 and 262, respectively.

[0175] A plurality of light emitting elements 300 may be arranged to be spaced apart from each other and aligned substantially parallel to each other. The spacing distance between the light emitting elements 300 is not particularly limited. In some cases, a plurality of light emitting elements 300 may be arranged adjacent to each other to form a group, and a plurality of other light emitting elements 300 may be grouped in a state spaced apart at a predetermined spacing, and may be oriented and aligned in one direction with an uneven density. In addition, in an embodiment, the light emitting element 300 may have a shape extending in one direction, and the direction in which each of the electrodes 210 and 220 extends may be substantially perpendicular to the direction in which the light emitting element 300 extends. However, the invention is not limited thereto, and the light emitting element 300 may be arranged obliquely, without being perpendicular to the direction in which each of the electrodes 210 and 220 extends.

[0176] The light emitting element 300 according to one embodiment may include a light emitting layer 330 having different materials to emit light of different wavelength ranges to the outside. According to one embodiment, each of the sub-pixels PXn may include a light emitting element 300 emitting light of different wavelength ranges. The light emitting element 300 of the first sub-pixel PX1 may include a light emitting layer 330 emitting light of a first color having a first wavelength within the center wavelength range, the light emitting element 300 of the second sub-pixel PX2 may include a light emitting layer 330 emitting light of a second color having a second wavelength within the center wavelength range, and the light emitting element 300 of the third sub-pixel PX3 may include a light emitting layer 330 emitting light of a third color having a third wavelength within the center wavelength range.

[0177] Thus, light of a first color may be emitted from the first subpixel PX1, light of a second color may be emitted from the second subpixel PX2, and light of a third color may be emitted from the third subpixel PX3. However, the invention is not limited thereto. In some cases, the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 may include the same type of light emitting element 300 to emit light of substantially the same color.

[0178] The light emitting element 300 may be disposed on the first insulating layer IL1 between the inner banks 410 and 420 or between the electrodes 210 and 220. In addition, the light emitting element 300 may be disposed so that a partial region thereof overlaps each of the electrodes 210 and 220 in the thickness direction. One end portion of the light emitting element 300 may overlap the first electrode 210 in the thickness direction and may be placed on the first electrode 210, and the other end portion thereof may overlap the second electrode 220 in the thickness direction and may be placed on the second electrode 220. However, the invention is not limited thereto, and although not shown in the drawings, at least some of the light emitting elements 300 disposed in each sub-pixel PXn may be disposed in a region other than the region formed between the inner banks 410 and 420 (e.g., a region between the inner banks 410 and 420 and the outer bank 450).

[0179] Meanwhile, the light emitting element 300 may be disposed between the first inner bank 410 and the second inner bank 420, and the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be disposed between the first voltage wiring VDL and the data line DTL. According to one embodiment, at least some of the light emitting elements 300 may be disposed to overlap with the first capacitor electrode CSE1 and the second capacitor electrode CSE2 of the circuit element layer in the thickness direction. As described above, in a plan view, the inner banks 410 and 420 and the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be located between the first voltage wiring VDL and the data line DTL. At least some of the light emitting elements 300 disposed between the inner banks 410 and 420 may be disposed to overlap with the first capacitor electrode CSE1 and the second capacitor electrode CSE2 of the circuit element layer. Light emitted from both end surfaces of the light emitting element 300 may be reflected by the electrodes 210 and 220 disposed on the side surfaces of the inner banks 410 and 420 to be emitted in an upward direction relative to the first substrate 101.

[0180] However, the invention is not limited thereto. In some embodiments, the non-luminous region in which the circuit element is disposed and the luminous region EMA in which the luminous element 300 is disposed may be separately located in the first display substrate 10, and the luminous element 300 may not overlap with the circuit element in the thickness direction. In the first display substrate 10, the light emitted from the luminous element 300 may be emitted in an upward or backward direction relative to the first substrate 101.

[0181] The light emitting element 300 may include a plurality of layers arranged therein in a direction parallel to the upper surface of the first substrate 101 or the first planarization layer 109. The light emitting element 300 according to one embodiment may have a shape extending in one direction and have a structure in which a plurality of semiconductor layers are sequentially arranged in one direction. The light emitting element 300 may be arranged so that one direction in which the light emitting element 300 extends is parallel to the first planarization layer 109, and a plurality of semiconductor layers included in the light emitting element 300 may be sequentially arranged in a direction parallel to the upper surface of the first planarization layer 109. However, the invention is not limited thereto. In some cases, when the light emitting element 300 has a different structure, a plurality of layers may be arranged in a direction perpendicular to the first planarization layer 109.

[0182] The second insulating layer IL2 may be partially disposed on the light emitting element 300 disposed between the first electrode 210 and the second electrode 220. The second insulating layer IL2 may be disposed on the first insulating layer IL1 between the first electrode 210 and the second electrode 220, and the light emitting element 300 may be disposed between the first insulating layer IL1 and the second insulating layer IL2. In the embodiment, the insulating film 380 (see FIG. 1 ) formed on the outer surface of the light emitting element 300 Fig.11 ) may be in direct contact with the first insulating layer IL1 and the second insulating layer IL2. For example, the second insulating layer IL2 may be provided to partially surround the outer surface of the light emitting element 300, so that during the manufacturing process, the light emitting element 300 may be protected and the light emitting element 300 may be fixed at the same time.

[0183] A portion of the second insulating layer IL2 disposed on the light emitting element 300 may have a shape in a plan view extending in the second direction DR2 between the first electrode 210 and the second electrode 220. As an example, the second insulating layer IL2 may form a stripe pattern or an island pattern in each subpixel PXn.

[0184] The second insulating layer IL2 may be disposed on the light emitting element 300 and may expose one end and the other end of the light emitting element 300. The exposed ends of the light emitting element 300 may be in contact with the contact electrodes 261 and 262, respectively, which will be described below. Such a shape of the second insulating layer IL2 may be formed by using a patterning process of a material forming the second insulating layer IL2 using a typical mask process. The mask for forming the second insulating layer IL2 has a width smaller than the length of the light emitting element 300, and the material forming the second insulating layer IL2 may be patterned to expose both ends of the light emitting element 300. However, the invention is not limited thereto.

[0185] In addition, in the embodiment, a portion of the material of the second insulating layer IL2 may be disposed between the first insulating layer IL1 and the lower surface of the light emitting element 300. The second insulating layer IL2 may be formed to fill the space between the first insulating layer IL1 and the light emitting element 300 formed during the manufacturing process. Therefore, the second insulating layer IL2 may be formed to surround the outer surface of the light emitting element 300. However, the invention is not limited thereto.

[0186] A plurality of contact electrodes 261 and 262 and a third insulating layer IL3 may be disposed on the second insulating layer IL2 .

[0187] The plurality of contact electrodes 261 and 262 may each have a shape extending in one direction. The plurality of contact electrodes 261 and 262 may respectively contact the electrodes 210 and 220 and the light emitting element 300 , and the light emitting element 300 may receive electrical signals from the first electrode 210 and the second electrode 220 through the contact electrodes 261 and 262 .

[0188] The contact electrodes 261 and 262 may include a first contact electrode 261 and a second contact electrode 262. The first contact electrode 261 and the second contact electrode 262 may be disposed on the first electrode 210 and the second electrode 220, respectively. For example, the first contact electrode 261 may be disposed on the first electrode branch portion 210B, the second contact electrode 262 may be disposed on the second electrode branch portion 220B, and the first contact electrode 261 and the second contact electrode 262 may each have a shape extending in the second direction DR2. The first contact electrode 261 and the second contact electrode 262 may be spaced apart from each other in the first direction DR1 and face each other, and may form a stripe pattern in the emission area EMA of each subpixel PXn.

[0189] In some embodiments, the width of each of the first contact electrode 261 and the second contact electrode 262 measured in one direction may be greater than or equal to the width of each of the first electrode branch portion 210B and the second electrode branch portion 220B measured in the one direction. The first contact electrode 261 and the second contact electrode 262 may be disposed to contact one end and the other end of the light emitting element 300, respectively, and simultaneously cover both side surfaces of the first electrode branch portion 210B and the second electrode branch portion 220B, respectively. As described above, the upper surface of each of the first electrode 210 and the second electrode 220 may be partially exposed, and the first contact electrode 261 and the second contact electrode 262 may contact the exposed upper surfaces of the first electrode 210 and the second electrode 220, respectively. The first contact electrode 261 may contact a portion of the first electrode 210 located on the first inner bank 410, and the second contact electrode 262 may contact a portion of the second electrode 220 located on the second inner bank 420. However, the present invention is not limited thereto, and in some cases, the widths of the first contact electrode 261 and the second contact electrode 262 may be formed to be smaller than the widths of the first electrode 210 and the second electrode 220, respectively, and the first contact electrode 261 and the second contact electrode 262 may be disposed to respectively cover only the exposed portions of the upper surfaces of the first electrode 210 and the second electrode 220. In addition, at least a partial region of each of the first contact electrode 261 and the second contact electrode 262 is disposed on the first insulating layer IL1.

[0190] According to one embodiment, the light emitting element 300 has a semiconductor layer exposed on both end surfaces thereof in the extension direction, and the first contact electrode 261 and the second contact electrode 262 may contact the light emitting element 300 on the end surfaces of the semiconductor layer (the semiconductor layer is exposed on the end surfaces). However, the invention is not limited thereto. Both end side surfaces of the light emitting element 300 may be partially exposed. In the process of forming the second insulating layer IL2 covering the outer surface of the light emitting element 300, the insulating film 380 (see FIG. 1 ) surrounding the outer surface of the semiconductor layer of the light emitting element 300 may be formed. Fig.11 ) may be partially removed, and the exposed side surface of the semiconductor layer of the light emitting element 300 may be in contact with the first contact electrode 261 and the second contact electrode 262. One end of the light emitting element 300 may be electrically connected to the first electrode 210 through the first contact electrode 261, and the other end thereof may be electrically connected to the second electrode 220 through the second contact electrode 262.

[0191] In the drawings, two first contact electrodes 261 and one second contact electrode 262 are provided in one subpixel PXn, but the invention is not limited thereto. The number of first contact electrodes 261 and second contact electrodes 262 may vary according to the number of first electrodes 210 and second electrodes 220 provided in each subpixel PXn.

[0192] The first contact electrode 261 may be disposed on the first electrode 210 and the second insulating layer IL2. The first contact electrode 261 may contact one end of the light emitting element 300 and the exposed upper surface of the first electrode 210. One end of the light emitting element 300 may be electrically connected to the first electrode 210 through the first contact electrode 261.

[0193] The third insulating layer IL3 is disposed on the first contact electrode 261. The third insulating layer IL3 can electrically insulate the first contact electrode 261 and the second contact electrode 262 from each other. The third insulating layer IL3 may be disposed to cover the first contact electrode 261, and may not be disposed on the other end of the light emitting element 300 so that the light emitting element 300 can contact the second contact electrode 262. The third insulating layer IL3 may partially contact the first contact electrode 261 and the second insulating layer IL2 at the upper surface of the second insulating layer IL2. The side surface of the third insulating layer IL3 in the direction in which the second electrode 220 is disposed may be aligned with one side surface of the second insulating layer IL2. In addition, the third insulating layer IL3 may also be disposed on the first insulating layer IL1 disposed on the first planarization layer 109. However, the invention is not limited thereto.

[0194] The second contact electrode 262 is disposed on the second electrode 220, the second insulating layer IL2, and the third insulating layer IL3. The second contact electrode 262 may contact the other end of the light emitting element 300 and the exposed upper surface of the second electrode 220. The other end of the light emitting element 300 may be electrically connected to the second electrode 220 through the second contact electrode 262.

[0195] In other words, the first contact electrode 261 may be disposed between the first electrode 210 and the third insulating layer IL3, and the second contact electrode 262 may be disposed on the third insulating layer IL3. The second contact electrode 262 may partially contact the second insulating layer IL2, the third insulating layer IL3, the second electrode 220, and the light emitting element 300. An end portion of the second contact electrode 262 in the direction in which the first electrode 210 is disposed may be disposed on the third insulating layer IL3. The first contact electrode 261 and the second contact electrode 262 may not contact each other due to the second insulating layer IL2 and the third insulating layer IL3. However, the invention is not limited thereto, and in some cases, the third insulating layer IL3 may be omitted.

[0196] The contact electrodes 261 and 262 may include a conductive material. For example, the contact electrodes 261 and 262 may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the contact electrodes 261 and 262 may include a transparent conductive material, and the light emitted from the light emitting element 300 may pass through the contact electrodes 261 and 262 and travel toward the electrodes 210 and 220. Each of the electrodes 210 and 220 may include a material having a high reflectivity, and the electrodes 210 and 220 disposed on the inclined side surfaces of the inner dams 410 and 420 may reflect the incident light in an upward direction relative to the first substrate 101. However, the invention is not limited thereto.

[0197] The first insulating layer IL1, the second insulating layer IL2 and the third insulating layer IL3 may include an inorganic insulating material or an organic insulating material. In an embodiment, the first insulating layer IL1, the second insulating layer IL2 and the third insulating layer IL3 may include a silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), etc. Optionally, the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 may each include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, PI resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, or polymethyl methacrylate-polycarbonate synthetic resin. However, the present invention is not limited thereto.

[0198] The thin film encapsulation structure TFE may be disposed on the third insulating layer IL3 and the second contact electrode 262. The thin film encapsulation structure TFE may include at least one thin film encapsulation layer. For example, the thin film encapsulation structure TFE may include a first inorganic film TFE1, an organic film TFE2, and a second inorganic film TFE3. Each of the first inorganic film TFE1 and the second inorganic film TFE3 may include silicon nitride, silicon oxide, silicon oxynitride, etc. The organic film TFE2 may include an organic insulating material such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, benzocyclobutene (BCB), etc.

[0199] Meanwhile, the light emitting element 300 may be a light emitting diode, specifically, an inorganic light emitting diode having a size of micrometer or nanometer and made of an inorganic material. When an electric field is formed in a specific direction between two electrodes facing each other, the inorganic light emitting diode may be aligned between the two electrodes in which polarity is formed. The light emitting element 300 may be aligned between the two electrodes due to the electric field formed between the two electrodes.

[0200] The light emitting element 300 according to an embodiment may have a shape extending in one direction. The light emitting element 300 may have a shape such as a rod, a wire or a tube. In an embodiment, the light emitting element 300 may have a cylindrical shape or a rod shape. However, the shape of the light emitting element 300 is not limited thereto, and the light emitting element 300 may have various shapes, including shapes such as a cube, a cuboid, a polygonal column such as a hexagonal column, or a shape extending in one direction and having a partially inclined outer surface. A plurality of semiconductors included in the light emitting element 300 may have a structure in which the semiconductors are sequentially arranged or stacked in one direction.

[0201] The light emitting element 300 may include a semiconductor layer doped with impurities of any conductive type (eg, p-type or n-type). The semiconductor layer may receive an electrical signal applied from an external power source and emit light within a specific wavelength range.

[0202] Fig.11 is a schematic diagram of a light emitting element according to an embodiment.

[0203] Reference Fig.11 , the light emitting element 300 may include a semiconductor core and an insulating film 380 surrounding the outer surface of the semiconductor core. The semiconductor core may include at least a first semiconductor layer 310, a second semiconductor layer 320, and a light emitting layer 330. In some embodiments, the semiconductor core of the light emitting element 300 may further include an electrode layer 370. Hereinafter, the embodiment will be described by taking the case where the light emitting element 300 includes the first semiconductor layer 310, the second semiconductor layer 320, the light emitting layer 330, the electrode layer 370, and the insulating film 380 as an example.

[0204] The first semiconductor layer 310 may be an n-type semiconductor. As an example, when the light emitting element 300 emits light in a blue wavelength range, the first semiconductor layer 310 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-yN (0≤x≤1, 0≤y≤1, and 0≤x+y≤1) semiconductor material. For example, the semiconductor material may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type impurities. The first semiconductor layer 310 may be doped with an n-type dopant, and as an example, the n-type dopant may be Si, Ge, Se, Sn, etc. In an embodiment, the first semiconductor layer 310 may be n-GaN doped with n-type Si. The length of the first semiconductor layer 310 may be in the range of 1.5μm to 5μm, but the invention is not limited thereto.

[0205] The second semiconductor layer 320 is disposed on the light emitting layer 330 to be described below. The second semiconductor layer 320 may be a p-type semiconductor. As an example, when the light emitting element 300 emits light in a blue wavelength range or a green wavelength range, the second semiconductor layer 320 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, and 0≤x+y≤1) semiconductor material. For example, the semiconductor material may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type impurities. The second semiconductor layer 320 may be doped with a p-type dopant, and as an example, the p-type dopant may be Mg, Zn, Ca, Ba, etc. In an embodiment, the second semiconductor layer 320 may be p-GaN doped with p-type Mg. The length of the second semiconductor layer 320 may be in the range of 0.05 μm to 0.10 μm, but the invention is not limited thereto.

[0206] Meanwhile, in the drawings, each of the first semiconductor layer 310 and the second semiconductor layer 320 is shown as being formed as one layer, but the invention is not limited thereto. According to some embodiments, each of the first semiconductor layer 310 and the second semiconductor layer 320 may further include a greater number of layers (e.g., a cap layer or a tensile strain barrier reduction (TSBR) layer) according to the material of the light emitting layer 330. A description thereof will be provided below with reference to other drawings.

[0207] The light emitting layer 330 is disposed between the first semiconductor layer 310 and the second semiconductor layer 320. The light emitting layer 330 may include a material having a single quantum well structure or a multi-quantum well structure. When the light emitting layer 330 includes a material having a multi-quantum well structure, the light emitting layer 330 may have a structure in which quantum layers and well layers are alternately stacked. The light emitting layer 330 may emit light due to the combination of electron-hole pairs in response to an electrical signal applied through the first semiconductor layer 310 and the second semiconductor layer 320. As an example, when the light emitting layer 330 emits light in a blue wavelength range, the light emitting layer 330 may include materials such as AlGaN, AlGaInN, etc. In particular, when the light emitting layer 330 has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layers may include materials such as AlGaN or AlGaInN, and the well layers may include materials such as GaN or AlInN. In an embodiment, the light emitting layer 330 includes AlGaInN as a quantum layer and AlInN as a well layer. As described above, the light emitting layer 330 may emit blue light having a central wavelength ranging from 450 nm to 495 nm.

[0208] However, the invention is not limited thereto, and the light emitting layer 330 may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, or include other III-V semiconductor materials according to the wavelength range of the emitted light. The light emitted by the light emitting layer 330 is not limited to light in the blue wavelength range, and in some cases, the light emitting layer 330 may also emit light in the red wavelength range or in the green wavelength range. The length of the light emitting layer 330 may be in the range of 0.05 μm to 0.10 μm, but the invention is not limited thereto.

[0209] Meanwhile, light emitted from the light emitting layer 330 may be emitted not only to the outer surface of the light emitting element 300 in the length direction but also to both side surfaces of the light emitting element 300. Directivity of light emitted from the light emitting layer 330 is not limited to one direction.

[0210] The electrode layer 370 may be an ohmic contact electrode. However, the present invention is not limited thereto, and the electrode layer 370 may also be a Schottky contact electrode. The light emitting element 300 may include at least one electrode layer 370. Fig.11 370, but the invention is not limited thereto. In some cases, the light emitting element 300 may include a greater number of electrode layers 370, or the electrode layer 370 may be omitted. Even when the number of electrode layers 370 is changed or another structure is further included, the description of the light emitting element 300 may be similarly applied.

[0211] When the light emitting element 300 is electrically connected to the electrodes 210 and 220 or the contact electrodes 261 and 262, the electrode layer 370 can reduce the resistance between the light emitting element 300 and the electrodes or the contact electrodes. The electrode layer 370 may include a conductive metal. For example, the electrode layer 370 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In addition, the electrode layer 370 may include a semiconductor material doped with n-type impurities or p-type impurities. The electrode layer 370 may include the same material or different materials, but the invention is not limited thereto.

[0212] The insulating film 380 is provided to surround the outer surface of the semiconductor core (e.g., multiple semiconductor layers) and the electrode layer as described above. In an embodiment, the insulating film 380 may be provided to surround at least the outer surface of the light emitting layer 330, and may extend in one direction in which the light emitting element 300 extends. The insulating film 380 may be used to protect the member. As an example, the insulating film 380 may be formed to surround the side surface portion of the member and expose both ends of the light emitting element 300 in the length direction.

[0213] In the drawings, the insulating film 380 is shown to be formed to extend in the length direction of the light emitting element 300 to cover the side surface of the electrode layer 370 from the first semiconductor layer 310, but the invention is not limited thereto. Since the insulating film 380 covers only the outer surfaces of the light emitting layer 330 and some semiconductor layers, or only covers a part of the outer surface of the electrode layer 370, the outer surface of the electrode layer 370 may be partially exposed. In addition, the upper surface of the insulating film 380 may be formed so that the cross section in the region adjacent to at least one end of the light emitting element 300 is circular.

[0214] The thickness of the insulating film 380 may be in the range of 10 nm to 1.0 μm, but the invention is not limited thereto. Preferably, the thickness of the insulating film 380 is about 40 nm.

[0215] The insulating film 380 may include a material having an insulating property, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ) etc. Therefore, it is possible to prevent an electrical short circuit that may occur when the light emitting layer 330 is in direct contact with an electrode through which an electrical signal is transmitted to the light emitting element 300. In addition, since the insulating film 380 protects the outer surface of the light emitting element 300 including the light emitting layer 330, it is possible to prevent the light emitting efficiency from being deteriorated.

[0216] In addition, in some embodiments, the outer surface of the insulating film 380 may be surface treated. The light emitting element 300 may be aligned by spraying onto the electrode in a state dispersed in the ink. Here, in order to maintain a state in which the light emitting element 300 is dispersed in the ink without agglomerating with another adjacent light emitting element 300, the surface of the insulating film 380 may be hydrophobically treated or hydrophilically treated.

[0217] The length h of the light emitting element 300 may be in the range of 1 μm to 10 μm or 2 μm to 6 μm, preferably in the range of 3 μm to 5 μm. In addition, the diameter of the light emitting element 300 may be in the range of 300 nm to 700 nm, and the aspect ratio of the light emitting element 300 may be in the range of 1.2 to 100. However, the invention is not limited thereto, and the plurality of light emitting elements 300 may have different diameters according to the composition difference of the light emitting layer 330. Preferably, the diameter of the light emitting element 300 may be about 500 nm.

[0218] The light emitting element 300 included in the first display substrate 10 may be electrically connected to the first electrode 210 and the second electrode 220 to emit light within a specific wavelength range. The light emitted from the first display substrate 10 may travel in an upward direction relative to the first substrate 101 to be incident on the second display substrate 50. Hereinafter, the second display substrate 50 will be further described with reference to other drawings.

[0219] Fig.12 is a schematic cross-sectional view of a display device according to an embodiment.

[0220] Reference Fig.12 , the second display substrate 50 may be disposed above the thin film encapsulation structure TFE so as to be opposite thereto. When the cross-sectional structure of the second display substrate 50 is described in a downward order in the accompanying drawings, the second substrate 501 of the second display substrate 50 may include a transparent material. The second substrate 501 may include a transparent insulating material such as glass or quartz. The second substrate 501 may be a rigid substrate. However, the second substrate 501 is not limited to the materials shown above, and the second substrate 501 may also include a plastic such as polyimide and may have a flexible property that can be twisted, bent, folded or rolled.

[0221] The second substrate 501 may include the same substrate as the first substrate 101, but the material, thickness, transmittance, etc. of the second substrate 501 may be different from those of the first substrate 101. For example, the second substrate 501 may have a transmittance higher than that of the first substrate 101. The second substrate 501 may be thicker or thinner than the first substrate 101.

[0222] The upper light absorbing member UAB may be disposed on one surface of the second substrate 501 facing the first substrate 101 along the boundary between the sub-pixels PXn. The upper light absorbing member UAB may overlap the outer bank 450 of the first display substrate 10 and may be located in the light blocking area BA. The upper light absorbing member UAB may include a light emitting area EMA (see FIG. 1 ) that exposes the second substrate 501 and the first display substrate 10. Figure 8 ) is overlapped with one surface. The upper light absorbing member UAB may be used not only to block light emitted from the display device but also to suppress external light from being reflected. The upper light absorbing member UAB may be formed in a grid shape in a plan view.

[0223] The upper light absorbing member UAB may be made of an organic material. In one embodiment, the upper light absorbing member UAB may include a light absorbing material that absorbs visible light wavelength range. For example, the upper light absorbing member UAB may be made of a material used as a black matrix of a display device. The upper light absorbing member UAB may be a light blocking member.

[0224] The upper light absorption member UAB may define a light blocking area BA and a light output area TA. The area in which the upper light absorption member UAB is disposed may be the light blocking area BA, and the area of ​​the second substrate 501 that is not covered by the upper light absorption member UAB or exposed by the upper light absorption member UAB may be the light output area TA. In some embodiments, in the second display substrate 50, the light output area TA may be formed to correspond to each pixel PX or sub-pixel PXn of the first display substrate 10. As an example, the second display substrate 50 may include a first light output area TA1 disposed to correspond to the first sub-pixel PX1 of the first display substrate 10, a second light output area TA2 disposed to correspond to the second sub-pixel PX2, and a third light output area TA3 disposed to correspond to the third sub-pixel PX3. Each of the light output areas TA1, TA2, and TA3 may be repeatedly disposed in a matrix form, wherein the light blocking area BA in which the upper light absorption member UAB is disposed may be disposed between the light output areas TA1, TA2, and TA3.

[0225] In another embodiment, the upper light absorbing member UAB may absorb light within a specific wavelength range of the visible light wavelength range, and may transmit light within other specific wavelength ranges. For example, the upper light absorbing member UAB may include the same material as that of one color filter layer CFL. Specifically, the upper light absorbing member UAB may be made of the same material as that of the third color filter layer (see "CFL_3") for blue. In some embodiments, the upper light absorbing member UAB may be formed integrally with the third color filter layer CFL_3. The upper light absorbing member UAB may be omitted.

[0226] The color filter layer CFL may be disposed on one surface of the second substrate 501 on which the upper light absorbing member UAB is disposed. The color filter layer CFL may be used to block light of a color that does not correspond to each sub-pixel PXn from being emitted. The color filter layer CFL may be disposed on one surface of the second substrate 501 exposed by the opening of the upper light absorbing member UAB. In addition, the color filter layer CFL may also be partially disposed on the adjacent upper light absorbing member UAB.

[0227] The color filter layer CFL may include a first color filter layer CFL_1 disposed in the first sub-pixel PX1, a second color filter layer CFL_2 disposed in the second sub-pixel PX2, and a third color filter layer CFL_3 disposed in the third sub-pixel PX3. Each color filter layer CFL may include a colorant such as a dye or pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter layer CFL_1 may be a red color filter layer, the second color filter layer CFL_2 may be a green color filter layer, and the third color filter layer CFL_3 may be a blue color filter layer. Adjacent color filter layers CFL are shown in the drawings as being spaced apart from each other on the upper light absorbing member UAB. However, adjacent color filter layers CFL may also partially overlap each other on the upper light absorbing member UAB.

[0228] The first cover layer CPL1 may be disposed on the color filter layer CFL. The first cover layer CPL1 may prevent impurities such as external moisture or air from penetrating into the color filter layer CFL to damage or contaminate the color filter layer CFL. In addition, the first cover layer CPL1 may prevent the colorant of the color filter layer CFL from diffusing into other components.

[0229] The first cover layer CPL1 may be adjacent to one surface ( Fig.12 The first cap layer CPL1 may be made of an inorganic material. For example, the first cap layer CPL1 may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, silicon oxynitride, etc.

[0230] Meanwhile, a lower light absorbing member BAB may be disposed on the thin film encapsulation structure TFE of the first display substrate 10. The lower light absorbing member BAB may be disposed to overlap with the outer bank 450. The lower light absorbing member BAB may be used to block light emitted from the light emitting element 300 from mixing into the light output area TA of the adjacent sub-pixel PXn. According to one embodiment, the display device 1 may further include a lower light absorbing member BAB, so that color mixing of each sub-pixel PXn may be further blocked.

[0231] The lower light absorbing member BAB may be made of an organic material. In one embodiment, the lower light absorbing member BAB may include a light absorbing material that absorbs a visible light wavelength range. For example, the lower light absorbing member BAB may be made of a material used as a black matrix of a display device. The lower light absorbing member BAB may be a light blocking member. The lower light absorbing member BAB may overlap with the upper light absorbing member UAB in the thickness direction. The width of the lower light absorbing member BAB may be less than or equal to the width of the outer embankment 450, or may be greater than the width of the outer embankment 450.

[0232] The filler 90 may be disposed between the first display substrate 10 and the second display substrate 50. The filler 90 may fill the space between the first display substrate 10 and the second display substrate 50, and may be used to combine the first display substrate 10 and the second display substrate 50 with each other. The filler 90 may be disposed between the thin film encapsulation structure TFE of the first display substrate 10 and the first cover layer CPL1 of the second display substrate 50. The filler 90 may be made of a silicon (Si)-based organic material, an epoxy-based organic material, etc., but the invention is not limited thereto.

[0233] Hereinafter, various embodiments of the display device 1 will be described with reference to other drawings.

[0234] Fig.13 is a partial cross-sectional view of a first display substrate according to another embodiment.

[0235] Reference Fig.13 , the first display substrate 10_1 of the display device 1 may further include a reflective layer LRL formed on one surface of the outer bank 450 . Fig.13 Examples and Fig.10 The embodiment of FIG. 1 is different in that a reflective layer LRL is further included.

[0236] The light emitting element 300 is disposed between the inner banks 410 and 420, and light emitted from the light emitting element 300 may be reflected by the electrodes 210 and 220 respectively disposed on the inclined side surfaces of the inner banks 410 and 420. However, the invention is not limited thereto, and at least some of the light emitted from the light emitting element 300 may not be reflected by the electrodes 210 and 220, but may be emitted in an upward direction relative to the first substrate 101. In addition, some of the light may travel toward the outer bank 450 located at the boundary of the adjacent sub-pixel PXn.

[0237] According to one embodiment, a reflective layer LRL may also be provided on at least one surface of the outer bank 450, and at least a portion of the light emitted from the light emitting element 300 may be reflected toward the second display substrate 50 due to the reflective layer LRL. The reflective layer LRL may include a material having a high reflectivity. In the drawings, the reflective layer LRL is shown as being formed only on a portion of one surface of the outer bank 450 facing the region in which the light emitting element 300 is provided, but the invention is not limited thereto. The area, width, etc. of the region in which the reflective layer LRL is formed on one surface of the outer bank 450 may be modified differently according to the arrangement and number of the light emitting element 300. Other descriptions may be the same as the above description.

[0238] Fig.14 is a schematic cross-sectional view showing one sub-pixel of a display device according to still another embodiment. Fig.15 It is along Fig.14 A cross-sectional view taken along the line Q2-Q2' and the line Q3-Q3'. Fig.14 , for convenience of description, description will be made by omitting the semiconductor layer and the contact electrodes 261 and 262.

[0239] Reference Fig.14 and Fig.15 , in the first display substrate 10_2 of the display device 1 according to one embodiment, the second voltage wiring VSL_2 may further include a portion extending in the first direction DR1, and the second electrode trunk portion 220S may be omitted from the second electrode 220_2. Fig.14 and Fig.15 The embodiment is different from the other embodiments in that since the second voltage wiring VSL_2 further includes a portion extending in the first direction DR1, the second electrode 220_2 of each subpixel PXn may be electrically connected to the second voltage wiring VSL_2.

[0240] Although not shown in the drawings, Figure 7 In addition to the portion extending in the second direction DR2 in the embodiment of the present invention, the second voltage wiring VSL_2 may further include a portion extending in the first direction DR1. Similar to the outer bank 450, the second voltage wiring VSL_2 may form a grid pattern or a mesh pattern on the first substrate 101. The second voltage wiring VSL_2 may be disposed in each sub-pixel PXn, and the second electrode 220_2 of each sub-pixel PXn may be electrically connected to the second voltage wiring VSL_2.

[0241] For example, the second electrode stem portion 220S may be omitted from the second electrode 220_2. The second electrode 220_2 has a shape extending in the second direction DR2 and may be disposed between the first electrode branch portions 210B. The second conductive pattern VCP_2 may be disposed in each subpixel PXn and may contact each of the second electrode 220_2 and the second voltage wiring VSL_2.

[0242] The second conductive pattern VCP_2 may contact the second voltage wiring VSL_2 through the first wiring contact hole CTS1_2 exposing a portion of the upper surface of the second voltage wiring VSL_2 through the first interlayer insulating layer 105. The second electrode 220_2 may contact the second conductive pattern VCP_2 through the second wiring contact hole CTS2_2 exposing a portion of the upper surface of the second conductive pattern VCP_2 through the first planarization layer 109 and the first protective layer 107. According to one embodiment, since the second electrode 220_2 may be electrically connected to the second voltage wiring VSL_2 through the second conductive pattern VCP_2 provided in each sub-pixel PXn, and the second voltage wiring VSL_2 is provided in each sub-pixel PXn, there is an effect of preventing a voltage drop of the second power voltage VSS.

[0243] Fig.16 is a schematic plan view of a display element layer included in one sub-pixel of a display device according to still another embodiment. Fig.17 It is along Fig.16 A cross-sectional view taken along line Q4-Q4'. Fig.16 , for ease of description, the circuit element layer is omitted, and only a plan view of the display element layer is shown.

[0244] Reference Fig.16 and Fig.17 According to an embodiment, the first display substrate 10_3 of the display device 1 may further include a shielding electrode LSP_3 disposed in a partial region on the first electrode 210_3 and the second electrode 220_3 . Fig.16 and Fig.17 Examples and Figure 8 The difference of the embodiment is that the first display substrate 10_3 further includes a shielding electrode LSP_3.

[0245] The light emitting element 300 may be disposed between the first electrode 210_3 and the second electrode 220_3, or between the first inner bank 410 and the second inner bank 420. For example, the light emitting element 300 may be disposed between the first electrode branch portion 210B_3 and the second electrode branch portion 220B_3 and electrically connected to the first electrode branch portion 210B_3 and the second electrode branch portion 220B_3. In the process of disposing the light emitting element 300 between the first electrode 210_3 and the second electrode 220_3 or between the first inner bank 410 and the second inner bank 420, an alignment signal may be applied to the first electrode 210_3 and the second electrode 220_3, so that an electric field may be generated between the first electrode 210_3 and the second electrode 220_3. The light emitting element 300 placed in the electric field may be disposed between the first electrode 210_3 and the second electrode 220_3 while changing the alignment direction and position. However, it may be preferred that the light emitting element 300 is not disposed in a portion in which at least one end of the light emitting element 300 is not electrically connected to each of the electrodes 210_3 and 220_3, for example, not disposed between the first electrode branch portion 210B_3 and the external embankment 450, or not disposed in each of the electrode trunk portions 210S_3 and 220S_3.

[0246] According to one embodiment, the display device 1 may further include a shielding electrode LSP_3 disposed to cover at least a portion of each of the first electrode 210_3 and the second electrode 220_3 of the first display substrate 10_3. When the alignment signal is applied to the first electrode 210_3 and the second electrode 220_3, the shielding electrode LSP_3 may prevent an electric field from being generated in a partial area. The shielding electrode LSP_3 may include a shielding material that prevents the generation of an electric field. For example, the shielding electrode LSP_3 may include a carbon pigment, Cr / CrO x CrO x 、MoO x Etc. However, the invention is not limited thereto.

[0247] The shielding electrode LSP_3 may be disposed to cover one side of the first electrode branch portion 210B_3. For example, the shielding electrode LSP_3 may be disposed to cover a portion of the first electrode branch portion 210B_3 facing the outer bank 450 (i.e., the other side of the first electrode branch portion 210B_3 that is opposite to the side of the first electrode branch portion 210B_3 that faces the second electrode branch portion 220B_3). The shielding electrode LSP_3 may overlap with the other side of the first inner bank 410 in the thickness direction, the other side facing the side of the first inner bank 410 that is spaced apart from the second inner bank 420 and faces the second inner bank 420. The first insulating layer IL1_3 may be disposed between the shielding electrode LSP_3 and the first electrode 210_3, and the shielding electrode LSP_3 and the first electrode 210_3 may be insulated from each other. The shielding electrode LSP_3 may have a shape extending in the second direction DR2 along the first electrode branch portion 210B_3, and may prevent an electric field from being generated between the first electrode branch portion 210B_3 and the outer bank 450.

[0248] In addition, the shielding electrode LSP_3 may also be disposed at a portion where the electrode branch portions 210B_3 and 220_B are connected to the electrode trunk portions 210S_3 and 220S_3, respectively. The shielding electrode LSP_3 may also include a portion extending in the first direction DR1, and may also be disposed at a portion where the first electrode branch portion 210B_3 and the first electrode trunk portion 210S_3 are connected and a portion where the second electrode branch portion 220B_3 and the second electrode trunk portion 220S_3 are connected. That is, the shielding electrode LSP_3 may be disposed to surround an area (i.e., a space between the first inner bank 410 and the second inner bank 420) in which the light emitting element 300 is substantially disposed. The shielding electrode LSP_3 may be disposed to cover a portion of each of the first electrode branch portion 210B_3 and the first inner bank 410 relative to the outside of the area in which the light emitting element 300 is disposed.

[0249] In the process of disposing the light emitting element 300 , the shielding electrode LSP_3 may block an electric field generated outside the region between the first inner bank 410 and the second inner bank 420 , and the light emitting element 300 may be centrally disposed in the region between the inner banks 410 and 420 .

[0250] Figures 18 to 20 is a schematic plan view of a display element layer included in one sub-pixel of a display device according to still another embodiment. Figures 18 to 20 In the figure, for convenience of description, only the first voltage wiring VDL and the data line DTL are shown in addition to the display element layer.

[0251] Reference Figures 18 to 20In the first display substrate 10_4 of the display device 1 according to an embodiment, a greater number of internal banks and electrodes may be further included in each sub-pixel PXn. The electrode further provided for each sub-pixel PXn may be a repair electrode 230_4 prepared for a defect in the first electrode 210_4 or the second electrode 220_4. Figures 18 to 20 Examples and Figure 7 The difference of the embodiment is that each sub-pixel PXn further includes a repair electrode 230_4.

[0252] Each subpixel PXn may further include a third inner bank 430_4 disposed between the first inner bank 410 and the outer bank 450. The third inner bank 430_4 may have the same shape as the second inner bank 420 except for the position at which the third inner bank 430_4 is disposed. That is, the third inner bank 430_4 may have a shape extending in the second direction DR2 and may be spaced apart from and face the first inner bank 410.

[0253] The repair electrode 230_4 may be disposed on the third inner bank 430_4. The repair electrode 230_4 may have a shape substantially the same as that of each of the electrode branch portions 210B_4 and 220B_4. The repair electrode 230_4 may have a shape extending in the second direction DR2 and may be disposed on the third inner bank 430_4. The repair electrode 230_4 may be spaced apart from and face the first electrode branch portion 210B_4, and the light emitting element 300 may be disposed between the repair electrode 230_4 and the first electrode branch portion 210B_4.

[0254] In addition, a third contact electrode 263_4 may be further disposed on the repair electrode 230_4. The third contact electrode 263_4 may have substantially the same shape as that of the first contact electrode 261_4. A detailed description of its arrangement and shape will be omitted.

[0255] As the third inner bank 430_4 and the repair electrode 230_4 are further provided, the first electrode 210_4 may have a shape in which the first electrode trunk portion 210S_4 is further extended. The first electrode trunk portion 210S_4 may protrude in the first direction DR1 from a portion connected to any one of the first electrode branch portions 210B_4 and face the repair electrode 230_4.

[0256] With the further provision of the third inner bank 430_4 and the repair electrode 230_4, each sub-pixel PXn may have a larger area. That is, the area surrounded by the outer bank 450 may have a larger width in the first direction DR1. However, the circuit element layer may be formed in the same manner as Figure 7 In the same manner as in the embodiment of the present invention, the third inner bank 430_4 and the repair electrode 230_4 may be arranged between the data line DTL and the outer bank 450 in a plan view. The data line DTL may extend in the second direction DR2 between the second inner bank 420 and the third inner bank 430_4 or between the first inner bank 410 and the third inner bank 430_4 without overlapping the inner bank. The data line DTL may overlap the light emitting element 300 electrically connected to the repair electrode 230_4 in the thickness direction. However, the invention is not limited thereto.

[0257] Meanwhile, the light emitting element 300 may include a first light emitting element 300A disposed between the first inner bank 410 and the second inner bank 420 and electrically connected to the first electrode 210_4 and the second electrode 220_4, and a second light emitting element 300B disposed between the first inner bank 410 and the third inner bank 430_4 and having at least one end electrically connected to the repair electrode 230_4. The first light emitting element 300A may be the same as the above-mentioned light emitting element 300. However, since one end of the second light emitting element 300B is electrically connected to the repair electrode 230_4, it may be determined whether light is emitted according to the connection of the repair electrode 230_4.

[0258] For example, Fig.18 As shown in FIG. 1 , the first display substrate 10_4 of the display device 1 may include a first type sub-pixel PXA in which the repair electrode 230_4 is not electrically connected to the first electrode 210_4 or the second electrode 220_4. The repair electrode 230_4 may be disposed to be spaced apart from the first electrode trunk portion 210S_4 and the second electrode trunk portion 220S_4, and may be disconnected ( Fig.18 The repair electrode 230_4 may be disposed to be spaced apart from the first electrode trunk portion 210S_4 or the second electrode trunk portion 220S_4 by being formed in a state of being electrically connected to the first electrode trunk portion 210S_4 or the second electrode trunk portion 220S_4 and then being disconnected from the electrode trunk portion during a manufacturing process.

[0259] When the first electrode 210_4 and the second electrode 220_4 are smoothly connected and thus no defect occurs, the repair electrode 230_4 can be disconnected from each of the electrode trunk portions 210S_4 and 220S_4 and can remain as a floating electrode that is not electrically connected to each of the electrode trunk portions 210S_4 and 220S_4. The second light-emitting element 300B electrically connected to the repair electrode 230_4 can be set in the sub-pixel PXn in a state in which the electrical signal is not transmitted to the second light-emitting element 300B and thus no light is emitted. However, the invention is not limited thereto. In some embodiments, when all electrodes 210_4 and 220_4 are smoothly connected to the contact electrode, the repair electrode 230_4 can also be set in a state electrically connected to the first electrode 210_4 or the second electrode 220_4.

[0260] On the other hand, when the first electrode 210_4 or the second electrode 220_4 is partially disconnected or has a defective electrical connection, the repair electrode 230_4 may be connected to replace the electrode.

[0261] like Fig.19 and Fig. 20 As shown in the figure, the first display substrate 10_4 may include a second type sub-pixel PXB and a third type sub-pixel PXC. In the second type sub-pixel PXB, any one of the first electrode branch portions 210B_4 is disconnected and the repair electrode 230_4 is electrically connected to the first electrode 210_4, and in the third type sub-pixel PXC, the second electrode branch portion 220B_4 is disconnected and the repair electrode 230_4 is electrically connected to the second electrode 220_4.

[0262] In the second type sub-pixel PXB, the first electrode branch portion 210B_4 between the second electrode branch portion 220B_4 and the repair electrode 230_4 may be disconnected from the first electrode trunk portion 210S_4 ( Fig.19 The repair electrode 230_4 may be electrically connected to the first electrode trunk portion 210S_4, and an electrical signal may also be transmitted to the second light emitting element 300B through the repair electrode 230_4 and the third contact electrode 263_4.

[0263] In the third type sub-pixel PXC, the second electrode branch portion 220B_4 may be disconnected from the second electrode trunk portion 220S_4 ( Fig. 20 In the third type sub-pixel PXC, the second electrode branch portion 220B_4 may remain as a floating electrode.

[0264] Meanwhile, in the first display substrate 10 of the display device 1, the display element layer and the circuit element layer in which the light emitting element 300 is disposed may be arranged not to overlap in the thickness direction. According to one embodiment, in the first display substrate 10, the light emitting region and the non-light emitting region may be defined as regions distinguished from each other on the first substrate 101. The light emitting element 300 may be disposed in the light emitting region, and the circuit element may be disposed in the non-light emitting region.

[0265] Fig.21 is a schematic plan view showing one sub-pixel of a display device according to still another embodiment. Fig. 22 It is along Fig.21 A cross-sectional view taken along line Q5-Q5' and line Q6-Q6'. Fig.21 The portion Q5 - Q5 ′ is a cross section of a partial area of ​​the non-emission area NEA of each sub-pixel PXn, and the portion Q6 - Q6 ′ is a cross section of a partial area of ​​the emission area EMA of each sub-pixel PXn.

[0266] Reference Fig.21 and Fig. 22 In each pixel PX or sub-pixel PXn of the first display substrate 10_5 of the display device 1 according to one embodiment, the display element layer and the circuit element layer may not overlap each other in the thickness direction. Each of the sub-pixels PXn may include a light-emitting area EMA in which the light-emitting element 300 is disposed and a non-light-emitting area NEA in which a circuit element such as a driving transistor DRT is disposed, and the light-emitting area EMA and the non-light-emitting area NEA may be respectively disposed in areas distinguished from each other on the first substrate 101. That is, the light-emitting element 300 may not be disposed on the circuit element of each sub-pixel PXn, and light may be emitted in an upward direction or a backward direction relative to the area in which the light-emitting element 300 is disposed. Hereinafter, repeated descriptions will be omitted, and descriptions will be provided based on differences from the above.

[0267] Each of the sub-pixels PXn of the first display substrate 10 may include an emission area EMA and a non-emission area NEA. The light emitting element 300 and the first and second electrodes 210 and 220 may be disposed in the emission area EMA, and the circuit elements including the driving transistor DRT may be disposed in the non-emission area NEA located on one side of the emission area EMA. Fig.21 , the light emitting area EMA and the non-light emitting area NEA are shown to be arranged in the second direction DR2, but the invention is not limited thereto. In the first display substrate 10_5 of the display device 1, the arrangement of the light emitting area EMA and the non-light emitting area NEA is not particularly limited as long as the light emitting element 300 and the circuit element disposed in each of the sub-pixels PXn do not overlap each other in the thickness direction.

[0268] For example, a semiconductor layer including an active layer of each of the transistors, a first gate conductive layer, and a first data conductive layer may be disposed in the non-emission area NEA. However, as wirings included in the first gate conductive layer and the first data conductive layer, the first voltage wiring VDL, the data line DTL, the reference voltage wiring RVL, and the second voltage wiring VSL may be disposed to extend in the second direction DR2, and thus may be disposed throughout the non-emission area NEA and the emission area EMA.

[0269] In the light emitting region EMA, in addition to the wiring extending in the second direction DR2, internal banks 410 and 420, electrodes 210 and 220, light emitting elements 300, and contact electrodes 261 and 262 may be provided. These may be provided so as not to overlap with the circuit element layer in the thickness direction. That is, the plurality of light emitting elements 300 may not overlap with the first capacitor electrode CSE1 and the second capacitor electrode CSE2. The arrangement of the internal banks 410 and 420, electrodes 210 and 220, light emitting elements 300, and contact electrodes 261 and 262 is the same as that described above with reference to FIG. Figure 8 The description is essentially the same.

[0270] At the same time, since the display element and the circuit element are respectively arranged in the light emitting area EMA and the non-light emitting area NEA, a larger number of layers can be arranged to electrically connect the display element and the circuit element. According to one embodiment, the first display substrate 10_5 may further include a second interlayer insulating layer 108 and a second data conductive layer arranged between the first planarization layer 109 and the first data conductive layer. The second interlayer insulating layer 108 may be arranged on the first data conductive layer and the first interlayer insulating layer 105, and the second data conductive layer may be arranged on the second interlayer insulating layer 108. The description of the second interlayer insulating layer 108 is substantially the same as that described above with respect to the first interlayer insulating layer 105.

[0271] The second data conductive layer may include a third conductive pattern VDP disposed at a boundary of the light emitting area EMA and the non-light emitting area NEA. The third conductive pattern VDP may contact the source / drain electrode DRT_SD of the driving transistor DRT through a contact hole VDC exposing a portion of the source / drain electrode DRT_SD of the driving transistor DRT through the second interlayer insulating layer 108. The contact hole VDC may be formed in the non-light emitting area NEA. The first electrode 210 may be formed in an area where the first electrode trunk portion 210S overlaps the third conductive pattern VDP, and may contact the third conductive pattern VDP through an electrode contact hole CTD_5 exposing a portion of the upper surface of the third conductive pattern VDP through the first planarizing layer 109. The first electrode 210 may be electrically connected to the driving transistor DRT through the third conductive pattern VDP.

[0272] Meanwhile, the outer bank 450 may be provided to surround the light emitting area EMA in which the light emitting element 300 is provided, and may completely cover the non-light emitting area NEA. According to one embodiment, the outer bank 450 may be provided to cover the non-light emitting area NEA, and may be provided to expose the light emitting area EMA in which the light emitting element 300 is provided. That is, the outer bank 450 may have a structure that is completely provided on the first substrate 101 and has an opening formed to expose a portion of the light emitting area EMA. In addition, the arrangement of each of the wiring, the conductive layer, the electrode, and the light emitting element is the same as described above, and therefore, a detailed description thereof will be omitted.

[0273] In the display device 1 according to one embodiment, the first display substrate 10_5 may include a light emitting area EMA and a non-light emitting area NEA as areas distinguished from each other. Since the light emitting element 300 is disposed in the light emitting area EMA and the pixel circuit element is disposed in the non-light emitting area NEA, the light emitting element 300 and the pixel circuit element may not overlap each other in the thickness direction. In the first display substrate 10_5, in addition to the upward direction relative to the first substrate 101, light emitted from the light emitting element 300 may also be emitted in a backward direction relative to the first substrate 101, and the first display substrate 10_5 may have a bottom emission structure.

[0274] Meanwhile, in the display device 1 , the second display substrate 50 may include more components. More color control structures may be disposed between the second substrate 501 of the second display substrate 50 and the thin film encapsulation structure TFE of the first display substrate 10 .

[0275] Fig.23 is a schematic cross-sectional view of a display device according to yet another embodiment.

[0276] Reference Fig.23 , in the display device 1_6 according to one embodiment, the second display substrate 50_6 may further include color control layers WCL and TPL and a color mixture preventing member MBM. Fig.23 The display device 1_6 and Fig.12 The embodiment of the present invention is different in that the second display substrate 50_6 further includes color control layers WCL and TPL and a color mixing prevention member. Hereinafter, repeated descriptions will be omitted and descriptions will be provided based on differences from the above contents.

[0277] The color control layer WCL and TPL may be disposed on the first cover layer CPL1 of the second display substrate 50_6. The color control layer may include a wavelength conversion layer WCL that converts the wavelength of the incident light and / or a light-transmitting layer TPL that allows the incident light to pass therethrough in a state in which the wavelength of the incident light is maintained. The wavelength conversion layer WCL or the light-transmitting layer TPL may be disposed separately for each sub-pixel PXn. The wavelength conversion layer WCL or the light-transmitting layer TPL may overlap with the light-emitting area EMA and the light output area TA in the thickness direction. Adjacent wavelength conversion layers WCL or light-transmitting layers TPL may be spaced apart from each other. The separation space between adjacent wavelength conversion layers WCL or light-transmitting layers TPL may substantially overlap with the light blocking area BA. The separation space forms a valley having a grid shape in a plan view.

[0278] The wavelength conversion layer WCL may be disposed in a sub-pixel PXn in which the wavelength of light emitted from the light emitting element 300 is different from the color of the corresponding sub-pixel PXn and thus the wavelength of the light needs to be converted. The light-transmitting layer TPL may be disposed in a sub-pixel PXn in which the wavelength of light emitted from the light emitting element 300 is the same as the color of the corresponding sub-pixel PXn. Fig.23 In the display device 1_6, the light emitting element 300 of each sub-pixel PXn emits light of a third color, so the wavelength conversion layer WCL may be provided in the first sub-pixel PX1 and the second sub-pixel PX2, and the light-transmitting layer TPL may be provided in the third sub-pixel PX3. However, the invention is not limited thereto, and when the light emitting element 300 of each sub-pixel PXn emits light having a wavelength different from that of each light output region TA (such as ultraviolet light), only the wavelength conversion layer WCL may be provided without the light-transmitting layer TPL. As another example, when the light emitting element 300 of each sub-pixel PXn emits light corresponding to the color of each light output region TA, only the light-transmitting layer TPL may be provided without the wavelength conversion layer WCL.

[0279] In the illustrated embodiment, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 disposed in the first subpixel PX1 and a second wavelength conversion pattern WCL2 disposed in the second subpixel PX2 .

[0280] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The light transmitting layer TPL may include a third base resin BRS3 and a scatterer SLP disposed in the third base resin BRS3.

[0281] The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may include a transparent organic material. For example, the first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may be made of epoxy resin, acrylic resin, cardo resin, imide resin, etc. All of the first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may be made of the same material, but the invention is not limited thereto.

[0282] The scatterer SLP may be metal oxide particles or organic particles. Examples of metal oxides may include titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 )、ZnO、SnO 2 ) etc. Examples of the material of the organic particles may include acrylic resin, polyurethane resin, etc.

[0283] The first wavelength conversion material WCP1 may be a material that converts blue light into red light, and the second wavelength conversion material WCP2 may be a material that converts blue light into green light. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, fluorescent materials, etc. The quantum dots may include IV-based nanocrystals, II-VI-based compound nanocrystals, III-V-based compound nanocrystals, IV-VI-based compound nanocrystals, or a combination thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SLP for increasing the wavelength conversion efficiency.

[0284] The light-transmitting layer TPL disposed in the third subpixel PX3 transmits the blue light emitted from the light emitting element 300 while maintaining the wavelength of the blue light. The scatterer SLP of the light-transmitting layer TPL may be used to scatter the light and adjust the emission angle of the light emitted through the light-transmitting layer TPL. The light-transmitting layer TPL may not include a wavelength conversion material.

[0285] The second cover layer CPL2 is disposed on the wavelength conversion layer WCL and the light-transmitting layer TPL. The second cover layer CPL2 may be made of an inorganic material. The second cover layer CPL2 may be made of at least one material selected from the materials described as the material of the first cover layer CPL1. The second cover layer CPL2 and the first cover layer CPL1 may be made of the same material, but the invention is not limited thereto.

[0286] The second cover layer CPL2 may cover each of the wavelength conversion patterns WCL1 and WCL2 and the light-transmitting layer TPL. The second cover layer CPL2 may cover not only one surface of each of the wavelength conversion patterns WCL1 and WCL2 and the light-transmitting layer TPL, but also the side surfaces of each of the wavelength conversion patterns WCL1 and WCL2 and the light-transmitting layer TPL. The second cover layer CPL2 may contact the first cover layer CPL1 in the separation space between adjacent color control layers WCL and TPL. The second cover layer CPL2 may have a shape that is partially conformal to the surface step formed by the color control layers WCL and TPL. The valley of the separation space between the color control layers WCL and TPL may not be completely filled by the second cover layer CPL2, but may have a certain depth.

[0287] The color mixing prevention member MBM is disposed on the second cover layer CPL2. The color mixing prevention member MBM is made of a material capable of blocking light transmission, and is used to prevent light from being introduced into adjacent sub-pixels PXn and causing color mixing. The color mixing prevention member MBM may be disposed along the boundary between the sub-pixels PXn. For example, the color mixing prevention member MBM may be disposed along the separation space between the color control layer WCL and the TPL. The color mixing prevention member MBM may fill the valley formed in the separation space between the color control layer WCL and the TPL. The invention is not limited thereto, and one surface of the color mixing prevention member MBM may further protrude in the thickness direction compared to one surface of each of the color control layers WCL and TPL. The height (or thickness) of the color mixing prevention member MBM protruding from the surrounding wavelength conversion pattern WCL1 or WCL2 or the light-transmitting layer TPL may be in the range of 1 μm to 3 μm, in the range of 1.4 μm to 1.8 μm, or about 1.6 μm, but the invention is not limited thereto.

[0288] The color mixing preventing member MBM may include an organic material. The color mixing preventing member MBM may include a light absorbing material that absorbs a visible light wavelength range. In one embodiment, the color mixing preventing member MBM may include an organic light blocking material. The color mixing preventing member MBM is a light blocking member and may be made of the same material as the upper light absorbing member UAB described above, but the invention is not limited thereto.

[0289] Fig.24 is a schematic cross-sectional view of a display device according to yet another embodiment.

[0290] Reference Fig.24In the display device 1_7 according to one embodiment, the color control layers WCL and TPL and the color mixing prevention member MBM of the second display substrate 50_7 may be directly disposed on the first display substrate 10. According to one embodiment, the second substrate 501 may be omitted, and the second display substrate 50_7 may be formed substantially integrally with the first display substrate 10.

[0291] Specifically, the first cover layer CPL1 may be disposed on the lower light absorbing member BAB of the first display substrate 10. The color control layers WCL and TPL may be disposed on the first cover layer CPL1 to correspond to each sub-pixel PXn, and the second cover layer CPL2 may be disposed on the color control layers WCL and TPL. The color mixing preventing member MBM is disposed on the second cover layer CPL2 in the valley between the adjacent color control layers WCL and TPL. The color filter layer CFL and the upper light absorbing member UAB may be disposed on the second cover layer CPL2 and the color mixing preventing member MBM for each sub-pixel PXn, and the third cover layer CPL3 may be disposed on the color filter layer CFL and the upper light absorbing member UAB.

[0292] exist Fig.24 In the display device 1_7, the light output area TA and the light blocking area BA may be defined by the color mixing prevention member MBM and / or the color control layers WCL and TPL. In addition, since the components of the second display substrate 50_7 may be directly formed on the first display substrate 10, the filler 90 and the sealing portion 70 for combining the first display substrate 10 and the second display substrate 50_7 may be omitted. Hereinafter, repeated descriptions will be omitted.

[0293] Fig.25 is a schematic cross-sectional view of a portion of a display device according to an embodiment in which an invalid area is located.

[0294] Reference Fig.25 , the metal wiring PDE, the transistor GTR of the scan driver SDR, the dam structure DAM, and the plurality of patterns PBP and MSP may be disposed in the inactive area DS of the display device 1. The metal wiring PDE, the transistor GTR of the scan driver SDR, and the dam structure DAM may be sequentially disposed from the active area AA to the outermost portion of the display device 1. However, the invention is not limited thereto.

[0295] The metal wiring PDE may be disposed on the first interlayer insulating layer 105 and may be disposed in the invalid area DS of the first display substrate 10. That is, the metal wiring PDE may be disposed in the same layer as the first data conductive layer of the active area AA. Although not specifically shown in the drawings, a plurality of metal wirings PDE may be disposed in the invalid area DS and may be electrically connected to the wiring disposed in the active area AA. For example, the metal wiring PDE may be electrically connected to a plurality of wirings disposed in the active area AA, such as the first voltage wiring VDL, the second voltage wiring VSL, the data line DTL, and the reference voltage wiring RVL. The metal wiring PDE may extend in the invalid area DS along the active area AA and may be connected to the wiring pad WPD disposed in the pad area PDA, and the wiring disposed in the active area AA may be electrically connected to the wiring pad WPD through the metal wiring PDE. An electrical signal may be applied to the wiring through the metal wiring PDE.

[0296] On the metal wiring PDE, a wiring protection layer PEI may be further disposed in addition to the first protection layer 107. The wiring protection layer PEI may include an insulating material and protect the metal wiring PDE.

[0297] The insulating pattern PBP may be disposed to be spaced apart from the metal wiring PDE. The insulating pattern PBP may be substantially the same layer as the first planarization layer 109. That is, the insulating pattern PBP may have the same material and the same thickness as the first planarization layer 109.

[0298] The transistor GTR of the scan driver SDR may be disposed in the inactive area DS of the first display substrate 10. In the drawings, it is shown that only one transistor GTR is disposed, but the invention is not limited thereto, and one or more transistors GTR may be disposed according to the driving circuit of the scan driver SDR. Similar to the driving transistor DRT, the transistor GTR of the scan driver SDR may include an active layer GTR_ACT (see Fig.25 )、gate electrode GTR_G (see Fig.25 ) and source / drain electrodes GTR_SD1 and GTR_SD2 (see Fig.25 ). The active layer GTR_ACT may include a first doping region GTR_ACTa, a second doping region GTR_ACTb, and a channel region GTR_ACTc. The description thereof is the same as that described above with reference to the driving transistor DRT.

[0299] In addition, the light blocking layer BML may be disposed under the active layer GTR_ACT of the transistor GTR of the scan driver SDR, and the first source / drain electrode GTR_SD1 of the transistor GTR of the scan driver SDR may be connected to the light blocking layer BML. However, the invention is not limited thereto.

[0300] The dam structure DAM may be disposed at the outer edge of the scan driver SDR. A plurality of dam structures DAM may be disposed in the inactive area DS, and the number thereof is not particularly limited. In addition, only the cross-sectional shape of the dam structure DAM is shown in the drawings, but the dam structure DAM may be disposed to surround the active area AA of the first display substrate 10. That is, the dam structure DAM may be disposed in a shape extending in the first direction DR1 and the second direction DR2.

[0301] The dam structure DAM may include a plurality of layers. As an example, the dam structure DAM may include a dam base layer DAM_BP and a dam upper layer DAM_UP disposed on the dam base layer DAM_BP. The dam base layer DAM_BP and the dam upper layer DAM_UP may be formed simultaneously with the layers disposed in the active area AA. For example, the dam base layer DAM_BP may be formed in the same process as the first planarization layer 109, and the thickness of the dam base layer DAM_BP may be the same as the thickness of the first planarization layer 109. In addition, the dam upper layer DAM_UP may be formed in the same process as the outer dam 450. However, the first insulating layer IL1 may be disposed between the outer dam 450 and the first planarization layer 109, and the dam upper layer DAM_UP may be disposed directly on the dam base layer DAM_BP. The dam upper layer DAM_UP and the outer dam 450 may have different thicknesses or heights, but the invention is not limited thereto.

[0302] A dummy pattern MSP may be further disposed between the sealing portion 70 and the dam structure DAM. The dummy pattern MSP may be disposed on the outermost portion of the inactive area DS of the first display substrate 10. The dummy pattern MSP may support a mask used in a process of forming a member disposed on the first display substrate 10. That is, as an example, the dummy pattern MSP may function as a mask support during a manufacturing process of the first display substrate 10.

[0303] Fig.26 and Fig. 27 is a schematic cross-sectional view of a portion of a display device according to another embodiment in which an invalid area is located.

[0304] Reference Fig.26 , the display device 1 may further include a cover electrode layer CPE disposed on the first data conductive layer. The cover electrode layer CPE may be disposed on wirings included in the first data conductive layer (e.g., metal wirings PDE, source / drain electrodes GTR_SD1 and GTR_SD2 of transistors GTR of the scan driver SDR). In addition, although not shown in the drawings, the cover electrode layer CPE may also be disposed on the first data conductive layer (e.g., first voltage wirings VDL, data lines DTL, reference voltage wirings RVL, and source / drain electrodes of each of the transistors) disposed in the active area AA.

[0305] The cover electrode layer CPE may be provided to reduce the contact resistance between an electrode or wiring provided in the first data conductive layer and a member provided in another layer in a region where the electrode or wiring contacts the member. For example, when the first electrode 210 contacts the source / drain electrode DRT_SD of the driving transistor DRT or the second electrode 220 contacts the second conductive pattern VCP, the cover electrode layer CPE may be provided between the first electrode 210 and the source / drain electrode DRT_SD of the driving transistor DRT or between the second electrode 220 and the second conductive pattern VCP to reduce the contact resistance. In an embodiment, the cover electrode layer CPE may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., but the invention is not limited thereto.

[0306] Reference Fig. 27 , in the display device 1, the gate electrode GTR_G of the transistor GTR of the scan driver SDR may be connected to the light blocking layer BML. The gate electrode GTR_G of the transistor GTR of the scan driver SDR may have the same voltage as that of the light blocking layer BML, the gate electrode GTR_G may be used as an upper gate electrode, and the light blocking layer BML may be used as a lower gate electrode. The transistor GTR of the scan driver SDR may be driven in a dual-gate manner, and leakage current may be prevented or reduced from flowing in the channel region GTR_ACTc of the active layer GTR_ACT when the transistor GTR is turned off. Other repeated descriptions will be omitted.

[0307] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the invention. Therefore, the disclosed preferred embodiments of the invention are used only in a generic and descriptive sense and not for purposes of limitation.

Claims

1. A display device, comprising: A first voltage wiring extending in a first direction; a data line spaced apart from the first voltage wiring and extending in the first direction; a scan line extending in a second direction different from the first direction; a sensing line spaced apart from the scanning line and extending in the second direction; a first inner bank and a second inner bank disposed on the first voltage wiring and the data line, extending in the first direction, and disposed to be spaced apart from and facing each other; a first electrode disposed on the first inner bank and extending in the first direction; a second electrode disposed on the second inner bank and extending in the first direction; as well as A plurality of light emitting elements are arranged between the first electrode and the second electrode, Each of the plurality of light emitting elements includes a semiconductor core and an insulating film surrounding at least a portion of an outer surface of the semiconductor core, wherein the semiconductor core includes a light emitting layer. wherein the first inner bank partially overlaps the first voltage wiring in a plan view, and Wherein, the second inner bank is arranged not to overlap with the data line in a thickness direction.

2. The display device according to claim 1, further comprising: a reference voltage wiring, spaced apart from the data line in the second direction and extending in the first direction; as well as a reference voltage distribution line spaced apart from the sensing line in the first direction and extending in the second direction, Wherein, the reference voltage distribution line is electrically connected to the reference voltage wiring.

3. The display device according to claim 2, wherein: The data line is provided between the first voltage wiring and the reference voltage wiring, and The sensing line is disposed between the scan line and the reference voltage distribution line.

4. The display device according to claim 2 , further comprising a second voltage wiring extending in the first direction and disposed to be spaced apart from the reference voltage wiring, in, The first electrode is electrically connected to the first voltage wiring through a driving transistor, and The second electrode is electrically connected to the second voltage wiring.

5. The display device according to claim 4, wherein: The second voltage wiring further includes a portion extending in the second direction, and The portion of the second voltage wiring extending in the second direction partially overlaps the second electrode in a plan view.

6. The display device according to claim 1, further comprising an outer bank disposed to extend in the first direction and the second direction to surround a region in which the first inner bank and the second inner bank are disposed, in, The first voltage wiring extends in the first direction between the second inner bank and the outer bank, and The data line overlaps a portion of the outer bank extending in the first direction in the thickness direction.

7. The display device according to claim 1, further comprising a shielding electrode having at least a portion overlapping the first electrode and disposed to surround a region in which the light emitting element is disposed, in, The shield electrode is provided to cover a portion of each of the first electrode and the first inner bank relative to the outer side of the region in which the light emitting element is provided.

8. The display device according to claim 1, further comprising: a third inner bank disposed to be spaced apart from the first inner bank and to face the first inner bank; as well as a repair electrode, disposed on the third inner bank, The plurality of light-emitting elements further include a first light-emitting element disposed between the first electrode and the second electrode and a second light-emitting element disposed between the first electrode and the repair electrode.

9. The display device according to claim 1, wherein: The semiconductor core of the light emitting element includes a first semiconductor layer, a second semiconductor layer, and the light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and The insulating film is provided to surround at least an outer surface of the light emitting layer.

10. The display device according to claim 9, further comprising: a first contact electrode disposed on the first electrode and electrically connected to the first electrode and one end of the light emitting element; as well as The second contact electrode is provided on the second electrode and is electrically connected to the second electrode and the other end of the light emitting element.

11. A display device, comprising: first base; A semiconductor layer, disposed on the first substrate and including a first active layer of a driving transistor; A first gate insulating layer, disposed on the first substrate and the semiconductor layer; a first gate conductive layer, disposed on the first gate insulating layer and comprising a first gate electrode of the driving transistor; A first interlayer insulating layer, disposed on the first gate conductive layer; a first data conductive layer disposed on the first interlayer insulating layer and including a source / drain electrode of the driving transistor and a first voltage wiring; A first protective layer, disposed on the first data conductive layer; A first planarization layer, disposed on the first protective layer; a first inner bank and a second inner bank disposed on the first planarization layer and spaced apart from each other and facing each other; A first electrode and a second electrode are disposed on the first inner bank and the second inner bank, respectively; as well as a light emitting element disposed between the first electrode and the second electrode, The light emitting element includes a semiconductor core and an insulating film surrounding at least a portion of an outer surface of the semiconductor core, and the semiconductor core includes a light emitting layer.

12. The display device according to claim 11, wherein: The first electrode is electrically connected to the source / drain electrodes of the driving transistor through an electrode contact hole penetrating the first protection layer and the first planarization layer.

13. The display device according to claim 12, wherein: The first gate conductive layer further includes a second voltage wiring, and The second electrode is electrically connected to the second voltage wiring.

14. The display device according to claim 12, wherein: The first data conductive layer further includes a second voltage wiring, and The second electrode is electrically connected to the second voltage wiring.

15. The display device according to claim 13, wherein: The first data conductive layer further includes a conductive pattern contacting the second voltage wiring through a first wiring contact hole penetrating through the first interlayer insulating layer, and The second electrode contacts the conductive pattern through a second wiring contact hole that passes through the first protection layer and the first planarization layer.

16. The display device according to claim 11, further comprising: a first contact electrode disposed on the first electrode and electrically connected to the first electrode and one end of the light emitting element; as well as The second contact electrode is provided on the second electrode and is electrically connected to the second electrode and the other end of the light emitting element.

17. The display device according to claim 16, further comprising: A thin film encapsulation structure, disposed on the first contact electrode and the second contact electrode; as well as The color filter layer is arranged on the thin film encapsulation structure. 18 . The display device of claim 17 , further comprising a color control layer disposed between the color filter layer and the thin film encapsulation structure.

19. The display device according to claim 16, further comprising an outer bank disposed on the first planarization layer and spaced apart from each of the first inner bank and the second inner bank, in, The outer bank has a height greater than a height of each of the first inner bank and the second inner bank. 20 . The display device of claim 19 , further comprising a reflective layer disposed on one surface of the outer bank.

21. The display device according to claim 11, further comprising: A buffer layer, disposed between the first substrate and the semiconductor layer; as well as A light blocking layer is disposed between the buffer layer and the first substrate and is configured to partially overlap the first active layer.

22. A display device, comprising: a first substrate, in which a light-emitting region and a non-light-emitting region are defined; a semiconductor layer disposed in the non-light emitting region of the first substrate and including a first active layer of a driving transistor; a first gate conductive layer disposed in the non-light emitting region and comprising a first gate electrode disposed to overlap with the first active layer; A first voltage wiring is provided in the non-light emitting area and the light emitting area and extends in a first direction; a first inner bank and a second inner bank disposed in the light emitting region, extending in the first direction, and spaced apart from each other in a second direction; a first electrode including at least a portion disposed on the first inner bank and including a portion extending in the first direction; a second electrode including at least a portion disposed on the second inner bank and including a portion extending in the first direction; as well as a plurality of light emitting elements disposed between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, Each of the plurality of light emitting elements includes a semiconductor core and an insulating film surrounding at least a portion of an outer surface of the semiconductor core, and the semiconductor core includes a light emitting layer.

23. The display device according to claim 22, further comprising: a scanning line, arranged in the non-luminescent area and extending in the second direction; as well as The sensing line extends in the second direction and is spaced apart from the scanning line.

24. The display device according to claim 23, further comprising: a reference voltage wiring, disposed in the non-light emitting area and the light emitting area and extending in the first direction; as well as A reference voltage distribution line is provided in the non-light emitting region, extends in the second direction, and is electrically connected to the reference voltage wiring.

25. The display device according to claim 22, wherein: The first electrode includes a first electrode trunk portion extending in the second direction and a first electrode branch portion branching from the first electrode trunk portion along the first direction, and The second electrode includes a second electrode trunk portion extending in the second direction and second electrode branch portions branching from the second electrode trunk portion along the first direction.

26. The display device according to claim 25, further comprising: a first contact electrode disposed on the first electrode branch portion and electrically connected to the first electrode and one end of the light emitting element; as well as A second contact electrode is provided on the second electrode branch portion and is electrically connected to the second electrode and the other end of the light emitting element.

27. The display device according to claim 26, further comprising an outer bank arranged to cover the non-luminescent area and surround the luminescent area, in, The outer bank has a height greater than a height of each of the first inner bank and the second inner bank.

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