Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes a semiconductor film including a Schottky junction region and an ohmic junction region; a Schottky electrode disposed on the Schottky junction region of the semiconductor film; and an ohmic electrode disposed on the ohmic junction region, the semiconductor device characterized in that a dislocation density of the Schottky junction region of the semiconductor film is smaller than a dislocation density of the ohmic junction region of the semiconductor film.

Description

Technical Field

[0001] This invention relates to a semiconductor device useful for power devices, etc. Furthermore, this invention relates to a method for manufacturing a semiconductor device. Background Technology

[0002] As a second-generation switching element capable of achieving high voltage withstand, low loss, and high heat resistance, gallium oxide (Ga2O3) semiconductor devices with large band gaps have attracted attention, with prospects for application in power semiconductor devices such as inverters. Furthermore, due to their wide band gap, they are expected to be widely used in light receiving / emitting devices such as LEDs or sensors. In particular, α-Ga2O3, which has a corundum structure in gallium oxide, can have its band gap controlled, according to Non-Patent Document 1, by forming mixed crystals with indium or aluminum, or by combining them to form mixed crystals, making it a highly attractive material system for InAlGaO-based semiconductors. Here, InAlGaO-based semiconductors are composed of In... X Al Y Ga Z O3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5) is represented (Patent Document 9, etc.), and can be generally considered as the same material system containing gallium oxide.

[0003] However, since the most stable phase of gallium oxide is the β-gallia structure, it is difficult to form crystalline films with a metastable corundum structure without special film-forming methods. For example, crystal growth conditions are often limited by heteroepitaxial growth, thus tending towards higher dislocation densities. Furthermore, beyond crystalline films with corundum structures, many challenges remain regarding improving film formation rate and crystal quality, suppressing crack or abnormal growth, inhibiting twinning, and preventing substrate breakage due to warping. In this context, some research is currently being conducted on the film formation of crystalline semiconductors with corundum structures.

[0004] Patent Document 1 describes a method for manufacturing oxide crystalline thin films using gallium or indium bromides or iodides via atomization CVD (chemical vapor deposition). Patent Documents 2-4 describe a multilayer structure in which a semiconductor layer with a corundum-type crystal structure and an insulating film with a corundum-type crystal structure are stacked on a substrate with a corundum-type crystal structure. Furthermore, as in Patent Documents 5-7, research is also being conducted on film formation using ELO (Epitaxial lateral Overgrowth) substrates or vias and performed via atomization CVD.

[0005] Patent Document 8 describes the formation of gallium oxide films with a corundum structure using at least gallium and oxygen raw materials via hydride vapor phase epitaxy (HVPE). Furthermore, Patent Documents 10 and 11 describe the growth of ELO crystals using a PSS substrate, yielding a film with a surface area of ​​9 μm. 2 The above and the dislocation density is 5×10 6 cm -2 Gallium oxide (GaO) has the problem of heat dissipation. To address this, the GaO film thickness needs to be reduced to less than 30 μm. However, this involves complex grinding processes and increased costs. Furthermore, there is the issue of poor adhesion between the dielectric film and the semiconductor layer. Additionally, the series resistance in vertically mounted devices is not satisfactory. Therefore, to maximize the performance of GaO as a power device, a GaO film with superior crystal quality is desired, and such a crystalline film is highly anticipated.

[0006] In addition, patent documents 1 to 11 are all related publications of the applicant's patents or patent applications, and research on them is still ongoing.

[0007] [Patent Document 1] Japanese Patent No. 5397794

[0008] [Patent Document 2] Japanese Patent No. 5343224

[0009] [Patent Document 3] Japanese Patent No. 5397795

[0010] [Patent Document 4] Japanese Patent Publication No. 2014-72533

[0011] [Patent Document 5] Japanese Patent Publication No. 2016-100592

[0012] [Patent Document 6] Japanese Patent Publication No. 2016-98166

[0013] [Patent Document 7] Japanese Patent Publication No. 2016-100593

[0014] [Patent Document 8] Japanese Patent Publication No. 2016-155714

[0015] [Patent Document 9] International Patent Publication No. 2014 / 050793

[0016] [Patent Document 10] U.S. Patent Publication No. 2019 / 0057865

[0017] [Patent Document 11] Japanese Patent Publication No. 2019-034883

[0018] [Non-Patent Literature 1] Kentaro Kaneko, “Growth and Properties of Gallium Oxide-Based Cobalt Structure Mixed Crystal Thin Films”, Doctoral Dissertation, Kyoto University, March 2016 Summary of the Invention

[0019] The purpose of this invention is to provide a stacked structure that is useful for semiconductor devices, etc., having a large area, good film thickness distribution and a crystalline film with a thickness of less than 30 μm, and excellent heat dissipation.

[0020] One aspect of the semiconductor device according to the present invention is to reduce the dislocation density of the semiconductor. According to embodiments of the semiconductor device of the present invention, one objective is to provide a semiconductor device comprising a semiconductor film having a lower dislocation density in the Schottky junction region than in the Ohm junction region.

[0021] To achieve at least the aforementioned objectives, the inventors conducted in-depth research and discovered that by performing epitaxial lateral overgrowth (ELO) under specific conditions, it is possible to obtain a semiconductor device in which the dislocation density in the Schottky junction region of the semiconductor film is lower than the dislocation density in the ohmic junction region of the semiconductor film. Furthermore, it was found that such a semiconductor device exhibits superior semiconductor characteristics and can solve the aforementioned conventional problems. Details will be described along with the embodiments.

[0022] Furthermore, after obtaining the above insights, the inventors conducted further and repeated research to complete this invention.

[0023] That is, the present invention relates to the following technical solutions.

[0024] [1] A semiconductor device includes: a semiconductor film comprising a Schottky junction region and an ohmic junction region; a Schottky electrode disposed on the Schottky junction region of the semiconductor film; and an ohmic electrode disposed on the ohmic junction region, wherein the semiconductor device is characterized in that the dislocation density of the Schottky junction region of the semiconductor film is smaller than the dislocation density of the ohmic junction region of the semiconductor film.

[0025] [2] According to the semiconductor device described above [1], the semiconductor film includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer including the Schottky junction region and the second semiconductor layer including the Ohm junction region.

[0026] [3] In the semiconductor device described in [2] above, the second semiconductor layer is an n+ type semiconductor layer.

[0027] [4] The semiconductor device according to [2] or [3] above, wherein the first semiconductor layer is an n-type semiconductor layer.

[0028] [5] The semiconductor device according to any one of [2] to [4] above, wherein the first semiconductor layer has at least one trench.

[0029] [6] The semiconductor device according to any one of [1] to [5] above, wherein the semiconductor film includes a lateral growth region.

[0030] [7] The semiconductor device according to any one of [1] to [6] above, wherein the thickness of the semiconductor film is 1 μm or more.

[0031] [8] The semiconductor device according to any one of [2] to [7] above, wherein the second semiconductor layer has a corundum structure.

[0032] [9] The semiconductor device according to any one of [2] to [8] above, wherein the second semiconductor layer comprises at least gallium.

[0033]

[10] The semiconductor device according to any one of [2] to [9] above, wherein the first semiconductor layer comprises at least gallium.

[0034]

[11] The semiconductor device according to any one of [2] to

[10] above, wherein the first semiconductor layer includes a p-type semiconductor region.

[0035]

[12] The semiconductor device according to any one of [1] to

[11] above, wherein the semiconductor device is a power device.

[0036]

[13] The semiconductor device according to any one of [1] to

[12] above, wherein the semiconductor device is a Schottky barrier diode (SBD).

[0037]

[14] The semiconductor device according to any one of [1] to

[12] above, wherein the semiconductor device is a junction barrier Schottky diode (JBS).

[0038]

[15] A semiconductor system comprising a semiconductor device, wherein the semiconductor device is any one of the semiconductor devices described in [1] to

[14] above.

[0039]

[16] A method for manufacturing a semiconductor device includes the following steps: placing a mask on a crystal substrate with the c-axis direction of the crystal substrate as the length direction; and growing a semiconductor film on a crystal substrate on which the mask is placed.

[0040]

[17] A method for manufacturing a semiconductor device includes the following steps: placing a mask on a crystalline layer formed on a crystal substrate with the c-axis as the length direction; and growing a semiconductor film on the crystalline layer with the mask placed on it.

[0041]

[18] According to the manufacturing method described above

[16] to

[17] , the mask comprises an electrode material.

[0042]

[19] According to the manufacturing method described above

[16] to

[17] , the mask comprises a dielectric material.

[0043]

[20] The manufacturing method according to any one of

[16] to

[19] above includes the following step: converging the dislocations in the a-axis direction of the crystal substrate.

[0044]

[21] The manufacturing method according to any one of

[16] to

[20] above, wherein the process includes the following step: at least removing the crystal substrate.

[0045]

[22] The manufacturing method according to any one of

[16] to

[20] above includes the following steps: at least removing the crystal substrate and the mask.

[0046]

[23] The manufacturing method according to any one of

[17] to

[20] above includes the following step: at least removing the crystal substrate and the crystal layer.

[0047]

[24] According to the manufacturing method described above

[17] , the crystalline layer is formed on the crystal substrate by atomization CVD.

[0048] Regarding one embodiment of the semiconductor device of the present invention, in this embodiment, the dislocation density in the Schottky junction region of the semiconductor film is smaller than the dislocation density in the Ohmic junction region of the semiconductor film, resulting in superior semiconductor characteristics. Details will be described together with the embodiments. Attached Figure Description

[0049] Figure 1 This is a schematic diagram illustrating a part of a manufacturing process as one embodiment of the method for manufacturing a semiconductor device according to the present invention.

[0050] Figure 2 This is a diagram illustrating the hydride vapor phase epitaxy (HVPE) apparatus preferably used in embodiments of the present invention.

[0051] Figure 3 This is a schematic diagram illustrating one embodiment of the irregularities formed on the surface of a crystalline matrix preferred in the present invention.

[0052] Figure 4 This is a diagram illustrating the atomizing CVD apparatus preferably used in an embodiment of the present invention.

[0053] Figure 5 This is a diagram that schematically represents an example of a power supply system.

[0054] Figure 6 This is a diagram that schematically represents an example of a system device.

[0055] Figure 7 This is a diagram illustrating an example of a power supply circuit diagram for a power supply device.

[0056] Figure 8 This is a schematic diagram illustrating an example of a semiconductor device bonded to a lead frame, circuit board, or heat sink.

[0057] Figure 9 This is a diagram that schematically represents an example of a power card.

[0058] Figure 10 The images shown represent transmission electron microscope (TEM) images from embodiments of the present invention.

[0059] Figure 11 This represents the main part of a semiconductor device as an example of an embodiment of the present invention.

[0060] Figure 12 This represents the main part of a semiconductor device as an example of an embodiment of the present invention.

[0061] Figure 13 This is a cross-sectional view showing a semiconductor device (SBD) as an embodiment of the present invention.

[0062] Figure 14 This is a cross-sectional view showing a semiconductor device (JBS) as an embodiment of the present invention.

[0063] Figure 15-a This is a schematic diagram illustrating a part of the manufacturing process of a semiconductor device as an embodiment of the present invention.

[0064] Figure 15-b This is a schematic diagram illustrating a part of the manufacturing process of a semiconductor device as an embodiment of the present invention.

[0065] Figure 16-a This is a schematic diagram illustrating a part of the manufacturing process of a semiconductor device as an embodiment of the present invention.

[0066] Figure 16-bThis is a cross-sectional view showing a laminated structure obtained from a semiconductor device manufacturing process, as an embodiment of the present invention.

[0067] Figure 17-a This is a cross-sectional view showing a laminated structure obtained from a semiconductor device manufacturing process, as an embodiment of the present invention.

[0068] Figure 17-b This is a cross-sectional view showing a laminated structure obtained from a semiconductor device manufacturing process, as an embodiment of the present invention.

[0069] Figure 17-c This is a cross-sectional view showing an example of a semiconductor device obtained from a semiconductor device manufacturing process, as an embodiment of the present invention. Detailed Implementation

[0070] As one embodiment of the semiconductor device of the present invention, the semiconductor device includes: a semiconductor film comprising a Schottky junction region and an ohmic junction region; a Schottky electrode disposed on the Schottky junction region of the semiconductor film; and an ohmic electrode disposed on the ohmic junction region. The semiconductor device is characterized in that the dislocation density of the Schottky junction region of the semiconductor film is smaller than the dislocation density of the ohmic junction region of the semiconductor film. According to an embodiment of the present invention, the dislocations in the region forming the Schottky junction can be selectively reduced, thus obtaining a semiconductor device with excellent semiconductor characteristics. Here, the Schottky junction region refers, for example, to a region in the semiconductor film within 100 nm of the interface between the semiconductor film and the Schottky electrode. Similarly, the ohmic junction region refers, for example, to a region in the semiconductor film within 100 nm of the interface between the semiconductor film and the ohmic electrode. In an embodiment of the present invention, preferably, the semiconductor film has a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer forms a Schottky junction with the Schottky electrode, and the second semiconductor layer forms an ohmic junction with the ohmic electrode. Furthermore, in embodiments of the present invention, it is preferable that the dislocation density of the first semiconductor layer is smaller than that of the second semiconductor layer.

[0071] Additionally, as one embodiment, the semiconductor device is a semiconductor device comprising at least electrodes and a semiconductor film, characterized in that the semiconductor film has a crystal structure including a c-axis, and the electrodes extend along the c-axis direction. Here, "the electrodes extend along the c-axis direction" means that the length direction of the electrodes is parallel to the c-axis direction of the semiconductor film and includes an angle range of less than 5° relative to the c-axis direction. Furthermore, the shape of the electrodes is not particularly limited, but when the electrode shape is configured to have length in more than two directions, the length direction refers to the longer direction.

[0072] As one embodiment of the semiconductor device manufacturing method of the present invention, the manufacturing method includes: arranging a mask on the m-surface of a crystalline substrate with the m-surface as the main surface, with the c-axis direction of the crystalline substrate as the length direction, and performing crystal growth of a semiconductor film on the m-surface of the crystalline substrate. Furthermore, according to an embodiment of the present invention, the mask may be formed of an electrode material. Since the ELO-grown semiconductor layer extends from the crystalline substrate to the mask, when the mask is used as an electrode, the crystallinity near the interface between the electrode and the semiconductor layer is good. Additionally, when the mask is used as an electrode, a semiconductor device with good bonding between the ELO-grown semiconductor layer and the electrode can be obtained.

[0073] As one embodiment of the semiconductor device manufacturing method of the present invention, the manufacturing method is characterized by forming a semiconductor layer composed of a crystalline film on a crystal substrate having an ELO mask by lateral growth, and using the ELO mask as an electrode or gate insulating film. Alternatively, according to another embodiment, the mask may also be formed of a material containing Si with a conductivity lower than that of the electrode. According to one embodiment, the mask may contain a dielectric material, or it may be a mask made of a dielectric material. The mask can also be used as a dielectric film in a semiconductor device. The inventors have discovered that by performing ELO under specific conditions, a semiconductor device with good interfacial bonding between the dielectric film and the semiconductor layer, good crystallinity of the channel layer, and excellent semiconductor properties can be easily obtained.

[0074] As another embodiment of the semiconductor device of the present invention, the semiconductor device is a semiconductor device comprising at least a dielectric film and a semiconductor film, characterized in that the semiconductor film has a crystal structure including a c-axis, and the dielectric film extends along the c-axis direction. Here, "the dielectric film extends along the c-axis direction" means that the length direction of the dielectric film is parallel to the c-axis direction of the semiconductor film and includes a direction with an angle range of less than 5° relative to the c-axis direction.

[0075] Furthermore, as one embodiment of the semiconductor device manufacturing method of the present invention, the manufacturing method includes: forming a semiconductor layer containing lateral growth regions on a crystalline substrate on which a mask is disposed. As another embodiment, a mask containing electrode material may also be disposed on the crystalline substrate, and after ELO growth, the mask may be used as an electrode of the semiconductor device.

[0076] In another embodiment of the present invention, a mask containing a dielectric material can be configured and used as a gate insulating film for a semiconductor device after ELO growth. Furthermore, "the dielectric film extends along the c-axis direction" means, as described above, that the length direction of the dielectric film is parallel to the c-axis direction of the semiconductor film and includes a direction with an angle range of less than 5° relative to the c-axis direction. This can be either the entire length direction of the dielectric film being parallel to the c-axis direction, or a portion of the dielectric film extending along the c-axis direction. In this embodiment, "c-axis direction" refers to a direction perpendicular to the c-plane. Examples of crystal structures including the c-axis include corundum structures. By employing such a structure, a semiconductor device with good interface bonding between the dielectric film and the semiconductor layer, good crystallinity of the channel layer, and excellent semiconductor properties can be obtained in the present invention. Furthermore, as one embodiment of the present invention, it is preferable that the semiconductor layer includes a laterally grown region. In an embodiment of the present invention, it is preferable that the semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region being bonded to the dielectric film, and the second crystalline conductor region containing more dislocations than the first semiconductor region. Furthermore, it is also preferred that the thickness of the semiconductor layer is 1 μm or more. Furthermore, it is also preferred that the semiconductor layer has a corundum structure. Furthermore, it is also preferred that the semiconductor layer contains at least gallium. Furthermore, it is also preferred that the dielectric film is a gate insulating film. Furthermore, as one embodiment of the present invention, it is also preferred that the semiconductor device includes at least a dielectric film, a first semiconductor layer, and a second semiconductor layer, the first semiconductor layer having a crystal structure including a c-axis, and the dielectric film extending along the c-axis direction. Furthermore, preferably, the first semiconductor layer includes a first semiconductor region and a second semiconductor region, the second semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region of the first semiconductor layer is bonded to the dielectric film, and the first semiconductor region in the first semiconductor layer has fewer dislocations than the second semiconductor region. Examples of the above-preferred semiconductor devices can be cited as... Figure 11 or Figure 12 The semiconductor device shown is an example. Based on such a semiconductor device, a higher quality channel layer can be formed, resulting in superior semiconductor characteristics. Furthermore, more specifically, Figure 11 This is a diagram showing the main components of a MOSFET. Figure 11 The MOSFET at least includes a substrate 11, a gate electrode 14, a gate insulating film 15, a channel layer 18, an n-type semiconductor layer 18a, and an n+ type semiconductor layer 18b. In this invention, by using the dielectric film as the gate insulating film, the channel layer can be preferably made a dislocation-free layer, thereby exhibiting superior semiconductor characteristics. Furthermore, Figure 12 This is a diagram showing the main parts of the SBD. Figure 12The SBD at least comprises a substrate 11, an electrode (Schottky electrode) 14, a semi-insulating layer 16, and an n-type semiconductor layer 18a. In this invention, the Schottky electrode material is used as the Schottky electrode in the ELO mask, thereby not only ensuring a good Schottky junction, but also better enabling the area near the Schottky interface, for example, to be a dislocation-free layer, thus achieving superior semiconductor characteristics.

[0077] The dielectric film (dielectric material) is not particularly limited and can be any known dielectric film. The relative permittivity of the dielectric film is also not particularly limited, but a relative permittivity of 5 or less is preferred. "Relative permittivity" refers to the ratio of the dielectric constant of the film to the dielectric constant of vacuum. Examples of dielectric films include oxide films, phosphate films, and nitride films. In this invention, the dielectric film is preferably a Si-containing film. Silicon oxide-based films are preferred examples of Si-containing films. Examples of silicon oxide-based films include SiO2 films, phosphorus-added SiO2 (PSG) films, boron-added SiO2 films, boron phosphorus-phosphate-added SiO2 films (BPSG films), SiOC films, and SiOF films. The method for forming the dielectric film is not particularly limited, and examples include CVD, atmospheric pressure CVD, plasma CVD, atomization CVD, and thermal oxidation. In this invention, atomization CVD or atmospheric pressure CVD is preferred as the method for forming the dielectric film. Furthermore, the thickness of the dielectric film is not particularly limited, but preferably at least a portion of the dielectric film has a thickness of 1 μm or more. According to the present invention, even when such a thick dielectric film is stacked on the semiconductor layer, it is even more preferable to obtain a dielectric film free from crystal defects caused by stress concentration within the semiconductor layer.

[0078] Furthermore, the gate insulating film is not particularly limited as long as it does not hinder the purpose of the present invention, and can be a known gate insulating film. Preferred examples of the gate insulating film include oxide films such as SiO2, Si3N4, Al2O3, GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, MgO, GdO, and oxide films containing at least phosphorus. The method for forming the gate insulating film can be a known method, such as dry methods and wet methods. Examples of dry methods include sputtering, vacuum evaporation, CVD, and PLD (pulse laser deposition). Examples of wet methods include screen printing or die coating.

[0079] The semiconductor layer (hereinafter also referred to as "oxide semiconductor film", "semiconductor film", "crystalline film") is preferably an oxide having a corundum structure. Furthermore, in this invention, the oxide preferably contains one or more metals selected from Group 9 (e.g., cobalt, barium, or iridium) and Group 13 (e.g., aluminum, gallium, or indium) of the periodic table; more preferably, it contains a metal oxide selected from at least one metal selected from aluminum, indium, gallium, and iridium; even more preferably, it contains at least gallium or iridium; and most preferably, it contains at least gallium. In this invention, having the m-plane as the principal surface of the oxide semiconductor film can further suppress the diffusion of oxygen, etc., and further improve the electrical properties, so it is more preferred. Additionally, the oxide semiconductor film may also have an offset angle. In this invention, the oxide is preferably α-Ga₂O₃ or a mixture thereof. Furthermore, "principal component" refers to the total composition of the oxide relative to the semiconductor layer, preferably containing 50% or more in atomic proportion, more preferably 70% or more, even more preferably 90% or more, and may also refer to 100%. Furthermore, the thickness of the semiconductor layer is not particularly limited and can be less than 1 μm or more than 1 μm. In this invention, it is preferably more than 1 μm, and more preferably more than 10 μm. The surface area of ​​the semiconductor film is not particularly limited and can be 1 mm. 2 The above can also be 1mm. 2 The following is preferred: 10mm 2 ~300cm 2 More preferably 100mm 2 ~100cm 2 Furthermore, the semiconductor film is preferably a monocrystalline film, but it can also be a polycrystalline film or a crystalline film containing polycrystalline material. According to one embodiment of the manufacturing method of the present invention, an n+ type semiconductor layer can be formed on a crystalline substrate, and an n- type semiconductor layer with a lower dopant concentration than the n+ type semiconductor layer can be formed on the n+ type semiconductor layer, for example, and a semiconductor film comprising at least a first semiconductor layer and a second crystalline conductor layer can be formed. Furthermore, according to embodiments of the present invention, since the dislocation growth direction can be converged, the crystallinity of the semiconductor film, especially in regions highly related to the characteristics of the semiconductor device (particularly Schottky characteristics), can be further improved.

[0080] The semiconductor layer preferably contains a dopant. The dopant is not particularly limited and can be any known dopant. Examples of dopants include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as magnesium, calcium, or zinc. In this invention, the semiconductor layer preferably contains an n-type dopant, more preferably an n-type oxide semiconductor layer. Furthermore, in this invention, the n-type dopant is preferably Sn, Ge, or Si. Regarding the dopant content, in the composition of the semiconductor layer, it is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.00001 atomic% to 10 atomic%. More specifically, the dopant concentration is typically about 1 × 10⁻⁶. 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the concentration of the dopant can be set to, for example, approximately 1 × 10⁻⁶. 17 / cm 3 The following low concentrations. Additionally, according to one aspect of the invention, it is also possible to achieve approximately 1 × 10⁻⁶. 20 / cm 3 The above-mentioned high concentrations contain dopants. Furthermore, the concentration of the fixed charge in the semiconductor layer is not particularly limited; as one embodiment of the semiconductor device of the present invention, when the concentration of the fixed charge is 1 × 10⁻⁶... 17 / cm 3 In the following cases, a depletion layer can be well formed through the semiconductor layer, which is therefore preferred.

[0081] The semiconductor layer can be formed using known methods. Examples of methods for forming the semiconductor layer include CVD (chemical vapor deposition), MOCVD (metal-organic chemical vapor deposition), MOVPE (metal-organic vapor phase epitaxy), atomized CVD, atomized epitaxy, MBE (molecular beam epitaxy), HVPE, pulsed growth, or ALD (atomic layer deposition).

[0082] Hereinafter, an example of a method for manufacturing the semiconductor device will be described using the HVPE method to form the semiconductor layer (hereinafter also referred to as "crystal growth layer" or "crystalline film").

[0083] As one implementation method of the HVPE method, for example, it can be described using... Figure 2The HVPE apparatus shown vaporizes a metal source containing metal to form a metal-containing feed gas. Then, the metal-containing feed gas and an oxygen-containing feed gas are supplied to a crystalline substrate in a reaction chamber for film formation. A crystalline substrate with an ELO mask (e.g., composed of the dielectric film) on its surface is used. A reactive gas is supplied to the crystalline substrate, and film formation occurs under the flow of the reactive gas. According to one embodiment of the invention, the crystalline substrate is preferably a crystalline substrate. Alternatively, according to another embodiment of the invention, the crystalline substrate may also comprise a crystalline substrate and a crystalline layer disposed on the crystalline substrate.

[0084] (Metal source)

[0085] The metal source is not particularly limited as long as it contains a metal and can be vaporized; it can be an elemental metal or a metal compound. Examples of the metal include one or more metals selected from gallium, aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In this invention, the metal is preferably selected from one or more metals selected from gallium, aluminum, and indium, and gallium is more preferred. The metal source is most preferably elemental gallium. Furthermore, the metal source can be a gas, a liquid, or a solid. In this invention, for example, when gallium is used as the metal, the metal source is preferably a liquid.

[0086] The method of vaporization is not particularly limited as long as it does not hinder the purpose of the present invention, and can be a known method. In the present invention, the vaporization method is preferably performed by halogenating a metal source. The halogenating agent used for the halogenation is not particularly limited as long as it can halogenate the metal source, and can be a known halogenating agent. Examples of halogenating agents include halogens or hydrogen halides. Examples of halogens include fluorine, chlorine, bromine, or iodine. Examples of hydrogen halides include hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In the present invention, hydrogen halides are preferably used in the halogenation, and hydrogen chloride is more preferably used. In the present invention, the vaporization is preferably performed by supplying a halogen or hydrogen halide as a halogenating agent to a metal source, and reacting the metal source with the halogen or hydrogen halide at a temperature above the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited. In this invention, for example, when the metal source is gallium and the halogenating agent is HCl, it is preferably below 900°C, more preferably below 700°C, and most preferably between 400°C and 700°C. The metal-containing feed gas is not particularly limited as long as it contains the metal source. Examples of metal-containing feed gases include metal halides (fluorides, chlorides, bromides, iodides, etc.).

[0087] In embodiments of the present invention, after vaporizing a metal source containing a metal to form a metal-containing raw material gas, the metal-containing raw material gas and the oxygen-containing raw material gas are supplied to a crystalline substrate in the reaction chamber. Alternatively, in embodiments of the present invention, a reactive gas is supplied to the substrate. Examples of the oxygen-containing raw material gas include O2, CO2, NO, N2O, H2O, or O3. In the present invention, the oxygen-containing raw material gas is preferably selected from one or more of O2, H2O, and N2O, and more preferably a gas containing O2. Furthermore, as one embodiment, the oxygen-containing raw material gas may also contain CO2. The reactive gas is generally a reactive gas different from the metal-containing raw material gas and the oxygen-containing raw material gas, and does not contain inactive gases. There are no particular limitations on the reactive gas; for example, etching gases can be used. There are no particular limitations on the etching gas as long as it does not hinder the purpose of the present invention, and it can be a known etching gas. In this invention, the reactive gas is preferably a halogen gas (e.g., fluorine, chlorine, bromine, or iodine), a hydrogen halide gas (e.g., hydrofluoric acid, hydrogen chloride, hydrogen bromide, hydrogen iodide), hydrogen, or a mixture of two or more of these gases, more preferably containing hydrogen halide, and most preferably containing hydrogen chloride. Furthermore, the metal-containing feed gas, the oxygen-containing feed gas, and the reactive gas may also include a carrier gas. Examples of carrier gases include inert gases such as nitrogen or argon. The partial pressure of the metal-containing feed gas is not particularly limited, but in this invention, it is preferably 0.5 Pa to 1 kPa, more preferably 5 Pa to 0.5 kPa. The partial pressure of the oxygen-containing feed gas is not particularly limited, but in this invention, it is preferably 0.5 to 100 times the partial pressure of the metal-containing feed gas, more preferably 1 to 20 times. The partial pressure of the reactive gas is not particularly limited, but in embodiments of the present invention, it is preferably 0.1 to 5 times the partial pressure of the metal-containing raw material gas, more preferably 0.2 to 3 times.

[0088] In embodiments of the present invention, it is further preferred that a dopant-containing raw material gas is supplied to the substrate. The dopant-containing raw material gas is not particularly limited as long as it contains a dopant. The dopant is also not particularly limited; in the present invention, the dopant preferably contains one or more elements selected from germanium, silicon, titanium, zirconium, vanadium, niobium, and tin, more preferably germanium, silicon, or tin, and most preferably germanium. By using a dopant-containing raw material gas in this way, the conductivity of the obtained film can be easily controlled. The dopant-containing raw material gas preferably contains the dopant in the form of a compound (e.g., a halide, oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing raw material gas is not particularly limited, but in the present invention, it is preferably 1 × 10⁻⁶ of the partial pressure of the metal-containing raw material gas. -7 0.1 times. More preferably 2.5 × 10 -6 Times ~7.5×10 -2 The ratio is multiples. Furthermore, in this invention, it is preferable to supply the dopant-containing raw material gas together with the reactive gas onto the crystalline matrix.

[0089] (Crystal substrate)

[0090] As one embodiment of the present invention, the crystalline substrate is preferably a crystal substrate. There are no particular limitations on the crystal substrate, as long as it contains crystalline material as the main component; it can be any known substrate. The crystal substrate can be an insulating substrate, a conductive substrate, or a semiconductor substrate. The crystal substrate can be a single-crystal substrate or a polycrystalline substrate. Examples of such crystal substrates include substrates containing crystalline material having a corundum structure as the main component. Furthermore, the term "main component" refers to the crystalline material comprising 50% or more of the composition in the substrate, preferably 70% or more, and more preferably 90% or more.

[0091] Examples of substrates containing crystalline materials with a corundum structure as the main component include sapphire substrates and alpha-type gallium oxide substrates.

[0092] In embodiments of the present invention, the crystal substrate is preferably a sapphire substrate. Examples of sapphire substrates include an m-plane sapphire substrate and an a-plane sapphire substrate. In the present invention, the sapphire substrate is preferably an m-plane sapphire substrate. Furthermore, the sapphire substrate may have an offset angle. The offset angle is not particularly limited, but is preferably 0° to 15°. Additionally, the thickness of the crystal substrate is not particularly limited, but is preferably 50 μm to 2000 μm, more preferably 200 μm to 800 μm. Furthermore, the area of ​​the crystal substrate is not particularly limited, but is preferably 15 cm². 2 The above, preferably 100cm 2above.

[0093] Furthermore, in one embodiment of the semiconductor device of the present invention, the crystalline substrate preferably includes, for example, a mask (also called an ELO mask) composed of the electrodes. The constituent material of the ELO mask is not particularly limited, but an electrode material is preferred. Additionally, the constituent material preferably has electrical conductivity and is used as both an ohmic electrode and a Schottky electrode. The electrode material can be a known metal. Preferably, at least one metal selected from Groups 4 to 11 of the periodic table is used. Examples of Group 4 metals include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of Group 5 metals include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of Group 6 metals include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of Group 7 metals include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals belonging to Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals belonging to Group 9 include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals belonging to Group 10 include nickel (Ni), palladium (Pd), and platinum (Pt). Examples of metals belonging to Group 11 include copper (Cu), silver (Ag), and gold (Au). The thickness of each of the aforementioned metal layers is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. The method for forming the electrode is not particularly limited and can be any known method. Specifically, examples of the forming method include dry methods and wet methods. Examples of dry methods include sputtering, vacuum evaporation, and CVD. Examples of wet methods include screen printing or molding.

[0094] Furthermore, in one embodiment of the present invention, the crystalline substrate preferably comprises an ELO mask, for example, composed of the dielectric film (e.g., a gate insulating film). In this case, the ELO mask typically includes a gate electrode. Examples of electrode materials for the gate electrode include the following. By covering the gate electrode with the ELO mask, a semiconductor device (especially a MOSFET) with a channel layer having higher crystal quality can be easily obtained. The constituent material of the ELO mask is not particularly limited and can be any known mask material. It can be an insulating material, a conductive material, or a semiconductor material. Furthermore, the constituent material can be amorphous, single-crystal, or polycrystalline. Examples of constituent materials for the ELO mask include oxides, nitrides, or carbides of Si, Ge, Ti, Zr, Hf, Ta, Sn, etc., carbon, diamond, metals, and mixtures thereof. More specifically, examples include Si-containing compounds with SiO2, SiN, or polycrystalline silicon as the main component, and metals with melting points higher than the crystal growth temperature of the oxide semiconductor film (e.g., noble metals such as platinum, gold, silver, palladium, rhodium, iridium, and ruthenium). Furthermore, the content of the constituent material in the ELO mask, by composition ratio, is preferably 50% or more, more preferably 70% or more, and most preferably 90% or more.

[0095] The method for forming the ELO mask can be a known method, such as photolithography, electron beam lithography, laser patterning, and subsequent etching (e.g., dry etching or wet etching), or other known patterning processing methods. Furthermore, the spacing within the shape of the pattern is not particularly limited; in embodiments of the present invention, it is preferably 100 μm or less, more preferably 0.5 μm to 50 μm, and most preferably 0.5 μm to 10 μm.

[0096] The following will use the accompanying drawings to illustrate an example of an embodiment of a crystal growth substrate (crystal substrate) preferred for use in this invention.

[0097] Figure 3 This refers to a type of protrusion formed by the ELO mask that is provided on the crystal growth surface of a crystal substrate preferably used in this invention. Figure 3 The crystal substrate containing the ELO mask is formed from a crystal substrate 1 and convex protrusions 2a on a crystal growth surface 1a. The protrusions 2a are striped relative to the crystal growth surface 1a and extend along the c-axis. The striped protrusions 2a are periodically arranged on the crystal growth surface 1a of the crystal substrate 1. Furthermore, the protrusions 2a are made of silicon-containing compounds such as SiO2 and can be formed using known methods such as photolithography. Alternatively, in another embodiment, a metal layer may be disposed as the ELO mask.

[0098] The width, height, and spacing of the protrusions are not particularly limited. In this invention, each of them is, for example, in the range of about 10 nm to about 1 mm, preferably about 10 nm to about 300 μm, and more preferably about 10 nm to about 10 μm.

[0099] In embodiments of the present invention, for example, such as Figure 15-a As shown, the crystalline substrate 110 may include a crystal substrate 1 and a crystalline layer 3 (e.g., a buffer layer including a stress relaxation layer, etc.) disposed on the crystal substrate 1. Furthermore, in an embodiment of the present invention, the buffer layer 3 is disposed on at least a portion of the surface of the crystal substrate 1. Additionally, the ELO mask 2 is disposed on at least a portion of the buffer layer 3. Alternatively, as another embodiment, the crystalline substrate may also have an ELO mask disposed on at least a portion of the crystal substrate and have a buffer layer epitaxially grown from the crystal substrate. The method for forming the buffer layer is not particularly limited and can be a known method. Examples of such methods include spraying, atomized CVD, HVPE, MBE, MOCVD, sputtering, etc. Hereinafter, a preferred method for forming the buffer layer by atomized CVD will be described in more detail.

[0100] Preferably, for example, it can be used Figure 4 The atomized CVD apparatus shown forms the buffer layer through the following steps: atomizing or dropletizing the raw material solution (atomization step), transporting the resulting atomized droplets to the substrate using a carrier gas (transportation step), and then subjecting the atomized droplets to a thermal reaction on a portion or all of the surface of the substrate (buffer layer formation step), thereby forming the buffer layer. Furthermore, in this invention, the crystal growth layer can also be formed using the same method.

[0101] (Atomization process)

[0102] The atomization process atomizes the raw material solution to obtain the atomized droplets. The atomization method for the raw material solution is not particularly limited as long as it can be atomized; any known method can be used. In the embodiments of the present invention, an ultrasonic atomization method is preferred. The atomized droplets obtained using ultrasound have an initial velocity of zero and float in the air, which is therefore preferable. Since it is not sprayed like a mist but is transported in space as a gas, there is no damage caused by collision energy, which is highly preferred. The droplet size of the atomized droplets is not particularly limited; it can be droplets of a few millimeters, preferably less than 50 μm, and more preferably 0.1 μm to 10 μm.

[0103] (Raw material solution)

[0104] The raw material solution is not particularly limited as long as it is a solution capable of being atomized and the buffer layer can be obtained by atomization CVD. Examples of the raw material solution include, for example, aqueous solutions of organometallic complexes (e.g., acetylacetone complexes) or halides (e.g., fluorides, chlorides, bromides, or iodides) of the atomizing metal. The atomizing metal is not particularly limited; examples include one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In this invention, the atomizing metal preferably contains at least gallium, indium, or aluminum, and more preferably at least gallium. The content of the atomizing metal in the raw material solution is not particularly limited as long as it does not hinder the purpose of this invention; preferably 0.001 mol% to 50 mol%, more preferably 0.01 mol% to 50 mol%.

[0105] Furthermore, the raw material solution preferably contains a dopant. By including a dopant in the raw material solution, the crystal structure is not damaged without ion implantation or similar procedures, and the conductivity of the buffer layer can be easily controlled. In this invention, the dopant is preferably tin, germanium, or silicon, more preferably tin or germanium, and most preferably tin. The concentration of the dopant is typically about 1 × 10⁻⁶. 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the concentration of the dopant can be, for example, about 1 × 10⁻⁶. 17 / cm 3 The following low concentrations can also be achieved at approximately 1×10 20 / cm 3 The above high concentrations contain dopants.

[0106] The solvent for the raw material solution is not particularly limited; it can be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixture of inorganic and organic solvents. In this invention, the solvent preferably contains water, more preferably water or a mixture of water and alcohol, and most preferably water. More specifically, examples of water include pure water, ultrapure water, tap water, well water, mineral water, mineralized water, hot spring water, spring water, fresh water, and seawater. In this invention, ultrapure water is preferred.

[0107] (Transportation process)

[0108] In the transport process, a carrier gas is used to transport the atomized droplets into the film-forming chamber. There are no particular limitations on the carrier gas as long as it does not hinder the purpose of the invention; preferred examples include inactive gases such as oxygen, ozone, nitrogen, or argon, or reducing gases such as hydrogen or synthesis gases. Furthermore, there can be one or more types of carrier gas, and a dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) can be used as a second carrier gas. Additionally, there can be more than one, or even two, supply points for the carrier gas. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 L / min to 20 L / min, more preferably 1 L / min to 10 L / min. When a dilution gas is present, the flow rate of the dilution gas is preferably 0.001 L / min to 2 L / min, more preferably 0.1 L / min to 1 L / min.

[0109] (Buffer layer formation process)

[0110] In the buffer layer formation process, the buffer layer is formed on the crystal substrate by subjecting the atomized droplets to a thermal reaction in a film-forming chamber. The thermal reaction can be performed using heat to cause the atomized droplets to react, and the reaction conditions are not particularly limited as long as they do not hinder the purpose of this invention. In this process, the thermal reaction is typically carried out at a temperature above the solvent's evaporation temperature, preferably below a temperature not too high (e.g., 1000°C), more preferably below 650°C, and most preferably between 400°C and 650°C. Furthermore, the thermal reaction can be carried out under any atmosphere, including vacuum, non-oxygen atmosphere, reducing gas atmosphere, and oxygen atmosphere, as long as it does not hinder the purpose of this invention. It can also be carried out under any conditions, including atmospheric pressure, pressurized atmosphere, and depressurized atmosphere; in this invention, atmospheric pressure is preferred. Furthermore, the thickness of the buffer layer can be set by adjusting the formation time.

[0111] After forming the buffer layer as described above, the crystal growth layer is formed by configuring a mask layer on the buffer layer using the above method. This can further reduce defects such as tilting in the crystal growth layer and make the film of better quality.

[0112] Furthermore, the buffer layer is not particularly limited, but in this invention, it is preferable to include a metal oxide as the main component. Examples of the metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In this invention, the metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably at least indium and / or gallium, and most preferably at least gallium. As one embodiment of the film formation method of this invention, the buffer layer contains a metal oxide as the main component, and the metal oxide contained in the buffer layer may contain gallium and aluminum in a smaller quantity than gallium. By using a buffer layer containing aluminum in a smaller quantity than gallium, not only can crystal growth be good, but good high-temperature growth can also be achieved. Furthermore, as one embodiment of the film formation method of this invention, the buffer layer may contain a superlattice structure. By using a buffer layer containing a superlattice structure, not only is good crystal growth easier to achieve, but warping during crystal growth is also easier to suppress. Furthermore, the term "main component" here refers to the total composition relative to the buffer layer in atomic ratio. The metal oxide preferably comprises 50% or more, more preferably 70% or more, and even more preferably 90% or more, and can also be 100%. The crystal structure of the crystalline oxide semiconductor film is not particularly limited; in this invention, a corundum structure is preferred. Additionally, regarding the crystal growth layer and the buffer layer, their respective main components can be the same or different, provided they do not hinder the purpose of this invention; in this invention, they are preferably the same.

[0113] In the embodiments of the present invention, a metal-containing raw material gas, an oxygen-containing raw material gas, a reactive gas, and a dopant-containing raw material gas as needed are supplied to the substrate on which the buffer layer may be provided, and film formation is performed under the flow of the reactive gas. In the present invention, the film formation is preferably performed on a heated substrate. The film formation temperature is not particularly limited as long as it does not hinder the purpose of the present invention, but is preferably below 900°C, more preferably below 700°C, and most preferably between 400°C and 700°C. In addition, the film formation can be performed under any atmosphere selected from vacuum, non-vacuum, reducing gas atmosphere, inactive gas atmosphere, and oxidizing gas atmosphere, as long as it does not hinder the purpose of the present invention. Furthermore, it can be performed under any conditions selected from atmospheric pressure, atmospheric pressure, pressurized atmosphere, and depressurized atmosphere. In the foregoing embodiments of the present invention, it is preferred to perform the film formation under atmospheric pressure or atmospheric pressure. Moreover, the film thickness can be set by adjusting the film formation time.

[0114] The crystal growth layer typically comprises a crystalline metal oxide as the main component. Examples of such crystalline metal oxides include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In this invention, the crystalline metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably at least indium and / or gallium, and most preferably crystalline gallium oxide or a mixture thereof. Furthermore, in the crystal growth layer of embodiments of this invention, "main component" refers to the total composition of the crystal growth layer in atomic proportions, preferably containing 50% or more of the crystalline metal oxide, more preferably 70% or more, further preferably 90% or more, and may also be 100%. In embodiments of this invention, a substrate containing a corundum structure is used as the substrate for film formation, thereby obtaining a crystal growth film having a corundum structure. The crystalline metal oxide can be a single crystal or a polycrystalline material; in embodiments of this invention, a single crystal is preferred. Furthermore, there is no particular limitation on the upper limit of the thickness of the crystal growth layer, but it is preferably, for example, 100 μm, and there is no particular limitation on the lower limit of the thickness of the crystal growth layer, but it is preferably, for example, 1 μm, more preferably 10 μm, and most preferably 20 μm. In this invention, the thickness of the crystal growth layer is preferably 3 μm to 100 μm, more preferably 10 μm to 100 μm, and most preferably 20 μm to 100 μm.

[0115] Hereinafter, preferred manufacturing methods of the semiconductor device of the present invention will be described in more detail with reference to the accompanying drawings.

[0116] As one embodiment of the semiconductor device manufacturing method of the present invention, such as Figure 1 As described in (a) to (c), a sapphire substrate is preferably used as the crystalline substrate. In embodiments of the present invention, a sapphire substrate with the m-plane or a-plane as the main surface is preferably used as the sapphire substrate. Furthermore, as one embodiment of the present invention, it is preferable to use the m-plane of the crystalline substrate as the crystal growth surface, and to form an ELO mask on the m-plane with the c-axis as the length direction. Figure 1 (a) represents sapphire substrate 1. For example... Figure 1 As shown in (b), an ELO mask 5 is formed on the crystal growth surface of the sapphire substrate 1. The ELO mask 5 is arranged with the c-axis as its length direction and has a striped pattern relative to the crystal growth surface. Figure 1 (b) A crystal growth substrate is formed to obtain a crystal growth layer. Figure 1The stacked structure (c) is an example of a crystal growth layer 8 formed on a sapphire substrate 1 having an ELO mask 5 serving as an electrode on its surface. The region near the interface in contact with the electrode is, for example, a dislocation-free region, thereby exhibiting excellent semiconductor properties. In one embodiment of the present invention, after the ELO mask 5 is used to form the crystal growth layer 8, it can serve as an electrode (e.g., an ohmic electrode) of a semiconductor device.

[0117] In addition, as another embodiment of the manufacturing method of the present invention, using Figures 15-a to 16-b The crystalline substrate 110 has a crystal substrate 1 and a crystalline layer 3 disposed on the crystal substrate. A first crystal growth layer 120 is grown on the crystal substrate 1, which has the crystalline layer 3 and a mask layer (ELO mask) 2 on its surface, to obtain... Figure 15-a The layered structure shown. Here, for example, an m-plane sapphire substrate is used as the crystal substrate 1, and α-Ga2O3 is used as the crystal layer 3 (buffer layer). Further, on the crystalline substrate 110 (the crystal growth plane, here on the buffer layer), mask layers 2, for example with the c-axis as the length direction, are arranged at certain intervals to form a first crystal growth layer 120. When the crystal is grown under the conditions described above, dislocations extend from the top of the crystalline substrate towards the m-axis direction, enabling... Figure 15-a The dislocations extending from the m-axis in the crystal bend towards the a-axis, causing them to converge. Since the crystal grows laterally on the mask layer 2, the dislocation density in the crystal growth region 120B is lower than that in the crystal growth region 120A. Next, the upper surface 120a of the first crystal growth layer 120 is flattened by grinding or the like. As a result, a portion of the crystal growth region 120A with its high dislocation density converging in the a-axis direction is removed. Then, as... Figure 15-b As shown, crystal growth continues on the flat upper surface 120a of the first crystal growth layer 120 to form a second crystal growth layer 130, thereby obtaining... Figure 15-b The structure is a stacked structure. The crystal growth region 120B of the first crystal growth layer 120 located on the mask layer 2 is a good crystal growth region with low dislocation density, including ELO growth. In addition, since the region with high dislocation density that converges in a certain direction is removed, a crystal film with a second crystal growth layer 130 having a lower dislocation density than the first crystal growth layer 120 can be obtained on the first crystal growth layer 120. The dislocation density of the crystal growth region 130B of the second crystal growth layer 130 located above the mask layer 2 can be lower than the dislocation density of the crystal growth region 120B of the first crystal growth layer 120 located on the mask layer 2.

[0118] After forming the desired crystal growth layer, for example, as Figure 16-aAs shown, the crystalline substrate 110 can be removed. As described above, the crystalline substrate can be a crystal substrate, or it can include a crystal substrate and a crystalline layer (or multiple layers) disposed on the crystal substrate. According to an embodiment of the manufacturing method of the present invention, at least the crystal substrate is removed. Furthermore, according to an embodiment, the crystal substrate and the crystalline layer disposed on the crystal substrate can also be removed. Further, depending on the material of the mask layer 2, if it is not necessary to include it in the completed semiconductor device, then... Figure 17-a As shown, it can remove not only crystalline substrates but also masks. Additionally, as... Figure 16-a As shown, by cutting the first crystal growth layer and the second crystal growth layer along, for example, an XVIb-XVIb line, multiple stacked structures comprising a semiconductor film and electrodes disposed on the semiconductor film, which are included in a semiconductor device, can be obtained from a crystalline film formed over a large area. Furthermore, to obtain multiple such stacked structures, a method of forming over a large area followed by longitudinal and transverse dicing can be used, or a method of forming a crystalline film of the desired area separately without dicing for separation can be used.

[0119] As one embodiment, an n+ type α-Ga2O3 layer can be crystal grown on a crystalline substrate 11 on which the mask layer 2 is disposed as described above, for example, as a first crystal growth layer 120. After removing the convergent dislocations on the surface of the first crystal growth layer 120 and flattening it, the dopant concentration is lower than when the first crystal growth layer 120 is formed, thereby allowing the n- type α-Ga2O3 layer to crystal grow to form a second crystal growth layer 130. For example, if the mask layer 2 containing the electrode material is used as an ohmic electrode, an ohmic electrode can be obtained. Figure 16-b The diagram shows a stacked structure comprising a semiconductor film containing an ohmic junction region and an ohmic electrode disposed on the ohmic junction region. The semiconductor film comprises an n-type α-Ga₂O₃ layer as a first semiconductor layer 13 and an n+ type α-Ga₂O₃ layer as a second semiconductor layer 12. Alternatively, a mask disposed on the second semiconductor layer 12 can be used as the ohmic electrode, and a Schottky electrode can be formed on the first semiconductor layer 13, for example, using a known electrode formation method. By forming the electrode in this way, the adhesion between the electrode and the semiconductor film can be improved, and a better electrode can be obtained. Figure 13 The semiconductor device 100 shown.

[0120] about Figure 13The semiconductor device 100 shown, for example in an SBD, includes: a semiconductor film 123 comprising a Schottky junction region 13B and an ohmic junction region 12B; a Schottky electrode 32 disposed on the Schottky junction region 13B of the semiconductor film 123; and an ohmic electrode 35 disposed on the ohmic junction region 12B. According to an embodiment of the semiconductor device of the present invention, a region in the semiconductor film 123 where the dislocation density of the Schottky junction region 13B is smaller than that of the ohmic junction region 12B and where the crystallinity is good can be defined as the Schottky junction region. Here, the Schottky junction region 13B refers, for example, to a region in the semiconductor film 123 within 100 nm of the interface between the semiconductor film 123 and the Schottky electrode 32. Similarly, the ohmic junction region 12B refers, for example, to a region in the semiconductor film 123 within 100 nm of the interface between the semiconductor film 123 and the ohmic electrode 35. In an embodiment of the present invention, the semiconductor film 123 preferably has a first semiconductor layer 13 and a second semiconductor layer 12, wherein the first semiconductor layer 13 forms a Schottky junction with the Schottky electrode 32, and the second semiconductor layer 12 forms an ohmic junction with the ohmic electrode 35. Furthermore, in an embodiment of the present invention, it is preferable that the dislocation density of the first semiconductor layer 13 is smaller than the dislocation density of the second semiconductor layer 12.

[0121] about Figure 14 The semiconductor device 200 shown, for example in a JBS, includes: a semiconductor film 123 comprising a Schottky junction region 13B and an ohmic junction region 12B; a Schottky electrode 32 disposed on the Schottky junction region 13B of the semiconductor film 123; and an ohmic electrode 35 disposed on the ohmic junction region 12B. For example, by the above-described semiconductor device manufacturing method, a semiconductor device is obtained... Figure 16-b or Figure 17-b After the stacked structure shown, a plurality of trenches 36 are formed in the Schottky junction region of the first semiconductor layer 13. As one embodiment of the JBS, a p-type semiconductor region 33 can be buried within the trenches 36. The trenches 36 can be formed, for example, by selectively etching the first semiconductor layer 13, or by etching using atomization CVD. Within the trenches, for example, atomization CVD can also be used to form the p-type semiconductor region. Alternatively, as another embodiment of the JBS, a dielectric layer can be formed within the trenches 36, and the semiconductor region can be buried within the dielectric layer. According to an embodiment of the semiconductor device manufacturing method of the present invention, a region with good crystallinity can be used as the Schottky junction region. Furthermore, according to this embodiment, by arranging the p-type semiconductor region buried in the plurality of trenches in the Schottky junction region, a semiconductor device with good semiconductor characteristics can be obtained.

[0122] As described above, in embodiments of the semiconductor device of the present invention, the ELO mask may include an electrode material. By using an ELO mask as described above, it is possible to easily obtain a higher quality semiconductor device (especially a SBD) having a drift layer and a Schottky interface, etc. Furthermore, as the electrode material, examples include metals or alloys of two or more of the aforementioned metals; metal oxide conductive films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof, etc. In the present invention, metals are preferred. As the metal, examples include at least one metal selected from Groups 4 to 10 of the periodic table. Examples of Group 4 metals include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of Group 5 metals include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals belonging to Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals belonging to Group 7 include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals belonging to Group 8 include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals belonging to Group 9 include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals belonging to Group 10 include nickel (Ni), palladium (Pd), and platinum (Pt). The method of forming the electrode is not particularly limited. It can be formed on the crystalline substrate using a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum evaporation, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into account compatibility with the aforementioned materials.

[0123] In another embodiment of the invention, the ELO mask preferably includes a gate electrode. By covering the gate electrode with the ELO mask, which serves as a gate insulating film, an excellent semiconductor device (especially a MOSFET) can be easily obtained.

[0124] The aforementioned stacked structure is particularly suitable for semiconductor devices that include at least electrodes and semiconductor layers, especially for power devices. Examples of such semiconductor devices include SBDs, MOSFETs, MIS (metal-insulator-semiconductor), HEMTs (high electron mobility transistors), TFTs (thin-film transistors), Schottky barrier diodes utilizing semiconductor-metal junctions, PN or PIN diodes combined with another P layer, and photodetectors / emitters.

[0125] In addition to the above-described aspects, the semiconductor device according to embodiments of the present invention is preferably used as a semiconductor device by being bonded to a lead frame, circuit board, or heat sink using common methods, and is particularly preferred as a power module, inverter, or converter. Furthermore, it is preferably used as a semiconductor system, for example, that utilizes a power supply device. A preferred example of the semiconductor device bonded to a lead frame, circuit board, or heat sink is shown in [illustration / description]. Figure 8 .exist Figure 8 In the semiconductor device, the two sides of the semiconductor element 500 are respectively bonded to a lead frame, a circuit board, or a heat dissipation board 502 by solder 501. This configuration allows for the formation of a semiconductor device with excellent heat dissipation. Furthermore, in this invention, it is preferable that the area around the solder or other bonding components is sealed with resin.

[0126] Regarding the power supply device, it can be manufactured by using known methods, such as connecting to a wiring pattern, thereby manufacturing a power supply device from a semiconductor device, or manufacturing a power supply device including a semiconductor device. Figure 5 In this system, multiple power supply devices 171, 172 and control circuit 173 are used to construct the power supply system 170. Regarding the power supply system, as... Figure 6 As shown, electronic circuitry 181 and power supply system 182 can be combined for use in system device 180. Furthermore, Figure 7 An example of a power circuit diagram showing a power supply device. Figure 7 The power supply circuit of the power supply device, which includes power circuitry and control circuitry, is shown. An inverter 192 (MOSFETs: composed of A to D converters) switches the DC voltage to AC at high frequency. A transformer 193 provides insulation and voltage transformation. After rectification by a rectifier MOSFET 194, the voltage is smoothed by a DCL 195 (smoothing coils L1 and L2) and a capacitor, resulting in the output DC voltage. A voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and the rectifier MOSFET 194 to obtain the desired output voltage.

[0127] In this invention, preferably, the semiconductor device is a power card; more preferably, it includes a cooler and an insulating component, and the cooler is disposed on both sides of the semiconductor layer at least via the insulating component; most preferably, a heat dissipation layer is disposed on both sides of the semiconductor layer, and the cooler is disposed on the outside of the heat dissipation layer at least via the insulating component. Figure 9 The power card is shown as one of the preferred embodiments of the present invention. Figure 9The power card is a double-sided cooled power card 201, comprising: a refrigerant pipe 202, a spacer 203, an insulating plate (insulating spacer) 208, a resin sealing portion 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal portion) 302b, a heat sink and electrodes 303, a metal heat transfer plate (protruding terminal portion) 303b, a solder layer 304, control electrode terminals 305, and bonding wires 308. The refrigerant pipe 202 has a plurality of flow paths 222 in its thickness direction cross-section, which are divided by a plurality of partition walls 221 spaced apart from each other and extending in the flow path direction. According to this preferred power card, stronger heat dissipation can be achieved, and higher reliability can be met.

[0128] Semiconductor chip 301a is bonded to the inner main surface of metal heat transfer plate 302b via solder layer 304. On the remaining main surface of semiconductor chip 301a, metal heat transfer plate (protruding terminal portion) 302b is bonded via solder layer 304, thereby connecting the anode and cathode electrode surfaces of flywheel diodes in a so-called anti-parallel configuration on the collector and emitter surfaces of the IGBT (Insulated Gate Bipolar Transistor). Materials for metal heat transfer plates (protruding terminal portions) 302b and 303b include, for example, Mo or W. Metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that absorbs the thickness difference of semiconductor chip 301a, thereby making the outer surfaces of metal heat transfer plates 302b and 303b planar.

[0129] The resin sealing portion 209, for example, is made of epoxy resin and is molded to cover the sides of the metal heat transfer plates 302b and 303b. The semiconductor chip 301a is molded by the resin sealing portion 209. However, the outer main surfaces of the metal heat transfer plates 302b and 303b, i.e., the surfaces in contact with heat, are completely exposed. The metal heat transfer plates (protruding terminal portions) 302b and 303b extend from the resin sealing portion 209 towards... Figure 9 The right side of the protrusion is related to the so-called control electrode terminal 305, which is a lead frame terminal. For example, the gate (control) electrode surface of the semiconductor chip 301a on which the IGBT is formed is connected to the control electrode terminal 305.

[0130] The insulating plate 208, serving as an insulating spacer, is made of, for example, an aluminum nitride film, but can also be other insulating films. The insulating plate 208 completely covers and adheres to the metal heat transfer plates 302b and 303b; however, the insulating plate 208 may only be in contact with the metal heat transfer plates 302b and 303b, or it may be coated with a good thermally conductive material such as silicone grease, or they may be bonded together by various methods. Alternatively, the insulating layer can be formed by ceramic thermal spraying, or the insulating plate 208 can be bonded to the metal heat transfer plates, or it can be bonded to or formed on the refrigerant pipes.

[0131] The refrigerant pipe 202 is manufactured by cutting a sheet of aluminum alloy formed by drawing or extrusion to the required length. The thickness-direction cross-section of the refrigerant pipe 202 has multiple flow paths 222, which are divided by multiple partition walls 221 spaced apart from each other and extending in the flow path direction. The spacer 203 can be a soft metal plate, such as a welded alloy, or it can be a film formed on the contact surface of the metal heat transfer plates 302b and 303b by coating. The surface of this soft spacer 203 is easily deformable, adapting to the minor irregularities or warping of the insulating plate 208 and the refrigerant pipe 202, thereby reducing thermal resistance. Furthermore, a known lubricating oil with good thermal conductivity can be coated on the surface of the spacer 203, or the spacer 203 can be omitted.

[0132] Example

[0133] 1. Fabrication of semiconductor devices

[0134] As a substrate for crystal growth, a crystalline matrix having an m-plane sapphire substrate and a buffer layer disposed on at least a portion of the m-plane sapphire substrate is used. An ELO mask extending along the c-axis direction on its surface is formed in a stripe pattern relative to the crystal growth surface. Furthermore, regarding the ELO mask, depending on the purpose of the semiconductor device, either an electrode material or an insulating material can be used. In this embodiment, an SiO2 film is used as an example of the mask material. Figure 15-a As shown, the crystalline substrate 110 has a crystal substrate 1 and a crystalline layer 3 disposed on the crystal substrate. The crystalline layer 3 (α-Ga2O3 film) disposed on the m-surface of the sapphire substrate is configured as a buffer layer. An ELO mask 5 with a striped pattern is formed on the crystal growth surface of the crystalline substrate. The length direction of the ELO mask 5 is the c-axis direction. Using the above-described crystal growth substrate, such as... Figure 15-a As shown, a first crystal growth layer 120 composed of α-Ga2O3 is formed by atomization CVD, thereby obtaining a stacked structure. After obtaining the stacked structure, electrodes and the like are formed using known methods, thereby obtaining a semiconductor device. The semiconductor device obtained in this way has excellent adhesion between the ELO mask and the crystal growth layer (semiconductor layer), and a high-quality crystalline region is formed at the interface between the semiconductor layer and the mask, thus resulting in excellent semiconductor properties.

[0135] 2. Evaluation

[0136] The semiconductor device obtained in section 1 above was observed using TEM. The results are as follows: Figure 10 As shown. From Figure 10 It can be seen that the ELO mask and the crystal growth layer (semiconductor layer) have no gaps, resulting in excellent adhesion. Furthermore, from... Figure 10It can also be seen that high-quality crystalline regions are formed on the ELO mask.

[0137] Industrial availability

[0138] The semiconductor device of the present invention can be used in all fields such as semiconductors (e.g., compound semiconductor electronic devices), electronic components and electrical equipment components, optical and electronic photographic devices, and industrial components, and is particularly useful for power devices.

[0139] Symbol Explanation

[0140] 1. Substrate (Sapphire substrate)

[0141] 1a The surface of the substrate (crystal growth surface)

[0142] 2. Mask layer (ELO mask)

[0143] 2a convex part

[0144] 2b concave part

[0145] 3. Crystalline layer (buffer layer)

[0146] 5 ELO Mask

[0147] 8. Crystal growth layer (semiconductor layer)

[0148] 11 base plate

[0149] 12 Second semiconductor layer

[0150] 12B Ohm junction region

[0151] 13 First semiconductor layer

[0152] 13B Schottky junction region

[0153] 14. Electrode (Grid Electrode)

[0154] 15. Dielectric film (gate insulating film)

[0155] 18. Semiconductor layer (channel layer)

[0156] 18a n-type semiconductor layer

[0157] 18b n+ type semiconductor layer

[0158] 19. Atomized CVD Unit

[0159] 20 Samples to be formed

[0160] 21 Sample Stage

[0161] 22a Carrier Gas Source

[0162] 22b Carrier gas (dilution) source

[0163] 23a Flow regulating valve

[0164] 23b Flow regulating valve

[0165] 24. Sources of Fog

[0166] 24a Raw material solution

[0167] 24b Fog

[0168] 25 containers

[0169] 25a Water

[0170] 26. Ultrasonic transducer

[0171] 27 Film-forming chamber

[0172] 28 Heaters

[0173] 32 Schottky electrode

[0174] 33 p-type semiconductor region

[0175] 35 Ohm Electrode

[0176] 36. Grooves

[0177] 50 Hydride Vapor Phase Epitaxy (HVPE) Apparatus

[0178] 51 Reaction Chamber

[0179] 52a heater

[0180] 52b heater

[0181] 53a Halogen-containing feed gas supply source

[0182] 53b Metal-containing raw material gas supply pipe

[0183] 54a Reactive gas supply source

[0184] 54b Reactive gas supply pipe

[0185] 55a Oxygen-containing feed gas supply source

[0186] 55b Oxygen-containing raw material gas supply pipe

[0187] 56. Substrate support

[0188] 57 Metal Source

[0189] 58 Protective Film

[0190] 59 Gas Exhaust Section

[0191] 100 Semiconductor Devices

[0192] 110 Crystalline matrix

[0193] 120 First crystal growth layer

[0194] 120A is a crystal growth region with high dislocation density that converges along the a-axis.

[0195] After removing the crystal growth region with high dislocation density that converges along the a-axis, 120A'

[0196] 120a Above the first crystal growth layer

[0197] 120B is the crystal growth region of the first crystal growth layer 120 located on mask layer 2.

[0198] 123 Semiconductor film

[0199] 130 Second crystal growth layer

[0200] 130B Second Crystal Growth Layer Crystal Growth Region

[0201] 170 Power System

[0202] 171 Power Supply Unit

[0203] 172 Power Supply Unit

[0204] 173 Control Circuit

[0205] 180 System Device

[0206] 181 Electronic Circuits

[0207] 182 Power System

[0208] 192 Inverter

[0209] 193 Transformer

[0210] 194 Rectifier MOSFET

[0211] 195 DCL

[0212] 196 PWM control circuit

[0213] 197 Voltage comparator

[0214] 200 Semiconductor Devices

[0215] 201 Double-sided cooling power card

[0216] 202 Refrigerant Pipe

[0217] 203 Spacer

[0218] 208 Insulating board (insulating spacer)

[0219] 209 Resin Sealing Part

[0220] 221 Partition wall

[0221] 222 flow path

[0222] 301a Semiconductor Chip

[0223] 302b Metal heat transfer plate (protruding terminal section)

[0224] 303 Heat sink and electrodes

[0225] 303b Metal heat transfer plate (protruding terminal section)

[0226] 304 weld layer

[0227] 305 Control Electrode Terminal

[0228] 308 joint line

[0229] 500 semiconductor components

[0230] 501 solder

[0231] 502 lead frame, circuit board or heat sink

Claims

1. A semiconductor device, comprising: The semiconductor film is an oxide semiconductor containing gallium and having a corundum structure, and the semiconductor film includes a Schottky junction region and an ohmic junction region; Schottky electrodes are disposed on the Schottky junction region; as well as Ohmic electrodes are disposed on the ohmic junction region. The semiconductor device is characterized in that the dislocation density in the Schottky junction region of the semiconductor film is smaller than the dislocation density in the Ohmic junction region of the semiconductor film. The ohmic electrode extends along the c-axis.

2. The semiconductor device according to claim 1, wherein, The semiconductor film includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer including the Schottky junction region and the second semiconductor layer including the Ohm junction region.

3. The semiconductor device according to claim 2, wherein, The second semiconductor layer is an n+ type semiconductor layer.

4. The semiconductor device according to claim 2 or 3, wherein, The first semiconductor layer is an n-type semiconductor layer.

5. The semiconductor device according to claim 2 or 3, wherein, The first semiconductor layer has at least one trench.

6. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor film includes laterally grown regions.

7. The semiconductor device according to any one of claims 1 to 3, wherein, The thickness of the semiconductor film is 1 μm or more.

8. The semiconductor device according to claim 2 or 3, wherein, The second semiconductor layer has a corundum structure.

9. The semiconductor device according to claim 2 or 3, wherein, The second semiconductor layer contains at least gallium.

10. The semiconductor device according to claim 2 or 3, wherein, The first semiconductor layer contains at least gallium.

11. The semiconductor device according to claim 2 or 3, wherein, The first semiconductor layer includes a p-type semiconductor region.

12. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor device is a power device.

13. A semiconductor device, comprising: The semiconductor film is an oxide semiconductor containing gallium and having a corundum structure, and the semiconductor film includes a channel layer and an n+ type semiconductor layer; Gate insulating film, and The gate electrode is disposed on the channel layer via the gate insulating film. The dislocation density of the channel layer is less than that of the n+ type semiconductor layer. The gate electrode or the gate insulating film extends along the c-axis direction.

14. The semiconductor device according to claim 13, wherein, The channel layer is configured along the m-axis or the a-axis.

15. A semiconductor system comprising a semiconductor device, characterized in that, The semiconductor device is the semiconductor device according to any one of claims 1 to 14.

16. A method for manufacturing a semiconductor device, comprising the steps of: placing a mask directly or via a crystal layer on a crystal substrate having a corundum structure with the c-axis direction of the crystal substrate as the length direction; and growing a semiconductor film on the crystal substrate having the mask, wherein the semiconductor film is an oxide semiconductor containing gallium and having a corundum structure.

17. A method for manufacturing a semiconductor device, comprising the following steps: A mask is disposed directly or via a crystal layer on a crystal substrate having a corundum structure with the c-axis direction of the crystal substrate as the length direction. A semiconductor film is grown on the crystal substrate on which the mask is disposed, the semiconductor film being an oxide semiconductor containing gallium and having a corundum structure; The mask is used as an electrode or a gate insulating layer.

18. The manufacturing method according to claim 17, wherein, The mask contains electrode material and is used as an electrode.

19. The manufacturing method according to claim 17, wherein, The mask contains a dielectric material and is used as a gate insulating layer.

20. The manufacturing method according to any one of claims 16 to 19, wherein, The process includes at least the removal of the crystal substrate.

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