A NAND flash memory dynamic write voltage method and device

Abstract

The present invention relates to the field of data storage technology, and in particular to a NAND flash memory dynamic write voltage method and device. The present invention discloses a NAND flash memory dynamic write voltage method and device, wherein the method comprises: constructing a cost function according to a high-order channel error rate, a low-order channel error rate and a minimum Hamming distance estimated by an LDPC code; taking the minimum function value of the cost function as an optimization target, taking the first programming voltage and the second programming voltage as independent variables, performing convex optimization calculation on the cost function, and outputting an optimal first programming voltage and an optimal second programming voltage, thereby solving the technical problem in the prior art that when a codeword is only stored in a high-order bit page or a low-order bit page, the overall bit error rate performance will be deteriorated if the existing write voltage method is continued to be used due to unequal high and low-order channel error rates, thereby improving the overall bit error rate performance of the NAND flash memory.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a method and device for dynamically writing a voltage to a NAND flash memory. Background Art

[0002] With the advent of the intelligent era, the storage of large-capacity data has become a new challenge. Flash-based solid-state drives, with their large capacity and low power consumption, have gradually replaced traditional storage media and become one of the mainstream storage devices, especially NAND flash memory.

[0003] NAND flash memory is a non-volatile storage device that consists of many blocks, each of which contains many pages. A block is composed of multiple word lines and bit lines, and the intersection of a word line and a bit line is a storage unit (cell). Each word line contains one or more pages of user data. All bit lines in a block are connected to a source line, so that when an erase operation is performed, all storage cells on the block will be erased. When writing data, you only need to apply a high voltage to the corresponding word line, and then adjust the bit line voltage at the corresponding position.

[0004] After writing data into NAND flash memory, the voltage distribution in the flash memory is approximately Gaussian distribution. The voltage of the flash memory cell after injecting electrons is called threshold voltage. Taking MLC NAND flash memory as an example, under Gray mapping, a flash memory cell can be configured with four different levels, namely V min , V1, V2, V max , they can represent the data symbols "11", "10", "00", and "01" respectively. Generally, the bit on the left of the symbol is called the most significant bit (MSB), and the bit on the right is called the least significant bit (LSB). We regard all the high bits on a page of flash memory as a high-bit page, and all the low bits as a low-bit page.

[0005] Before writing data to the MLC NAND flash memory cell, the entire block of data will be erased to make the voltage in the flash memory cell become the lowest voltage V min , and then write their own data to the flash memory cells. Therefore, V min It is called the erase level or the minimum write voltage, V max is the maximum write level, V1 and V2 are programming levels. In practical applications, the minimum write voltage and the maximum write voltage are fixed. By solving the minimum channel error rate, the optimal programming levels V1 and V2 are obtained for data writing.

[0006] However, in the above data writing scheme, when the codeword is stored only in the high-order bit page or the low-order bit page, since the high and low channel error rates are not equal, continuing to use the above data writing method will deteriorate the overall bit error rate performance. Summary of the invention

[0007] The present invention provides a NAND flash memory dynamic write voltage method and device, which are used to improve the overall bit error rate performance of the NAND flash memory.

[0008] The present invention provides a NAND flash memory dynamic writing voltage method, wherein the writing voltage includes a first programming voltage and a second programming voltage, and the method includes:

[0009] Construct a cost function based on the high channel error rate, the low channel error rate and the minimum Hamming distance estimated by the LDPC code;

[0010] Taking minimizing the function value of the cost function as the optimization goal, the first programming voltage and the second programming voltage as independent variables, performing convex optimization calculation on the cost function, and outputting the optimal first programming voltage and the optimal second programming voltage.

[0011] Optionally, the minimization of the function value of the cost function is taken as the optimization target, the first programming voltage and the second programming voltage are taken as independent variables, a convex optimization calculation is performed on the cost function, and an optimal first programming voltage and an optimal second programming voltage are output, including:

[0012] S0: Acquire a flash channel parameter, where the flash channel parameter includes a first value range of a first programming voltage and a second value range of a second programming voltage;

[0013] S1: Selecting a second programming voltage value from the second value range as an initial value of the second programming voltage;

[0014] S2: uniformly selecting M first programming voltage values ​​from the first value range, and combining the M first programming voltage values ​​with the initial value of the second programming voltage to form M groups of first write voltages, where M is a constant;

[0015] S3: Calculate the cost function values ​​corresponding to the first write voltages of the M groups, and determine the optimal first programming voltage corresponding to the minimum cost function value;

[0016] S4: uniformly selecting M second programming voltage values ​​from the second value range, and combining the M second programming voltage values ​​with the optimal first programming voltage to form M groups of second write voltages;

[0017] S5: Calculate the cost function values ​​corresponding to the M groups of the second write voltages, and determine the optimal second programming voltage corresponding to the minimum cost function value;

[0018] S6: replacing the initial value of the second programming voltage with the optimal second programming voltage;

[0019] S7: Iterate S2-S6 until the iteration termination condition is met, and output the optimal first programming voltage and the optimal second programming voltage.

[0020] Optionally, the flash channel parameters further include a maximum write voltage and a minimum write voltage, and S3 specifically includes:

[0021] Generate M groups of first threshold voltage distribution curve graphs according to the M groups of the first write voltages, the maximum write voltage and the minimum write voltage respectively;

[0022] Determine the intersection of the first curves of the M group according to the first threshold voltage distribution curve diagram of the M group;

[0023] Substituting the intersection points of the first curves of the M groups into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substituting the high and low channel error rates into the cost function to obtain the cost function values ​​of the M groups;

[0024] Determine a first curve intersection point corresponding to the minimum cost function value from the M groups of cost function values;

[0025] The corresponding optimal first programming voltage is determined according to the first curve intersection point corresponding to the minimum cost function value.

[0026] Optionally, the S5 specifically includes:

[0027] Generate M groups of second threshold voltage distribution curves according to the M groups of the second write voltages, the maximum write voltage and the minimum write voltage;

[0028] Determine the intersection of the second curves of the M groups according to the second threshold voltage distribution curve graph of the M groups;

[0029] Substituting the intersection points of the second curves of the M groups into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substituting the high and low channel error rates into the cost function to obtain the M groups of cost function values;

[0030] Determine a second curve intersection point corresponding to the minimum cost function value from the M groups of cost function values;

[0031] The corresponding optimal second programming voltage is determined according to the second curve intersection point corresponding to the minimum cost function value.

[0032] Optionally, the S7 specifically includes:

[0033] Iterate S2-S6 until the number of iterations reaches the iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage remain unchanged compared with the optimal first programming voltage and the second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

[0034] The present invention also provides a NAND flash memory dynamic write voltage device, the write voltage includes a first programming voltage and a second programming voltage, and the device includes:

[0035] A construction module, for constructing a cost function according to a high-order channel error rate, a low-order channel error rate, and a minimum Hamming distance estimated by an LDPC code;

[0036] The optimization module takes minimizing the function value of the cost function as the optimization target, takes the first programming voltage and the second programming voltage as independent variables, performs convex optimization calculation on the cost function, and outputs the optimal first programming voltage and the optimal second programming voltage.

[0037] Optionally, the optimization module includes

[0038] An acquisition module, used for acquiring a flash memory channel parameter, wherein the flash memory channel parameter includes a first numerical range of a first programming voltage and a second numerical range of a second programming voltage;

[0039] A first selection module, used for selecting a second programming voltage value from the second value range as an initial value of the second programming voltage;

[0040] A second selection module is used to uniformly select M first programming voltage values ​​from the first value range, and respectively combine the M first programming voltage values ​​with the initial value of the second programming voltage to form M groups of first write voltages, where M is a constant;

[0041] A first calculation module, used for calculating the cost function values ​​corresponding to the first write voltages of the M groups, and determining the optimal first programming voltage corresponding to the minimum cost function value;

[0042] A third selection module is used to uniformly select M second programming voltage values ​​from the second value range, and respectively combine the M second programming voltage values ​​with the optimal first programming voltage to form M groups of second write voltages;

[0043] A second calculation module, used for calculating the cost function values ​​corresponding to the M groups of the second write voltages, and determining the optimal second programming voltage corresponding to the minimum cost function value;

[0044] A replacement module, used for replacing the initial value of the second programming voltage with the optimal second programming voltage;

[0045] A loop module is used to trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module in sequence until the trigger termination condition is met, and output the optimal first programming voltage and the optimal second programming voltage.

[0046] Optionally, the flash memory channel parameter further includes a maximum write voltage and a minimum write voltage, and the first calculation module specifically includes:

[0047] A first generating module, used for generating M groups of first threshold voltage distribution curve graphs according to the M groups of the first write voltages, the maximum write voltage and the minimum write voltage;

[0048] A first determination module, configured to determine the intersection points of the M groups of first curves according to the M groups of the first threshold voltage distribution curve graphs;

[0049] A first substitution module, used for substituting the intersection points of the first curves of the M groups into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substituting the high and low channel error rates into the cost function to obtain the M groups of cost function values;

[0050] A second determination module, used to determine a first curve intersection point corresponding to the minimum cost function value from the M groups of cost function values;

[0051] The third determination module is used to determine the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

[0052] Optionally, the second calculation module specifically includes:

[0053] A second generating module, used to generate M groups of second threshold voltage distribution curve graphs according to the M groups of the second write voltages, the maximum write voltage and the minimum write voltage;

[0054] A fourth determination module, configured to determine the intersection points of the M groups of second curves according to the M groups of second threshold voltage distribution curve graphs;

[0055] A second substitution module is used to substitute the M groups of intersection points of the second curve into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substitute the high and low channel error rates into the cost function to obtain the M groups of cost function values;

[0056] A fifth determination module, configured to determine a second curve intersection point corresponding to the minimum cost function value from the M groups of cost function values;

[0057] The sixth determination module is used to determine the corresponding optimal second programming voltage according to the intersection point of the second curve corresponding to the minimum cost function value.

[0058] Optionally, the loop module is specifically used to trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module in sequence until the number of iterations reaches an iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage remain unchanged compared with the optimal first programming voltage and the second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

[0059] It can be seen from the above technical solutions that the present invention has the following advantages:

[0060] The present embodiment provides a NAND flash memory dynamic write voltage method, which constructs a cost function according to a high-order channel error rate, a low-order channel error rate, and a minimum Hamming distance estimated by an LDPC code, taking into account the role of the LDPC code in data error correction, and taking into account the different effects of the high-order and low-order channel error rates on the bit error rate, and using the cost function to evaluate the high-order channel error rate and the low-order channel error rate corresponding to different first programming voltages and second programming voltages, how much cost will be caused to the bit error rate, thereby finding the first programming voltage and the second programming voltage corresponding to the minimum cost, and taking the minimum function value of the cost function as the optimization target, the first programming voltage and the second programming voltage as independent variables, and performing convex optimization calculation on the cost function. Since the constructed cost function is a concave function, the optimal first programming voltage and the optimal second programming voltage can be obtained more quickly, solving the technical problem that when the codeword is only stored in a high-order bit page or a low-order bit page, the overall bit error rate performance is deteriorated by using the existing write voltage method due to the unequal high and low-order channel error rates, thereby improving the overall bit error rate performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0062] Figure 1 A flow chart of a NAND flash memory dynamic write voltage method provided in Embodiment 1 of the present invention;

[0063] Figure 2 It is a schematic diagram of the structure of an existing NAND flash memory;

[0064] Figure 3 The basic structure diagram of the existing flash memory unit is shown below;

[0065] Figure 4 is a schematic diagram of the threshold voltage distribution curve;

[0066] Figure 5 A schematic diagram of interference between adjacent cells in an odd-even bit line structure;

[0067] Figure 6 It is a schematic diagram of an existing NAND flash memory channel model;

[0068] Figure 7 is a schematic diagram of the threshold voltage distribution curve;

[0069] Figure 8 is a schematic diagram of a threshold voltage distribution curve and a reference level;

[0070] Fig. 9 A flow chart of a NAND flash memory dynamic write voltage method provided in Embodiment 2 of the present invention;

[0071] Fig.10 A simulation result diagram provided by the present invention;

[0072] Fig.11 A schematic diagram of a NAND flash memory dynamic write voltage device provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0073] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the structure of an existing NAND flash memory. NAND flash memory is composed of many blocks, and each block of data contains many pages. Figure 2 As shown in the figure, a block in NAND flash memory is composed of multiple word lines and bit lines. The intersection of a word line and a bit line is a storage unit (cell). Each word line contains one or more pages of user data. In the current flash memory design, the length of these pages ranges from 512 bytes to 8K bytes. Each bit line usually contains 16 to 64 storage cells. All bit lines in the block are connected to a source line, so when an erase operation is performed, all storage cells on the block will be erased. When writing data, you only need to add a high voltage to the corresponding word line, and then adjust the bit line voltage at the corresponding position, so the programming operation unit is a page. Each block is also equipped with a page buffer area to facilitate writing and reading data.

[0074] According to the structure of the bit line, NAND flash memory can be divided into two structures: even / odd bit-line structure and all-bit-line structure. When the flash memory is an even / odd bit-line structure, the data written to it will be written to the even cell data first and then the odd cell data. All bit lines are written at the same time. Even bit lines constitute even pages, odd bit lines constitute odd pages, and there is no such distinction in the all-bit-line structure. Since even and odd pages share page buffers and peripheral circuits, the even / odd bit-line structure requires less hardware than the all-bit-line structure, and the all-bit-line structure causes less inter-cell interference than the even / odd bit-line structure.

[0075] See also Figure 3 , Figure 3 The basic structure diagram of the existing flash memory unit is shown below. The flash memory unit is a floating gate (FG) added to the original triode transistor, mainly to keep the electrons in it. The flash memory unit also includes several other parts: control gate (CG), source (S) and drain (Drain). According to the number of bits that can be represented by the voltage in the flash memory unit, it can be mainly divided into: single-level cell (SLC), multi-level cell (MLC) and triple-level cell (TLC). In SLC NAND flash memory, each cell can store 1 bit of data, while in MLC NAND flash memory, each cell can store 2 bits of data.

[0076] Before writing data to NAND flash memory, the entire block of data needs to be erased. The erase operation only requires applying a high voltage to the matrix layer to allow the electrons in the floating gate to flow into the matrix layer. When writing data, a high voltage needs to be applied to the control gate to transfer electrons from the matrix layer to the floating gate. After the data is written to the NAND flash memory cell, the voltage distribution in the cell is approximately Gaussian. The voltage presented by the flash memory cell after the electrons are injected is called the threshold voltage. Taking MLC NAND flash memory as an example, under Gray mapping, a flash memory cell can be configured with four different levels, namely V min , V1, V2, V max , they can represent the data symbols "11", "10", "00", and "01" respectively. Generally, the bit on the left of the symbol is called the most significant bit (MSB), and the bit on the right is called the less significant bit (LSB). We regard all the high bits on a page of flash memory as a high bit page, and all the low bits as a low bit page.

[0077] Before writing data to the MLC flash memory cell, the entire block of data will be erased to make the voltage in the cell become the lowest voltage V min Then adjust V1, V2, V max The voltage value of the flash memory is used to write the data to the flash memory cell. min Also called the erase level (or minimum write voltage), V1, V2, V max It is called programming level (V max Also called the maximum write voltage). Assume that V min =1.4, V max =3.93, V obtained by MLC NAND flash memory cell min , V1, V2, V max The distribution curve of the threshold voltage can be shown as Figure 4 As shown, Figure 4 There are four probability density curves in the graph, which are p s11 (the curve where the first peak is located), p s10 (the curve where the second peak is located), p s00 (the curve where the third peak is located), p s01 (the curve where the fourth peak is located), corresponding to V min , V1, V2, V max .

[0078] Flash memory cells will experience threshold voltage fluctuations due to the number of data erases, erase time, changes in the number of electrons in the cell, etc., that is, various types of noise will be generated, which will affect the error performance of the flash memory cell. Noise types include programming noise, random telegraph noise, data retention noise, and inter-cell interference. The details are as follows:

[0079] (1) Programming noise

[0080] The erase level and programming level are subject to different noises during programming, which is mainly reflected in the different variances of programming noise. The distribution of programming noise can be expressed by Gaussian distribution:

[0081]

[0082] Among them, i∈{11,10,00,01}, respectively represents the erase state and 3 programming states in MLC flash memory, i=11 represents the erase state, and the others represent other programming levels. In actual data writing, the voltage in the flash memory cell reaches the programming voltage by using an incremental step pulse program. The principle of this algorithm is to add a certain number of electrons to the cell each time, and then determine whether the voltage in the cell reaches the desired threshold voltage, and iterate in this way until the voltage value in the cell is greater than or equal to the threshold voltage. However, doing so will prevent the threshold voltage from reaching the accurate voltage value, and will generate a uniformly distributed noise, the noise expression is:

[0083]

[0084] Where vpp is the voltage that increases each time a step pulse is used. The noise of the erased state is not affected by this interference, while the programming noise distribution of the programmed state needs to convolve this uniform distribution and the above-mentioned Gaussian distribution. Therefore, the programming noise expression of the programmed state is as follows:

[0085]

[0086] in Corresponding to programming voltages V1, V2, V max .

[0087] (2) Random telegraph noise

[0088] Random telegraph noise is a non-fixed noise component that is related to the number of times the flash memory is erased. As the number of erases increases, the threshold voltage in the cell will fluctuate. This fluctuation in threshold voltage is called random telegraph noise. The probability density distribution of random telegraph noise can be expressed by a Gaussian function:

[0089]

[0090] where σ t is the variance, which is approximately proportional to the number of erasures.

[0091] (3) Data retention noise

[0092] Data retention noise is also a non-fixed noise component that is related to the erase time of the flash memory and the data retention time. The probability density distribution of data retention noise can be expressed by Gaussian distribution:

[0093]

[0094] in, and are the mean and variance of the Gaussian distribution, both of which have a power law relationship with the number of erasures and a logarithmic relationship with the data retention time. They can be expressed as:

[0095]

[0096] Where PE (program and erase) is the number of times the flash memory block is erased and written, T is the data retention time of the flash memory, x0 = 1.4 is the write voltage in the erase state, V s is the voltage value written to the flash memory cell. t , B t , α1, α0 are constants.

[0097] (4) Inter-unit interference

[0098] In flash memory, the change of the threshold voltage of a cell will affect the threshold voltage of the adjacent cell, which is inter-cell interference. With the development of manufacturing technology, the size of the chip is getting smaller and smaller, and the inter-cell interference is getting more and more serious, which has the greatest impact on the reliability of the data in NAND flash memory. Inter-cell interference can be expressed as:

[0099]

[0100] Where, ΔV t (k) Refers to the threshold voltage change value caused by the interference cell being programmed to the kth state, and γ refers to the coupling coefficient. Inter-cell interference is also related to the structure of the NAND flash memory bit line. From the above content, it can be seen that the word line structure can be divided into an odd-even bit line structure and an all-bit line structure. In the odd-even bit line structure, for the same word line, the cells on the even bit line are programmed first, and the cells on the odd bit line are programmed later. Therefore, the flash memory cell on the even bit line will be interfered by 5 adjacent flash memory cells, and the cell on the odd bit line will be interfered by 3 adjacent flash memory cells, such as Figure 5 As shown. In the full bit line structure, all flash memory cells on the same word line are programmed at the same time, so one cell in the full bit line structure is affected by three adjacent cells. It can be seen that the full bit line structure causes less inter-cell interference than the odd-even bit line structure.

[0101] According to the above analysis, after the flash memory cell writes data, the threshold voltage obtained inside it will be affected by various types of noise, thereby affecting the error performance of the flash memory cell. In practical applications, the data will be encoded into codewords before being written into the flash memory cell. Later, when you want to read out these data, you need to use decoding to restore these data from the codewords. The bit error rate is obtained based on the data error rate after decoding to determine the error performance of the flash memory cell. In order to reduce the bit error rate as much as possible, in the prior art, the write voltage is designed by establishing a minimum channel error rate. The channel error rate refers to the error rate before the codeword is decoded, and the bit error rate refers to the bit error rate obtained after the codeword is decoded.

[0102] The existing NAND flash channel model is as follows Figure 6 As shown in the figure, after being erased and programmed, the flash memory cell is affected by random telegraph noise, inter-cell interference, and data retention noise. After being affected by inter-cell interference, the post-compensation technology is used to offset the impact of inter-cell interference and output the final threshold voltage distribution. In practical applications, when there is no noise at all, since there are only four types of written voltages (minimum write voltage, maximum write voltage, programming voltage, programming voltage), the threshold voltage distribution at this time is an equal probability distribution with only four values ​​(the uniform distribution caused by the incremental step pulse program is also regarded as a kind of noise). Subsequently, it is affected by various noises, that is, by convolving the above-mentioned pre-constructed equal probability distribution with various noises, the final threshold voltage distribution is obtained. This distribution is reflected in four probability density function curves, and its function variables are expressed as Corresponding to the write voltage V min , V1, V2, V max , and then the intersection points R1, R2 and R3 of the adjacent curves are calculated by formula (1.8), specifically R1 is the minimum write voltage V min R2 is the intersection of the probability density curve of the first programming voltage V1 and the probability density curve of the second programming voltage V2, and R3 is the intersection of the probability density curve of the second programming voltage and the maximum write voltage V max The intersection point of the probability density curve.

[0103]

[0104] After that, a hard decision is made based on the obtained R1, R2 and R3, and the total channel error rate P at this time is calculated by formula (1.9): e .

[0105]

[0106] Assume that the parameter σ of the threshold voltage distribution in the erased state e and σp are 0.35 and 0.05 respectively, the incremental programming step voltage vpp is 0.3, the judgment voltages are 2.38, 3.0, and 3.93 respectively, the number of PE cycles is 6000, and the retention time T is 40000 hours. For random telegraph noise, let σ t Equal to 0.00025 (PE) 0.62 For inter-unit interference, set γ xy , γ y They are 0.006s and 0.08s respectively, where s refers to the coupling strength factor between cells, which is set to 0.75, and a full bit line structure is used. For data retention noise, set the parameter A t =0.000055, B t =0.000235, α1=0.62, α0=0.32, the threshold voltage distribution can be obtained as follows Figure 7 As shown in the figure, the distribution of the threshold voltage level and the reference voltage level of the flash memory is as follows Figure 8 shown. Figure 7 There are four probability density curves in the equation, from left to right, they are Corresponding to V min , V1, V2, V max .

[0107] In practical applications, the minimum write voltage V min and the maximum write voltage V max is fixed, therefore, the prior art is to minimize the current channel error rate by finding V1 and V2, which can be expressed as:

[0108]

[0109] The existing technology uses the gradient descent method to obtain the V1 to be found * and V2 * When the parameter changes greatly, for example, when PE changes from 5000 to 10000, the V1 with the lowest channel error rate can be calculated. * and V2 * , to achieve dynamic design of write voltage.

[0110] The current data storage basically uses error correction code technology to obtain further data protection capabilities. The main process is to add some redundancy to the information sequence. The information sequence and redundancy together form a codeword. When the information sequence is to be restored, it can be obtained by decoding the codeword. However, for the existing write voltage design scheme with the minimum channel error rate, when the codeword is stored in the flash memory unit in the order of high bit-low bit-high bit..., a better storage effect can be achieved. However, when the codeword is only stored in the high bit page or the low bit page, since the high and low channel error rates are not equal, continuing to use this scheme will cause the barrel effect, making the overall bit error rate performance worse.

[0111] In view of this, an embodiment of the present invention provides a NAND flash memory dynamic write voltage method and device, which are used to improve the overall bit error rate performance of the NAND flash memory.

[0112] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0113] See also Figure 1 , Figure 1 A flow chart of a NAND flash memory dynamic write voltage method provided in the first embodiment of the present invention, wherein the write voltage includes a first programming voltage V1 and a second programming voltage V2, and the specific method includes:

[0114] Step 101, constructing a cost function according to the high channel error rate, the low channel error rate and the minimum Hamming distance estimated by the LDPC code;

[0115] It should be noted that, because the channel error rates of high-order bits and low-order bits on MLC-type NAND flash memory have different effects on the total bit error rate of the flash memory unit, and when storing data, error correction codes are used to correct errors to reduce the bit error rate. Due to the involvement of error correction codes, the bit error rate is generally always lower than the channel error rate. Therefore, considering the impact of error correction codes, this embodiment constructs a cost function based on the error correction code. This cost function is used to evaluate the impact of the bit error rate caused by the channel error rates of high and low-order bits corresponding to different first programming voltages and second programming voltages. Then, the first programming voltage and the second programming voltage that minimize the cost function value (i.e., the smallest impact) are found as the optimal write voltage. The error correction code involved in this embodiment is an LDPC code.

[0116] The calculation formulas for the high channel error rate and the low channel error rate are shown in formula (2.1).

[0117]

[0118] Among them, ω msb is the high channel error rate, ω lsb is the low channel error rate. R1 is the minimum write voltage V min R2 is the intersection of the probability density curve of the first programming voltage V1 and the probability density curve of the second programming voltage V2, and R3 is the intersection of the probability density curve of the second programming voltage and the maximum write voltage V max The intersection point of the probability density curve. The minimum write voltage V min The probability density curve of the first programming voltage V1, the probability density curve of the second programming voltage V2, the maximum write voltage V max The probability density curve of .

[0119] It is understandable that the probability density curve The construction method of can refer to the prior art, and the other parameters required in the process of constructing the curve can be set by referring to the relevant contents in the aforementioned prior art. The cost function provided in this embodiment is applicable to probability density curves constructed with various parameters.

[0120] The cost function constructed based on the high channel error rate, low channel error rate and the minimum Hamming distance estimated by the LDPC code is as follows:

[0121]

[0122] Where d is the minimum Hamming distance of LDPC code estimation.

[0123] Step 102 , taking the minimum function value of the cost function as the optimization target, the first programming voltage and the second programming voltage as independent variables, performing convex optimization calculation on the cost function, and outputting the optimal first programming voltage and the optimal second programming voltage.

[0124] It should be noted that after multiple tests and verifications, it is known that the cost function constructed in this embodiment is a concave function, and a convex optimization calculation can be performed according to the parameters of the first programming voltage and the second programming voltage, so as to quickly find the optimal first programming voltage and the optimal second programming voltage. The convex optimization formula is as follows:

[0125]

[0126] Among them, V1 * ,V2 *They are the optimal first programming voltage and the optimal second programming voltage respectively.

[0127] The present embodiment provides a NAND flash memory dynamic write voltage method, which constructs a cost function according to a high-order channel error rate, a low-order channel error rate, and a minimum Hamming distance estimated by an LDPC code, taking into account the role of the LDPC code in data error correction, and taking into account the different effects of the high-order and low-order channel error rates on the bit error rate, and using the cost function to evaluate the high-order channel error rate and the low-order channel error rate corresponding to different first programming voltages and second programming voltages, how much cost will be caused to the bit error rate, thereby finding the first programming voltage and the second programming voltage corresponding to the minimum cost, and taking the minimum function value of the cost function as the optimization target, the first programming voltage and the second programming voltage as independent variables, and performing convex optimization calculation on the cost function. Since the constructed cost function is a concave function, the optimal first programming voltage and the optimal second programming voltage can be obtained more quickly, solving the technical problem that when the codeword is only stored in a high-order bit page or a low-order bit page, the overall bit error rate performance is deteriorated by using the existing write voltage method due to the unequal high and low-order channel error rates, thereby improving the overall bit error rate performance.

[0128] See also Fig. 9 , Fig. 9 A schematic flow chart of a NAND flash memory dynamic write voltage method provided in the second embodiment of the present invention, the specific method includes:

[0129] 201. Construct a cost function according to the high channel error rate, the low channel error rate and the minimum Hamming distance estimated by the LDPC code.

[0130] It should be noted that step 201 may refer to step 101 and will not be described in detail here.

[0131] 202. Obtain flash channel parameters, where the flash channel parameters include a first value range of a first programming voltage, a second value range of a second programming voltage, a maximum write voltage, and a minimum write voltage.

[0132] It should be noted that the flash memory channel parameters refer to the parameters required to construct the threshold voltage distribution. In addition to the first numerical range of the first programming voltage, the second numerical range of the second programming voltage, the maximum write voltage, and the minimum write voltage, the threshold distribution parameter σ in the erased state is also included. e and σ p , incremental programming step voltage vpp, number of cycles PE, retention time T, parameter σ used for random electric wave noise t , the parameter γ used for inter-unit interference xy , γ y , coupling strength factor s, parameter A used for data hold noise t , Bt , α1, α0, etc. The specific values ​​of these parameters can be pre-set according to different types of flash memory cells. The maximum write voltage and the minimum write voltage are both preset fixed values.

[0133] As an example, let the parameter σ of the threshold voltage distribution in the erased state be e and σ p are 0.35 and 0.05 respectively, the incremental programming step voltage vpp is 0.3; the minimum write voltage V min and the maximum write voltage V max are 1.4 and 3.93 respectively. The first value range of the first programming voltage V1 is [2, 2.6], and the second value range of the second programming voltage V2 is set to (2.6, 3.3]. The experiment is simulated at different PE cycle times, and the retention time T is 0. For random telegraph noise, set σ t Equal to 0.00025 (PE) 0.62 For inter-unit interference, set γ xy , γ y They are 0.006s and 0.08s respectively, where s refers to the coupling strength factor between cells, which is set to 0.75. The flash memory cell adopts a full bit line structure. For data retention noise, set the parameter A t =0.000055, B t =0.000235, α1=0.62, α0=0.32.

[0134] 203. Select a second programming voltage value from the second value range as an initial value of the second programming voltage.

[0135] It should be noted that, an arbitrary value is selected from the second numerical range as the initial value of the second programming voltage. As an example, the initial value of the second programming voltage is 3.3.

[0136] 204. Evenly select M first programming voltage values ​​from the first value range, and combine the M first programming voltage values ​​with the initial value of the second programming voltage to form M groups of first write voltages, where M is a constant.

[0137] It should be noted that, as an example, M first programming voltage values ​​can be uniformly selected from the first value range [2, 2.6], where M can be determined according to actual needs.

[0138] The M first programming voltage values ​​are respectively combined with the second programming voltage initial value to form M groups of first write voltages, that is, the first write voltage includes the first programming voltage and the second programming voltage initial value. Since there are M first programming voltages, M groups of first write voltages can be formed.

[0139] 205. Calculate the cost function values ​​corresponding to the M groups of first write voltages, and determine the optimal first programming voltage corresponding to the minimum cost function value.

[0140] It should be noted that step 205 specifically includes the following sub-steps:

[0141] S21: Generate M groups of first threshold voltage distribution curves according to the M groups of first write voltages, the maximum write voltage and the minimum write voltage.

[0142] It should be noted that when calculating the minimum value of the cost function, the probability density curve of each voltage is used. Therefore, after obtaining M groups of first write voltages, a first threshold voltage distribution curve is generated based on each group of first write voltages, the maximum write voltage, and the minimum write voltage. Since there are M groups of first write voltages, M groups of first threshold voltage distribution curves can be generated accordingly.

[0143] After determining the values ​​of the first programming voltage, the second programming voltage, the maximum write voltage, and the minimum write voltage, the corresponding Figure 8 The threshold voltage distribution curve shown in the figure can be generated by referring to the prior art.

[0144] S22: determining the intersection points of the M groups of first curves according to the M groups of first threshold voltage distribution curves;

[0145] It should be noted that each threshold voltage distribution curve diagram is distributed with a minimum write voltage curve, a first programming voltage curve, a second programming voltage curve, and a maximum write voltage curve. Based on this, the intersection points of adjacent curves, namely R1, R2 and R3, can be determined in the threshold distribution curve diagram.

[0146] Since there are M groups of threshold voltage distribution curves, the M groups of first curve intersection points can be correspondingly confirmed.

[0147] S23: Substitute the M groups of first curve intersection points into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substitute the high and low channel error rates into the cost function to obtain the M groups of cost function values.

[0148] S24: Determine a first curve intersection point corresponding to a minimum cost function value from the M groups of cost function values.

[0149] S25: Determine the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

[0150] It should be noted that the obtained M groups of R1, R2 and R3 values ​​are respectively substituted into the high and low channel error rate calculation formula (2.1) to obtain the high channel error rate and the low channel error rate, and the obtained high channel error rate and the low channel error rate are substituted into the cost function formula (2.2) to obtain M groups of cost function values. From these M groups of cost function values, the intersection point corresponding to the minimum cost function value can be found, and the corresponding first write voltage can be determined based on this group of intersection points. The first write voltage obtained at this time is the initial value of the optimal first programming voltage and the second programming voltage. Therefore, the optimal first programming voltage can be determined.

[0151] 206. Evenly select M second programming voltage values ​​from the second value range, and combine the M second programming voltage values ​​with the optimal first programming voltage to form M groups of second write voltages.

[0152] It should be noted that the second write voltage includes the second programming voltage and the optimal first programming voltage. Since there are M second programming voltages, there are M groups of corresponding second write voltages.

[0153] 207 . Calculate the cost function values ​​corresponding to the M groups of second write voltages, and determine the optimal second programming voltage corresponding to the minimum cost function value.

[0154] It should be noted that the principle of determining the optimal second programming voltage is similar to the principle of determining the optimal first programming voltage, and reference may be made to step 205. Step 207 specifically includes the following sub-steps:

[0155] S31: generating M groups of second threshold voltage distribution curves according to the M groups of second write voltages, the maximum write voltage and the minimum write voltage;

[0156] A corresponding second threshold voltage distribution curve graph may be generated according to the second write voltage, the maximum write voltage, and the minimum write voltage. Since there are M groups of second write voltages, M groups of second threshold voltage distribution curve graphs may be generated accordingly.

[0157] S32: determining the intersection points of the M groups of second curves according to the M groups of second threshold voltage distribution curves;

[0158] Each threshold voltage distribution curve diagram includes a minimum write voltage curve, a first programming voltage curve, a second programming voltage curve, and a maximum write voltage curve. Based on this, the intersection points of adjacent curves, namely R1, R2, and R3, can be determined in the threshold distribution curve diagram.

[0159] S33: Substitute the intersection points of the M groups of second curves into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substitute the high and low channel error rates into the cost function to obtain the M groups of cost function values;

[0160] S34: determining a second curve intersection point corresponding to a minimum cost function value from the M groups of cost function values;

[0161] S35: Determine the corresponding optimal second programming voltage according to the second curve intersection point corresponding to the minimum cost function value.

[0162] It should be noted that the obtained M groups of R1, R2 and R3 values ​​are respectively substituted into the high and low channel error rate calculation formula (2.1) to obtain the high channel error rate and the low channel error rate, and the obtained high channel error rate and the low channel error rate are substituted into the cost function formula (2.2) to obtain M groups of cost function values. From these M groups of cost function values, the intersection point corresponding to the minimum cost function value is found, and the corresponding second write voltage can be determined based on this group of intersection points. The second write voltage obtained at this time is the optimal first programming voltage and the optimal second programming voltage. Therefore, the optimal second programming voltage can be determined.

[0163] 208. Replace the initial value of the second programming voltage with the optimal second programming voltage.

[0164] It should be noted that in the next iteration, the optimal second programming voltage will replace the initial value of the second programming voltage. Step 203 uses the optimal second programming voltage and M first programming voltage values ​​to form M groups. The first write voltage obtained in S25 of step 205 is the optimal first programming voltage and the optimal second programming voltage.

[0165] 209. Iterate steps 203-208 until an iteration termination condition is met, and output an optimal first programming voltage and an optimal second programming voltage.

[0166] It should be noted that steps 203-208 are iterated until the number of iterations reaches the iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage remain unchanged compared with the optimal first programming voltage and the optimal second programming voltage obtained in the previous iteration, and the optimal first programming voltage and the optimal second programming voltage are output.

[0167] In order to further illustrate the technical effect achieved by this embodiment, the following will be analyzed and explained based on the data obtained from the simulation test.

[0168] See also Fig.10 , Fig.10 The bit error rate performance simulation results provided by the embodiments of the present invention.

[0169] This experimental simulation was carried out under the Window 10 operating system, and the bit error rate simulation experiment was carried out using Matlab software. The original model LDPC code with a code rate of 0.89 was selected for the experiment. The simulation result diagram can be referred to Fig.10 , the specific parameters of the simulation are set as follows:

[0170] Assume that the parameter σ of the threshold voltage distribution in the erased state e and σ p are 0.35 and 0.05 respectively, the incremental programming step voltage vpp is 0.3; the minimum write voltage V min and the maximum write voltage V max are 1.4 and 3.93 respectively. The first value range of the first programming voltage V1 is [2, 2.6], and the second value range of the second programming voltage V2 is set to (2.6, 3.3]. The experiment is simulated at different PE cycle times, and the retention time T is 0. For random telegraph noise, set σ t Equal to 0.00025 (PE) 0.62 For inter-unit interference, set γ xy , γ y They are 0.006s and 0.08s respectively, where s refers to the coupling strength factor between cells, which is set to 0.75, and a full bit line structure is used. For data retention noise, set the parameter A t =0.000055, B t =0.000235, α1=0.62, α0=0.32.

[0171] Depend on Fig.10 It can be seen that, under the same number of programming / erasing times, the bit error rate performance of the NAND flash memory dynamic write voltage method provided by the embodiment of the present invention is better than the fixed write voltage scheme and the write voltage scheme constructed by the existing minimum channel error rate. Therefore, the technical solution provided by the embodiment of the present invention takes into account the imbalance problem of high and low channel error rates, and combines the role of LDPC code in data error correction to significantly improve the overall bit error rate performance.

[0172] See also Fig.11 , Fig.11 A NAND flash memory dynamic write voltage device is provided in the third embodiment of the present invention, wherein the device comprises:

[0173] A construction module 301 is used to construct a cost function according to a high channel error rate, a low channel error rate and a minimum Hamming distance estimated by an LDPC code;

[0174] The optimization module 302 takes the minimum function value of the cost function as the optimization target, takes the first programming voltage and the second programming voltage as independent variables, performs convex optimization calculation on the cost function, and outputs the optimal first programming voltage and the optimal second programming voltage.

[0175] Furthermore, the optimization module 302 includes:

[0176] An acquisition module, used for acquiring a flash memory channel parameter, wherein the flash memory channel parameter includes a first numerical range of a first programming voltage and a second numerical range of a second programming voltage;

[0177] A first selection module, used for selecting a second programming voltage value from a second value range as an initial value of the second programming voltage;

[0178] A second selection module is used to uniformly select M first programming voltage values ​​from the first value range, and respectively combine the M first programming voltage values ​​with the initial value of the second programming voltage to form M groups of first write voltages, where M is a constant;

[0179] A first calculation module, used to calculate the cost function values ​​corresponding to the M groups of first write voltages, and determine the optimal first programming voltage corresponding to the minimum cost function value;

[0180] A third selection module is used to uniformly select M second programming voltage values ​​from the second value range, and respectively combine the M second programming voltage values ​​with the optimal first programming voltage to form M groups of second write voltages;

[0181] A second calculation module, used to calculate the cost function values ​​corresponding to the M groups of second write voltages, and determine the optimal second programming voltage corresponding to the minimum cost function value;

[0182] A replacement module, used for replacing the initial value of the second programming voltage with the optimal second programming voltage;

[0183] The circulation module is used to trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module in sequence until the trigger termination condition is met, and output the optimal first programming voltage and the optimal second programming voltage.

[0184] Furthermore, the flash memory channel parameters also include a maximum write voltage and a minimum write voltage, and the first calculation module specifically includes:

[0185] A first generating module, used to generate M groups of first threshold voltage distribution curve graphs according to the M groups of first write voltages, the maximum write voltage and the minimum write voltage;

[0186] A first determination module, configured to determine the intersection points of the M groups of first curves according to the M groups of first threshold voltage distribution curve graphs;

[0187] A first substitution module is used to substitute the intersection points of the M groups of first curves into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substitute the high and low channel error rates into the cost function to obtain the M groups of cost function values;

[0188] A second determination module is used to determine a first curve intersection point corresponding to a minimum cost function value from the M groups of cost function values;

[0189] The third determination module is used to determine the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

[0190] Furthermore, the second calculation module specifically includes:

[0191] A second generating module, used to generate M groups of second threshold voltage distribution curves according to the M groups of second write voltages, the maximum write voltage and the minimum write voltage;

[0192] A fourth determination module, configured to determine the intersection points of the M groups of second curves according to the M groups of second threshold voltage distribution curve graphs;

[0193] The second substitution module is used to substitute the intersection points of the M groups of second curves into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substitute the high and low channel error rates into the cost function to obtain the M groups of cost function values;

[0194] A fifth determination module, used to determine a second curve intersection point corresponding to a minimum cost function value from the M groups of cost function values;

[0195] The sixth determination module is used to determine the corresponding optimal second programming voltage according to the intersection point of the second curve corresponding to the minimum cost function value.

[0196] Furthermore, the loop module is specifically used to trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module in sequence until the number of iterations reaches an iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage remain unchanged compared with the optimal first programming voltage and the optimal second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

[0197] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0198] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0199] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0200] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0201] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0202] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A NAND flash memory dynamic write voltage method, characterized in that: The write voltage includes a first programming voltage and a second programming voltage, and the method includes: Construct a cost function based on the high channel error rate, the low channel error rate and the minimum Hamming distance estimated by the LDPC code; Taking the minimum function value of the cost function as the optimization goal, the first programming voltage and the second programming voltage as independent variables, performing convex optimization calculation on the cost function, and outputting the optimal first programming voltage and the optimal second programming voltage; The calculation formulas for the high channel error rate and the low channel error rate are: ； in, is the high channel error rate, is the low channel error rate; is the minimum write voltage The probability density curve of the first programming voltage The intersection point of the probability density curve of The first programming voltage The probability density curve of the second programming voltage The intersection point of the probability density curve of The probability density curve of the second programming voltage and the maximum write voltage The intersection point of the probability density curve of ; , , , The minimum write voltage is The probability density curve of the first programming voltage The probability density curve of the second programming voltage Probability density curve, maximum write voltage The probability density curve of The expression of the cost function is: ； Where d is the minimum Hamming distance of LDPC code estimation.

2. The method according to claim 1, characterized in that The method takes the minimum function value of the cost function as the optimization target, takes the first programming voltage and the second programming voltage as independent variables, performs convex optimization calculation on the cost function, and outputs the optimal first programming voltage and the optimal second programming voltage, including: S0: Acquire a flash channel parameter, where the flash channel parameter includes a first value range of a first programming voltage and a second value range of a second programming voltage; S1: Selecting a second programming voltage value from the second value range as an initial value of the second programming voltage; S2: uniformly selecting M first programming voltage values ​​from the first value range, and combining the M first programming voltage values ​​with the initial value of the second programming voltage to form M groups of first write voltages, where M is a constant; S3: Calculate the cost function values ​​corresponding to the first write voltages of the M groups, and determine the optimal first programming voltage corresponding to the minimum cost function value; S4: uniformly selecting M second programming voltage values ​​from the second value range, and combining the M second programming voltage values ​​with the optimal first programming voltage to form M groups of second write voltages; S5: Calculate the cost function values ​​corresponding to the M groups of the second write voltages, and determine the optimal second programming voltage corresponding to the minimum cost function value; S6: The optimal second programming voltage replaces the initial value of the second programming voltage; S7: Iterate S2-S6 until the iteration termination condition is met, and output the optimal first programming voltage and the optimal second programming voltage.

3. The method according to claim 2, characterized in that The flash channel parameters also include a maximum write voltage and a minimum write voltage, and S3 specifically includes: Generate M groups of first threshold voltage distribution curve graphs according to the M groups of the first write voltages, the maximum write voltage and the minimum write voltage respectively; Determine the intersection of the first curves of the M group according to the first threshold voltage distribution curve diagram of the M group; Substituting the intersection points of the first curves of the M groups into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substituting the high and low channel error rates into the cost function to obtain the cost function values ​​of the M groups; Determine a first curve intersection point corresponding to the minimum cost function value from the M groups of cost function values; The corresponding optimal first programming voltage is determined according to the first curve intersection point corresponding to the minimum cost function value.

4. The method according to claim 3, characterized in that The S5 specifically includes: Generate M groups of second threshold voltage distribution curve graphs respectively according to the M groups of the second write voltage, the maximum write voltage and the minimum write voltage; Determine the intersection of the second curves of the M groups according to the second threshold voltage distribution curve graph of the M groups; Substituting the intersection points of the second curves of the M groups into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substituting the high and low channel error rates into the cost function to obtain the M groups of cost function values; Determine a second curve intersection point corresponding to the minimum cost function value from the M groups of cost function values; The corresponding optimal second programming voltage is determined according to the second curve intersection point corresponding to the minimum cost function value.

5. The method according to claim 2, characterized in that: The S7 specifically includes: Iterate S2-S6 until the number of iterations reaches the iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage remain unchanged compared with the optimal first programming voltage and the second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

6. A NAND flash memory dynamic write voltage device, characterized in that: The write voltage includes a first programming voltage and a second programming voltage, and the device includes: A construction module, for constructing a cost function according to a high-order channel error rate, a low-order channel error rate, and a minimum Hamming distance estimated by an LDPC code; An optimization module, taking the minimum function value of the cost function as an optimization target, taking the first programming voltage and the second programming voltage as independent variables, performing convex optimization calculation on the cost function, and outputting an optimal first programming voltage and an optimal second programming voltage; The calculation formulas for the high channel error rate and the low channel error rate are: ； in, is the high channel error rate, is the low channel error rate; is the minimum write voltage The probability density curve of the first programming voltage The intersection point of the probability density curve of The first programming voltage The probability density curve of the second programming voltage The intersection point of the probability density curve of The probability density curve of the second programming voltage and the maximum write voltage The intersection point of the probability density curve of ; , , , The minimum write voltage is The probability density curve of the first programming voltage The probability density curve of the second programming voltage Probability density curve, maximum write voltage The probability density curve of The expression of the cost function is: ； Where d is the minimum Hamming distance of LDPC code estimation.

7. The device according to claim 6, characterized in that The optimization module includes An acquisition module, used for acquiring a flash memory channel parameter, wherein the flash memory channel parameter includes a first numerical range of a first programming voltage and a second numerical range of a second programming voltage; A first selection module, used for selecting a second programming voltage value from the second value range as an initial value of the second programming voltage; A second selection module is used to uniformly select M first programming voltage values ​​from the first value range, and respectively combine the M first programming voltage values ​​with the initial value of the second programming voltage to form M groups of first write voltages, where M is a constant; A first calculation module, used for calculating the cost function values ​​corresponding to the first write voltages of the M groups, and determining the optimal first programming voltage corresponding to the minimum cost function value; A third selection module is used to uniformly select M second programming voltage values ​​from the second value range, and respectively combine the M second programming voltage values ​​with the optimal first programming voltage to form M groups of second write voltages; A second calculation module, used for calculating the cost function values ​​corresponding to the M groups of the second write voltages, and determining the optimal second programming voltage corresponding to the minimum cost function value; A replacement module for replacing the initial value of the second programming voltage with the optimal second programming voltage; A loop module is used to trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module in sequence until the trigger termination condition is met, and output the optimal first programming voltage and the optimal second programming voltage.

8. The device according to claim 7, characterized in that The flash channel parameters also include a maximum write voltage and a minimum write voltage, and the first calculation module specifically includes: A first generating module, used for generating M groups of first threshold voltage distribution curve graphs according to the M groups of the first write voltages, the maximum write voltage and the minimum write voltage; A first determination module, configured to determine the intersection points of the M groups of first curves according to the M groups of the first threshold voltage distribution curve graphs; A first substitution module, used for substituting the intersection points of the first curves of the M groups into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substituting the high and low channel error rates into the cost function to obtain the M groups of cost function values; A second determination module, used to determine a first curve intersection point corresponding to the minimum cost function value from the M groups of cost function values; The third determination module is used to determine the corresponding optimal first programming voltage according to the first curve intersection point corresponding to the minimum cost function value.

9. The device according to claim 8, characterized in that The second calculation module specifically includes: A second generating module, used to generate M groups of second threshold voltage distribution curve graphs according to the M groups of the second write voltages, the maximum write voltage and the minimum write voltage; A fourth determination module, configured to determine the intersection points of the M groups of second curves according to the M groups of second threshold voltage distribution curve graphs; A second substitution module is used to substitute the M groups of intersection points of the second curve into the high and low channel error rate calculation formulas respectively to obtain the high and low channel error rates, and substitute the high and low channel error rates into the cost function to obtain the M groups of cost function values; A fifth determination module, configured to determine a second curve intersection point corresponding to the minimum cost function value from the M groups of cost function values; The sixth determination module is used to determine the corresponding optimal second programming voltage according to the intersection point of the second curve corresponding to the minimum cost function value.

10. The device according to claim 7, characterized in that The loop module is specifically used to trigger the second selection module, the first calculation module, the third selection module, the second calculation module and the replacement module in sequence until the number of iterations reaches an iteration number threshold, or until the current optimal first programming voltage and the optimal second programming voltage remain unchanged compared with the optimal first programming voltage and the second programming voltage obtained in the previous iteration, and output the optimal first programming voltage and the optimal second programming voltage.

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