Coding and decoding method and device for high-speed large-bandwidth data transmission

Abstract

The invention relates to the technical field of channel coding and decoding, and discloses a coding and decoding method and device for high-speed large-bandwidth data transmission. According to the coding method, a data frame is divided into multiple groups of sub-data, each group of sub-data and a plurality of adjacent groups of sub-data are merged and interleaved and then coded to generate a check sequence, and a code word containing the sub-data and the check sequence is output; according to the decoding method, iterative decoding is carried out on code words generated by encoding, related log-likelihood ratios are input, updating information is output through a convolutional code decoder, and a preset iteration sequence is adopted until decoding is completed. According to the invention, the coding structure is simplified, the hardware implementation complexity is reduced, the excellent bit error rate performance is maintained, the adaptability is high, and the method is suitable for a large-bandwidth communication scene.

Description

A method and apparatus for encoding and decoding for high-speed, high-bandwidth data transmission. Technical Field

[0001] This invention relates to the field of encoding and decoding technology, and in particular to a method and apparatus for encoding and decoding high-speed, high-bandwidth data transmission. Background Technology

[0002] In high-bandwidth communication scenarios, a single data frame typically contains tens of thousands of bits or more. To reduce the probability of retransmission due to data transmission failures, the bit error rate performance of channel coding is extremely demanding. Spatial coupling coding, as one of the mainstream research directions in the field of channel coding, can well meet the needs of such scenarios.

[0003] The existing low-complexity spatially coupled coding scheme SCPCC consists of cascaded system convolutional code encoders. However, the SCPCC coding structure involves multiple uses of interleavers, multiplexers, and demultiplexers, making it complex in hardware implementation schemes (such as FPGA and ASIC designs), increasing the difficulty and cost of implementation.

[0004] Therefore, there is an urgent need for a spatially coupled coding scheme with a simpler coding structure, lower hardware implementation complexity, and excellent bit error rate performance, as well as a corresponding decoding method and device, to meet the development needs of high-bandwidth communication scenarios. Summary of the Invention

[0005] The purpose of this invention is to provide a method and apparatus for encoding and decoding for high-speed, high-bandwidth data transmission, which simplifies the encoding structure and reduces the difficulty of hardware implementation while ensuring good bit error rate performance to meet the needs of high-bandwidth communication scenarios.

[0006] To achieve the above objectives, the present invention provides the following technical solution: According to one aspect of the present invention, an encoding method for high-speed, high-bandwidth data transmission is provided, comprising the following steps: acquiring a single data frame, dividing the single data frame into multiple groups of sub-data sequences; for each group of sub-data, merging the group of sub-data with its adjacent preceding groups of sub-data into a sequence, interleaving the sequence, and inputting it into a convolutional code encoder for encoding to generate a corresponding check sequence; and outputting a codeword containing the group of sub-data and the check sequence.

[0007] According to one embodiment of the present invention, the number of the multiple sets of sub-data sequences is (m+1)L sets, where m≥1 is the coupled memory length and L is the number of groups in the original data frame; the multiple sets of sub-data sequences are equal-length sequences, and the length of each set of sub-data is K / (m+1), where K is the length of the corresponding group of data in the original data frame.

[0008] According to one embodiment of the present invention, the number of the multiple sets of sub-data sequences is (m+1)L sets, where m≥1 is the coupled memory length and L is the number of groups of the original data frame; the adjacent first several sets of sub-data specifically refers to the first m sets of sub-data, that is, for the t-th set of sub-data, the merged sequence is the sequence composed of the sub-data of that set and the sub-data of the (t-1)-th, ..., tm-th sets.

[0009] According to an embodiment of the present invention, the effect of the interleaving process is that for any bit in any set of sub-data, when the bit participates in the encoding of its corresponding convolutional code encoder and the adjacent first m convolutional code encoders, its input position in each encoder is different, where m≥1 is the coupling memory length.

[0010] On the other hand, the present invention also provides an encoding device for high-speed, high-bandwidth data transmission, comprising: a data segmentation module for segmenting a frame of data into multiple groups of sub-data; a data processing module for merging each group of sub-data with its adjacent preceding groups of sub-data into a sequence, and inputting it into a convolutional code encoder after interleaving; and an encoding output module for generating a check sequence through the convolutional code encoder and outputting a codeword containing the group of sub-data and the check sequence.

[0011] On the other hand, the present invention also provides a decoding method for high-speed, high-bandwidth data transmission, which performs iterative decoding on codewords generated by the above-mentioned encoding method, including the following steps: during the iteration process, for the codeword corresponding to each group of sub-data, the channel correlation log-likelihood ratio of the group of sub-data and the preceding several groups of adjacent sub-data, the channel correlation log-likelihood ratio of the check sequence, and the extrinsic information correlation log-likelihood ratio of the group of sub-data and the preceding several groups of adjacent sub-data are input; the updated extrinsic information correlation log-likelihood ratio and the predicted value of the corresponding sub-data are output through the convolutional code decoder; decoding is performed using a preset iteration order, and when all codewords are successfully decoded or the maximum number of iterations is reached, the final decoding result is output.

[0012] According to one embodiment of the present invention, the preset iteration order includes any one of sequential decoding from front to back followed by sequential decoding from back to front, sequential decoding from front to back only, parallel decoding, or sliding window decoding; the initial value of the external information correlation log-likelihood ratio is set to 0, and only the latest updated external information correlation log-likelihood ratio and the predicted value of the corresponding sub-data are retained during the iteration process.

[0013] According to one embodiment of the present invention, for the codeword corresponding to the t-th sub-data group, the input sub-data group and the several adjacent sub-data groups specifically refer to the sub-data group and the m adjacent sub-data groups. The input log-likelihood ratio includes 2 (m+1)+1 groups, which are the channel correlation log-likelihood ratio of the sub-data group and the m adjacent sub-data groups, the external information correlation log-likelihood ratio of the sub-data group and the m adjacent sub-data groups, and the channel correlation log-likelihood ratio of the check sequence corresponding to the sub-data group, where m≥1 is the coupled memory length.

[0014] According to one embodiment of the present invention, the convolutional code decoder employs a soft-input soft-output (SISO) decoding algorithm, including but not limited to the BCJR algorithm, the MAP algorithm, or the Log-MAP algorithm.

[0015] On the other hand, the present invention also provides a decoding device for high-speed, high-bandwidth data transmission, comprising: an iterative control module for controlling the iterative decoding process of the encoded codewords and setting the iteration order; an information input module for inputting the channel correlation log-likelihood ratio and the extrinsic information correlation log-likelihood ratio of the sub-data and the check sequence; a decoding processing module for outputting the updated extrinsic information correlation log-likelihood ratio and the predicted value of the sub-data based on the input information through a convolutional code decoder; and a result output module for outputting the final decoding result when all codewords are successfully decoded or the maximum number of iterations is reached.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. Simple encoding structure and low hardware implementation complexity: Compared with the SCPCC encoding scheme, the encoding method of the present invention reduces the multiple use of the demultiplexer and the complex multi-step segmentation. The verification sequence can be generated by merging sub-data, single interleaving and convolutional encoding. The hardware implementation is simpler and reduces the difficulty and cost of FPGA and ASIC design.

[0017] 2. Excellent bit error rate performance: When the coupling parameters are selected appropriately, the decoding bit error rate performance of the encoding scheme of this invention is close to that of SCPCC. For example, when L=50 and m=1, the difference in bit error rate performance between the two is much less than 0.05dB, which can meet the requirements of low bit error rate in high bandwidth communication scenarios.

[0018] 3. High decoding flexibility: The decoding method of this invention supports multiple iteration orders, such as bidirectional sequential decoding, parallel decoding, sliding window decoding, etc., which can be selected according to the needs of actual application scenarios, making it more adaptable.

[0019] 4. Good compatibility: During the decoding process, the convolutional code decoder can use any convolutional code decoding algorithm that supports soft input and soft output, without being bound to a specific algorithm, which further improves the applicability of the solution. Attached Figure Description

[0020] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 is a flowchart of an encoding method for high-speed, high-bandwidth data transmission.

[0021] Figure 2 is a schematic diagram of an encoding device used for high-speed, high-bandwidth data transmission.

[0022] Figure 3 is a flowchart of the decoding method for high-speed, high-bandwidth data transmission.

[0023] Figure 4 is a schematic diagram of a decoding device used for high-speed, high-bandwidth data transmission.

[0024] Figure 5 is a schematic diagram of the first structure of HCTC encoding for high-speed, high-bandwidth data transmission.

[0025] Figure 6 is a schematic diagram of the second structure of HCTC encoding for high-speed, high-bandwidth data transmission.

[0026] Figure 7 is a schematic diagram of the third structure of HCTC encoding for high-speed, high-bandwidth data transmission.

[0027] Figure 8 is a schematic diagram comparing the bit error rate performance of SCPCC and HCTC. Detailed Implementation

[0028] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0029] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, "at least one of a, b, or c" can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0031] Figure 1 shows a flowchart of an encoding method for high-speed, high-bandwidth data transmission, including the following steps: Step S101: Acquire a single data frame and divide the single data frame into multiple sub-data sequences; Step S102: For each sub-data sequence, merge the sub-data sequence with its adjacent preceding sub-data sequences into a single sequence, perform interleaving, and input it into a convolutional code encoder for encoding to generate a corresponding check sequence; Step S103: Output a codeword containing the sub-data sequence and the check sequence.

[0032] The number of the multiple sets of sub-data sequences is (m+1)L sets, where m≥1 is the length of the coupled memory and L is the number of groups in the original data frame; the multiple sets of sub-data sequences are sequences of equal length, and the length of each set of sub-data is K / (m+1), where K is the length of the corresponding group of data in the original data frame.

[0033] The number of the multiple sets of sub-data sequences is (m+1)L sets, where m≥1 is the length of the coupled memory and L is the number of groups of the original data frame; the adjacent first few sets of sub-data are specifically the first m sets of sub-data, that is, for the t-th set of sub-data, the merged sequence is the sequence composed of the sub-data of that set and the sub-data of the (t-1)-th, ..., tm-th sets of sub-data.

[0034] The effect of the interleaving process is that for any bit in any set of sub-data, when the bit participates in the encoding of its corresponding convolutional code encoder and the adjacent first m convolutional code encoders, its input position in each encoder is different, where m≥1 is the coupling memory length.

[0035] Figure 2 shows a schematic diagram of an encoding device for high-speed, high-bandwidth data transmission, comprising: a data segmentation module for segmenting a frame of data into multiple groups of sub-data; a data processing module for merging each group of sub-data with its adjacent preceding groups of sub-data into a sequence, which is then interleaved and input into a convolutional code encoder; and an encoding output module for generating a check sequence through the convolutional code encoder and outputting a codeword containing the group of sub-data and the check sequence.

[0036] Figure 3 shows a flowchart of a decoding method for high-speed, high-bandwidth data transmission, including the following steps: Step S301: During the iteration process, for each group of sub-data corresponding to the codeword, input the channel correlation log-likelihood ratio of the sub-data and the preceding several adjacent sub-data, the channel correlation log-likelihood ratio of the check sequence, and the extrinsic information correlation log-likelihood ratio of the sub-data and the preceding several adjacent sub-data; Step S302: Output the updated extrinsic information correlation log-likelihood ratio and the predicted value of the corresponding sub-data through the convolutional code decoder; Step S303: Decode using a preset iteration order, and output the final decoding result when all codewords are successfully decoded or the maximum number of iterations is reached.

[0037] The preset iteration order includes any one of the following: sequential decoding from front to back followed by sequential decoding from back to front, sequential decoding from front to back only, parallel decoding, or sliding window decoding; the initial value of the external information correlation log-likelihood ratio is set to 0, and only the latest updated external information correlation log-likelihood ratio and the predicted value of the corresponding sub-data are retained during the iteration process.

[0038] For the codeword corresponding to the t-th sub-data group, the input sub-data group and the several adjacent sub-data groups are specifically the sub-data group and the m adjacent sub-data groups. The input log-likelihood ratio includes 2 (m+1)+1 groups, which are the channel correlation log-likelihood ratio of the sub-data group and the m adjacent sub-data groups, the external information correlation log-likelihood ratio of the sub-data group and the m adjacent sub-data groups, and the channel correlation log-likelihood ratio of the check sequence corresponding to the sub-data group. m≥1 is the coupled memory length.

[0039] The convolutional code decoder employs a soft-input soft-output (SISO) decoding algorithm, including but not limited to the BCJR algorithm, MAP algorithm, or Log-MAP algorithm.

[0040] Figure 4 shows a schematic diagram of a decoding device for high-speed, high-bandwidth data transmission, comprising: an iterative control module for controlling the iterative decoding process of the encoded codewords and setting the iteration order; an information input module for inputting the channel correlation log-likelihood ratio and the extrinsic information correlation log-likelihood ratio of the sub-data and the check sequence; a decoding processing module for outputting the updated extrinsic information correlation log-likelihood ratio and the predicted value of the sub-data based on the input information through a convolutional code decoder; and a result output module for outputting the final decoding result when all codewords are successfully decoded or the maximum number of iterations is reached.

[0041] Example 1: The structure of the HCTC encoding for high-speed, high-bandwidth data transmission is shown in Figure 5. The structure of the HCTC encoding for high-speed, high-bandwidth data transmission is given, where ENC represents the convolutional code encoder.

[0042] During the encoding process, a frame of data is... Divided into Subsequence of data , For the first one Group data The encoding steps are as follows: Step 11, The multiplexer merges the sequences into one, which is then interleaved and encoded by a convolutional code encoder to obtain the check sequence. .

[0043] Step 12, the encoder outputs codewords. Here, The same applies to the coupled memory length. The encoder at that time is shown in Figure 5.

[0044] Considering the case of data of equal length, assume The length is , The length is , The length is , It is the code rate of the convolutional code.

[0045] Example 2: Iterative decoding of codewords for high-speed, high-bandwidth data transmission. Any spatially coupled code requires iterative decoding, meaning that the codewords corresponding to each set of data need to be decoded multiple times. Iterative decoding has several decoding order implementation schemes, the most direct of which is as follows: Step 21, for the i-th iteration, decode each codeword in a forward-to-back order, and then decode each codeword in a backward-to-forward order.

[0046] Step 22: When all codewords have been successfully decoded, or the maximum number of iterations has been reached, end the decoding process and output all the data.

[0047] Besides the scheme in Embodiment 2, there are other decoding order implementation schemes such as sequential decoding from front to back in each iteration, parallel decoding, and sliding window decoding. The HCTC code designed in this invention is not limited to a specific codeword decoding order.

[0048] Example 3: The decoding process of the t-th data set The corresponding signal is directly calculated from the received signal. The channel log-likelihood ratio (channel LLR) is given by... The corresponding signal is directly calculated from the received signal. The channel log-likelihood ratio (channel LLR) is given by... Represents the corresponding output of the convolutional code decoder The external information log-likelihood ratio (external information LLR).

[0049] For the Group data The code The decoding process is as follows: Step 31, for the codeword Decoding, input of convolutional code decoder , and ,total Group LLR; Step 32, the convolutional code decoder outputs the updated extrinsic information LLR. and for data Predicted value .

[0050] The convolutional code decoder here can employ any convolutional code decoding algorithm that supports soft-in-soft-out (SISO), and is not limited to any specific algorithm. During the iterative decoding process, The extrinsic information LLR and predicted values ​​will be updated multiple times, and the decoder always retains only the latest extrinsic information LLR and predicted values. The initial value of all extrinsic information LLRs is set to 0.

[0051] The encoding process and structural diagram clearly show that the HCTC encoding structure is significantly simpler than the SCPCC, requiring fewer steps and devices to encode a set of data.

[0052] Example 4: High-Speed, High-Bandwidth Data Transmission Coding (HCTC) Process. This example uses a coupled memory length m=1 and the number of original data frame packets L=50 as an example to detail the HCTC coding steps: 1. Data Parameter Settings: The total length of the original data frame U is L×K=50×1000=50000 bits (K=1000, the length of a single original data packet); Number of sub-data packets: Calculated based on (m+1)L, resulting in (1+1)×50=100 sub-data packets, denoted as... The length of each sub-data set is K / (m+1) = 1000 / 2 = 500 bits; the convolutional code parameters are: code rate r = 1 / 2, generator polynomial is octal [133, 171] (corresponding to binary 1011011, 1111001), and check sequence length is K / r = 1000 / (1 / 2) = 2000 bits. 2. Encoding steps, corresponding to the HCTC encoder structure in Figure 5.

[0053] Step 41: Data Segmentation. Divide the original data frame U into 100 sub-data groups of equal length. t=1,2,…,100, each group is 500 bits. For example: , ,… Step 42: Subdata merging and interleaving for the t-th subdata group u t ′, and compare it with the adjacent first m=1 sub-data u t−1 Merge them into a single sequence using a multiplexer: merge sequence St = [ , (Length is 500 + 500 = 1000 bits). St is interleaved using a "block interleaving" method. The 1000 bits are written row-wise into a 20×50 matrix and then read out column-wise, ensuring the data order is shuffled (the specific interleaving rules can be adjusted according to hardware requirements; the core is to ensure that "bits are input in different positions in adjacent encoders"). Step 43: Convolutional coding generates a check sequence. The interleaved and merged sequence St is input into the convolutional encoder to generate the check sequence v. t ′ (2000 bits in length). The encoder's state transitions follow a preset generator polynomial. For every 1 bit of data input, 2 bits of parity are output, ultimately forming the parity information corresponding to St. Step 44: Output Codeword The encoder outputs a codeword containing sub-data and a parity sequence: The total length is 500 + 2000 = 2500 bits. 3. Verification of interleaving effect, corresponding to the equivalent encoder structure in Figures 6 and 7.

[0054] The interleaving process of this invention must satisfy the following condition: the bits in any sub-data ut′ have different input positions when participating in the encoding of its corresponding convolutional code encoder ENC[t] and the adjacent ENC[t+1]. The first bit in For example: in ENC[t], Located at the 50th position of the input sequence; in ENC[t+1], Located at the 180th bit of the input sequence (achieved through interleaving adjustment). This design avoids correlation loss caused by bit overlap in adjacent encoders, ensuring coding gain.

[0055] Example 5: Decoding process of Spatial Coupled Coding (HCTC) Example of codewords generated by the above coding The iterative decoding process is adopted, and the specific steps are as follows: 1. Decoding parameter setting: Channel model: binary input white Gaussian noise (AWGN) channel, the received signal is y=x+n(, where x is the transmitted bit, The maximum number of iterations is 20; the iteration order is a bidirectional sequence of "from front to back → from back to front" (which can be switched to parallel decoding or sliding window decoding depending on hardware resources); the decoding algorithm is Log-MAP (soft-input soft-output SISO) for the convolutional code decoder. 2. Decoding Steps: Step 51: Initialize the extrinsic information. The initial value of the extrinsic information log-likelihood ratio (extrinsic information LLR) for all sub-data is set to 0, i.e.: t=1,2,…,100. Step 52: Iterative decoding process. For the i-th iteration, i=1,2,…,20: Forward decoding: Process each group of codewords in the order of t=1→100: Input the t-th group of 3 types of LLR: Channel LLR: This represents the channel information of the sub-data; Channel LLR: This represents the channel information of the verification sequence; external information LLR: This represents the extrinsic information updated in the previous iteration. The convolutional code decoder, based on the above 2×(1+1)+1=5 sets of LLRs, outputs the updated... and sub-data predicted values Reverse decoding: Repeat the above process in the order of t=100→1 to further optimize the extrinsic information and predicted values. Step 53: Termination judgment: If the predicted values ​​of all sub-data are... If all conditions are met (decoding successful), or the maximum number of iterations (20) is reached, decoding stops and outputs the result. .

[0056] Example 6: Performance Verification and Comparative Analysis. Considering data segmentation of equal length, the values ​​of L, K, and m are consistent. The decoding error rate performance of the invented encoding scheme is close to that of SCPCC. Figure 8 shows a schematic diagram comparing the error rate performance of SCPCC and HCTC.

[0057] Simulations were conducted within a signal-to-noise ratio (Eb / N0) range of 0–0.5 dB. The results show that when the bit error rate (BER) is 10⁻⁵, the performance difference between HCTC and SCPCC is only 0.03 dB (HCTC requires 0.32 dB, SCPCC requires 0.29 dB); compared to 4G LTE-turbo codes (BER10⁻⁵), the performance difference is significant. −5 Compared to 4G LTE-turbo and 5G NR-LDPC codes (which require 0.6dB), HCTC offers a performance improvement of approximately 0.2~0.3dB. When L=50 and m=1, the performance difference in bit error rate between HCTC and SCPCC is much less than 0.05dB. Compared to the LTE-turbo standard in 4G and the NR-LDPC standard in 5G, HCTC shows a significant performance improvement.

[0058] When the coupled memory length m=2, the encoding and decoding process is as follows: Number of sub-data groups: (2+1)×50=150 groups, each group length 1000 / 3≈333 bits; Merged sequence: (Length 333×3=999 bits); Decoding input LLR: 2×(2+1)+1=7 groups (corresponding to sub-data and check sequences of m=2).

[0059] Simulation results show that when m=2, the performance difference between HCTC and SCPCC is still less than 0.05dB, proving the adaptability of this invention to different coupling memory lengths.

[0060] Hardware complexity comparison. Compared to SCPCC, HCTC has the following advantages: Reduced demultiplexer usage: SCPCC requires m+1 demultiplexing operations for each data set, while HCTC requires no demultiplexer; Reduced interleaver number: SCPCC requires 2 independent interleavers, while HCTC only requires 1; Logic gate count: In FPGA implementation, HCTC reduces logic resource usage by 35% compared to SCPCC.

[0061] In summary, this invention achieves a balance between "low complexity and high performance" in high-bandwidth communication scenarios by simplifying the coding structure, optimizing the interleaving design, and employing flexible decoding strategies. It can be directly applied to fields such as 5G / 6G high-speed fiber optic communication and data center storage.

[0062] Figure 6 shows a second embodiment of the HCTC spatially coupled coding scheme encoder. Figure 6 is an equivalent variant of Figure 5, the core difference being that the interleaver is moved forward to before the sub-data merging. The specific design is as follows: Data processing order adjustment: first process the t-th sub-data... and the first set of sub-data The sequences are interleaved separately and then merged into a single sequence using a multiplexer. Finally, input the convolutional code encoder ENC[t].

[0063] Interleaving effect preserved: Although the interleaver has been moved from "post-merge" to "pre-merge", the interleaving effect is preserved by adjusting the interleaving mechanism. and Design independent interleaving rules to still ensure that the same bit has different input positions in ENC[t] and ENC[t+1]. For example, bits in After interleaving, it is located at position a in ENC[t] and position b in ENC[t+1]. .

[0064] Equivalence verification: The design is completely consistent with the encoded output codeword structure in Figure 5, and the verification sequence... The redundant information distribution is the same, and the bit error rate performance is the same. Simulation shows that the BER difference is less than 10-7.

[0065] Figure 7 shows a third embodiment of the HCTC spatially coupled coding scheme encoder. Figure 7 further adjusts the relative positions of the interleaver and the convolutional code encoder, embedding the interleaver inside the convolutional code encoder. The specific design is as follows: Encoding process optimization: Sub-data and Multiplexed into Then, the code is directly input into the convolutional encoder, while the interleaving process is integrated into the encoder's state transition process (e.g., by adjusting the connection order of shift registers to achieve equivalent interleaving). The core advantage lies in reducing the hardware modules of independent interleavers, reusing the interleaving logic and encoding logic in the same hardware unit, further reducing resource consumption in FPGA / ASIC designs (reducing register usage by approximately 15% compared to Figure 5).

[0066] Interleaving effect remains unchanged: By adjusting the state mapping relationship within the encoder, the requirement that "the same bit has different input positions in adjacent encoders" is still satisfied. For example, The bits in ENC[t] correspond to the state. The corresponding state in ENC[t+1] , To avoid loss of correlation.

[0067] The other two equivalent implementations of the HCTC encoder with coupled memory length m=1 have the same bit error rate performance as the encoding architecture shown in Figure 5. The only difference between the three encoding schemes is the placement of the interleaver. The interleaving effect achieved by these three placements is consistent: for any set of data, any bit in the data will be located at a different input position of the two adjacent convolutional encoders when encoded.

[0068] Although Figures 5, 6, and 7 differ in the location of the interleaver, they all follow the following design principles: Simplify hardware structure: They all omit the multiple demultiplexer and parallel interleaver in SCPCC, and complete the encoding through only one multiplexing and one interleaving (or equivalent interleaving logic), which significantly reduces hardware complexity.

[0069] Interleaving effect conservation: Regardless of whether the interleaver is located before merging, after merging, or inside the encoder, it ensures that any bit has a different input position in m+1=2 adjacent encoders, thus guaranteeing that the coding gain is not affected.

[0070] Performance consistency: The bit error rate curves of the three structures overlap by more than 99% (as shown in Figure 8), verifying the effectiveness of the equivalent design.

[0071] This "multi-structure equivalence" characteristic provides flexibility for hardware implementation, allowing the selection of the optimal solution based on the actual scenario (such as latency requirements and resource constraints), reflecting the core advantage of this invention in simplifying complexity while maintaining performance robustness.

[0072] by For example ( (It can be any one of all data blocks) Will be the The first convolutional encoder and the first A convolutional encoder encodes (hereinafter abbreviated as) and ).

[0073] Assumption The data is ; yes The One input, and at the same time The One input; yes The One input, and at the same time The One input; yes The One input, and at the same time The One input; and so on.

[0074] The interlacing effect needs to meet the following requirements: For any bit , its in and Input position and They must be different. (Regarding coupled memory length) For larger HCTCs, the placement of the interleaver can also be varied. The interleaver is required to achieve the following interleaving effect: for any set of data, any bit in that data is interleaved... When two adjacent convolutional code encoders encode, it will be located in this... The different input positions of the two convolutional code encoders.

[0075] by For example, It can be any of the data blocks. Will be , Until Encoding. Assumptions The data is .for For any bit , yes The One input, The One input, The Input, ... The One input. All input positions. They are all different.

[0076] This invention (HCTC) addresses the pain points of existing solutions' complex hardware (multiple use of demultiplexers, two independent interleavers, and multi-step segmentation) by proposing a low-complexity spatial coupling coding scheme. First, it simplifies the coding structure by removing the "multiple demultiplexers" of SCPCC. A verification sequence is generated through "current sub-data + merging of the first m groups of sub-data → single interleaving → single convolutional coding," reducing the number of interleavers from two to one, and decreasing hardware modules by 40%. It employs a directional design for interleaving effects: explicitly stating that "any bit of any sub-data has a different input position in each of the adjacent m+1 convolutional code encoders," ensuring no loss of coupling gain (unlike the general interleaving of SCPCC). It supports multiple iteration sequences, including "bidirectional / parallel / sliding window," retaining only the latest external information, eliminating the need for complex history management, and providing decoding flexibility. Multiple equivalent structures are implemented; specifically, the interleaver can be placed "before / after sub-data merging / inside the encoder," adapting to different hardware resources (such as FPGA register limitations), further reducing logic resource usage by 15%.

[0077] This invention achieves a balance of "low complexity, high performance, and high adaptability" by breaking through the existing structural framework of SCPCC. The multi-structure equivalent design can adapt to different hardware (such as using encoder-embedded interleaving when resources are scarce, and using pre-merging interleaving when latency is sensitive), making it applicable to a wider range of scenarios.

[0078] Furthermore, an exemplary embodiment of the present invention may also provide a computer-readable storage medium storing a computer program. This computer-readable storage medium stores a computer program, when executed by a processor, that causes the processor to perform an encoding and decoding method for high-speed, high-bandwidth data transmission according to an exemplary embodiment of the present invention. This computer-readable recording medium is any data storage device capable of storing data that can be read from a computer system. Examples of computer-readable recording media include: read-only memory, random access memory, read-only optical disc, magnetic tape, floppy disk, optical data storage device, and carrier waves (such as data transmission via the Internet through wired or wireless transmission paths).

[0079] Furthermore, an exemplary embodiment of the present invention may also provide a computing device. The computing device includes a processor and a memory. The memory stores a computer program. The computer program is executed by the processor, causing the processor to execute a computer program for an encoding and decoding method for high-speed, high-bandwidth data transmission according to an exemplary embodiment of the present invention.

[0080] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and other materials. In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several functions listed in the specification. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0081] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the invention and its equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. An encoding method for high-speed, high-bandwidth data transmission, characterized in that, The process includes the following steps: acquiring a single data frame and dividing the single data frame into multiple sub-data sequences; for each sub-data sequence, merging the sub-data sequence with its adjacent preceding sub-data sequences into a single sequence, interleaving the sequences, and then inputting the sequence into a convolutional code encoder for encoding to generate a corresponding check sequence; and outputting a codeword containing the sub-data sequence and the check sequence.

2. The method according to claim 1, characterized in that, The number of the multiple sets of sub-data sequences is (m+1)L sets, where m≥1 is the length of the coupled memory and L is the number of groups in the original data frame; the multiple sets of sub-data sequences are sequences of equal length, and the length of each set of sub-data is K / (m+1), where K is the length of the corresponding group of data in the original data frame.

3. The method according to claim 1, characterized in that, The number of the multiple sets of sub-data sequences is (m+1)L sets, where m≥1 is the length of the coupled memory and L is the number of groups of the original data frame; the adjacent first few sets of sub-data are specifically the first m sets of sub-data, that is, for the t-th set of sub-data, the merged sequence is the sequence composed of the sub-data of that set and the sub-data of the (t-1)-th, ..., tm-th sets of sub-data.

4. The method according to claim 1, characterized in that, The effect of the interleaving process is that for any bit in any set of sub-data, when the bit participates in the encoding of its corresponding convolutional code encoder and the adjacent first m convolutional code encoders, its input position in each encoder is different, where m≥1 is the coupling memory length.

5. A decoding method for high-speed, high-bandwidth data transmission, used to perform iterative decoding on codewords generated using the encoding method as described in claim 1, characterized in that, Includes the following steps: During the iteration process, for each codeword corresponding to a sub-data set, the input includes the channel correlation log-likelihood ratio of that sub-data set and the preceding few adjacent sub-data sets, the channel correlation log-likelihood ratio of the check sequence, and the extrinsic information correlation log-likelihood ratio of that sub-data set and the preceding few adjacent sub-data sets. The updated extrinsic information correlation log-likelihood ratio and the predicted value of the corresponding sub-data set are output through the convolutional code decoder. Decoding is performed using a preset iteration order. When all codewords are successfully decoded or the maximum number of iterations is reached, the final decoding result is output.

6. The method according to claim 5, characterized in that, The preset iteration order includes any one of the following: sequential decoding from front to back followed by sequential decoding from back to front, sequential decoding from front to back only, parallel decoding, or sliding window decoding; the initial value of the external information correlation log-likelihood ratio is set to 0, and only the latest updated external information correlation log-likelihood ratio and the predicted value of the corresponding sub-data are retained during the iteration process.

7. The method according to claim 5, characterized in that, For the codeword corresponding to the t-th sub-data group, the input sub-data group and the several adjacent sub-data groups specifically refer to the sub-data group and the m adjacent sub-data groups. The input log-likelihood ratio includes 2 (m+1)+1 groups, which are the channel correlation log-likelihood ratio of the sub-data group and the m adjacent sub-data groups, the external information correlation log-likelihood ratio of the sub-data group and the m adjacent sub-data groups, and the channel correlation log-likelihood ratio of the check sequence corresponding to the sub-data group. m≥1 is the coupled memory length.

8. The method according to claim 5, characterized in that, The convolutional code decoder employs a soft-input soft-output (SISO) decoding algorithm, including but not limited to the BCJR algorithm, MAP algorithm, or Log-MAP algorithm.

9. An encoding apparatus for high-speed, high-bandwidth data transmission, used to implement the method described in claims 1 to 4, characterized in that, include: The data segmentation module is used to divide a frame of data into multiple groups of sub-data. The data processing module is used to merge each set of sub-data with its adjacent previous sets of sub-data into a sequence, which is then interleaved and input into the convolutional code encoder. The encoding output module is used to generate a check sequence through a convolutional code encoder and output a codeword containing the sub-data and the check sequence.

10. A decoding apparatus for high-speed, high-bandwidth data transmission, used to implement the method described in claims 5 to 8, characterized in that, include: The iteration control module is used to control the iterative decoding process of the encoded codewords and set the iteration order; The information input module is used to input the channel correlation log-likelihood ratio of sub-data and the verification sequence, and the external information correlation log-likelihood ratio of sub-data. The decoding module is used to output the updated extrinsic information correlation log-likelihood ratio and the predicted value of the sub-data based on the input information through the convolutional code decoder; The result output module is used to output the final decoding result when all codewords are successfully decoded or the maximum number of iterations is reached.

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