Ultra-compact CAM array based on a single MTJ and method of operating same

Abstract

The present invention discloses an ultra-compact CAM array based on a single MTJ and its operation method. The CAM array includes an M*N CAM core for storing content, additional reference rows and columns for storing "0" and "1", a row decoder, a column decoder, a transmission gate EN, a write driver WD, a search current source I search and two-stage sense amplifiers. The present invention constructs a CAM array using 1T-1MTJ cells, combines the advantages of MTJ and CMOS, and realizes less area overhead and lower search latency compared to traditional CMOS-based CAMs while ensuring search energy efficiency by utilizing the unique structure of MTJ, and also realizes non-volatility. The present invention also adopts a two-stage sense amplifier and a segmented design scheme to further improve the search reliability and the scalability of the CAM array.

Description

Technical Field

[0001] The present invention relates to the field of storage, and particularly to a super-compact CAM array based on a single MTJ and an operation method thereof. Consider using the MTJ device for a super-compact high-performance CAM design with non-volatility. Background Art

[0002] With the advent of the big data era, more and more data-intensive applications require in-memory computing (CiM) hardware with parallel data processing capabilities to overcome the "memory wall" bottleneck of the von Neumann architecture, especially for data search operations. As a promising in-memory computing hardware solution, content addressable memory (CAM) realizes parallel search functions by content-addressing a storage array given an input query, and has great potential in various application scenarios such as pattern matching, IP routers, and machine learning.

[0003] Due to the defects of high leakage power consumption and low area density in traditional CMOS-based CAM designs, researchers are looking for device-level alternatives to construct compact CAM arrays. In recent years, many new emerging non-volatile memories (eNVMs) with near-zero leakage power consumption, high storage density, and high switching speed have become ideal choices in the development trend of CAMs. These new non-volatile memories include resistive random access memory (ReRAM), phase-change memory (PCM), ferroelectric field effect transistor (FeFET), and magnetic tunnel junction (MTJ), etc. The high / low resistance states of these new non-volatile storage devices can be encoded as "1" / "0", thus enabling a more compact CAM design.

[0004] Existing MTJ-based CAM technologies can be divided into two categories: one is the CAM cell based on voltage division search, and the other is the CAM cell based on latch search. For the CAM design based on voltage division search, due to the limited switching ratio of MTJ, the search accuracy of CAM is sensitive to the process variations of MTJ. To improve the search reliability, another type of CAM design based on latch search adds differential detection and positive feedback circuits in the cell to increase the detection margin, but this method significantly increases the number of transistors in the cell. In addition, both of the above two technologies use multiple transistors and MTJ pairs for complementary data storage to facilitate search, but this results in a large area overhead, so the compact and CMOS-compatible advantages of MTJ are not fully utilized. Based on the problems existing in the above-mentioned existing technologies, it is necessary to design a new MTJ-based CAM design to reduce the area cost of CAM cells while maintaining high search reliability and high energy efficiency. Summary of the Invention

[0005] The object of the present invention is to provide a CAM design based on a single MTJ to solve the problems of large area cost and poor performance of existing CAMs, achieving lower area overhead and better performance, and proposing a segmentation scheme to improve scalability.

[0006] The object of the present invention is achieved by the following technical solutions:

[0007] A super-compact CAM array based on a single MTJ, the CAM array includes an M*N CAM core for storing content, additional reference rows for storing "0" and "1" and reference columns for storing "0" and "1", a row decoder, a column decoder, a transmission gate EN, a write driver WD, a search current source I search and two-stage sense amplifiers.

[0008] Further, the CAM core includes M*N CAM cells, and each CAM cell is composed of 1 MTJ and 1 NMOS;

[0009] At both ends of the MTJ in the CAM cell, they are respectively connected to the bit line BL and the drain of the NMOS. The gate of the NMOS is connected to the word line WL, and the source of the NMOS is connected to another bit line BLB;

[0010] In the CAM array, the bit lines of each row of CAM cells are connected, and each column shares the same longitudinal WL.

[0011] Further, the row decoder controls the transmission gate EN and the search current source I search, the column decoder controls WL, the write driver WD is divided into write driver WD1 and write driver WD2. Write driver WD1 is connected to BL through transmission gate EN, write driver WD2 is connected to BLB. The BL of each memory row in the CAM core is connected to the positive input terminals of two two-stage sense amplifiers SA. The two-stage sense amplifier SA is divided into two-stage sense amplifier SA0 and two-stage sense amplifier SA1. The BL of the "0" reference row is connected to the negative input terminals of all two-stage sense amplifiers SA0, and the BL of the "1" reference row is connected to the negative input terminals of all two-stage sense amplifiers SA1.

[0012] Further, two types of storage, "0" and "1", are performed on the MTJ by generating bidirectional currents through two write drivers WD for each row.

[0013] Further, during the search, through the search current source I search A read voltage and a reference voltage are respectively generated on the BL of the memory row and the reference row, and the information of whether they match is obtained through two two-stage sense amplifiers SA for each row.

[0014] Further, all 1T-1MTJ cells in the "0" reference row and the "0" reference column store data "0", all 1T-1MTJ cells in the "1" reference row and the "1" reference column store data "1", and at the intersection of the two reference rows and the two reference columns are four 2T cells, which are used to ensure that the reference voltage on the BL of the reference row is different from the read voltages of other memory rows during the search.

[0015] Further, the two-stage sense amplifier SA is composed of a first-stage differential preamplifier and a second-stage dynamic latch voltage comparator.

[0016] The present invention also provides an operation method for the CAM array as described above, and the method includes:

[0017] Before the CAM array starts to work, data is stored in each cell, that is, after encoding the information into a binary sequence, it is written to the 1MTJ through a bidirectional current;

[0018] For each search operation, a two-step search scheme is adopted;

[0019] The first step: Enable the WL corresponding to all "0" bits in the search sequence and the WL of the "0" reference column, set the WL of the remaining columns to 0, ground BLB, apply a search current to generate a read voltage V on the BL of the memory row SEARCH0 , generate a reference voltage V on the BL of the "0" reference row REF0 , when the clock signal CLK is at a high level, the two output terminals of the two-stage sense amplifier SA0 are precharged to a high level; when CLK goes low, if there is a mismatch of storing "1" and searching for "0" in this row, V SEARCH0 is greater than VREF0 , causing the reverse output terminal ML0 of the two-stage detection amplifier SA0 to be pulled down to the ground; if the row matches, ML0 remains high;

[0020] Step 2: Enable the WLs corresponding to all "1" bits in the search sequence and the WLs of the reference column storing "1", set the WLs of the remaining columns to 0, ground BLB, and apply a search current to generate a read voltage V on the storage row BL SEARCH1 , generating a reference voltage V on the reference row BL storing "1" REF1 , when the clock signal CLK is high, the two output terminals of the two-stage detection amplifier SA1 are pre-charged to a high level; when CLK goes low, if there is a mismatch of storing "0" and searching for "1" in this row, V SEARCH1 is less than V REF1 , causing the forward output terminal ML1 of the two-stage detection amplifier SA1 to be pulled down to the ground; if the row matches, ML1 remains high;

[0021] When a segmented design is adopted for long-byte search, the MLs of each segment are short-circuited through a logic circuit to obtain the search results of the first step and / or the second step. In the global detector, the search result of the first step and the search result of the second step are connected to an AND gate through a D latch to obtain the search result of the entire row; observe the output of the AND gate during the search stage of the second step. If it is high, the row matches.

[0022] The beneficial effects of the present invention are as follows:

[0023] (1) For the CAM design of 1T-1MTJ, different from the default CAM unit that uses multiple MTJs for complementary storage and differential detection, each unit of this CAM only contains 1 MTJ and 1 NMOS. By means of an additional reference row and reference column, a two-stage detection amplifier is used to obtain the matching result of the entire row, reducing the search delay while ensuring the search energy efficiency; since the number of devices in the 1T-1MTJ unit is small, the CAM array composed of it significantly improves the area efficiency; since 1T-1MTJ is the mainstream MTJ product design, the CAM of the present invention reduces the design overhead and can bring about a reduction in production cost; in addition, this design can also be adopted by other NVM devices, having universality.

[0024] (2) For the CAM design of 1T-1MTJ, a segmented design can be adopted when performing long-byte search. Each segment is equipped with an additional reference row, reference column, and two-stage detection amplifier. During one search process, each segment performs an in-segment search in parallel. The outputs generated by the two-stage detection amplifier of each segment are short-circuited through a logic circuit, and the search result is obtained through a global detector. This parallel data search design method improves the scalability while ensuring the search reliability. Description of the Drawings

[0025] Figure 1 is the structural diagram of the CAM cell of 1T-1MTJ in (a) and the schematic diagram of its operating principle in (b);

[0026] Figure 2 is V in (a) P and V REF and (b) V AP and V REF voltage comparison schematic diagram and the size relationship diagram of the three in (c);

[0027] Figure 3 is the schematic diagram of the 1T-1MTJ CAM array of size M*N;

[0028] Figure 4 is the symbol of the two-stage detection amplifier in (a), the first-stage differential preamplifier in (b) and the schematic diagram of the second-stage dynamic latch voltage comparator in (c);

[0029] Figure 5 is the schematic diagram of the principle of the first step in (a) and the second step in (b) of the two-step search scheme of the 1T-1MTJ CAM array;

[0030] Figure 6 is the schematic diagram of searching for (a) "1010" and (b) "0110" in the stored content "1010" under the two-step search operation;

[0031] Figure 7 is the schematic diagram of (a) the whole, (b) the logical circuit and the internal structure of the global detector of the segmented design of the 1T-1MTJ CAM array and the schematic diagram of the clock signal and the latch enable signal in (c);

[0032] Figure 8 is the simulation waveform diagram of writing "0" and "1" into the 1T-1MTJ CAM cell;

[0033] Figure 9 is the simulation waveform diagram of searching for "1010" in the stored content "1010", "1011", "0010" and "0011" by the 1T-1MTJ CAM array using the two-step search scheme;

[0034] Figure 10 is the relationship diagram of the minimum write voltage (V WRITE ) required to complete the write operation at different transmission gate transistor widths in the 1T-1MTJ CAM array and the enable voltage (V TG ) on WL and EN and the relationship diagram of the write time and the write energy consumption per bit and V en ) in (b); WRITE ;

[0035] Figure 11is the relationship diagram of the search-error-rate (SER) of the 1T-1MTJ CAM array in the worst case with (a) word length N, (b) TMR rate, (c) power supply voltage V DD and (d) search current;

[0036] Figure 12 is the relationship diagram of (a) the minimum preparation time required for the 1T-1MTJ CAM array to complete the search operation and the bias current of the first-stage differential preamplifier, and the search delay and the search energy consumption per bit with (b) word length N, (c) power supply voltage V DD and (d) search current. Detailed implementation manners

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] 1. 1T-1MTJ cell structure and operation process:

[0039] As Figure 1 (a) shows, the 1T-1MTJ cell includes an MTJ and an NMOS. Both ends of the MTJ device are respectively connected to the bit line BL and the drain of the NMOS. The gate of the NMOS is connected to the word line WL, and the source of the NMOS is connected to another bit line BLB. When the magnetization directions of the free layer and the fixed layer of the MTJ are the same, the MTJ is in the parallel state, and the corresponding equivalent resistance R P is smaller, indicating storing "0"; when the magnetization directions are opposite, the MTJ is in the antiparallel state, and the corresponding equivalent resistance R AP is larger, indicating storing "1". The switching ratio of the MTJ is represented by TMR The bias conditions for the read and write operations of the 1T-1MTJ cell are as Figure 1 (b) shows. When writing data, WL is set to V EN-WRITE to turn on the transistor, and appropriate bias voltages are provided on BL and BLB to generate a large current to control the magnetization direction of the free layer of the MTJ, so as to write "1" or "0". When reading data, as Figure 2 shown, WL is set to V EN-READ to turn on the transistor, and a read current I READ is applied to the cell, so that the read voltage V P (V AP ) corresponding to the "0" ("1") state is generated at the BL node. This voltage is compared with the reference voltage V REF through two-stage detection amplifier SA. It should be noted that Figure 2 (a) and Figure 2 the R REF in (b) is the equivalent resistance of the bias transistor, asFigure 2 As shown in (c), the reference voltage V corresponding to BL REF has a magnitude between V P and V AP to achieve a read operation.

[0040] 2. Overall structure and operation process of the 1T-1MTJ CAM array:

[0041] As Figure 3 shown, in the 1T-1MTJ CAM array, it includes an M*N CAM core for storing content, additional reference rows and columns for storing '0' and '1', a row decoder, a column decoder, a transmission gate EN, a write driver WD, a search current source I search and two-stage sense amplifiers SA, etc. All 1T-1MTJ cells in the reference row and reference column for storing '0' store the data '0', and all 1T-1MTJ cells in the reference row and reference column for storing '1' store the data '1'. Four cells at the intersection of the reference row and reference column are of 2T structure, where one NMOS is also controlled by the word line WL, and the other NMOS is under the control of the gate potential V b , and its equivalent resistance R REF is between R P and R AP to ensure that the reference voltage on the BL of the reference row during the search is different from the read voltage of other storage rows. The BL of the storage row is connected to the positive input terminals of two two-stage sense amplifiers SA, which are the two-stage sense amplifier SA0 and the two-stage sense amplifier SA1 respectively. The BL of the reference row for storing '0' is connected to the negative input terminals of all two-stage sense amplifiers SA0, and the BL of the reference row for storing '1' is connected to the negative input terminals of all two-stage sense amplifiers SA1.

[0042] Figure 4 shows the specific structure of the two-stage sense amplifier SA, which consists of a first-stage differential preamplifier and a second-stage dynamic latch voltage comparator. When the clock signal CLK is at a high level, both output terminals of the two-stage sense amplifier SA are precharged to a high level; when CLK is at a low level, the voltage difference between the two input terminals of the two-stage sense amplifier SA is amplified by the positive feedback of the cross-coupled inverters in the second-stage dynamic latch voltage comparator, causing the output terminals of the two-stage sense amplifier SA to produce a comparison result. If the second-stage dynamic latch voltage comparator is directly used in the two-stage sense amplifier SA, when CLK jumps, due to the unbalanced capacitive loads on the two input terminals of the two-stage sense amplifier SA (i.e., the BLs of the storage row and the reference row), there will be different degrees of feedback noise on the two BLs, resulting in a differential error. Therefore, the present invention introduces a first-stage differential preamplifier to suppress the feedback noise, thereby improving the search reliability.

[0043] The operation process of the entire 1T-1MTJ CAM array is as follows:

[0044] (1) Before the 1T-1MTJ CAM array starts to work, data is stored in each CAM cell first: after encoding the information into binary, by enabling the transmission gate EN and WL, two write drivers WD in each row provide a large enough write current. The write operation is performed row by row, divided into two steps of writing "0" and writing "1". When writing, the transmission gates EN of all unselected rows and the WL of unselected columns should be closed to avoid write interference.

[0045] (2) For each search operation, a two-step search scheme is adopted:

[0046] (2.1) The first step: find out all the non-matching situations of storing "1" and searching for "0". As Figure 5 (a) shows, enable the WL corresponding to all "0" bits in the search sequence and the WL of the storage "0" reference column, set the WL of the remaining columns to 0, ground the BLB, and close the transmission gate. Assume that among the I cells in a certain row participating in the search for "0", K cells store "1", and the actual number of cells storing "0" is I - K. Plus one cell storing "0" in the storage "0" reference column, the resistance after parallel connection of these I + 1 cells is where R on is the on-resistance of the NMOS controlled by WL in each cell. Then, applying the search current I SEARCH generates a read voltage V SEARCH0 on the BL of this row as:

[0047]

[0048] At the same time, I cells storing "0" and one 2T cell are enabled on the storage "0" reference row, and the resistance after parallel connection is Then, applying the search current I SEARCH generates a reference voltage V REF0 on the BL of the storage "0" reference row as:

[0049]

[0050] When CLK is at a high level (pre-charge stage), the two output terminals of the two-stage detection amplifier SA0 are pre-charged to a high level; when CLK becomes low (search stage), if there is a non-matching situation of storing "1" and searching for "0" in this row, V SEARCH0 is greater than V REF0 , causing the reverse output terminal ML0 of the two-stage detection amplifier SA0 to be pulled down to the ground; if this row is matched, V SEARCH0 is less than V REF0 , and ML0 remains at a high level.

[0051] (2.2) Step 2: Identify all the mismatches where the stored value is "0" and the searched value is "1". As shown in Figure 5 (b), enable the WLs corresponding to all the "1" bits in the search sequence and the WL of the stored "1" reference column, set the WLs of the remaining columns to 0, ground the BLB, and turn off the transmission gates. Assume that among the J cells participating in the search for "1" in a certain row, L cells store "0", and the number of cells actually storing "1" is J - L. Plus one cell storing "1" in the stored "1" reference column, the resistance after parallel connection of these J + 1 cells is Then apply the search current I SEARCH to generate the read voltage V SEARCH1 on the BL of this row, which is:

[0052]

[0053] Meanwhile, on the stored "1" reference row, J cells storing "0" and one 2T cell are enabled, and the resistance after parallel connection is Then apply the search current I SEARCH to generate the reference voltage V REF1 on the BL of the stored "1" reference row, which is:

[0054]

[0055] When CLK is at high level (pre-charge stage), the two output terminals of the two-stage sense amplifier SA1 are pre-charged to high level; when CLK goes low (search stage), if there is a mismatch where the stored value is "0" and the searched value is "1" in this row, V SEARCH1 is less than V REF1 , causing the positive output terminal ML1 of the two-stage sense amplifier SA0 to be pulled down to ground; if this row is a match, V SEARCH1 is greater than V REF1 , and ML1 remains at high level.

[0056] Therefore, combining the above two-step search operations, only when ML0 is at high level in the first step and ML1 is at high level in the second step, it indicates that the stored content matches the search sequence; otherwise, there is a mismatch. Figure 6 The following shows an example of the two-step search scheme when the stored content is "1100". When searching for the matching data "1100", as shown in Figure 6 (a), ML0 remains at high level in the first step and ML1 remains at high level in the second step, so the search result is a match. When searching for the mismatching data "0110", as shown in Figure 6 (b), ML1 is pulled down to the bottom in the search stage in the first step and ML1 is pulled down to the bottom in the search stage in the second step, so the search result is a mismatch. By using the above two-step search scheme, the parallel search function is implemented in the 1T-1MTJ CAM array.

[0057] 3. Segmented Design Scheme of 1T-1MTJ CAM Array:

[0058] As the search word length increases, the difference between the read voltage and the reference voltage gradually decreases, which will affect the search reliability. Therefore, the present invention proposes a segmented design scheme to support long-byte search. As Figure 7 shown in (a), the CAM array is segmented, and each segment includes a reference row, a reference column, and two additional detection amplifiers to generate the search results of each segment simultaneously, and then the search results of the entire row are obtained through a logic circuit and a global detector. Figure 7 (b) explains the internal structure of the logic circuit and the global detector. In the logic circuit, the output ML of each segment is shorted together through a conventional inverter and a tilted inverter. The width-to-length ratio β of the NMOS in the tilted inverter is less than the width-to-length ratio α of the PMOS, so that the tilted inverter has a strong pull-down effect. Therefore, only when the outputs of all segments are high, the output after shorting the logic circuits of all segments is high, thus constituting an AND logic. Subsequently, in the global detector, the search result of the first step and the search result of the second step are connected to an AND gate together through a D latch to obtain the search result of the entire row. Figure 7 (c) shows the relationship between the clock signal and the enable signal of the D latch. Finally, observe the output of the global detector in the second search stage. If it is high, it indicates that the row matches; if it is low, it means that at least one segment has a mismatch.

[0059] The functions and effects of the present invention are further illustrated and demonstrated through the following simulation experiments:

[0060] 1. Simulation Conditions

[0061] The experiment uses a compatible SPECTRE and SPICE model based on a physical circuit to simulate the MTJ. This model enables efficient design and analysis. The basic transistors use a 45-nanometer Predictive Technology Model (PTM), the voltage is set to 1.1V, and the key technical parameters of the MTJ set in the simulation are shown in the following table.

[0062]

[0063] During simulation, for the CAM design of 1T-1MTJ, SPECTRE software is used for simulation. In addition to simulating the CAM design in the present invention, we compare our results with Non-Patent Document 1 (A.T. Do, C. Yin, K.S. Yeo, and T.T.-H. Kim, “Design of a power-efficient cam using automated background checking scheme for small match line swing,” in 2013 Proceedings of the ESSCIRC (ESSCIRC). IEEE, 2013, pp. 209–212.), Non-Patent Document 2 (S. Matsunaga, A. Katsumata, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, “Design of a nine-transistor / two-magnetic-tunnel-junction cell-based low-energy nonvolatile ternary content-addressable memory,” Japanese Journal of Applied Physics, vol. 51, no. 2S, p. 02BM06, 2012.), Non-Patent Document 3 (B. Song, T. Na, J.P. Kim, S.H. Kang, and S.-O. Jung, “A 10t-4mtj nonvolatile ternary cam cell for reliable search operation and a compact area,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 6, pp. 700–704, 2016.), Non-Patent Document 4 (C. Wang, D. Zhang, L. Zeng, E. Deng, J. Chen, and W.Zhao, "A novel mtj-based non-volatile ternary content-addressable memory for high-speed, low-power, and high-reliable search operation," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 4, pp. 1454–1464, 2018.) was compared with five CAM designs in Non-Patent Document 5 (C. Wang, D. Zhang, L. Zeng, and W. Zhao, "Design of magnetic nonvolatile tcam with priority-decision in memory technology for high speed, low power, and high reliability," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 2, pp. 464–474, 2019.).

[0064] The comparison metrics mainly include the number of transistors, the area of each CAM cell, the write energy consumption per write to each CAM cell, the search error rate, the search latency, and the search energy consumption per search for each CAM cell. For the CAM design in this invention, the worst-case scenario is adopted for measuring the search error rate and search delay, that is, only one CAM cell does not match; the average of the energy consumption for writing the unit data "0" and the energy consumption for writing the unit data "1" is taken as the write energy consumption; the average case where half of the CAM cells in a row match is adopted for measuring the search energy consumption.

[0065] 2. Simulation Results

[0066] 1) 1T-1MTJ CAM Function Verification

[0067] 1.1) Figure 8 The simulation waveforms of writing "0" and "1" to the 1T-1MTJ CAM cell are given. The MTJ cell is initially in the parallel state, and EN is enabled TGWL is used to control the conduction of the transfer gate EN and the transistor in the 1T-1MTJ cell respectively. SL is set to zero, and the two write drivers WD1 and WD2 are set to 2V and ground respectively to generate a write current, making the MTJ change to the anti-parallel state. Subsequently, the write drivers WD1 and WD2 are set to ground and 2V respectively, causing the MTJ to change back from the anti-parallel state to the parallel state, thus completing the verification of the write function.

[0068] 1.2) Figure 9 The simulation waveforms of the 1T-1MTJ CAM array using a two-step search scheme to search for "1010" in the stored contents "1010", "1011", "0010", and "0011" are given. Enabling SL generates a search current I SEARCH , EN TG is set to zero to turn off the transfer gate. In the first step of the search, WL[P] corresponding to the reference column storing "0" and WL[1] and WL[3] corresponding to all "0" bits in the search sequence are enabled. When CLK is low, the ML0 of the stored contents "1011" and "0011" becomes low, indicating a mismatch of storing "1" and searching for "0". In the second step, WL[AP] corresponding to the reference column storing "1" and WL[2] and WL[4] corresponding to all "0" bits in the search sequence are enabled. When CLK is low, the ML1 of the stored contents "0010" and "0011" becomes low, indicating a mismatch of storing "0" and searching for "1". Combining the above two steps, only the ML0 of the stored content "1010" remains high in the first step and the ML1 remains high in the second step, indicating a match, while the other three rows do not match, thus completing the verification of the search function.

[0069] 2) Write speed and write energy consumption analysis

[0070] The width of the transfer gate transistor, WL, and EN TG The enabling voltage V en on and the write voltage V WRITE on the write driver WD are set, which will affect the write efficiency of the 1T-1MTJ CAM array. Figure 10 (a) shows the minimum V WRITE required to complete the write operation under different transfer gate transistor widths TG and the relationship between V en on WL and EN en . It can be seen that as V WRITE increases, the required minimum V WRITE decreases. At the same time, a larger transfer gate transistor width can also result in a lower minimum V enwith a size of 1.3V, and different Vs were explored in this configuration WRITE write speed and write energy consumption at different sizes Figure 10 As shown in (b), as V WRITE increases, the write time becomes shorter. When V WRITE is 2V, each write can be Figure 8 completed within 20ns as shown, and the average energy consumption per write is 1.26 pJ / bit.

[0071] 3) Search reliability analysis

[0072] On the premise that the process variation rates of the TMR ratio, oxide layer thickness, and free layer thickness of the MTJ are set to 3%, and the process variation rates of the width and threshold voltage of the transistor are set to 10%, a Monte Carlo simulation with only one CAM cell mismatch is performed to obtain the search error rate (SER) for search reliability analysis. Figure 11 (a) shows that as the search word length N increases, the SER also gradually increases. Therefore, a segmented design is needed to ensure search reliability. On the other hand, as Figure 11 shown in (b), an increase in the TMR ratio of the MTJ leads to an increase in the read voltage difference between different states of the 1T-1MTJ CAM cell, thus reducing the SER. At the same time, when the power supply voltage increases, the current difference between the two discharge branches in the second-stage dynamic latch voltage comparator of the SA also increases, resulting in a reduction in the SER. Figure 11 (d) shows that when the search current I SEARCH is too small, it is difficult for the SA to accurately compare the voltage difference, thus introducing additional SER. However, when I SEARCH is greater than 25 μA, the impact on the SER can be ignored.

[0073] 4) Search latency and search energy consumption analysis

[0074] After confirming the search reliability of the 1T-1MTJ CAM design, it is also necessary to analyze the search latency and search energy consumption. During the pre-charge stage (CLK is high), not only the output of the SA needs to be pre-charged to a high level, but the first-stage differential pre-amplifier also needs to prepare two voltage signals for comparison at the input of the second stage, enabling the SA to generate a comparison result when CLK goes low. Therefore, when increasing the bias current to improve the bandwidth of the first stage, as Figure 12 (a) shows, the time required for the pre-charge stage will decrease. In addition, Figure 12 (b) shows that the search latency increases with the increase in the word length N, which is caused by the increase in the parasitic capacitance on the BL. At the same time, the unit search energy consumption shows the opposite trend, and there are two reasons for this phenomenon: (1) the voltage on the BL decreases as the word length N increases, and (2) the search time does not increase significantly with the increase in the word length N. Figure 12(c) indicates that a higher power supply voltage can reduce the search latency, thereby further improving the search energy efficiency. Figure 12 (d) indicates that as SEARCH I increases, the voltage difference between the read voltage and the reference voltage increases, thereby reducing the search latency, but at the same time, it will also reduce the search energy efficiency.

[0075] 5) Performance comparison

[0076] The following table gives a comparison of various indicators between the CAM design based on a single MTJ in the present invention and other CAM designs.

[0077]

[0078]

[0079] The above table summarizes the technical indicators of 1T-1MTJ CAM and other CAMs, where the segmented word length of 1T-1MTJ CAM is set to 16 bits per segment. It can be seen from the above table that the cell area of the 1T-1MTJ CAM of the present invention is 1.82% of the 10T cell based on traditional CMOS technology, and this advantage is further amplified when compared with other MTJ-based CAMs. Although 1T-1MTJ CAM requires reference rows, reference columns, and SA to complete the search operation, these additional area overheads can be ignored during long-byte searches, and the search latency of 1T-1MTJ CAM is only 16% of that of 10T CAM. Although the search energy consumption of 15T-4MTJ / 20T-6MTJ CAM is lower than that of 1T-1MTJ CAM, their area overheads are much larger. In addition, when increasing the segmented word length, the search energy consumption of 1T-1MTJ CAM will be further reduced. At the same time, since there are fewer MTJs and transistors in the write path of 1T-1MTJ CAM, the write energy efficiency is increased by 4.60 times / 1.26 times / 1.89 times compared with 10T-4MTJ / 15T-4MTJ / 20T-6MTJ CAM. Although the write energy consumption of 9T-2MTJ CAM is lower, the search error rate of 1T-1MTJ CAM is only 28% of that of 9T-2MTJ CAM.

[0080] It can be seen from the above results that the present invention not only has non-volatility that is difficult to achieve in CMOS design and robustness against process variations, but also has the characteristics of compact design, low energy consumption, and low latency. In addition, the above results also verify the effectiveness of the 1T-1MTJ CAM array adopting a two-step search scheme and segmented design in data-intensive search applications.

[0081] The above embodiments are used to explain the present invention rather than limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims of the present invention fall within the protection scope of the present invention.

Claims

1. A super-compact CAM array based on a single MTJ, characterized in that, The CAM array includes an M*N CAM core for storing content, additional reference rows for storing "0" and "1", reference columns for storing "0" and "1", a row decoder, a column decoder, a transmission gate EN, a write driver WD, a search current source I search and two-stage sense amplifiers; The CAM core includes M*N CAM cells, and each CAM cell is composed of 1 MTJ and 1 NMOS; both ends of the MTJ in the CAM cell are respectively connected to the bit line BL and the drain of the NMOS, the gate of the NMOS is connected to the word line WL, and the source of the NMOS is connected to another bit line BLB; in the CAM array, the bit lines of each row of CAM cells are connected, and each column shares the same longitudinal WL; The row decoder controls the transmission gate EN and the search current source I search , the column decoder controls WL, the write driver WD is divided into write driver WD1 and write driver WD2. Write driver WD1 is connected to BL through the transmission gate EN, write driver WD2 is connected to BLB. The BL of each memory row in the CAM core is connected to the positive input terminals of two two-stage sense amplifiers SA. The two-stage sense amplifiers SA are divided into two-stage sense amplifier SA0 and two-stage sense amplifier SA1. The BL of the "0" reference row is connected to the negative input terminals of all two-stage sense amplifiers SA0, and the BL of the "1" reference row is connected to the negative input terminals of all two-stage sense amplifiers SA1.

2. The ultra-compact CAM array based on a single MTJ according to claim 1, wherein, Two types of storage, "0" and "1", are performed on the MTJ through bidirectional currents generated by two write drivers WD in each row.

3. The ultra-compact CAM array based on a single MTJ according to claim 1, characterized in that During search, through the search current source I search A read voltage and a reference voltage are respectively generated on the BLs of the storage row and the reference row, and information on whether there is a match is obtained through two two-stage sense amplifiers SA in each row.

4. A super-compact CAM array based on a single MTJ according to claim 1, characterized in that All 1T-1MTJ cells in the "0" storage reference row and the "0" storage reference column store the data "0", and all 1T-1MTJ cells in the "1" storage reference row and the "1" storage reference column store the data "1". At the intersection of the two reference rows and the two reference columns are four 2T cells, which are used to ensure that the reference voltage on the BL of the reference row is different from the read voltage of other storage rows during the search.

5. A super-compact CAM array based on a single MTJ according to claim 1, characterized in that, The two-stage detection amplifier SA is composed of a first-stage differential preamplifier and a second-stage dynamic latch voltage comparator.

6. A method for operating a CAM array according to any one of claims 1-5, characterized in that, The method includes: Before the CAM array starts to work, data is stored in each cell, that is, after the information is encoded into a binary sequence, it is written to the 1MTJ through a bidirectional current; For each search operation, a two-step search scheme is adopted; Step 1: Enable the WLs corresponding to all "0" bits in the search sequence and the WL storing the "0" reference column, set the WLs of the remaining columns to 0, ground the BLB, and apply a search current to generate a read voltage V on the storage row BL SEARCH0 , and generate a reference voltage V on the "0" storing reference row BL REF0 . When the clock signal CLK is high, pre-charge the two output terminals of the two-stage sense amplifier SA0 to a high level; when CLK goes low, if there is a mismatch of storing "1" and searching "0" in this row, V SEARCH0 is greater than V REF0 , causing the reverse output terminal ML0 of the two-stage sense amplifier SA0 to be pulled down to ground; if this row is matched, ML0 remains at a high level; Step 2: Enable the WLs corresponding to all "1" bits in the search sequence and the WL of the reference column storing "1", set the WLs of the remaining columns to 0, ground BLB, and apply a search current to generate a read voltage V on the storage row BL. SEARCH1 , and generate a reference voltage V on the reference row BL storing "1". REF1 , when the clock signal CLK is at a high level, pre-charge the two output terminals of the two-stage sense amplifier SA1 to a high level; when CLK goes low, if there is a mismatch of storing "0" and searching for "1" in this row, V SEARCH1 is less than V REF1 , causing the positive output terminal ML1 of the two-stage sense amplifier SA1 to be pulled down to ground; if this row is matched, ML1 remains at a high level. When a segmented design is adopted for long-byte search, the ML of each segment is short-circuited through a logic circuit to obtain the search results of the first step and / or the second step. In the global detector, the search results of the first step pass through a D latch and are connected to an AND gate together with the search results of the second step to obtain the search results of the entire row; observe the output of the AND gate during the second-step search stage. If it is high level, the row matches.

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