A circuit structure, chip and module based on 8T-SRAM unit

Abstract

The present invention relates to a circuit structure, chip, and module based on an 8T-SRAM cell. The 8T-SRAM cell includes: NMOS transistors N1-6; and PMOS transistors P1-2. P1 and P2 are cross-coupled with N1 and N2 to latch data on storage nodes Q and QB. The source of P1 and P2 are electrically connected to VDD, enabling power supply paths for storage nodes Q and QB. The source of N1 and N2 are connected to VSS, enabling ground paths for storage nodes Q and QB. Storage nodes Q and QB are connected to bit lines BL and BLB, respectively, via transistors N4 and N3. Transistors N3 and N4 are controlled by word line WL. Word lines LCM and RCM are connected to bit lines SLB and SL, respectively, via transistors N5 and N6. Transistors N5 and N6 are controlled by storage nodes Q and QB, respectively. The present invention enables comparison operations to be performed within the memory, improving search efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of static random access memory (SRAM), and in particular to a circuit structure, chip and module based on an 8T-SRAM unit. Background Art

[0002] As artificial intelligence technology expands into more and more devices, the demand for computing efficiency and energy consumption is increasing. In the traditional von Neumann architecture, the computing module and memory are separated. When data is needed during the calculation process, it must be read from the memory and transferred to the computing module. However, the current development of computing module computing power has far exceeded the development of memory access speed. Therefore, a large amount of running time and power consumption is spent waiting for data, which increases and wastes running time. Summary of the Invention

[0003] In order to reduce the time spent on data movement in the computing process, a circuit structure, chip and module based on 8T-SRAM unit are proposed.

[0004] The present invention is achieved by adopting the following technical solutions:

[0005] An 8T-SRAM cell, comprising:

[0006] NMOS transistor N1;

[0007] an NMOS transistor N2, wherein a gate of N2 is electrically connected to a gate of N1, a source of N2 is electrically connected to a source of N1, and a drain of N2 is electrically connected to a gate of N1;

[0008] NMOS transistor N3, wherein the drain of N3 is electrically connected to the drain of N1 and the gate of N2, the gate of N3 is electrically connected to the word line WL, and the source of N3 is electrically connected to the bit line BLB;

[0009] an NMOS transistor N4, wherein a drain of N4 is electrically connected to a drain of N2 and a gate of N1, a gate of N4 is electrically connected to a word line WL, and a source of N4 is electrically connected to a bit line BL;

[0010] NMOS transistor N5, the gate of N5 is electrically connected to the drain of N4, the drain of N2, and the gate of N1, the source of N5 is electrically connected to the bit line SLB, and the drain of N5 is electrically connected to the word line LCM;

[0011] NMOS transistor N6, the gate of N6 is electrically connected to the drain of N3, the drain of N1, and the gate of N2, the source of N6 is electrically connected to the bit line SL, and the drain of N6 is electrically connected to the word line RCM;

[0012] PMOS transistor P1, the gate of P1 is electrically connected to the gate of N1, the drain of N4, and the gate of N5, the drain of P1 is electrically connected to the drain of N1, the drain of N3, the gate of N6, and the gate of N2, and the source of P1 is electrically connected to the source of P2;

[0013] PMOS transistor P2, the gate of P2 is electrically connected to the gate of N2, the drain of N3, and the gate of N6, the drain of P2 is electrically connected to the drain of N2, the drain of N4, the gate of N5, and the gate of N1, and the source of P2 is electrically connected to the source of P1;

[0014] Transistors P1 and P2 are cross-coupled with transistors N1 and N2 to latch data on storage nodes Q and QN. The source of transistors P1 and P2 are electrically connected to VDD, opening a path for storage nodes Q and QB to the power supply. The source of transistors N1 and N2 are connected to VSS, opening a path for storage nodes Q and QB to the ground.

[0015] Storage nodes Q and QB are connected to bit lines BL and BLB respectively through transistors N4 and N3, which are controlled by word line WL. Word lines LCM and RCM are connected to bit lines SLB and SL respectively through transistors N5 and N6, which are controlled by storage nodes Q and QB respectively.

[0016] Furthermore, in the pre-charge phase, the word lines LCM and RCM of the cell are maintained at a high level, and the bit lines SL and SLB are also pre-charged to a high level. The internal storage nodes Q and QB act on transistors N5 and N6 to control the opening and closing of the transistors. Assuming that the data stored in the cell is '1', that is, "Q=1, QB=0", in the search phase, the search data is loaded onto the bit lines SL and SLB. Assuming that "SL=0, SLB=1", transistor N5 is turned on and N6 is turned off. LCM and RCM are output as a high level '1' after being acted upon by the SA sensitive amplifier and the AND gate, that is, the data matches; on the contrary, if the search data is "SL=1, SLB=0", the word line LCM is at a high level and the bit line SLB is at a low level, the output is '0' after being outputted by SA, and then a logical AND is performed with the word line RCM, the output is '0', that is, the data does not match.

[0017] The present invention also includes a circuit structure for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, characterized in that it uses the aforementioned 8T-SRAM cells, and the circuit structure includes N*N 8T-SRAM cells;

[0018] Among them, in the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL; the drains of all transistors N5 are electrically connected to the word line LCM; and the drains of all transistors N6 are electrically connected to the word line RCM.

[0019] In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB; the sources of all transistors N4 are electrically connected to the bit line BL; the sources of all transistors N5 are electrically connected to the bit line SLB; and the sources of all transistors N6 are electrically connected to the bit line SL.

[0020] In one embodiment, it includes 2*2 8T-SRAM cells; wherein, in two 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL; the drains of all transistors N5 are electrically connected to the word line LCM; and the drains of all transistors N6 are electrically connected to the word line RCM.

[0021] In two 8T-SRAM cells in the same column, sources of all transistors N3 are electrically connected to bit line BLB; sources of all transistors N4 are electrically connected to bit line BL; sources of all transistors N5 are electrically connected to bit line SLB; and sources of all transistors N6 are electrically connected to bit line SL.

[0022] Furthermore, in the precharge stage of the circuit structure, word lines LCM and RCM are precharged to a high level, bit lines SL and SLB are precharged to a high level, and the two rows of cells that are turned on are respectively denoted as A and B. Assume that the data stored in A is "Q=1, QB=0", and the data stored in B is "Q=0, QB=1";

[0023] In the calculation stage, the word lines LCM and RCM in A and B are all grounded and discharged to a low level. The LCM and RCM of the word lines in other rows are kept at VDD. SLB outputs '0' through SA, that is, "NOR (A, B) = 0", then the other end of SA outputs '1', that is, "OR (A, B) = 1", SL outputs '0' through SA, that is, "AND (A, B) = 0", then the other end of SA outputs '1', that is, "NAND (A, B) = 1". As long as one of the data stored in A or B is '0', SL and SLB will discharge to the ground, and the output result is the same as above; when the data stored in A and B are both '1', that is, "Q = 1, QB = 0" in A and B, SLB outputs '0' through SA, that is, Then the output of the other end of SA is '1', that is, "A+B=1", the output of SL through SA is '1', that is, "AB=1", then the output of the other end of SA is '0', that is When the data stored in A and B are both '0', that is, "Q=0, QB=1" in A and B, SLB outputs '1' through SA, that is, Then the output of the other end of SA is '0', that is, "A+B=0", and the output of SL through SA is '0', that is, "AB=0", then the output of the other end of SA is '0', that is,

[0024] In one embodiment, it includes 4*4 8T-SRAM cells; wherein, in the four 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL, the drains of all transistors N5 are electrically connected to the word line LCM, and the drains of all transistors N6 are electrically connected to the word line RCM;

[0025] In the four 8T-SRAM cells in the same column, sources of all transistors N3 are electrically connected to bit line BLB, sources of all transistors N4 are electrically connected to bit line BL, sources of all transistors N5 are electrically connected to bit line SLB, and sources of all transistors N6 are electrically connected to bit line SL.

[0026] Furthermore, the circuit structure precharges the word lines LCM and RCM to a high level in the precharge phase, and precharges the search bit lines SL and SLB to a high level. In the search phase, data is loaded onto SL and SLB. Assuming that the search data is "1010", that is, "SL <0> =1, SL <1> =0, SL <2> =1, SL <3> =0, SLB <0> =0, SLB <1> =1, SLB <2> =0, SLB <3> =1", according to the data stored in the array, when the 0th row is consistent with the search data, that is, the stored data in QB is consistent with the search data on SL, both are "1010", the output is '1', and the output of the remaining rows is '0', indicating a mismatch.

[0027] The present invention also includes an 8T-SRAM chip, which is packaged using the aforementioned 8T-SRAM unit; the pins of the 8T-SRAM chip include:

[0028] A first pin electrically connected to the gates of transistors N3 and N4 through a word line WL;

[0029] a second pin electrically connected to the drain of the transistor N5 through the word line LCM;

[0030] a third pin electrically connected to the drain of the transistor N6 through the word line RCM;

[0031] a fourth pin electrically connected to the source of the transistor N3 through the bit line BLB;

[0032] a fifth pin electrically connected to the source of the transistor N4 through the bit line BL;

[0033] a sixth pin electrically connected to the source of the transistor N5 through the bit line SLB;

[0034] The seventh pin is electrically connected to the source of the transistor N6 through the bit line SL.

[0035] The present invention also includes a circuit chip for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, characterized in that it is encapsulated using the aforementioned circuit structure for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells; the pins of the circuit chip for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells include:

[0036] In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL, thereby leading to the first pin; the drains of all transistors N5 are electrically connected to the word line LCM, thereby leading to the second pin; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to the third pin. Each row has one first pin, one second pin, and one third pin.

[0037] In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, from which the fourth pin is led out; the sources of all transistors N4 are electrically connected to the bit line BL, from which the fifth pin is led out; the sources of all transistors N5 are electrically connected to the bit line SLB, from which the sixth pin is led out; the sources of all transistors N6 are electrically connected to the bit line SL, from which the seventh pin is led out. There is one fourth pin, one fifth pin, one sixth pin and one seventh pin in each column.

[0038] The present invention also includes a circuit module for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, characterized in that it adopts the circuit structure of the aforementioned circuit module for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, and the circuit module for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells includes:

[0039] In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to WL, thereby leading to a first connection terminal; the drains of all transistors N5 are electrically connected to the word line LCM, thereby leading to a second connection terminal; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to a third connection terminal; each row has one first connection terminal, one second connection terminal, and one third connection terminal;

[0040] In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, thereby leading to the fourth connection terminal; the sources of all transistors N4 are electrically connected to the bit line BL, thereby leading to the fifth connection terminal; the sources of all transistors N5 are electrically connected to the bit line SLB, thereby leading to the sixth pin; the sources of all transistors N6 are electrically connected to the bit line SL, thereby leading to the seventh connection terminal. There is one fourth connection terminal, one fifth connection terminal, one sixth pin and one seventh connection terminal in each column.

[0041] The technical solution provided by the present invention has the following beneficial effects:

[0042] By using a circuit structure based on in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, column-wise Boolean logic operations and row-wise addressing functions can be implemented. The above circuit can be used for in-memory Boolean logic operations and unidirectional BCAM operations, ensuring the independence of stored data, improving the stability of the cells, greatly enhancing the operational efficiency, and exhibiting good structural symmetry. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Schematic diagram of the structure of the 8T-SRAM unit of the present invention;

[0044] Figure 2 For Figure 1 Schematic diagram of the structure of 8T-SRAM cells distributed in a 2*2 array based on 8T-SRAM cells;

[0045] Figure 3 for Figure 2 Simulation diagram of Boolean logic operation;

[0046] Figure 4 For Figure 1 Schematic diagram of the structure of 8T-SRAM cells distributed in a 4*4 array based on 8T-SRAM cells;

[0047] Figure 5 for Figure 4 Simulation diagram of row-wise BCAM search in ;

[0048] Figure 6 For Figure 1 Schematic diagram of the structure of an 8T-SRAM chip based on the 8T-SRAM unit. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0050] like Figure 1 As shown, this embodiment provides an 8T-SRAM cell, which includes an NMOS transistor N1, a MOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, an NMOS transistor N6, a PMOS transistor P1, and a PMOS transistor P2.

[0051] The gate of N2 is electrically connected to the gate of N1, the source of N2 is electrically connected to the source of N1, and the drain of N2 is electrically connected to the gate of N1. The drain of N3 is electrically connected to the drain of N1 and the gate of N2, the gate of N3 is electrically connected to word line WL, and the source of N3 is electrically connected to bit line BLB. The drain of N4 is electrically connected to the drain of N2 and the gate of N1, the gate of N4 is electrically connected to word line WL, and the source of N4 is electrically connected to bit line BL. The gate of N5 is electrically connected to the drain of N4, the drain of N2, and the gate of N1, the source of N5 is electrically connected to bit line SLB, and the drain of N5 is electrically connected to word line LCM. The gate of N6 is electrically connected to the drain of N3, the drain of N1, and the gate of N2, the source of N6 is electrically connected to bit line SL, and the drain of N6 is electrically connected to word line RCM. The gate of P1 is electrically connected to the gate of N1, the drain of N4, and the gate of N5. The drain of P1 is electrically connected to the drain of N1, the drain of N3, the gate of N6, and the gate of N2. The source of P1 is electrically connected to the source of P2. The gate of P2 is electrically connected to the gate of N2, the drain of N3, the gate of N6, and the drain of P1. The drain of P2 is electrically connected to the drain of N2, the drain of N4, the gate of N5, and the gate of N1. Transistors P1 and P2 are cross-coupled with transistors N1 and N2 to latch data at storage nodes Q and QN. The source of transistors P1 and P2 is electrically connected to VDD, enabling storage nodes Q and QB to pass through the power supply. The source of transistors N1 and N2 is connected to VSS, enabling storage nodes Q and QB to pass through the ground.

[0052] Storage nodes Q and QB are connected to bit lines BL and BLB respectively through transistors N4 and N3, which are controlled by word line WL. Word lines LCM and RCM are connected to bit lines SLB and SL respectively through transistors N5 and N6, which are controlled by storage nodes Q and QB respectively.

[0053] The cross-coupling connection is described in detail, that is, the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1, the drain of the PMOS transistor P1 is electrically connected to the drain of the NMOS transistor N1, the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2, the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N2, the gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P2, and the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P1, so that the data of the storage nodes Q and QN are latched.

[0054] The implementation principle of an 8T-SRAM cell is as follows: During the precharge phase, word lines LCM and RCM remain high, and bit lines SL and SLB are also precharged high. Internal storage nodes Q and QB act on transistors N5 and N6, controlling their on and off switching. Assuming the cell stores a '1' value (Q = 1, QB = 0), during the search phase, the search data is loaded onto bit lines SL and SLB. Assuming SL = 0, SLB = 1, transistors N5 turn on and N6 turn off. Because both bit line SLB and word line LCM are high, charge sharing does not occur. Therefore, after the SA sense amplifier and AND gate, LCM and RCM outputs are high, indicating a data match. On the contrary, if the search data is "SL=1, SLB=0", because transistor N5 is turned on and N6 is turned off, the word line LCM is at a high level and the bit line SLB is at a low level, the two will share charge, causing the word line LCM voltage to drop, and the output is '0' after passing through SA. After performing logical AND with the word line RCM, the output is '0', that is, the data does not match. Therefore, as long as the data on the bit line SLB is different from the data stored in Q, or the data on the bit line SL is different from the data stored in QB, it will be displayed as a mismatch, that is, the output is '0', otherwise it will be displayed as a match output '1'.

[0055] The 8T-SRAM cell of the present invention can be used to form various in-memory Boolean logic operations and unidirectional BCAM circuit structures, forming a circuit structure of in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, and the circuit structure can include N*N 8T-SRAM cells.

[0056] For N*N 8T-SRAM cells, in the same row of 8T-SRAM cells, the gates of all transistors N3 and N4 are electrically connected to word line WL; the drains of all transistors N5 are electrically connected to word line LCM; and the drains of all transistors N6 are electrically connected to word line RCM. For the same column of 8T-SRAM cells, the sources of all transistors N3 are electrically connected to bit line BLB; the sources of all transistors N4 are electrically connected to bit line BL; the sources of all transistors N5 are electrically connected to bit line SLB; and the sources of all transistors N6 are electrically connected to bit line SL.

[0057] For the N*N 8T-SRAM cells in the array structure, the circuit structure is symmetrical, so N is an even number.

[0058] Taking the SRAM mode as an example, based on the above N*N 8T-SRAM cells, the SRAM mode is performed as follows:

[0059] S1. Keep operating

[0060] During the period when the memory cell holds data, the word line WL remains at a low level, causing the NMOS transistors N3 and N4 to be turned off, and the bit lines BL and BLB to be precharged to a high level. The internal circuit remains in its initial state and the circuit does not work.

[0061] S2. Write operation

[0062] In the data writing phase, word line WL is at a high level. If bit line BL is at a high level and bit line BLB is at a low level, then '1' is written to storage node Q through transistor N4. If bit line BL is at a low level and bit line BLB is at a high level, then '1' is written to storage node QB through transistor N3.

[0063] S3, read operation

[0064] During the data reading phase, both bit lines BL and BLB are precharged to a high level, the word line WL is at a high level, and the transfer transistors N3 and N4 are turned on. If the data stored in the circuit is '0', then "Q=0, QB=1", and the bit line BL will be discharged to ground through transistors N4 and N2, causing a voltage difference between the bit lines BLB and BL, and then the data is read out through the sense amplifier. If the data stored in the circuit is '1', then "Q=1, QB=0", and the bit line BLB will be discharged to ground through transistors N3 and N1, causing a voltage difference between the bit lines BLB and BL, and then the data is read out through the sense amplifier.

[0065] like Figure 2As shown, taking 2*2 8T-SRAM cells as an example, in-memory calculation is performed using Boolean logic. In the two 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL; the drains of all transistors N5 are electrically connected to the word line LCM; and the drains of all transistors N6 are electrically connected to the word line RCM.

[0066] In two 8T-SRAM cells in the same column, sources of all transistors N3 are electrically connected to bit line BLB; sources of all transistors N4 are electrically connected to bit line BL; sources of all transistors N5 are electrically connected to bit line SLB; and sources of all transistors N6 are electrically connected to bit line SL.

[0067] For 2*2 8T-SRAM cells, the implementation principle is as follows: between the same columns, the word lines LCM and RCM are controlled to be turned on and off, and two-row logical AND, NAND, OR, and NOR operations are implemented through SL and SLB. In the precharge phase, word lines LCM and RCM are precharged to a high level, and bit lines SL and SLB are precharged to a high level. The two rows of cells that are turned on are denoted as A and B, respectively. Assume that the data stored in A is "Q=1, QB=0", and the data stored in B is "Q=0, QB=1". In the calculation phase, word lines LCM and RCM in A and B are all grounded and discharged to a low level. The LCM and RCM of the word lines in the remaining rows are maintained at VDD. This turns on transistor N5 in A and transistor N6 in B, causing SL and SLB to be discharged to ground through transistors N6 in B and N5 in A, respectively. SLB outputs '0' through SA, i.e., "NOR(A, B)=0", and the other end of SA outputs '1', i.e., "OR(A, B)=1". SL outputs '0' through SA, i.e., "AND(A, B)=0", and the other end of SA outputs '1', i.e., "NAND(A, B)=1". As long as one of the data stored in A or B is '0', SL and SLB will discharge to the ground, and the output result is the same as above. When the data stored in A and B are both '1', that is, "Q=1, QB=0" in A and B, this will turn on the N5 transistor in A and the N5 transistor in B, causing SLB to discharge to the ground through the transistors N5 in A and B, while SL remains at a high level. SLB outputs '0' through SA, that is Then the output of the other end of SA is '1', that is, "A+B=1", the output of SL through SA is '1', that is, "AB=1", then the output of the other end of SA is '0', that is,

[0068] When the data stored in A and B are both '0', that is, "Q=0, QB=1" in A and B, the N6 transistor in A is turned on, and the N6 transistor in B is turned on, causing SL to discharge to the ground through the transistors N6 in A and B, while SLB remains at a high level. SLB is output as '1' through SA, that is Then the output of the other end of SA is '0', that is, "A+B=0", the output of SL through SA is '0', that is, "AB=0", then the output of the other end of SA is '0', that is, The truth table is as follows:

[0069] Boolean logic truth table

[0070] A B NOR OR NAND AND 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1

[0071] Combine Figure 3 As shown, the storage nodes are '1' and '0' respectively, that is, the Boolean logic operation simulation results obtained when the data "Q=1, QB=0" is stored in A and the data "Q=0, QB=1" is stored in B. According to the results, it can be seen that the output is consistent with the Boolean logic calculation, NOR(A, B)=0, OR(A, B)=1, NAND(A, B)=1, AND(A, B)=0, thereby realizing the vertical in-memory Boolean logic operation.

[0072] like Figure 4 As shown, a horizontal BCAM data search operation is performed using 4*4 8T-SRAM cells as an example. In the four 8T-SRAM cells in the same row, the gates of all transistors N3 and N4 are electrically connected to word line WL, the drains of all transistors N5 are electrically connected to word line LCM, and the drains of all transistors N6 are electrically connected to word line RCM. In the four 8T-SRAM cells in the same column, the sources of all transistors N3 are electrically connected to bit line BLB, the sources of all transistors N4 are electrically connected to bit line BL, the sources of all transistors N5 are electrically connected to bit line SLB, and the sources of all transistors N6 are electrically connected to bit line SL.

[0073] In the 4*4 8T-SRAM cells of this embodiment, the implementation principle is as follows: before data search, the memory cell writes data to the Q point for storage through the SRAM write mode. In the pre-charge phase, the word lines LCM and RCM are pre-charged to a high level, and the search bit lines SL and SLB are pre-charged to a high level. In the search phase, data is loaded onto SL and SLB. In this example, the search data is "1010", that is, "SL <0> =1, SL <1> =0, SL <2> =1, SL <3> =0, SLB <0> =0, SLB <1> =1, SLB <2> =0, SLB <3> =1". According to the data stored in the array, only row 0 is consistent with the search data, that is, the stored data in QB is consistent with the search data on SL, both are "1010", and the output is '1'. The output of the remaining rows is '0', indicating a mismatch.

[0074] Combine Figure 4 , the search data is "1010", and the QB storage data from the first row to the fourth row are "1010, 0101, 0111, 0100" respectively.

[0075] Combine Figure 5 , the search data is "1010", and the QB storage data from the first to the fourth row are "1010, 0101, 0111, 0100". From the output results, it can be seen that only the 0th row is consistent with the search data, so the output result of the 0th row is '1', which means it matches. The remaining rows are inconsistent with the search data and the output is '0', which means it does not match.

[0076] In summary, vertical in-memory logical operations and horizontal BCAM data search operations can be performed, and data independence during operation is guaranteed, thereby improving the unit's anti-interference capability.

[0077] Based on the aforementioned 8T-SRAM unit, an 8T-SRAM chip is further provided. The chip is packaged by the aforementioned 8T-SRAM unit. The chip packaging mode makes it easier to promote and apply the 8T-SRAM unit.

[0078] Among them, Figure 6 As shown, the pins of the 8T-SRAM chip include:

[0079] A first pin electrically connected to the gates of transistors N3 and N4 through a word line WL;

[0080] a second pin electrically connected to the drain of the transistor N5 through the word line LCM;

[0081] a third pin electrically connected to the drain of the transistor N6 through the word line RCM;

[0082] a fourth pin electrically connected to the source of the transistor N3 through the bit line BLB;

[0083] a fifth pin electrically connected to the source of the transistor N4 through the bit line BL;

[0084] a sixth pin electrically connected to the source of the transistor N5 through the bit line SLB;

[0085] The seventh pin is electrically connected to the source of the transistor N6 through the bit line SL.

[0086] Based on the above, a circuit chip for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells is further provided. The chip is packaged by N*N 8T-SRAM cells mentioned above. The packaging mode of the chip makes it easier to promote and apply the 8T-SRAM cell circuit.

[0087] Among them, the pins of the circuit chip based on the in-memory Boolean logic operation and unidirectional BCAM of the 8T-SRAM cell include:

[0088] In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL, from which the first pin is derived; the drains of all transistors N5 are electrically connected to the word line LCM, from which the second pin is derived; and the drains of all transistors N6 are electrically connected to the word line RCM, from which the third pin is derived. Each row has one first pin, one second pin, and one third pin.

[0089] In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, from which the fourth pin is led out; the sources of all transistors N4 are electrically connected to the bit line BL, from which the fifth pin is led out; the sources of all transistors N5 are electrically connected to the bit line SLB, from which the sixth pin is led out; the sources of all transistors N6 are electrically connected to the bit line SL, from which the seventh pin is led out. There is a fourth pin, a fifth pin, a sixth pin, and a seventh pin in each column.

[0090] Based on the above, this embodiment further includes a circuit module for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells, which uses the circuit in the aforementioned circuit structure of in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells. The circuit module for in-memory Boolean logic operations and unidirectional BCAM based on 8T-SRAM cells includes:

[0091] In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to WL, thereby leading to a first connection terminal; the drains of all transistors N5 are electrically connected to the word line LCM, thereby leading to a second connection terminal; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to a third connection terminal. Each row has a first connection terminal, a second connection terminal, and a third connection terminal.

[0092] In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, thereby leading to the fourth connection terminal; the sources of all transistors N4 are electrically connected to the bit line BL, thereby leading to the fifth connection terminal; the sources of all transistors N5 are electrically connected to the bit line SLB, thereby leading to the sixth pin; the sources of all transistors N6 are electrically connected to the bit line SL, thereby leading to the seventh connection terminal. Each column has a fourth connection terminal, a fifth connection terminal, a sixth pin and a seventh connection terminal.

[0093] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that variations and improvements are possible within the scope of the present invention, as would be apparent to one skilled in the art. These variations and improvements fall within the scope of the present invention. Therefore, the scope of the present invention is governed by the appended claims.

Claims

1. An 8T-SRAM cell, characterized in that: It includes: NMOS transistor N1; an NMOS transistor N2, wherein the gate of N2 is electrically connected to the drain of N1, the source of N2 is electrically connected to the source of N1, and the drain of N2 is electrically connected to the gate of N1; NMOS transistor N3, wherein the drain of N3 is electrically connected to the drain of N1 and the gate of N2, the gate of N3 is electrically connected to the word line WL, and the source of N3 is electrically connected to the bit line BLB; an NMOS transistor N4, wherein a drain of N4 is electrically connected to a drain of N2 and a gate of N1, a gate of N4 is electrically connected to a word line WL, and a source of N4 is electrically connected to a bit line BL; NMOS transistor N5, the gate of N5 is electrically connected to the drain of N4, the drain of N2, and the gate of N1, the source of N5 is electrically connected to the bit line SLB, and the drain of N5 is electrically connected to the word line LCM; NMOS transistor N6, the gate of N6 is electrically connected to the drain of N3, the drain of N1, and the gate of N2, the source of N6 is electrically connected to the bit line SL, and the drain of N6 is electrically connected to the word line RCM; PMOS transistor P1, the gate of P1 is electrically connected to the gate of N1, the drain of N4, and the gate of N5, the drain of P1 is electrically connected to the drain of N1, the drain of N3, the gate of N6, and the gate of N2, and the source of P1 is electrically connected to the source of P2; PMOS transistor P2, the gate of P2 is electrically connected to the gate of N2, the drain of N3, and the gate of N6, the drain of P2 is electrically connected to the drain of N2, the drain of N4, the gate of N5, and the gate of N1, and the source of P2 is electrically connected to the source of P1; Transistors P1 and P2 are cross-coupled with transistors N1 and N2 to latch data at storage nodes Q and QB. The source of transistors P1 and P2 are electrically connected to VDD, opening a path for storage nodes Q and QB to the power supply. The source of transistors N1 and N2 are connected to VSS, opening a path for storage nodes Q and QB to the ground. Storage nodes Q and QB are connected to bit lines BL and BLB respectively through transistors N4 and N3, which are controlled by word line WL. Word lines LCM and RCM are connected to bit lines SLB and SL respectively through transistors N5 and N6, which are controlled by storage nodes Q and QB respectively.

2. The 8T-SRAM cell according to claim 1, wherein: In the pre-charge phase, the word lines LCM and RCM of the cell are maintained at a high level, and the bit lines SL and SLB are also pre-charged to a high level. The internal storage nodes Q and QB act on transistors N5 and N6 to control the opening and closing of the transistors. Assuming that the data stored in the cell is '1', that is, "Q=1, QB=0", in the search phase, the search data is loaded onto the bit lines SL and SLB. Assuming that "SL=0, SLB=1", transistor N5 is turned on and N6 is turned off. LCM and RCM output a high level '1' after passing through the SA sensitive amplifier and the AND gate, that is, the data matches; on the contrary, if the search data is "SL=1, SLB=0", the word line LCM is high and the bit line SLB is low, and the output is '0' after SA, and the logic AND is performed with the word line RCM, the output is '0', that is, the data does not match.

3. An in-memory Boolean logic operation and unidirectional BCAM (Binary Content Addressable Memory) circuit structure based on 8T-SRAM cells, characterized in that: It adopts the 8T-SRAM cell according to claim 1 or 2, and the circuit structure includes N*N 8T-SRAM cells; The circuit structure is symmetrical, so N is an even number. In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL; the drains of all transistors N5 are electrically connected to the word line LCM; and the drains of all transistors N6 are electrically connected to the word line RCM. In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB; the sources of all transistors N4 are electrically connected to the bit line BL; the sources of all transistors N5 are electrically connected to the bit line SLB; and the sources of all transistors N6 are electrically connected to the bit line SL.

4. The circuit structure of in-memory Boolean logic operation and unidirectional BCAM based on 8T-SRAM cells according to claim 3, characterized in that: It includes 2*2 8T-SRAM cells; wherein, in the two 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL; the drains of all transistors N5 are electrically connected to the word line LCM; and the drains of all transistors N6 are electrically connected to the word line RCM. In the two 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB; the sources of all transistors N4 are electrically connected to the bit line BL; the sources of all transistors N5 are electrically connected to the bit line SLB; and the sources of all transistors N6 are electrically connected to the bit line SL.

5. The circuit structure of in-memory Boolean logic operation and unidirectional BCAM based on 8T-SRAM cells according to claim 4, characterized in that: In the precharge stage of the circuit structure, word lines LCM and RCM are precharged to a high level, bit lines SL and SLB are precharged to a high level, and the two rows of cells that are turned on are denoted as A and B respectively. Assume that the data stored in A is "Q=1, QB=0", and the data stored in B is "Q=0, QB=1". In the calculation stage, the word lines LCM and RCM in A and B are all grounded and discharged to a low level. The LCM and RCM of the word lines in other rows are kept at VDD. SLB outputs '0' through SA, that is, "NOR(A, B)=0", then the other end of SA outputs '1', that is, "OR(A, B)=1", SL outputs '0' through SA, that is, "AND(A, B)=0", then the other end of SA outputs '1', that is, "NAND(A, B)=1". As long as one of the data stored in A or B is '0', SL and SLB will discharge to the ground, and the output result is the same as above; when the data stored in A and B are both '1', that is, "Q=1, QB=0" in A and B, SLB outputs '0' through SA, that is, Then the output of the other end of SA is '1', that is, "A+B=1", the output of SL through SA is '1', that is, "AB=1", then the output of the other end of SA is '0', that is When the data stored in A and B are both '0', that is, "Q=0, QB=1" in A and B, SLB outputs '1' through SA, that is, Then the output of the other end of SA is '0', that is, "A+B=0", the output of SL through SA is '0', that is, "AB=0", then the output of the other end of SA is '0', that is, 6. The circuit structure of in-memory Boolean logic operation and unidirectional BCAM based on 8T-SRAM cells according to claim 3, characterized in that: It includes 4*4 8T-SRAM cells; among them, in the four 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL, the drains of all transistors N5 are electrically connected to the word line LCM, and the drains of all transistors N6 are electrically connected to the word line RCM; In the four 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, the sources of all transistors N4 are electrically connected to the bit line BL, the sources of all transistors N5 are electrically connected to the bit line SLB, and the sources of all transistors N6 are electrically connected to the bit line SL.

7. The circuit structure of in-memory Boolean logic operation and unidirectional BCAM based on 8T-SRAM cells according to claim 6, characterized in that: The circuit structure precharges the word lines LCM and RCM to a high level in the precharge phase, and precharges the search bit lines SL and SLB to a high level. In the search phase, data is loaded onto SL and SLB. Assuming that the search data is "1010", that is, "SL <0> =1, SL <1> =0, SL <2> =1, SL <3> =0, SLB <0> =0, SLB <1> =1, SLB <2> =0, SLB <3> =1", according to the data stored in the array, when the 0th row is consistent with the search data, that is, the stored data in QB is consistent with the search data on SL, both are "1010", the output is '1', and the output of the remaining rows is '0', indicating a mismatch.

8. An 8T-SRAM chip, characterized in that: It is packaged using the 8T-SRAM unit according to claim 1; the pins of the 8T-SRAM chip include: A first pin electrically connected to the gates of transistors N3 and N4 through a word line WL; a second pin electrically connected to the drain of the transistor N5 through the word line LCM; a third pin electrically connected to the drain of the transistor N6 through the word line RCM; a fourth pin electrically connected to the source of the transistor N3 through the bit line BLB; a fifth pin electrically connected to the source of the transistor N4 through the bit line BL; a sixth pin electrically connected to the source of the transistor N5 through the bit line SLB; The seventh pin is electrically connected to the source of the transistor N6 through the bit line SL.

9. A circuit chip based on in-memory Boolean logic operations and unidirectional BCAM of 8T-SRAM cells, characterized in that: It is encapsulated by the circuit structure of the in-memory Boolean logic operation and unidirectional BCAM based on the 8T-SRAM unit according to any one of claims 3 to 7; the pins of the circuit chip of the in-memory Boolean logic operation and unidirectional BCAM based on the 8T-SRAM unit include: In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to the word line WL, thereby leading to the first pin; the drains of all transistors N5 are electrically connected to the word line LCM, thereby leading to the second pin; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to the third pin; each row has one first pin, one second pin, and one third pin; In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, from which the fourth pin is led out; the sources of all transistors N4 are electrically connected to the bit line BL, from which the fifth pin is led out; the sources of all transistors N5 are electrically connected to the bit line SLB, from which the sixth pin is led out; the sources of all transistors N6 are electrically connected to the bit line SL, from which the seventh pin is led out. There is one fourth pin, one fifth pin, one sixth pin and one seventh pin in each column.

10. A circuit module based on in-memory Boolean logic operations and unidirectional BCAM of 8T-SRAM cells, characterized in that: The circuit structure of the circuit for the in-memory Boolean logic operation and unidirectional BCAM based on the 8T-SRAM cell according to any one of claims 1 to 7 is adopted, wherein the circuit module for the in-memory Boolean logic operation and unidirectional BCAM based on the 8T-SRAM cell comprises: In the 8T-SRAM cells located in the same row, the gates of all transistors N3 and N4 are electrically connected to WL, thereby leading to a first connection terminal; the drains of all transistors N5 are electrically connected to the word line LCM, thereby leading to a second connection terminal; the drains of all transistors N6 are electrically connected to the word line RCM, thereby leading to a third connection terminal; each row has one first connection terminal, one second connection terminal, and one third connection terminal; In the 8T-SRAM cells located in the same column, the sources of all transistors N3 are electrically connected to the bit line BLB, thereby leading to the fourth connection terminal; the sources of all transistors N4 are electrically connected to the bit line BL, thereby leading to the fifth connection terminal; the sources of all transistors N5 are electrically connected to the bit line SLB, thereby leading to the sixth pin; the sources of all transistors N6 are electrically connected to the bit line SL, thereby leading to the seventh connection terminal. There is one fourth connection terminal, one fifth connection terminal, one sixth pin and one seventh connection terminal in each column.

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