Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a first mask layer on a surface of an interlayer dielectric layer on the second region, the first mask layer also being located in the second opening; forming a first doped region on the surface of the first source-drain layer using the first mask layer as a mask; after forming the first doped region, removing an etching stop layer on the surface of the first source-drain layer using the first mask layer as a mask, so that the first opening exposes the surface of the first source-drain layer; after the surface of the first source-drain layer is exposed by the first opening, performing a first modification treatment on the surface of the first source-drain layer to form a first modified layer, so as to reduce the contact resistance between the first source-drain layer and the first conductive plug, thereby improving the overall performance of the device; meanwhile, the first modified layer and the first doped region are formed using the same mask, without the need to increase an additional mask, thereby reducing the production cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] In the existing semiconductor field, the FinFET is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the FinFET has stronger short-channel rejection capability and higher operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, the gate size of fin field-effect transistors is constantly decreasing, the width of the source and drain active regions of transistors is constantly shrinking, the size of the back-end interconnect contact holes is also constantly shrinking, and the contact resistance of a single contact hole is constantly increasing. In order to reduce the contact resistance of the active region, existing technologies form metal silicides on the active region or implant N-type or P-type ions on the surface of the active region.

[0004] However, the performance of semiconductor structures formed using existing fin field-effect transistors urgently needs improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first gate structure, a second gate structure, a first source / drain layer, a second source / drain layer, an interlayer dielectric layer, and an etch stop layer, wherein the first gate structure is located on the first region, the second gate structure is located on the second region, the first source / drain layer is located in the first region on both sides of the first gate structure, the second source / drain layer is located in the second region on both sides of the second gate structure, the interlayer dielectric layer is located on the first region and the second region, the interlayer dielectric layer is located on the top and sidewalls of the first gate structure and the second gate structure, the etch stop layer is located between the substrate surface and the interlayer dielectric layer, and the etch stop layer is also located on the first gate structure. The structure includes the sidewalls and top surface of the second gate structure; a first opening and a second opening are formed within the interlayer dielectric layer, the first opening exposing the etch stop layer surface of the first source / drain layer, and the second opening exposing the etch stop layer surface of the second source / drain layer; a first mask layer is formed on the surface of the interlayer dielectric layer on the second region, the first mask layer also being located within the second opening; a first doped region is formed on the surface of the first source / drain layer using the first mask layer as a mask; after forming the first doped region, the etch stop layer on the surface of the first source / drain layer is removed using the first mask layer as a mask, so that the first opening exposes the surface of the first source / drain layer; after exposing the surface of the first source / drain layer, the surface of the first source / drain layer is subjected to a first modification treatment to form a first modified layer.

[0007] Optionally, it further includes: forming a second doped region on the surface of the second source / drain layer; after forming the second doped region, performing a second modification treatment on the surface of the second source / drain layer to form a second modified layer.

[0008] Optionally, after removing the etch stop layer on the surface of the first source / drain layer and before forming the first modified layer, the first mask layer is removed.

[0009] Optionally, the method for forming the first modified layer and the second modified layer further includes: forming a first metal layer on the surface of the first source / drain layer; forming a second doped region on the surface of the second source / drain layer after forming the first metal layer; removing the etch stop layer on the surface of the second source / drain layer after forming the second doped region, so that the second opening exposes the surface of the second source / drain layer; forming a second metal layer on the surface of the second source / drain layer after the second opening exposes the surface of the second source / drain layer; performing a first annealing on the first metal layer and the first source / drain layer to form the first modified layer; and performing a second annealing on the second metal layer and the second source / drain layer to form the second modified layer.

[0010] Optionally, the method for forming the first metal layer includes: forming a first metal material layer on the surface of the first source / drain layer, the surface of the second source / drain layer, and the surface of the interlayer dielectric layer; forming a second mask layer on the surface of the first metal material layer in the first region, the second mask layer also being located within the first opening; using the second mask layer as a mask, removing the first metal material layer on the surface of the second source / drain layer and the surface of the interlayer dielectric layer in the second region, and using the first metal material layer on the surface of the first source / drain layer as the first metal layer.

[0011] Optionally, the material of the second mask layer includes photoresist.

[0012] Optionally, the method of exposing the second opening to the surface of the second source / drain layer includes: using the second mask layer as a mask, etching the etch stop layer on the surface of the second source / drain layer.

[0013] Optionally, the method for forming the second metal layer includes: forming a second metal material layer on the surface of the second source / drain layer and the surface of the interlayer dielectric layer, with the second metal material layer on the surface of the second source / drain layer serving as the second metal layer.

[0014] Optionally, it includes: after forming the first modified layer, forming a first conductive plug in the first opening; and after forming the second modified layer, forming a second conductive plug in the second opening.

[0015] Optionally, the method for forming the first conductive plug and the second conductive plug includes: forming a conductive material layer in the first opening, the second opening and the surface of the interlayer dielectric layer; planarizing the conductive material layer until the surface of the interlayer dielectric layer is exposed.

[0016] Optionally, the method for forming the first doped region and the second doped region includes: using the first mask layer as a mask, implanting a first ion into the surface of the first source / drain layer exposed at the bottom of the first opening; and using the second mask layer as a mask, implanting a second ion into the surface of the second source / drain layer exposed at the bottom of the second opening.

[0017] Optionally, the first ion is an N-type or P-type ion; the second ion is an N-type or P-type ion, and the first ion and the second ion have different conductivity types.

[0018] Optionally, the following configurations are included: the material of the first modified layer is a first metal compound or a second metal compound; the conductivity type of the first source / drain layer is N-type, and the material of the first modified layer is a first metal compound; the conductivity type of the first source / drain layer is P-type, and the material of the first modified layer is a second metal compound; the material of the second modified layer is a first metal compound or a second metal compound; the conductivity type of the second source / drain layer is N-type, and the material of the second modified layer is a first metal compound; the conductivity type of the second source / drain layer is P-type, and the material of the second modified layer is a second metal compound.

[0019] Optionally, the conductivity type of the second source / drain layer is different from that of the first source / drain layer.

[0020] Optionally, the material of the first metal compound includes titanium silicide; the material of the second metal compound includes cobalt silicide or nickel silicide.

[0021] Optionally, the material of the first mask layer includes photoresist.

[0022] Optionally, the material of the etch stop layer includes silicon nitride.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In the semiconductor structure formation method provided by this invention, a first doped region is formed on the surface of the first source / drain layer using the first mask layer as a mask, and a first modification treatment is performed on the surface of the first source / drain layer to form a first modified layer. Different conductivity types and concentrations of the first doped region, as well as different first modified layer materials, can be formed according to the different performance characteristics of the first source / drain layer, thereby reducing the Schottky barrier at the contact surface between the first source / drain layer and the first modified layer. This reduces the contact resistance between the first source / drain layer and the first conductive plug, thereby improving the overall performance of the device. In this technical solution, the first mask layer is used as a mask to form the first doped region and also as a mask to remove the etch stop layer on the surface of the first source / drain layer, exposing the first opening to the surface of the first source / drain layer for forming the first modified layer. That is, the same mask is used for both forming the first modified layer and the first doped region, eliminating the need for additional masks and reducing production costs.

[0025] Furthermore, a second doped region is formed on the surface of the second source / drain layer. After forming the second doped region, the surface of the second source / drain layer undergoes a second modification treatment to form a second modified layer. This second region can be used to form a device with a different conductivity type than the first region. Depending on the performance of the second source / drain layer, different conductivity types and concentrations of the second doped region, as well as different second modified layer materials, can be formed to reduce the Schottky barrier at the interface between the second source / drain layer and the second modified layer. This reduces the contact resistance between the second source / drain layer and the second conductive plug, thereby improving the overall performance of the device.

[0026] Furthermore, the first metal compound comprises titanium silicide; the second metal compound comprises cobalt silicide or nickel silicide. Since titanium silicide has a low Schottky barrier at the contact surface between the source / drain layer of an NMOS device, and cobalt silicide or nickel silicide has a low Schottky barrier at the contact surface between the source / drain layer of a PMOS device, using titanium silicide as the modification layer on the source / drain layer of the N-type device region, and using cobalt silicide or nickel silicide as the modification layer on the source / drain layer of the P-type device region, helps to reduce the overall contact resistance between the device's source / drain layer and the conductive plug, thereby improving the overall performance of the device.

[0027] Furthermore, the same mask (i.e., the second mask layer) is used to form the second modified layer and implant the second ions into the bottom of the second opening. Therefore, forming a modified layer of different materials on the surface of the second source / drain layer does not require adding an additional mask, thus reducing production costs. Attached Figure Description

[0028] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process;

[0029] Figures 4 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] As described in the background section, the performance of semiconductor structures formed using existing finned transistor (FMT) technology urgently needs improvement. This section will now illustrate and analyze one such semiconductor structure.

[0032] Please refer to Figure 1 and Figure 2 , Figure 1 It is a top view. Figure 2 yes Figure 1A cross-sectional structural schematic diagram along the XY direction shows a substrate, the substrate including a base 100, the base 100 including a first region I and a second region II, an isolation structure 101 located on the base 100, a first fin 102 located on the first region I, and a second fin 202 located on the second region II. The isolation structure 101 is also located on the sidewalls of the first fin 102 and the second fin 202, and the top surface of the isolation structure 101 is lower than the top surface of the first fin 102 and the top surface of the second fin 202. A top surface; forming a first gate structure 103 spanning the first fin 102, the first gate structure 103 being located on a portion of the top surface and a portion of the sidewall surface of the first fin 102; forming a second gate structure 203 spanning the second fin 202, the second gate structure 203 being located on a portion of the top surface and a portion of the sidewall surface of the second fin 202; forming a first source / drain layer 104 in the first fin 102 on both sides of the first gate structure 103; forming a second source / drain layer 204 in the second fin 202 on both sides of the second gate structure 203.

[0033] Please refer to Figure 3 The surfaces of the first source / drain layer 104 and the second source / drain layer 204 are modified using a self-aligned metal silicide process to form a modified layer 205.

[0034] The above method is used in the formation process of FinFET devices. The material of the modified layer 205 includes Ti2Si, Co2Si, or Ni2PtSi, etc. The first region I is used to form an N-type device, and the second region II is used to form a P-type device. The modified layer 205 on the surfaces of the first source / drain layer 104 and the second source / drain layer 204 uses the same metal silicide material. Since different metal silicide materials have different Schottky barriers with the surfaces of source / drain layers with different conductivity types and concentrations, the Schottky barrier of titanium silicide material at the contact surface of the source / drain layer of an NMOS device is low, while the Schottky barrier of cobalt silicide or nickel silicide material at the contact surface of the source / drain layer of a PMOS device is low. The above method uses the same metal silicide material as the modified layer for devices with different conductivity types, which is not conducive to reducing the overall contact resistance between the source / drain layer of the device and the conductive plug.

[0035] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. Using a first mask layer as a mask, a first doped region is formed on the surface of the first source / drain layer, and the surface of the first source / drain layer undergoes a first modification treatment to form a first modified layer. Different conductivity types and concentrations of the first doped region, as well as different first modified layer materials, can be formed depending on the performance of the first source / drain layer, thereby reducing the Schottky barrier at the interface between the first source / drain layer and the first modified layer. This lowers the contact resistance between the first source / drain layer and the first conductive plug located on the first source / drain layer, thus improving the overall performance of the device. In this technical solution, the first mask layer serves as a mask for forming the first doped region and also as a mask for removing the etch stop layer on the surface of the first source / drain layer, exposing the first opening to the surface of the first source / drain layer for forming the first modified layer. That is, the same mask is used for forming both the first modified layer and the first doped region, eliminating the need for additional masks and reducing production costs.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 4 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 4 and Figure 5 , Figure 4 It is a top view. Figure 5 yes Figure 4 A cross-sectional structural diagram along the XY direction is provided, showing a substrate including a first region I and a second region II.

[0039] In this embodiment, the substrate includes a base 200, a fin 201 located on the base, and a first isolation structure 202 located on the base 200. The first isolation structure 202 is located on the sidewall of the fin 201, and the top surface of the first isolation structure 202 is lower than the top surface of the fin 201. In other embodiments, the substrate may be a planar structure.

[0040] Different devices are formed on the first region I and the second region II. In this embodiment, the first region is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0041] Please refer to Figure 6The following structures are formed: a first gate structure 203, a second gate structure 204, a first source / drain layer 205, a second source / drain layer 206, an interlayer dielectric layer 207, and an etch stop layer 208. The first gate structure 203 is located on a first region I, and the second gate structure 204 is located on a second region II. The first source / drain layer 205 is located in the first region I on both sides of the first gate structure 203, and the second source / drain layer 206 is located in the second region II on both sides of the second gate structure 204. The interlayer dielectric layer 207 is located on the first region I and the second region II, and is located on the top and sidewalls of the first gate structure 203 and the second gate structure 204. The etch stop layer 208 is located between the substrate surface and the interlayer dielectric layer 202, and is also located on the sidewalls and top surface of the first gate structure 203 and the second gate structure 204.

[0042] The conductivity type of the second source / drain layer 206 is different from that of the first source / drain layer 205. In this embodiment, the first source / drain layer 205 contains N-type doped ions, and the second source / drain layer 206 contains P-type doped ions.

[0043] In this embodiment, the first gate structure 203 includes a first gate (not shown in the figure), a first sidewall located on the sidewall of the first gate (not shown in the figure), and a first protective layer located on top of the first gate (not shown in the figure); the second gate structure 204 includes a second gate (not shown in the figure), a second sidewall located on the sidewall of the second gate (not shown in the figure), and a second protective layer located on top of the second gate (not shown in the figure).

[0044] The method of forming the first gate structure 203 includes: forming a first pseudo gate structure (not shown in the figure) spanning the fin 201 on the first region I, the first pseudo gate structure being located on a portion of the sidewall and top surface of the fin 201, the first pseudo gate structure including a first pseudo gate (not shown in the figure) and a first sidewall located on the sidewall of the first pseudo gate; and replacing the first pseudo gate to form the first gate.

[0045] The method of forming the second gate structure 204 includes: forming a second pseudo-gate structure (not shown in the figure) spanning the fin 201 on the second region I, the second pseudo-gate structure being located on a portion of the sidewall and top surface of the fin 201, the second pseudo-gate structure including a second pseudo-gate (not shown in the figure) and a second sidewall located on the sidewall of the second pseudo-gate; and replacing the second pseudo-gate to form the second gate.

[0046] In this embodiment, the interlayer dielectric layer 207 includes a first dielectric layer located on the substrate and a second dielectric layer located on the first dielectric layer. The method for forming the first dielectric layer includes: forming a first dielectric material layer (not shown in the figure) on the substrate, the first dielectric material layer being located on the sidewalls of the first gate structure and the second gate structure, and on the surfaces of the first source / drain layer and the second source / drain layer; planarizing the first dielectric material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

[0047] In this embodiment, after forming the first dielectric layer and before forming the second dielectric layer, a second isolation structure 209 is also formed. The second isolation structure 209 is located within the fin 201 and the substrate 200, and between adjacent first gate structures 203 and second gate structures 204. The second isolation structure 209 is used to isolate devices on the first region I and the second region II.

[0048] The material of the etch stop layer 208 includes silicon nitride.

[0049] In this embodiment, the etch stop layer 208 is formed after the first source / drain layer 205 and the second source / drain layer 206 are formed. The method for forming the etch stop layer 208 includes: forming an etch stop material layer (not shown in the figure) on the surface of the substrate, the first dummy gate structure, and the second dummy gate structure; planarizing the first dielectric material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed, during which the etch stop material layer is also planarized to form the etch stop layer.

[0050] Please refer to Figure 7 A first opening 210 and a second opening 211 are formed in the interlayer dielectric layer 207. The first opening 210 exposes the surface of the etch stop layer 208 on the surface of the first source / drain layer 205, and the second opening 211 exposes the surface of the etch stop layer 208 on the surface of the second source / drain layer 206.

[0051] The formation process of the first opening 210 and the second opening 211 includes one or a combination of dry etching and wet etching processes. In this embodiment, the formation process of the first opening 210 and the second opening 211 is a dry etching process, which is beneficial for forming openings with better morphology. In this embodiment, the first opening 210 and the second opening 211 are formed in the same process, reducing the number of processes and lowering production costs.

[0052] Please refer to Figure 8 A first mask layer 212 is formed on the surface of the interlayer dielectric layer 207 in the second region II, and the first mask layer 212 is also located in the second opening 211 (e.g. Figure 7 (as shown); using the first mask layer 212 as a mask, a first doped region 213 is formed on the surface of the first source / drain layer 205.

[0053] The method for forming the first doped region 213 includes: using the first mask layer 212 as a mask, implanting first ions into the surface of the first source / drain layer 205 exposed at the bottom of the first opening 210.

[0054] The first ion is either an N-type or a P-type ion. Depending on the conductivity of the first source / drain layer 205, different first ion types are selected to form first doped regions 213 with different conductivity types and concentrations, thereby reducing the contact resistance between the first source / drain layer 205 and the subsequently formed first conductive plug. In this embodiment, the first region I is used to form an NMOS device, and the first ion is an N-type ion.

[0055] The material of the first mask layer 212 includes photoresist.

[0056] Please refer to Figure 9 After the first doped region 213 is formed, the first mask layer 213 is used as a mask to remove the etch stop layer 208 on the surface of the first source / drain layer 205, so that the first opening 210 exposes the surface of the first source / drain layer 205.

[0057] Specifically, the etch stop layer 208 on the surface of the first source / drain layer 205 is removed, so that the first opening 210 exposes the first doped region 213 on the surface of the first source / drain layer 205.

[0058] The first mask layer 213 serves as a mask to form the first doped region 213, and also as a mask to remove the etch stop layer 208 on the surface of the first source / drain layer 205, exposing the first opening 210 to the surface of the first source / drain layer 205 for subsequent formation of the first modified layer on the surface of the first source / drain layer 205. That is, the same mask is used for both forming the first modified layer and the first doped region 213, eliminating the need for additional masks and reducing production costs.

[0059] Subsequently, after exposing the surface of the first source / drain layer 205 through the first opening 210, the surface of the first source / drain layer 205 is subjected to a first modification treatment to form a first modified layer.

[0060] In this embodiment, after removing the etching stop layer 208 on the surface of the first source / drain layer 205 and before forming the first modified layer, the first mask layer 212 is also removed.

[0061] Subsequently, a second doped region is formed on the surface of the second source / drain layer 206; after the second doped region is formed, a second modification treatment is performed on the surface of the second source / drain layer 206 to form a second modified layer. For the methods of forming the first modified layer and the second modified layer, please refer to [reference needed]. Figures 10 to 13 .

[0062] Please refer to Figure 10 A first metal material layer 214 is formed on the surface of the first source / drain layer 205, the surface of the second source / drain layer 206, and the surface of the interlayer dielectric layer 207.

[0063] In this embodiment, the first metal material layer 214 is also located on the sidewall of the first opening 210 and the sidewall of the second opening 211.

[0064] The first metal material layer 214 is used to form the first metal layer on the surface of the first source / drain layer 205.

[0065] Please refer to Figure 11 A second mask layer 215 is formed on the surface of the first metal material layer 214 on the first region I, and the second mask layer 215 is also located within the first opening 210; using the second mask layer 215 as a mask, the first metal material layer 214 on the surface of the second source / drain layer 206 and the surface of the interlayer dielectric layer 207 on the second region II is removed, and the first metal material layer 214 on the surface of the first source / drain layer 205 is used as the first metal layer 216.

[0066] The material of the second mask layer 215 includes photoresist.

[0067] Subsequently, the second mask layer 215 serves as a mask to form the second doped region and also as a mask to remove the etch stop layer 208 on the surface of the second source / drain layer 206, exposing the second opening 211 to the surface of the second source / drain layer 206 for forming the second modified layer on the surface of the second source / drain layer 206. That is, the same mask is used for both forming the second modified layer and the second doped region 215, eliminating the need for additional masks and reducing production costs.

[0068] In this embodiment, the first metal layer 216 is also located on the surface of the interlayer dielectric layer 207 and the sidewall of the first opening 210 in the first region I. In other embodiments, only the first metal material layer 214 on the surface of the first source / drain layer 205 may be retained as the first metal layer 216.

[0069] The method for forming the first modified layer includes: performing a first annealing on the first metal layer 216 and the first source / drain layer 205 to form the first modified layer. In this embodiment, the first annealing process and the subsequent second annealing process are completed in the same process after the second metal layer is formed, to save steps. In other embodiments, the first annealing process can be performed in any process after the first metal layer 216 is formed.

[0070] The material of the first modified layer is a first metal compound or a second metal compound; the conductivity type of the first source / drain layer 205 is N-type, and the material of the first modified layer is a first metal compound; the conductivity type of the first source / drain layer 205 is P-type, and the material of the first modified layer is a second metal compound; the material of the first metal compound includes titanium silicide; the material of the second metal compound includes cobalt silicide or nickel silicide.

[0071] The first metal compound is made of titanium silicide; the second metal compound is made of cobalt silicide or nickel silicide.

[0072] The first modified layer is used to reduce the contact resistance between the first metal material layer 214 and the subsequently formed first conductive plug. Since the Schottky barrier between titanium silicide and the source / drain layer of an NMOS device is low, and the Schottky barrier between cobalt silicide or nickel silicide and the source / drain layer of a PMOS device is low, using titanium silicide as the modified layer on the source / drain layer of the N-type device region, and using cobalt silicide or nickel silicide as the modified layer on the source / drain layer of the P-type device region, helps to reduce the overall contact resistance between the device's source / drain layer and the conductive plug, thereby improving the overall performance of the device.

[0073] Depending on the performance of the first source / drain layer, different conductivity types and concentrations of first doped regions, as well as different first modified layer materials, can be formed to lower the Schottky barrier at the interface between the first source / drain layer and the first modified layer. This reduces the contact resistance between the first source / drain layer and the first conductive plug, thereby improving the overall performance of the device.

[0074] In this embodiment, the first region I is used to form an NMOS device, the first source / drain layer 205 has an N-type conductivity, the first modified layer is made of a first metal compound, therefore the first metal material layer 214 is made of titanium, the first metal layer is made of titanium, and the first metal compound is made of titanium silicide.

[0075] Please continue to refer to this. Figure 11 After the first metal layer 216 is formed, a second doped region 217 is formed on the surface of the second source / drain layer 206.

[0076] The method for forming the second doped region 217 includes: using the second mask layer 215 as a mask, implanting second ions into the surface of the second source / drain layer 206 exposed at the bottom of the second opening 211.

[0077] The second ion is an N-type or P-type ion, and the first ion and the second ion have different conductivity types. Depending on the performance of the second source / drain layer, second doped regions 217 with different conductivity types and concentrations can be formed to reduce the contact resistance between the second source / drain layer 206 and the subsequently formed second conductive plug. In this embodiment, the conductivity type of the second source / drain layer 206 is N-type, and the second ion is N-type.

[0078] After forming the second doped region 217, the surface of the second source / drain layer 206 undergoes a second modification treatment to form a second modified layer. For the method of forming the second modified layer, please refer to [reference needed]. Figures 12 to 13 .

[0079] Please refer to Figure 12 After forming the second doped region 217, the etch stop layer 208 on the surface of the second source / drain layer 206 is removed, so that the second opening 211 exposes the surface of the second source / drain layer 206.

[0080] In this embodiment, the method of exposing the surface of the second source / drain layer 206 through the second opening 211 includes: using the second mask layer 215 as a mask, etching the etching stop layer 208 on the surface of the second source / drain layer 206.

[0081] Specifically, the etch stop layer 208 on the surface of the second source / drain layer 206 is removed, so that the second opening 211 exposes the second doped region 217 on the surface of the second source / drain layer 206.

[0082] The second mask layer 215 serves as a mask to form the second doped region 217, and also as a mask to remove the etch stop layer 208 on the surface of the second source / drain layer 206, exposing the second opening 211 to the surface of the second source / drain layer 206 for subsequent formation of the second modified layer on the surface of the second source / drain layer 206. That is, the same mask is used for both forming the second modified layer and the second doped region 217, eliminating the need for additional masks and reducing production costs.

[0083] In this embodiment, after removing the etch stop layer 208 on the surface of the second source / drain layer 206 and before forming the second modified layer, the second mask layer 215 is also removed.

[0084] The process for removing the etch stop layer 208 from the surface of the second source / drain layer 206 includes a dry etching process.

[0085] Please refer to Figure 13 After the second opening 211 exposes the surface of the second source / drain layer 206, a second metal layer 218 is formed on the surface of the second source / drain layer 206.

[0086] In this embodiment, specifically, after removing the second mask layer 215, a second metal layer 218 is formed on the surface of the second source / drain layer 206.

[0087] The method for forming the second metal layer 218 includes: forming a second metal material layer on the surface of the second source / drain layer 206 and the surface of the interlayer dielectric layer 207, with the second metal material layer on the surface of the second source / drain layer 206 serving as the second metal layer 218.

[0088] In this embodiment, the second metal layer 218 is also located on the surface of the first metal layer 214. In other embodiments, the second metal layer 218 is located only on the surface of the second source / drain layer 206. The second metal layer 218 serves to provide material for forming a second modified layer on the surface of the second source / drain layer 206.

[0089] The material of the second modified layer is a first metal compound or a second metal compound; the conductivity type of the second source / drain layer 206 is N-type, and the material of the second modified layer is the first metal compound; the conductivity type of the second source / drain layer 206 is P-type, and the material of the second modified layer is the second metal compound.

[0090] The first metal compound is made of titanium silicide; the second metal compound is made of cobalt silicide or nickel silicide.

[0091] In this embodiment, the method for forming the second modified layer further includes: performing a second annealing on the second metal layer 218 and the second source / drain layer 206 to form the second modified layer. In this embodiment, the first annealing process and the second annealing process are completed in the same step after the formation of the second metal layer 218, saving steps and reducing production costs.

[0092] Different second modified layer materials are formed according to the different properties of the second source / drain layer 206, thereby reducing the Schottky barrier at the contact surface between the second source / drain layer 206 and the second modified layer. This reduces the contact resistance between the second source / drain layer 206 and the second conductive plug, thus improving the overall performance of the device. In this embodiment, the conductivity type of the second source / drain layer 206 is P-type, the material of the second metal layer is cobalt, and during the second annealing process, the second metal layer 218 reacts with the second source / drain layer 206. Specifically, the second metal layer 218 reacts with the second doped region on the surface of the second source / drain layer 206 to form the second modified layer, which is made of cobalt silicide.

[0093] Please refer to Figure 14 After the first modified layer is formed, a first conductive plug 219 is formed in the first opening 210; after the second modified layer is formed, a second conductive plug 220 is formed in the second opening 211.

[0094] In this embodiment, the first conductive plug 219 and the second conductive plug 220 are formed simultaneously to save on processes and reduce costs. The method for forming the first conductive plug 219 and the second conductive plug 220 includes: forming a conductive material film (not shown in the figure) inside the first opening 210, inside the second opening 211, and on the surface of the interlayer dielectric layer 207; the conductive material film fills the first opening 210 and the second opening 211; and planarizing the conductive material film until the surface of the interlayer dielectric layer 207 is exposed.

[0095] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first gate structure, a second gate structure, a first source / drain layer, a second source / drain layer, an interlayer dielectric layer, and an etch stop layer are formed. The first gate structure is located on a first region, the second gate structure is located on a second region, the first source / drain layer is located in the first region on both sides of the first gate structure, the second source / drain layer is located in the second region on both sides of the second gate structure, the interlayer dielectric layer is located on the first region and the second region, the interlayer dielectric layer is located on the top and sidewalls of the first gate structure and the second gate structure, and the etch stop layer is located between the substrate surface and the interlayer dielectric layer. The etch stop layer is also located on the sidewalls and top surface of the first gate structure and the second gate structure. A first opening and a second opening are formed within the interlayer dielectric layer. The first opening exposes the etch stop layer surface of the first source / drain layer surface, and the second opening exposes the etch stop layer surface of the second source / drain layer surface. A first mask layer is formed on the surface of the interlayer dielectric layer in the second region, and the first mask layer is also located within the second opening; Using the first mask layer as a mask, a first doped region is formed on the surface of the first source / drain layer; After the first doped region is formed, the first mask layer is used as a mask to remove the etch stop layer on the surface of the first source / drain layer, so that the first opening exposes the surface of the first source / drain layer. After exposing the surface of the first source / drain layer through the first opening, the surface of the first source / drain layer is subjected to a first modification treatment to form a first modified layer; A second doped region is formed on the surface of the second source / drain layer; After the second doped region is formed, the surface of the second source / drain layer is subjected to a second modification treatment to form a second modified layer. The materials of the first modified layer and the second modified layer are different. The method for forming the first modified layer and the second modified layer further includes: forming a first metal layer on the surface of the first source / drain layer; forming a second doped region on the surface of the second source / drain layer after forming the first metal layer; removing the etch stop layer on the surface of the second source / drain layer after forming the second doped region, so that the second opening exposes the surface of the second source / drain layer; forming a second metal layer on the surface of the second source / drain layer after the second opening exposes the surface of the second source / drain layer; performing a first annealing on the first metal layer and the first source / drain layer to form the first modified layer; performing a second annealing on the second metal layer and the second source / drain layer to form the second modified layer, wherein the first annealing and the second annealing are completed in the same step after forming the second metal layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the etch stop layer on the surface of the first source / drain layer and before forming the first modified layer, the first mask layer is removed.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first metal layer includes: forming a first metal material layer on the surface of the first source / drain layer, the surface of the second source / drain layer, and the surface of the interlayer dielectric layer; forming a second mask layer on the surface of the first metal material layer in the first region, the second mask layer also being located within the first opening; using the second mask layer as a mask, removing the first metal material layer on the surface of the second source / drain layer and the surface of the interlayer dielectric layer in the second region, and using the first metal material layer on the surface of the first source / drain layer as the first metal layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the second mask layer includes photoresist.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method of exposing the second source / drain layer surface through the second opening includes: using the second mask layer as a mask, etching the etch stop layer on the surface of the second source / drain layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the second metal layer includes: forming a second metal material layer on the surface of the second source / drain layer and the surface of the interlayer dielectric layer, with the second metal material layer on the surface of the second source / drain layer serving as the second metal layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, include: After the first modified layer is formed, a first conductive plug is formed in the first opening; After the second modified layer is formed, a second conductive plug is formed in the second opening.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the first conductive plug and the second conductive plug includes: forming a conductive material layer in the first opening, the second opening and the surface of the interlayer dielectric layer; planarizing the conductive material layer until the surface of the interlayer dielectric layer is exposed.

9. The method for forming a semiconductor structure as described in claim 3, wherein the method for forming the first doped region and the second doped region comprises: Using the first mask layer as a mask, first ions are injected into the surface of the first source / drain layer exposed at the bottom of the first opening; Using the second mask layer as a mask, second ions are injected into the surface of the second source / drain layer exposed at the bottom of the second opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first ion is an N-type or P-type ion; the second ion is an N-type or P-type ion, and the first ion and the second ion have different conductivity types.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, include: The material of the first modified layer is a first metal compound or a second metal compound; the conductivity type of the first source / drain layer is N-type, and the material of the first modified layer is a first metal compound; the conductivity type of the first source / drain layer is P-type, and the material of the first modified layer is a second metal compound; the material of the second modified layer is a first metal compound or a second metal compound; the conductivity type of the second source / drain layer is N-type, and the material of the second modified layer is a first metal compound; the conductivity type of the second source / drain layer is P-type, and the material of the second modified layer is a second metal compound.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The conductivity type of the second source / drain layer is different from that of the first source / drain layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first metal compound is made of titanium silicide; the second metal compound is made of cobalt silicide or nickel silicide.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first mask layer includes photoresist.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the etch stop layer includes silicon nitride.

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