Bump packaging structure and method for manufacturing bump packaging structure

Abstract

Embodiments of the present application provide a bump packaging structure and a preparation method thereof, and relate to the technical field of semiconductor packaging. The bump packaging structure comprises a wafer, a protective layer, a base conductive layer, a combined conductive layer, a conductive bump and a solder cap. The base conductive layer made of graphene material is arranged as the base structure of the conductive bump, which can better avoid deformation of the UBM layer at the bottom of the copper column and play a buffering role. Meanwhile, the base conductive layer made of graphene material covers the opening, and the good hydrophobicity and stability of the multilayer graphene can avoid the undercut problem of the bottom metal layer during the micro-etching process. The good stability, conductivity and heat dissipation of the multilayer graphene structure can further improve the conductivity and heat dissipation performance of the overall connection structure. Furthermore, the arrangement of the plurality of arc-shaped grooves effectively improves the contact area between the base conductive layer and the combined conductive layer, thereby improving the bonding force.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a bump packaging structure and a preparation method of the bump packaging structure. BACKGROUND

[0002] With the rapid development of the semiconductor industry, flip-chip packaging structures are widely used in the semiconductor industry. Flip-chip wafer packaging uses bumps to electrically connect the wafer and the substrate. The bump includes a copper column, a metal layer (UBM: under bump metalization), a protective layer (polyimide), a tin cap (Sn Cap), etc. After the metal layer UBM is made, the excess metal layer needs to be etched and removed. Since the polyimide material is extremely easy to absorb water, the UBM sidewall etching liquid remains at the bottom of the copper column bump, resulting in excessive corrosion of the bottom of the copper column bump to form an undercut opening. When the bump wafer is subjected to reliability testing, the copper column bump may fall off. The copper column bump of the prior art is completely connected to the wafer electrode at the bottom, which causes the stress on the copper column bump to directly act on the wafer electrode, poor stress release capability, poor bonding force, and wafer electrode cracking problems. Under the influence of the current, the metal atoms at the connection of the copper column bottom are simultaneously subjected to the influence of the electric field and the thermal field due to the Joule heating effect. The electromigration and thermal migration of the interconnection interface are abnormally active, which significantly reduces the service life and causes potential failure hazards. SUMMARY

[0003] The present application aims to provide a bump packaging structure and a preparation method of the bump packaging structure, which can avoid excessive corrosion to form an undercut opening, has good bonding force, and avoids falling off. The bump packaging structure and the preparation method of the bump packaging structure can also buffer the force between the bump and the pad, have good stress release capability, avoid wafer electrode cracking problems, and have better electrical conductivity and thermal conductivity.

[0004] Embodiments of the present application can be implemented as follows:

[0005] In a first aspect, the present application provides a bump packaging structure, comprising:

[0006] a wafer, a front surface of the wafer being provided with a pad;

[0007] a protective layer provided on the front surface of the wafer, the protective layer being provided with a protective opening corresponding to the pad;

[0008] a base conductive layer provided in the protective opening;

[0009] a combined conductive layer provided on the base conductive layer;

[0010] a conductive bump provided on the combined conductive layer;

[0011] and a solder cap disposed on the conductive stud;

[0012] The base conductive layer comprises a plurality of layers of graphene material, and a plurality of first arc-shaped grooves are disposed on a side of the base conductive layer away from the wafer, the plurality of first arc-shaped grooves are spaced apart, and the combined conductive layer is partially accommodated in the plurality of first arc-shaped grooves.

[0013] In an optional embodiment, the combined conductive layer comprises an adhesive layer, a barrier layer, and a wetting layer, the adhesive layer is covered on the base conductive layer and partially accommodated in the plurality of first arc-shaped grooves, the barrier layer is disposed on the adhesive layer, the wetting layer is disposed on the barrier layer, and the conductive stud is disposed on the wetting layer.

[0014] In an optional embodiment, the adhesive layer is a titanium layer, and a titanium carbide layer is formed at an interface between the adhesive layer and the base conductive layer.

[0015] In an optional embodiment, at least part of the base conductive layer has a thickness greater than a depth of the protective opening, and an edge of the base conductive layer extends outward to a surface of the protective layer to cover an edge of the protective opening.

[0016] In an optional embodiment, an edge of the adhesive layer extends outward to the surface of the protective layer to cover an edge of the base conductive layer, and a projection of the barrier layer on a front surface of the wafer and a projection of the wetting layer on the front surface of the wafer both fall within a projection range of the adhesive layer on the front surface of the wafer, and a projection of the conductive stud on the front surface of the wafer falls within the projection range of the adhesive layer on the front surface of the wafer.

[0017] In an optional embodiment, the barrier layer and the wetting layer are both planarized structures, a receiving groove is disposed on a side of the adhesive layer away from the wafer, the barrier layer and the wetting layer are disposed in the receiving groove, a depth of the receiving groove is D1, a thickness of the barrier layer is D2, and a thickness of the wetting layer is D3, wherein D1=D2+D3.

[0018] In an optional embodiment, a plurality of second arc-shaped grooves are disposed on a side surface of the barrier layer away from the wafer, the plurality of second arc-shaped grooves are spaced apart, and the wetting layer is accommodated in the plurality of second arc-shaped grooves.

[0019] In an optional embodiment, the plurality of second arc-shaped grooves are disposed in a staggered manner with the plurality of first arc-shaped grooves.

[0020] In an optional embodiment, the depth H2 of the second arc-shaped groove is the same as the depth H1 of the first arc-shaped groove, and the distance from the interface of the bonding layer and the barrier layer to the wetting layer and the conductive layer of the substrate is the same.

[0021] In an optional embodiment, the width of the first arc-shaped groove and the second arc-shaped groove is the same, and the interval distance between two adjacent first arc-shaped grooves is the same as the interval distance between two adjacent second arc-shaped grooves, so that part of the barrier layer and part of the bonding layer are symmetrically arranged along the interface.

[0022] In an optional embodiment, a first metal layer and a second metal layer are further arranged between the conductive pillar and the solder cap, the first metal layer is arranged on the surface of the conductive pillar, the second metal layer is arranged on the surface of the first metal layer, and the solder cap is arranged on the surface of the second metal layer, the second metal layer is used to block diffusion atoms between the solder cap and the conductive pillar, and the first metal layer is used to improve the adhesion between the second metal layer and the conductive pillar.

[0023] In a second aspect, the present application provides a preparation method of a bump packaging structure, which is used to prepare the bump packaging structure according to any one of the preceding embodiments, and the preparation method comprises the following steps:

[0024] providing a wafer with pads arranged on the front surface of the wafer;

[0025] forming a protective layer on the front surface of the wafer;

[0026] slotting the protective layer to form protective openings corresponding to the pads;

[0027] forming a conductive layer of substrate in the protective openings;

[0028] slotting the conductive layer of substrate to form a plurality of first arc-shaped grooves;

[0029] forming a combined conductive layer on the conductive layer of substrate;

[0030] forming a conductive pillar on the combined conductive layer;

[0031] forming a solder cap on the conductive pillar;

[0032] wherein the conductive layer of substrate comprises a plurality of layers of graphene material, the plurality of first arc-shaped grooves are arranged at intervals, and the combined conductive layer is partially accommodated in the plurality of first arc-shaped grooves.

[0033] The beneficial effects of the embodiments of the present application include, for example:

[0034] The application provides a bump packaging structure, which is provided with a pad and a protective layer on the front surface of a wafer, the protective layer is provided with a protective opening corresponding to the pad, a base conductive layer is arranged in the protective opening and covers the protective opening, a combined conductive layer is arranged on the base conductive layer, a conductive bump is arranged on the combined conductive layer, and a solder cap is arranged on the conductive bump, wherein the base conductive layer comprises a plurality of layers of graphene material, a plurality of first arc-shaped grooves are arranged on the side of the base conductive layer away from the wafer, the plurality of first arc-shaped grooves are arranged at intervals, and the combined conductive layer is arranged in the plurality of first arc-shaped grooves. The base conductive layer of graphene material is arranged as the base structure of the conductive bump, the thermal expansion coefficient CTE of graphene is only 1 / 10-1 / 20 of that of copper and aluminum, the deformation stress of the UBM layer at the bottom of the copper bump can be better avoided, the buffer effect can be achieved, the wafer pad can be protected, better stress release can be achieved, and the problem of wafer electrode (pad) cracking can be avoided. Meanwhile, the base conductive layer of graphene material covers the protective opening, the good hydrophobicity and stability of the plurality of layers of graphene are utilized, the undercut problem caused by the bottom metal layer can be avoided during the micro-etching process, whether chemical etching or plasma etching is used. Moreover, the conductivity of graphene is 100 times higher than that of other metals, the local good stability, conductivity and heat dissipation of the multi-layer graphene structure formed along with the increase of the volume of graphene, so that the conductivity and heat conduction performance of the overall connection structure are further improved. Moreover, the plurality of arc-shaped grooves are arranged, the contact area between the base conductive layer and the combined conductive layer is effectively improved, and the bonding force is improved. Compared with the prior art, the bump packaging structure provided by the application can avoid excessive corrosion to form an undercut opening, has good bonding force, avoids falling, can buffer the acting force between the bump and the pad, has good stress release capacity, avoids the problem of wafer electrode cracking, and has better conductivity and heat conduction performance. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0036] Figure 1 A schematic view of the bump packaging structure provided by the first embodiment of the application;

[0037] Figure 2 A schematic view of the soldering structure of the bump packaging structure provided by the first embodiment of the application; Figure 1 A partial enlarged view of the second embodiment of the application;

[0038] Figure 3 A schematic view of the soldering structure of the bump packaging structure provided by the first embodiment of the application;

[0039] Figures 4 to 11 Process flow chart of the preparation method of the bump package structure provided by the first embodiment of the present application;

[0040] Figure 12 Schematic diagram of the bump package structure provided by the second embodiment of the present application.

[0041] Figure: 100-bump package structure; 110-wafer; 111-pad; 120-protection layer; 121-protection opening; 130-substrate conductive layer; 131-first arc-shaped groove; 140-combined conductive layer; 141-adhesion layer; 143-barrier layer; 145-wetting layer; 147-housing groove; 149-second arc-shaped groove; 150-conductive bump; 160-solder cap; 170-first metal layer; 180-second metal layer; 200-substrate; 210-adhesive layer. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0044] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0045] In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application.

[0046] In addition, if the terms "first", "second" and the like appear, they are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0047] As disclosed in the background art, the bump connection structure in the prior art is to directly set a UBM layer at the bottom of the bump and directly connect with the pad (electrode) of the wafer by using a metal material. Such a conventional structure has the following problems:

[0048] 1. The protective layer is usually made of polyimide material. Since the polyimide material is extremely easy to absorb water, residual etching liquid is easy to appear when the sidewall of the UBM at the bottom of the metal column is etched, which causes the over-etch undercut opening at the bottom of the copper column bump, and then the copper column bump of the wafer is easy to fall off during the reliability test, which affects the soldering reliability.

[0049] 2. The UBM layer is usually a flat structure, that is, the adjacent metal layers are connected in a flat structure, which causes the contact area to be small and the bonding force to be weak, and the same is easy to fall off during the reliability test.

[0050] 3. The bottom of the copper column bump in the prior art is completely connected with the wafer electrode, which causes the stress on the copper column bump to directly act on the wafer electrode, the stress release capacity is weak, and the wafer electrode is prone to crack.

[0051] 4. As the pitch of the copper column bump becomes smaller and smaller, the bottom filling glue is often used to fill and protect the bottom of the flip chip. In order to increase the adhesion strength of the bottom filling glue and the surface protective layer of the chip, plasma bombardment of the organic surface is often used to improve the roughness of the organic surface and improve the adhesion strength of the filling glue. However, if silicon nitride or silicon nitride is used as the protective layer, the effect of plasma bombardment on the roughness of the surface is not good.

[0052] In order to solve the above problems, the present application provides a new type of bump packaging structure and a preparation method of the bump packaging structure. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0053] First embodiment

[0054] Referring to Figure 1 and Figure 2 , the present embodiment provides a bump packaging structure 100 which can avoid over-etching to form an undercut opening, has good bonding force and avoids falling off. Moreover, the bump packaging structure 100 can buffer the acting force between the bump and the pad 111, has good stress release capacity, avoids the problem of wafer 110 electrode cracking, and has better conductivity and thermal conductivity.

[0055] The bump package structure 100 provided by the embodiment comprises a wafer 110, a protective layer 120, a base conductive layer 130, a combined conductive layer 140, a conductive bump 150 and a solder cap 160. The wafer 110 is provided with a bonding pad 111 on the front side. The protective layer 120 is arranged on the front side of the wafer 110. The protective layer 120 is provided with a protective opening 121 corresponding to the bonding pad 111. The base conductive layer 130 is arranged in the protective opening 121 and covers the protective opening 121. The combined conductive layer 140 is arranged on the base conductive layer 130. The conductive bump 150 is arranged on the combined conductive layer 140. The solder cap 160 is arranged on the conductive bump 150. The base conductive layer 130 comprises a plurality of layers of graphene material. The side of the base conductive layer 130 away from the wafer 110 is provided with a plurality of first arc-shaped grooves 131. The plurality of first arc-shaped grooves 131 are arranged at intervals. The combined conductive layer 140 is partially accommodated in the plurality of first arc-shaped grooves 131.

[0056] In the embodiment, the plurality of first arc-shaped grooves 131 are uniformly distributed on the surface of the base conductive layer 130. The combined conductive layer 140 is partially embedded in the plurality of first arc-shaped grooves 131. Thus, the contact area between the combined conductive layer 140 and the base conductive layer 130 is greatly improved. In turn, the bonding force between the combined conductive layer 140 and the base conductive layer 130 is greatly improved. Thus, the purpose of preventing the conductive bump 150 from falling off is achieved. The strength of the solder structure is improved.

[0057] In the embodiment, the width of the protective opening 121 should be smaller than the width of the bonding pad 111. Thus, the bonding pad 111 is exposed in the protective opening 121. In the embodiment, the base conductive layer 130 of graphene material is arranged as the base structure of the conductive bump 150. The thermal expansion coefficient CTE of graphene is only 1 / 10-1 / 20 of that of copper and aluminum. Thus, the deformation stress of the UBM layer at the bottom of the copper bump can be better avoided. The base conductive layer 130 of graphene material covers the protective opening 121. The good hydrophobicity and stability of the multi-layer graphene can avoid the undercut problem of the bottom metal layer during the micro-etching process, regardless of chemical etching or plasma etching. Moreover, the conductivity of graphene is 100 times higher than that of other metals. The local good stability, conductivity and heat dissipation of the multi-layer graphene structure formed with the increase of the volume of graphene can further improve the conductivity and heat conduction performance of the overall connection structure. Moreover, the plurality of arc-shaped grooves effectively improve the contact area between the base conductive layer 130 and the combined conductive layer 140. Thus, the bonding force is improved.

[0058] In the embodiment, the combination conductive layer 140 includes the adhesive layer 141, the barrier layer 143, and the wetting layer 145. The adhesive layer 141 is covered on the base conductive layer 130 and partially accommodated in the plurality of first arc-shaped grooves 131. The barrier layer 143 is arranged on the adhesive layer 141. The wetting layer 145 is arranged on the barrier layer 143. The conductive protruding column 150 is arranged on the wetting layer 145. Specifically, the adhesive layer 141, the barrier layer 143, and the wetting layer 145 are arranged in sequence. The adhesive layer 141 can completely fill the plurality of first arc-shaped grooves 131, thereby playing a good adhesive role and improving the bonding force between the base conductive layer 130. The barrier layer 143 is used to prevent atomic diffusion. The wetting layer 145 is used to soak the conductive protruding column 150, thereby improving the wettability between the conductive protruding column 150 and the lower structure.

[0059] In the embodiment, the adhesive layer 141 is a titanium layer. A titanium carbide layer is formed at the interface between the adhesive layer 141 and the base conductive layer 130. Specifically, titanium carbide (TiC) can be formed at the interface between the adhesive layer 141 and the base conductive layer 130. The TiC is insoluble in water and has high chemical stability. The TiC hardly reacts with hydrochloric acid and sulfuric acid. The carbon atoms and titanium atoms are equivalent in the crystal lattice position. Therefore, the TiC atoms are combined by a strong covalent bond, have some properties similar to metals, such as high melting point, boiling point, and hardness, and have good thermal and electrical conductivity. The TiC even has superconducting performance at very low temperature. The titanium metal is added to improve the bonding force between the metals. The problem of poor bonding force caused by the combination of the graphene structure and the metal layer is solved. Compared with the plurality of first arc-shaped grooves 131, more titanium layers can be filled. The protruding column structure between the adjacent first arc-shaped grooves 131 can improve the support strength, thereby improving the bonding strength and the bonding force.

[0060] It is worth noting that, in the embodiment, the barrier layer 143 is at least one of nickel, chromium, and vanadium. The conductive protruding column 150 is a copper column. The wetting layer 145 is a copper layer, which can play a good soaking role.

[0061] In the embodiment, at least part of the thickness of the base conductive layer 130 is greater than the depth of the protection opening 121. The edge of the base conductive layer 130 extends outward to the surface of the protection layer 120 to cover the edge of the protection opening 121. Specifically, the height of the side of the base conductive layer 130 away from the wafer 110 is greater than the height of the protection layer 120. The protruding column structure between the adjacent two first arc-shaped grooves 131 can be higher than the protection opening 121. The edge of the base conductive layer 130 covers the edge of the protection opening 121, which can better prevent the etching solution from remaining at the edge of the protection opening 121, thereby further avoiding the undercut phenomenon.

[0062] In the embodiment, the edge of the adhesive layer 141 extends outward to the surface of the protection layer 120 to cover the edge of the base conductive layer 130, and the projection of the barrier layer 143 on the front surface of the wafer 110 and the projection of the wetting layer 145 on the front surface of the wafer 110 both fall within the projection range of the adhesive layer 141 on the front surface of the wafer 110, and the projection of the conductive stud 150 on the front surface of the wafer 110 falls within the projection range of the adhesive layer 141 on the front surface of the wafer 110. Specifically, in addition, the width of the adhesive layer 141 in the embodiment is greater than the width of the base conductive layer 130 and also greater than the width of the conductive stud 150, so as to form a stop structure at the bottom of the conductive stud 150, which can prevent the solder from side creeping to the bottom of the protection layer 120 and the bottom of the adhesive layer 141 after soldering.

[0063] Further, referring to Figure 3 , the conductive stud 150 is a copper stud, and the width of the copper stud is less than the width of the adhesive layer 141. After the wafer 110 is subsequently flipped onto the substrate 200 and the underfilling glue forms the glue layer 210, on one hand, the stop structure between the adhesive layer 141 and the conductive stud 150 can improve the roughness, so as to make the glue flow better and improve the adhesion between the glue and the metal layer and the conductive stud 150, and enhance the adhesion strength between the underfilling glue and the wafer 110 and the protection layer 120. On the other hand, the stop structure between the adhesive layer 141 and the conductive stud 150 can prevent the solder from side creeping to the bottom of the UBM layer after the solder cap 160 is soldered, so as to avoid the ion migration problem caused by the excessive solder contacting the adhesive layer 141 at the bottom, and also avoid the reaction between the solder and the metal layer at the bottom, so as to ensure the stability of the structure.

[0064] It should be noted that the width of the copper stud is less than the width of the adhesive layer 141, so that the width of the metal layer at the bottom of the copper stud is relatively increased, thereby improving the bearing area at the bottom, making the stress on the metal at the bottom more uniform, reducing the contact point pressure, and further avoiding the problem of cracking of the electrode at the bottom.

[0065] In the embodiment, the barrier layer 143 and the wetting layer 145 are both planarized structures, the adhesion layer 141 is provided with a receiving groove 147 away from the side of the wafer 110, the barrier layer 143 and the wetting layer 145 are arranged in the receiving groove 147, the depth of the receiving groove 147 is D1, the thickness of the barrier layer 143 is D2, and the thickness of the wetting layer 145 is D3, wherein D1=D2+D3. Specifically, the receiving groove 147 can be formed on the side surface of the adhesion layer 141 away from the wafer 110 by etching or laser slotting process or barrier mask electroplating process, the depth of the receiving groove 147 is D1, and then the barrier layer 143 and the wetting layer 145 are electroplated in the receiving groove 147, wherein the thickness D2 of the barrier layer 143 can be 4-6 μm, the thickness D3 of the wetting layer 145 is 2-4 μm, and the specific thickness can be determined according to the design requirement. By embedding the barrier layer 143 and the wetting layer 145 in the receiving groove 147, the overall bump height can be reduced, and the titanium carbide generated by graphene and titanium has good thermal and electrical conductivity and hardness, and even exhibits superconductivity at extremely low temperature, thereby protecting the barrier layer 143 and the wetting layer 145 and improving the bonding force of the copper pillar bump.

[0066] In the embodiment, the first metal layer 170 and the second metal layer 180 are further arranged between the conductive bump 150 and the cap 160, the first metal layer 170 is arranged on the surface of the conductive bump 150, the second metal layer 180 is arranged on the surface of the first metal layer 170, and the cap 160 is arranged on the surface of the second metal layer 180, the second metal layer 180 is used to block the diffusion atoms between the cap 160 and the conductive bump 150, and the first metal layer 170 is used to improve the adhesion between the second metal layer 180 and the conductive bump 150. Specifically, the first metal layer 170 can be a titanium layer, and the second metal layer 180 can be at least one of nickel, chromium, and vanadium.

[0067] The embodiment further provides a preparation method of the bump packaging structure 100, which is used for preparing the aforementioned bump packaging structure 100, and the preparation method comprises the following steps:

[0068] S1: providing a wafer 110 provided with a pad 111 on the front surface.

[0069] In combination with Figure 4 Firstly, a wafer 110 prepared in advance is provided, and the front surface of the wafer 110 is provided with a pad 111, and the pad 111 is electrically connected to the circuit layer inside the wafer 110.

[0070] S2: forming a protection layer 120 on the front surface of the wafer 110.

[0071] In combination with Figure 5Specifically, the liquid protective material, such as polyimide, is spin-coated on the front side of the wafer 110 by a spin-coating process, and then cured by soft baking in an oven.

[0072] S3: Slotting is performed on the protective layer 120 to form a protective opening 121 corresponding to the pad 111.

[0073] For reference, see Figure 6 Specifically, the position of the predetermined opening of the protective layer 120 can be shielded by a mask, and then the unexposed area is removed by spraying a developing solution by developing, so that the aluminum pad 111 opening position is exposed, and then the protective layer 120 is cured to a stable state by heating in an oven again. The surface of the protective layer 120 is cleaned of contaminants or residues using a plasma residue removal machine. Of course, the protective layer 120 here can also be a silicon nitride material.

[0074] S4: Forming a base conductive layer 130 in the protective opening 121.

[0075] For reference, see Figure 7 Specifically, the base conductive layer 130 includes multiple layers of graphene material. After the protective opening 121 is formed and the protective layer 120 is cured to a stable state, graphene material is coated on the protective layer 120, thereby forming a multi-layer graphene structure, wherein the graphene material fills the protective opening 121 and covers the surface of the protective layer 120 with a thickness of 4-8 μm, and then the graphene material is accelerated to a stable state by heating in an oven again, forming the base conductive layer 130.

[0076] S5: Slotting is performed on the base conductive layer 130 to form a plurality of first arc-shaped grooves 131.

[0077] For reference, see Figure 8 Specifically, an etching process is used, such as a plasma etching process or a chemical etching process, to etch and form a plurality of uniformly spaced first arc-shaped grooves 131 on the base conductive layer 130.

[0078] S6: Forming a combined conductive layer 140 on the base conductive layer 130.

[0079] For reference, see Figure 9 and Figure 10 Specifically, after the plurality of first arc-shaped grooves 131 are formed, the combined conductive layer 140 is formed to be partially accommodated in the first arc-shaped grooves 131, wherein an adhesive layer 141 is first electroplated on the base conductive layer 130, for example, using a barrier mask to electroplate a titanium layer with a thickness of 4-6 μm around the plurality of first arc-shaped grooves 131, the titanium layer having extremely high metal adhesion properties and being accommodated in the plurality of first arc-shaped grooves 131.

[0080] After the adhesive layer 141 is formed, a receiving groove 147 is formed on the side of the adhesive layer 141 away from the wafer 110, and then the barrier layer 143 and the wetting layer 145 are formed by electroplating in the receiving groove 147. The barrier layer 143 is at least one of nickel, vanadium, and chromium, and has a thickness of 4-6 microns. The wetting layer 145 is a copper layer, and has a thickness of 2-4 microns.

[0081] It is worth noting that when the barrier layer 143 is formed, the receiving groove 147 can be formed by first using a barrier mask to open the area to be electroplated on the adhesive layer 141, and then electroplating the metal layer again to form the barrier layer 143. A titanium layer is used to improve the bonding force between the metal layers, and then the metal layer is electroplated again using the barrier mask to form the wetting layer 145 covering the surface of the barrier layer 143. The use of the barrier mask for positioning electroplating can avoid the etching and patterning process after electroplating in the conventional process, and further avoid the problem of copper pillar undercut.

[0082] S7: Forming a conductive bump 150 on the combined conductive layer 140.

[0083] For a better understanding of the present application, refer to the accompanying drawings Figure 11 Specifically, after the wetting layer 145 is formed, a protective glue can be first coated, and then the wetting layer 145 is opened to electroplate a copper pillar on the wetting layer 145, thereby forming the conductive bump 150. Then the protective glue is removed, and the excess adhesive layer 141 is etched and removed.

[0084] S8: Forming a solder cap 160 on the conductive bump 150.

[0085] For a better understanding of the present application, refer to the accompanying drawings Figure 1 Specifically, before the solder cap 160 is formed, a first metal layer 170 and a second metal layer 180 need to be first formed on the conductive bump 150, i.e., after the conductive bump 150 is formed, a protective glue is coated again, and then the end surface of the conductive bump 150 is opened. The first metal layer 170 and the second metal layer 180 are then formed on the end surface of the conductive bump 150 by electroplating. Then the solder is filled into the opening by electroplating or printing process, and the excess photoresist is removed by a plasma residue removal machine to form a copper pillar with solder. After reflow, the solder cap 160 is formed. The solder can be tin solder.

[0086] In summary, the bump packaging structure 100 provided in the embodiment sets the graphene material base conductive layer 130 as the base structure of the conductive bump 150, the thermal expansion coefficient CTE of graphene is only 1 / 10-1 / 20 of copper and aluminum, which can better avoid deformation stress of the UBM layer at the bottom of the copper pillar, play a buffering role, protect the pads 111 of the wafer 110, achieve better stress release, and avoid the problem of cracking of the electrodes (pads 111) of the wafer 110. At the same time, the graphene material base conductive layer 130 covers and protects the opening 121, and the good hydrophobicity and stability of the multi-layer graphene can avoid the undercut problem of the bottom metal layer during the micro-etching process, whether chemical etching or plasma etching is used. Moreover, the conductivity of graphene is 100 times higher than that of other metals, and the local good stability, conductivity and heat dissipation of the multi-layer graphene structure formed with the increase of the volume of graphene can further improve the conductivity and heat dissipation performance of the overall connection structure. The stability of graphene (the thermal expansion coefficient CTE of graphene is only 1 / 10-1 / 20 of copper and aluminum) solves the problem that the copper pillar in the traditional technology causes a large stress in the package body, which leads to damage to the brittle material layer, such as rupture of the pads 111 of the wafer 110 at the bottom of the copper pillar, delamination of the UBM metal layer, or reduction of the solder fatigue life. Moreover, by setting multiple arc-shaped grooves, the contact area between the base conductive layer 130 and the combined conductive layer 140 is effectively improved, thereby improving the bonding force. In addition, by setting the width of the conductive bump 150 to be smaller than the width of the adhesive layer 141, a stop structure can be formed between the adhesive layer 141 and the conductive bump 150, thereby improving the adhesive properties of the colloid while preventing solder side climbing, further ensuring the stability of the structure.

[0087] Second embodiment

[0088] Reference Figure 12 The bump packaging structure 100 provided in the embodiment has the same basic structure, principle, and technical effects as the first embodiment. For brevity, the parts not mentioned in this embodiment can be referred to the corresponding contents in the first embodiment.

[0089] In the embodiment, the side surface of the barrier layer 143 away from the wafer 110 is provided with multiple second arc-shaped grooves 149, and the multiple second arc-shaped grooves 149 are arranged at intervals. The wetting layer 145 is accommodated in the multiple second arc-shaped grooves 149. Specifically, the thickness of the barrier layer 143 is relatively thick, and the second arc-shaped grooves 149 do not penetrate the barrier layer 143, which can avoid direct contact between the wetting layer 145 and the adhesive layer 141, and also improve the contact area between the wetting layer 145 and the barrier layer 143, thereby improving the bonding force.

[0090] In the embodiment, the plurality of second arc-shaped grooves 149 are arranged staggered with the plurality of first arc-shaped grooves 131. Specifically, the midlines of the plurality of second arc-shaped grooves 149 and the midlines of the plurality of first arc-shaped grooves 131 do not overlap with each other, so as to ensure that the first arc-shaped grooves 131 and the second arc-shaped grooves 149 are not structurally overlapped, and thus the whole structure is more staggered and uniformly distributed, avoiding that the local structural strength is too small to affect the overall structural strength.

[0091] In the embodiment, the depth H2 of the second arc-shaped groove 149 is the same as the depth H1 of the first arc-shaped groove 131, and the distance from the interface of the bonding layer 141 and the barrier layer 143 to the wetting layer 145 and the conductive layer 130 of the substrate is the same. Specifically, the thickness of the bonding layer 141 and the barrier layer 143 is the same in the embodiment, and the depth H1 of the first arc-shaped groove 131 is the same as the depth H2 of the second arc-shaped groove 149, so that the lower protruding part in the bonding layer 141 accommodated in the first arc-shaped groove 131 and the upper protruding part in the barrier layer 143 between the adjacent two second arc-shaped grooves 149 are symmetrically designed, and the support force can be improved. For example, when the stress direction is conducted from the conductive protruding column 150, the upper protruding block structure on the adjacent barrier layer 143 also can support the stress of the end of the conductive protruding column 150, and when the stress direction is conducted from the wafer 110 side, the lower protruding block structure formed by the bonding layer 141 plays a supporting role, so that good support can be obtained in any direction. At the same time, the plurality of first arc-shaped grooves 131 and the plurality of second arc-shaped grooves 149 can buffer the transverse stress, further improve the bottom stress release capability, and avoid the crack of the lower pad 111.

[0092] In the embodiment, the width of the first arc-shaped groove 131 and the second arc-shaped groove 149 is the same, and the interval distance between the adjacent two first arc-shaped grooves 131 is the same as the interval distance between the adjacent two second arc-shaped grooves 149, so that part of the barrier layer 143 and part of the bonding layer 141 are symmetrically arranged along the boundary surface. Specifically, the upper protruding block structure between the adjacent two first arc-shaped grooves 131 is symmetrical with the lower protruding block structure accommodated in the second arc-shaped groove 149 by the wetting layer 145, and the upper protruding block structure between the adjacent two second arc-shaped grooves 149 is symmetrical with the lower protruding block structure accommodated in the first arc-shaped groove 131 by the bonding layer 141.

[0093] It is worth noting that in the embodiment, the wetting layer 145 is filled in the second arc-shaped groove 149 structure, and the thickness of the wetting layer 145 is the same as the depth of the second arc-shaped groove 149, so that the wetting layer 145 is only accommodated in the second arc-shaped groove 149 and does not protrude upward relative to the barrier layer 143. When the copper is electroplated to form the conductive pillar 150, since the wetting layer 145 is only accommodated in the second arc-shaped groove 149, the volume of the wetting layer 145 can be increased, and the contact area of the conductive pillar 150 with the wetting layer 145 is reduced, thereby increasing the copper ions in the seed layer, and further improving the growth rate of the copper pillar and the wetting performance of the copper pillar.

[0094] It is also necessary to note that when the second arc-shaped groove 149 is formed, the step S6 provided in the first embodiment can be performed, that is, the combined conductive layer 140 is formed on the base conductive layer 130.

[0095] Specifically, when the combined conductive layer 140 is formed, first, the adhesion layer 141 is made, after the base conductive layer 130 is prepared, the area to be electroplated is opened by using the barrier mask, and then the metal layer (titanium layer) is electroplated again to form the adhesion layer 141, wherein the adhesion layer 141 fills the first arc-shaped groove 131. The titanium layer is used to improve the bonding force between the metal layers, and then the area to be electroplated is opened by using the barrier mask again, and then the metal layer is electroplated again to form the barrier layer 143 covering the surface of the adhesion layer 141, and then the barrier layer 143 is etched by using the plasma etching method or the chemical etching method to form a plurality of second arc-shaped grooves 149, and then the metal layer is electroplated again to form the wetting layer 145 and form a flat structure, wherein the wetting layer 145 only fills the groove, so that the wetting layer 145 is embedded in the inside of the barrier layer 143. The metal layer formed by using the barrier mask method can avoid the method of removing the metal layer by using micro-etching after the metal layer is formed around the copper pillar in the traditional technology, thereby further preventing the undercut problem of the copper pillar.

[0096] The bump package structure 100 provided in the embodiment adopts a double-layer groove structure, which can further improve the contact area between adjacent layers, thereby improving the bonding force, and can also improve the buffering and supporting capability, so that the structure is more stable.

[0097] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements within the technical range disclosed in the present application can be easily thought by those skilled in the art, which shall be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A bump encapsulation structure, characterized in that, include: A wafer, wherein pads are provided on the front side of the wafer; A protective layer is disposed on the front side of the wafer, and the protective layer has protective openings corresponding to the pads; It is disposed within the protective opening and covers the base conductive layer of the protective opening; A combined conductive layer disposed on the substrate conductive layer; Conductive protrusions disposed on the combined conductive layer; And, a solder cap disposed on the conductive protrusion; The conductive substrate layer comprises multiple layers of graphene material, and a plurality of first arc-shaped grooves are provided on the side of the conductive substrate layer away from the wafer. The plurality of first arc-shaped grooves are spaced apart, and the combined conductive layer is partially accommodated within the plurality of first arc-shaped grooves. The edge of the conductive base layer extends outward to the surface of the protective layer and is arc-shaped to cover the edge of the protective opening and prevent etching solution from remaining at the edge of the protective opening. The combined conductive layer includes an adhesive layer, a barrier layer, and a wetting layer. The adhesive layer covers the substrate conductive layer and is partially housed within the plurality of first arc-shaped grooves. The barrier layer is disposed on the adhesive layer, the wetting layer is disposed on the barrier layer, and the conductive protrusions are disposed on the wetting layer. The barrier layer has a plurality of second arc-shaped grooves on its surface away from the wafer. The second arc-shaped grooves do not penetrate the barrier layer. The plurality of second arc-shaped grooves are spaced apart, and the wetting layer is housed within the plurality of second arc-shaped grooves.

2. The bump encapsulation structure according to claim 1, characterized in that, The adhesive layer is a titanium layer, and a titanium carbide layer is formed at the interface between the adhesive layer and the substrate conductive layer.

3. The bump encapsulation structure according to claim 1, characterized in that, The thickness of at least a portion of the conductive layer on the substrate is greater than the depth of the protective opening.

4. The bump encapsulation structure according to claim 3, characterized in that, The edge of the adhesive layer extends outward to the surface of the protective layer to cover the edge of the substrate conductive layer, and the projections of the barrier layer and the wetting layer on the front side of the wafer both fall within the projection range of the adhesive layer on the front side of the wafer, and the projections of the conductive protrusions on the front side of the wafer also fall within the projection range of the adhesive layer on the front side of the wafer.

5. The bump encapsulation structure according to claim 1, characterized in that, The second arc-shaped grooves are staggered with the first arc-shaped grooves.

6. The bump encapsulation structure according to claim 5, characterized in that, The depth H2 of the second arc-shaped groove is the same as the depth H1 of the first arc-shaped groove, and the distance from the interface between the adhesive layer and the barrier layer to the wetting layer and the substrate conductive layer is the same.

7. The bump encapsulation structure according to claim 6, characterized in that, The first arc-shaped groove and the second arc-shaped groove have the same width, and the spacing between two adjacent first arc-shaped grooves is the same as the spacing between two adjacent second arc-shaped grooves, so that part of the blocking layer and part of the adhesive layer are symmetrically arranged along the interface.

8. The bump encapsulation structure according to claim 1, characterized in that, A first metal layer and a second metal layer are further disposed between the conductive protrusion and the solder cap. The first metal layer is disposed on the surface of the conductive protrusion, the second metal layer is disposed on the surface of the first metal layer, and the solder cap is disposed on the surface of the second metal layer. The second metal layer is used to block the diffusion of atoms between the solder cap and the conductive protrusion, and the first metal layer is used to improve the adhesion between the second metal layer and the conductive protrusion.

9. A method for fabricating a bump encapsulation structure, used to fabricate the bump encapsulation structure as described in any one of claims 1-8, characterized in that, The preparation method includes: Provide a wafer with pads on the front side; A protective layer is formed on the front side of the wafer; Grooves are cut into the protective layer to form protective openings corresponding to the solder pads; A base conductive layer is formed within the protective opening; Multiple first arc-shaped grooves are formed by slotting on the conductive substrate layer; A combined conductive layer is formed on the substrate conductive layer; Conductive protrusions are formed on the combined conductive layer; A solder cap is formed on the conductive protrusion; The substrate conductive layer comprises multiple layers of graphene material, and a plurality of first arc-shaped grooves are spaced apart. The combined conductive layer is partially accommodated within the plurality of first arc-shaped grooves.

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