Compensation capacitor layout in semiconductor devices

Abstract

This application relates to the layout of compensation capacitors in semiconductor devices. Apparatus and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer comprising a portion; a second conductive layer; a contact coupled to the portion of the first conductive layer; a third conductive layer located between the first and second conductive layers, the third conductive layer being coupled to the contact; and one or more capacitor elements, wherein each of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

Description

Technical Field

[0001] This application relates to semiconductor devices, and more particularly to the arrangement of compensation capacitors in semiconductor devices. Background Technology

[0002] High data reliability, high memory access speed, reduced chip size, and lower power consumption are desirable characteristics for semiconductor memories. Due to the reduced supply voltage and chip size, power supply noise can adversely affect performance. Compensation capacitors are already used in the device to stabilize the power supply. Semiconductor memory devices such as DRAM (Dynamic Random Access Memory) include, for example, an array of memory cells with memory cells. Compensation capacitors can be included in the peripheral circuitry area outside the memory cell array, which has a structure similar to that of the memory cells.

[0003] The compensation capacitors included in the peripheral circuit area may comprise capacitor cells consisting of two or more capacitors connected in series. Since the voltage across each capacitor, having a structure similar to a memory cell, is less than the voltage difference between the supply voltages (e.g., VDD and VSS), the voltage across the capacitor cell consisting of two or more capacitors can be matched to the voltage difference between the supply voltages. The capacitor cells consisting of two or more compensation capacitors connected in series can be contained in unused space within the logic block of the peripheral circuit area. However, space within the logic block of the peripheral circuit area smaller than the area containing two or more capacitors for the capacitor cell can remain unused. More flexible structures for the compensation capacitors included in the peripheral circuit area may be required for efficient use of space within the logic block of the peripheral circuit area. Summary of the Invention

[0004] In one aspect, this application provides an apparatus comprising: a first conductive layer including a portion; a second conductive layer; a contact coupled to a portion of the first conductive layer; a third conductive layer located between the first conductive layer and the second conductive layer, and coupled to the contact; and one or more capacitor elements, wherein each of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

[0005] In another aspect, this application provides a device comprising: a first conductive layer including a first electrical portion, a second electrical portion, a first intermediate portion, and a second intermediate portion; a second conductive layer including the first portion and the second portion; a third conductive layer located between the first conductive layer and the second conductive layer, and the third conductive layer including a first portion and a second portion respectively coupled to the first intermediate portion and the second intermediate portion of the first conductive layer; a first capacitor including: one or more first capacitor elements including one end and another end, the one end being coupled to the first portion of the third conductive layer and the other end being coupled to the first portion of the second conductive layer; and a first electrical contact including the first portion coupled to the second conductive layer. The capacitor comprises: one end of a first conductive layer and the other end of a first electrical portion coupled to a first conductive layer; a first contact comprising one end of a first portion coupled to a third conductive layer and the other end of a first intermediate portion coupled to the first conductive layer; and a second capacitor comprising: one or more second capacitor elements comprising one end and the other end, the one end being coupled to a second portion of the third conductive layer and the other end being coupled to a second portion of the second conductive layer; a second electrical contact comprising one end of a second portion coupled to a second conductive layer and the other end of a second electrical portion coupled to the first conductive layer; and a second contact comprising one end of a second portion coupled to a second conductive layer and the other end of a second intermediate portion coupled to the first conductive layer.

[0006] In another aspect, this application provides an apparatus comprising: a first capacitor coupled to a first power line; a second capacitor coupled to a second power line; and an intermediate line configured to couple the first capacitor to the second capacitor, wherein the first power line, the second power line, and the intermediate line are contained in a layer. Attached Figure Description

[0007] Figure 1 This is a diagram showing the layout of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a circuit diagram of a portion of a semiconductor device including a capacitor according to an embodiment of the present disclosure.

[0009] Figure 3 This is a diagram of a capacitor in a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4 This is a diagram showing the layout of a logic circuit block including a capacitor in a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5 This is a circuit diagram of a portion of a semiconductor device including a capacitor according to an embodiment of the present disclosure.

[0012] Figure 6AThis is a diagram of a portion of a semiconductor device including a capacitor element according to an embodiment of the present disclosure.

[0013] Figure 6B This is a diagram of a portion of a semiconductor device including a capacitor element according to an embodiment of the present disclosure.

[0014] Figure 7 This is a diagram showing the layout of a logic circuit block including a capacitor in a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 8A This is a vertical cross-sectional view showing a schematic structure of a capacitor element according to an embodiment of the present disclosure.

[0016] Figure 8B This is a horizontal cross-sectional view showing a schematic structure of a capacitor element according to an embodiment of the present disclosure.

[0017] Figure 9A This is a vertical cross-sectional view showing a schematic structure of a capacitor element according to an embodiment of the present disclosure.

[0018] Figure 9B This is a horizontal cross-sectional view showing a schematic structure of a capacitor element according to an embodiment of the present disclosure.

[0019] Figure 10A This is a vertical cross-sectional view showing a schematic structure of a capacitor element according to an embodiment of the present disclosure.

[0020] Figure 10B This is a horizontal cross-sectional view showing a schematic structure of a capacitor element according to an embodiment of the present disclosure. Detailed Implementation

[0021] Certain details are set forth below to provide a full understanding of examples of various embodiments of this disclosure. However, those skilled in the art will understand that the examples described herein can be practiced without these specific details. Furthermore, the specific examples of this disclosure described herein should not be construed as limiting the scope of this disclosure to those specific examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring embodiments of this disclosure. Additionally, terms such as “coupled” mean that two components can be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0022] Figure 1This is a diagram illustrating an example layout of a semiconductor device 10 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device 10 may include a memory cell array 11 and a peripheral region 12. The memory cell array 11 may be divided into sixteen memory banks BK0 to BK15. Various peripheral circuits and external terminals (not shown) may be disposed in the peripheral circuit region 12. For example, a line decoder circuit (not shown) may be disposed between adjacent memory banks and / or in the peripheral circuit region 12. Input / output (DQ) circuitry may be disposed in the peripheral circuit region 12. The peripheral circuit region 12 may include a logic circuit block 13. The logic circuit block 13 may include compensation capacitors (not shown).

[0023] Figure 2 This is a circuit diagram of a portion 20 of a semiconductor device including a pair of capacitors 21A and 21B and another pair of capacitors 21'A and 21'B according to embodiments of the present disclosure. In some embodiments, capacitor 21 may be provided Figure 1 In one or more logic circuit blocks 13. Each of capacitors 21A and 21'A has a node coupled to power node 22A and another node coupled to intermediate node 23. Each of capacitors 21B and 21'B has a node coupled to power node 22B and another node coupled to intermediate node 23. In some embodiments, power node 22A can provide a positive power supply voltage VDD. In some embodiments, power node 22B can provide a ground voltage GND or a negative power supply voltage VSS. In some embodiments, intermediate node 23 can provide an intermediate voltage. For example, in some embodiments of this disclosure, intermediate node 23 can provide a voltage that is the average of the voltages of power nodes 22A and 22B.

[0024] Figure 3 This is a diagram of a capacitor 30 in a semiconductor device according to an embodiment of the present disclosure. In some embodiments, Figure 2One or more of capacitors 21A, 21'A, 21B, and 21'B may include capacitor 30. Capacitor 30 may include capacitor elements 31 coupled in parallel. Each of the capacitor elements 31 may have one end coupled to a conductive layer 34 (e.g., conductive layer 0) and another end coupled to an intermediate layer 35. In some embodiments, each of the capacitor elements 31 may have a cylindrical shape. In some embodiments, each of the capacitor elements 31 may have a cylindrical shape. In some embodiments, the conductive layer 34 may be a metal layer 0 comprising one or more conductive materials. Capacitor 30 may include contacts 36 coupled to the conductive layer 34 and the power component 32. In some embodiments, the conductive layer 34 may be coupled to the contacts 36. The power component 32 may be included in another conductive layer (e.g., conductive layer 1). The power component 32 may provide a power supply voltage (e.g., VDD, ground voltage, or VSS). Therefore, the power component 32, contacts 36, and conductive layer 34 may be included in a power node such as power node 22A or power node 22B.

[0025] Intermediate layer 35 coupled to the other end of capacitor element 31 may comprise a conductive material, such as polysilicon. Capacitor 30 may include contacts 37 of an intermediate portion 33 coupled to intermediate layer 35 and to another conductive layer (e.g., conductive layer 1). Intermediate layer 35 may be coupled to contacts 37. The intermediate portion 33 may be included in a conductive layer (e.g., conductive layer 1) comprising one or more conductive materials. For example, the conductive layer may be a metal layer 1. Intermediate layer 35 may be disposed between conductive layer 34 (e.g., conductive layer 0) and a conductive layer (e.g., conductive layer 1) comprising power node 32 and intermediate node 33. Therefore, the intermediate portion 33, contacts 37, and conductive layer 35 may be included in an intermediate node such as intermediate node 23. Intermediate portion 33 may have a voltage different from the power supply voltage of power portion 32. Contacts 36 and 37 may comprise conductive material. Contacts 36 and 37 may be contact plugs or conductive vias. In some embodiments, contacts 36 and 37 may be formed in parallel. In some embodiments, contacts 36 and 37 may be formed separately.

[0026] Figure 4 This is a diagram showing the layout of a logic circuit block 40 including capacitors 41A and 41B in a semiconductor device according to an embodiment of the present disclosure. The layout is a plan view from a direction perpendicular to each of the conductive layers and intermediate layers included in the logic circuit block 40. In some embodiments, the logic circuit block 40 may be... Figure 1 One of the logic circuit blocks 13. The logic circuit block 40 may include conductive layers extending in a first direction 401 and a second direction 402 perpendicular to the first direction 401, such as... Figure 3 Conductive layer 0 and conductive layer 1 in the example. Figure 3One of the conductive layers 1 may include a plurality of power lines extending parallel in a first direction 401. In some embodiments, the power lines may be arranged in parallel at equal intervals defined by the distance between power lines in a second direction 402. In some embodiments, a logic row may be defined by two power lines spaced apart. In some embodiments, instead of a series of capacitors that may require more rows, each capacitor may be arranged across several rows, as in... Figure 4 In this example, there are three rows. Therefore, each capacitor can be placed in a relatively small available area. The power lines may comprise several types of power lines extending alternately in parallel along the first direction 401. The first type of power line, comprising power lines 42A, 42'A, and 42”A, can provide a power supply voltage (e.g., VDD). Power lines 42A, 42'A, and 42”A can be… Figure 2 Power node 22A or Figure 3 The conductive layer 1 contains a power node 32. A second type of power line, including power lines 42B and 42'B, can provide a ground voltage (GND). Power lines 42B and 42'B can be... Figure 2 Power node 22B or Figure 3 The power node 32 is included in the conductive layer 1. The logic circuit block 40 may include multiple capacitors, including capacitors 41A and 41B. In some embodiments, capacitor 41A may include... Figure 2 Capacitors 21A and 21'A are included, and capacitor 41B may include Figure 2 Capacitors 21B and 21'B are included. In some embodiments, each of capacitors 41A and 41B may be... Figure 3 The capacitor 30 is included. In some embodiments, the number of capacitors 41A and 41B may be the same. In some embodiments, a constant (equal) capacitance may be given to each of capacitors 41A and 41B.

[0027] Each of capacitors 41A may contain an orientation Figure 4 The top side and facing Figure 4 The bottom of the capacitor is located on the opposite side of the aforementioned side. When viewed from a direction perpendicular to directions 401 and 402, each of the capacitors 41A may be positioned between a power line (e.g., power line 42A) providing a power supply voltage (e.g., VDD) adjacent to or near one side of the capacitor 41A and another power line (e.g., power line 42B) providing a ground voltage (GND) adjacent to or near the other side of the capacitor 41A. The capacitor 41A may include another conductive layer 44A. For example, the conductive layer 44A may extend parallel to the conductive layer (e.g., conductive layer 1) containing the power lines. Figure 3 The conductive layer 34 (e.g., conductive layer 0). The conductive layer 44A may have an orientation towards Figure 4 The top side and facing Figure 4 The bottom side opposite to the said one side. In some embodiments, one side and the other side of the conductive layer 44A may extend in a first direction 401. The conductive layer 44A may be coupled to a power line 42A located above and close to one side of the conductive layer 44A. The conductive layer 44A may also be coupled to a power line 42'A located above and close to the other side of the conductive layer 44A. Therefore, the capacitor 41A may receive a power supply voltage (e.g., VDD) from the power lines 42A and 42'A.

[0028] Each of capacitors 41B may contain an orientation towards Figure 4 The top side and facing Figure 4 The bottom of the capacitor is opposite to the side described above. When viewed from directions perpendicular to directions 401 and 402, each of the capacitors 41A may be positioned between a power line (e.g., power line 42B) providing a ground voltage (GND) on one side of the capacitor 41B and another power line (e.g., power line 42”A) providing a power voltage (e.g., VDD) on the other side of the capacitor 41B. The capacitor 41B may include another conductive layer 44B. For example, the conductive layer 44B may extend parallel to the conductive layer (e.g., conductive layer 1) containing the power lines. Figure 3 The conductive layer 34 (e.g., conductive layer 0). The conductive layer 44B may have an orientation towards Figure 4 The top side and facing Figure 4 The bottom of the conductive layer 44B is opposite to the said one side. In some embodiments, one side and the other side of the conductive layer 44B may extend in a first direction 401. The conductive layer 44B may be coupled to a power line 42B located above and close to one side of the conductive layer 44B. The conductive layer 44B may also be coupled to a power line 42'B located above and close to the other side of the conductive layer 44B. Therefore, the capacitor 41B may receive ground voltage (GND) from the power lines 42B and 42'B.

[0029] Capacitor 41A may be coupled to intermediate line 43A, which is coupled to intermediate line 43. In some embodiments, intermediate line 43A may be... Figure 2 The intermediate node 23. The intermediate line 43A may be contained in the same conductive layer along with power lines 42A and 42'A. The intermediate line 43A may have a voltage different from that of the power lines 42A and 42'A. A capacitor 41B may be coupled to the intermediate line 43B, which in turn is coupled to the intermediate line 43. In some embodiments, the intermediate line 43B may be... Figure 2The intermediate node 23. The intermediate line 43B can be included in the same conductive layer along with the power lines 42B and 42'B. The intermediate line 43B may have a voltage different from that of the power lines 42B and 42'B. In some embodiments, the voltage of the intermediate line 43 may be the average of the voltages on the power lines 42A and 42B (e.g., VDD / 2). Because the intermediate line 43 can couple any of the capacitors 41A to any of the capacitors 41B, each pair of capacitors 41A and 41B can be arranged separately from each other. Each pair of capacitors 41A and 41B does not need to be able to accommodate a region (e.g., a region of five rows) that houses the pair of capacitors 41A and 41B together. Instead, the pair of capacitors 41A and 41B can be arranged individually in separate regions of three rows that are far apart from each other. Therefore, the intermediate line 43 provides the freedom to arrange the capacitors 41 together or separately in a relatively small area in a flexible manner.

[0030] Figure 5 This is a circuit diagram of a portion 50 of a semiconductor device including a pair of capacitors 51A and 51B and another pair of capacitors 51'A and 51'B according to embodiments of the present disclosure. In some embodiments, capacitor 51 may be provided Figure 1 In one or more logic circuit blocks 13. Capacitor 51A has a node coupled to power node 52A and another node coupled to intermediate node 53. Capacitor 51B has a node coupled to power node 52B and another node coupled to intermediate node 53. Capacitor 51'A has one node coupled to power node 52A and another node coupled to intermediate node 51'C. Capacitor 51'B has one node coupled to power node 52B and another node coupled to node 51'C. Therefore, capacitors 51'A and 51'B may be connected in series between power nodes 52A and 52B. In some embodiments, power node 52A may provide a positive power supply voltage VDD. In some embodiments, power node 52B may provide a ground voltage GND or a negative power supply voltage VSS. In some embodiments, intermediate node 53 may provide an intermediate voltage. For example, in some embodiments of this disclosure, intermediate node 23 may provide a voltage that is the average of the voltages of power nodes 52A and 52B.

[0031] Figure 6A This is a diagram of a portion 60 of a semiconductor device including capacitor elements 61A and 61B according to an embodiment of the present disclosure. In some embodiments, portion 60 may be included in... Figure 5 In some of the 50 portions, in some embodiments, Figure 5Each of capacitors 51A and 51B may respectively include a plurality of corresponding capacitor elements 61A and 61B. In some embodiments, each of capacitor elements 61A and 61B may have a cylindrical shape. In some embodiments, each of capacitor elements 61A and 61B may have a cylindrical shape.

[0032] Capacitor element 61A may be coupled in parallel, thus having one end coupled to conductive layer 64A (e.g., conductive layer 0) and the other end coupled to intermediate layer 65A. In some embodiments, contact 66A may be coupled to conductive layer 64A and to a power portion 62A coupled to another conductive layer (e.g., conductive layer 1). Power portion 62A may provide a supply voltage (e.g., VDD). In some embodiments, power portion 62A, contact 66A, and conductive layer 64A may be included in a power node such as power node 52A.

[0033] Intermediate layer 65A may be coupled to the other end of capacitor element 61A. Intermediate layer 65A may be coupled to contact 67A. Contact 67A may be coupled to intermediate portion 63A. Intermediate portion 63A may be contained in a conductive layer (e.g., conductive layer 1). Intermediate portion 63A may have a voltage different from the power supply voltage of power portion 62A.

[0034] Capacitor element 61B may be coupled in parallel, having one end coupled to conductive layer 64B (e.g., conductive layer 0) and another end coupled to intermediate layer 65B. In some embodiments, contact 66B may have one end coupled to conductive layer 64B and the other end coupled to another power portion 62B of another conductive layer (e.g., conductive layer 1). Power portion 62B may provide a supply voltage (e.g., ground voltage GND or VSS). In some embodiments, power portion 62B, contact 66B, and conductive layer 64B may be included in another power node such as power node 52B.

[0035] Intermediate layer 65B may be coupled to the other end of capacitor element 61B. Intermediate layer 65B may be coupled to contact 67B. Contact 67B may be coupled to intermediate portion 63B. Intermediate portion 63B may be contained in a conductive layer (e.g., conductive layer 1). Intermediate portion 63B may have a voltage different from the power supply voltage of power portion 62B. Intermediate portions 63A and 63B may be coupled to a common center line 63. Common center line 63 may be contained in a conductive layer (e.g., conductive layer 1).

[0036] Figure 6B This is a diagram of portion 60' of a semiconductor device including capacitor elements 61'A and 61'B according to an embodiment of the present disclosure. In some embodiments, portion 60' may be included in Figure 5 In some of the 50 portions, in some embodiments, Figure 5Each of capacitors 51'A and 51'B may respectively include a plurality of corresponding capacitor elements 61'A and 61'B. In some embodiments, each of capacitor elements 61'A and 61'B may have a cylindrical shape. In some embodiments, each of capacitor elements 61'A and 61'B may have a cylindrical shape.

[0037] Part 60' may include a pair of capacitors 61', the pair of capacitors 61' comprising capacitor elements 61'A and 61'B connected in series via an intermediate layer 65'. In some embodiments, the intermediate layer 65' may be included in Figure 5 In node 51'C. Capacitor element 61'A may be coupled in parallel, thus having one end coupled to conductive layer 64'A (e.g., conductive layer 0) and the other end coupled to intermediate layer 65'. In some embodiments, conductive layer 64'A may be coupled to a power portion 62'A of another conductive layer (e.g., conductive layer 1) via contact 66'A. Power portion 62'A may provide a power supply voltage (e.g., VDD). In some embodiments, power portions 62A and 62'A may be coupled to a power line providing a power supply voltage (e.g., VDD). In some embodiments, power portions 62A and 62'A may be coupled to a separate power line providing a power supply voltage (e.g., VDD).

[0038] Capacitor element 61'B may be coupled in parallel, thus having one end coupled to conductive layer 64'B (e.g., conductive layer 0) and the other end coupled to intermediate layer 65', which is coupled to capacitor element 61'A. In some embodiments, conductive layer 64'B may be coupled via contact 66'B to a power section 62'B included in another conductive layer (e.g., conductive layer 1). Power section 62'B may provide a power supply voltage (e.g., ground voltage GND or VSS). In some embodiments, power sections 62B and 62'B may be coupled to a power line providing a power supply voltage (e.g., ground voltage GND or VSS). In some embodiments, power sections 62B and 62'B may be coupled to a separate power line providing a power supply voltage (e.g., ground voltage GND or VSS).

[0039] In some embodiments, intermediate layers 65A and 65B may be disposed in the layers between conductive layers 64A and 64B in conductive layer 0 and intermediate portions 63A and 63B in conductive layer 1, respectively. In some embodiments, intermediate layer 65' may be disposed between conductive layer 0 containing conductive layers 64'A and 64'B and conductive layer 1 containing power portions 63A and 63B. In some embodiments, conductive layer 0 containing conductive layers 64A, 64B, 64'A, and 64'B may contain one or more conductive materials. For example, conductive layer 0 may be a metal layer. In some embodiments, conductive layer 1 containing intermediate portions 63A and 63B, a common intermediate line 63, and power nodes 62A, 62B, 62'A, and 62'B may contain one or more conductive materials. For example, conductive layer 1 may be a metal layer. In some embodiments, intermediate layers 65A, 65B, and 65' may contain conductive materials, such as polysilicon. Contacts 66A, 66B, 67A, 67B, 66'A, and 66'B may comprise conductive material. Contacts 66A, 66B, 67A, 67B, 66'A, and 66'B may be contact plugs or conductive vias. In some embodiments, contacts 66A, 66B, 67A, 67B, 66'A, and 66'B may be formed in parallel. In some embodiments, contacts 66A, 66B, 67A, 67B, 66'A, and 66'B may be formed individually.

[0040] Figure 7 This is a diagram showing the layout of a logic circuit block 70 comprising cells 71A, 71B, and 71' in a semiconductor device, according to an embodiment of the present disclosure. The layout is viewed from a direction perpendicular to the layers such as the conductive layers and intermediate layers included in the logic circuit block 70. In some embodiments, the logic circuit block 70 may be... Figure 1 One of the logic circuit blocks 13. Logic circuit block 70 may include conductive layers extending in a first direction 701 and a second direction 702 perpendicular to the first direction 701, such as conductive layer 0 and conductive layer 1 in FIG6. One of the conductive layers of conductive layer 1 in FIG6 may include a plurality of power lines extending parallel to each other in the first direction 701. In some embodiments, the power lines may be arranged in parallel at equal intervals defined by the distance between the power lines in the second direction 702. In some embodiments, a logic row may be defined by two power lines spaced apart. In some embodiments, each of capacitors 71A and 71B may be arranged across several rows, as in Figure 7 In this example, there are three rows. Therefore, each of capacitors 71A and 71B can be positioned within a relatively small available area. In some embodiments, each of capacitors 71A can be... Figure 5 The capacitor 51A in Figure 5 or the capacitor element 61A in Figure 6. Each of the capacitors 71B can be Figure 5The capacitor 51B in Figure 71A or capacitor element 61B in Figure 6. In some embodiments, the number of capacitors 71A and the number of capacitors 71B may be the same. In some embodiments, each of capacitors 71A and 71B may have a constant (same) capacitance.

[0041] Each pair of capacitors 71' can be set across several rows, such as in Figure 7 In this example, the five elements are represented. Therefore, each pair of capacitors 71' can be located in an area larger than the area where each of the capacitors 71A and 71B is located. Each pair of capacitors 71' can contain two or more capacitors connected in series, such as... Figure 5 The capacitor pair 51' in Figure 5 or the capacitor pair 61' in Figure 6. The power supply lines may comprise several types of power supply lines extending alternately in parallel in a first direction 701. A first type of power supply line, including power lines 72A, 72”A, and 72”'A, can provide a power supply voltage (e.g., VDD). Power lines 72A, 72”A, and 72”'A may be... Figure 5 The power node 52A in Figure 6 or the power node 62A and / or 62'A contained in conductive layer 1 in Figure 6. A second type of power line including power lines 72B, 72'B, 72”B, and 72”'B can provide ground voltage (GND). Power lines 72B, 72'B, 72”B, and 72”'B can be... Figure 5 The power node 52B in the figure or the power node 62B and / or 62'B contained in the conductive layer 1 in Figure 6.

[0042] Capacitors 71A and 71B may be coupled to centerline 73. In some embodiments, centerline 73 may be... Figure 5The intermediate node 53 or the common intermediate line 63 of Figure 6. The intermediate line 73 may be contained in the same conductive layer together with the power lines 72A, 72”A, 72”'A, 72B, 72’B, 72”B, and 72”'B. The intermediate line 43A is insulated from the power lines 72A, 72”A, 72”'A, 72B, 72’B, 72”B, and 72”'B (e.g., not coupled to the power lines 72A, 72”A, 72”'A, 72B, 72’B, 72”B, and 72”'B). In some embodiments, the voltage of the intermediate line 73 may be the average of the voltages on the power lines 72A and 72B (e.g., VDD / 2). Because the intermediate line 73 can couple any of the capacitors 71A to any of the capacitors 71B, each pair of capacitors 71A and 71B may be arranged separately from each other. Each pair of capacitors 71A and 71B does not need to be housed in a single area (e.g., a five-row area). Instead, the pair of capacitors 71A and 71B can be individually located in separate areas of three rows apart from each other. Thus, the center line 73 provides the freedom to arrange capacitors 71A and 71B together or separately in a relatively small area.

[0043] Figure 8A This is a vertical cross-sectional view showing a schematic structure of a capacitor element 80 according to an embodiment of the present disclosure. Figure 8B This is a horizontal cross-sectional view illustrating a schematic structure of a capacitor element 80 according to an embodiment of the present disclosure. In some embodiments, the capacitor element 80 may be... Figure 3 Any one of the capacitor elements 31 in Figure 6 or any one of the capacitor elements 61A, 61B, 61'A and 61'B in Figure 6.

[0044] Capacitor element 80 may include electrode layers 81 and 82 and an insulating layer 83 located between electrode layers 81 and 82. Electrode layer 81 may have a cylindrical shape with a hollow body, such as an inverted cup. Electrode layer 81 may have a top portion and a side portion located on the top and side portions of the insulating layer 83, respectively. In some embodiments, the top portion of electrode layer 81 may be coupled to... Figure 3 The intermediate layer 35 or the intermediate layers 65A, 65B and 65' of Figure 6 are located in the manner of... Figure 3The insulating layer 83 is located on the intermediate layer 35 or the intermediate layers 65A, 65B, and 65' of FIG. 6. The insulating layer 83 may have a cylindrical shape with a hollow body, such as an inverted cup. The insulating layer 83 may have a top portion and a side portion located between the electrode layers 81 and 82. The insulating layer 83 may insulate the electrode layers 81 and 82. The electrode layer 82 may have a columnar shape. The electrode layer 82 may have a top surface and a side surface on which the top portion and the side portion of the insulating layer 83 are respectively disposed. The electrode layer 82 may have a bottom surface not covered by the insulating layer 83. In some embodiments, the bottom surface of the electrode layer 82 may be coupled to the electrode layer 82. Figure 3 The conductive layer 34 (e.g., conductive layer 0) or the conductive layers 64A, 64B, 64'A, and 64'B (e.g., conductive layer 0) of FIG. 6 are located in such a manner that... Figure 3 On the conductive layer 34 (e.g., conductive layer 0) or the conductive layers 64A, 64B, 64'A and 64'B (e.g., conductive layer 0) of FIG. 6.

[0045] In some embodiments, electrode layers 81 and 82 may comprise, for example, titanium nitride (TiN). In some embodiments, insulating layer 83 may comprise a high-k material having a high relative capacitance. For example, the high-k material may comprise an oxide containing, for example, any one of yttrium (Y), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), and aluminum (Al). Insulating layer 83 may further comprise other elements, such as silicon and nitrogen.

[0046] Figure 9A This is a vertical cross-sectional view showing a schematic structure of a capacitor element 90 according to an embodiment of the present disclosure. Figure 9B This is a horizontal cross-sectional view illustrating a schematic structure of a capacitor element 90 according to an embodiment of the present disclosure. In some embodiments, the capacitor element 90 may be... Figure 3 Any one of the capacitor elements 31 in Figure 6 or any one of the capacitor elements 61A, 61B, 61'A and 61'B in Figure 6.

[0047] Capacitor element 90 may include electrode layers 91 and 92 and an insulating layer 93 located between electrode layers 91 and 92. Electrode layer 91 may have a cylindrical shape with a hollow body, such as an inverted cup. Electrode layer 91 may have a top portion and a side portion located on the top and side portions of the insulating layer 93, respectively. In some embodiments, the top portion of electrode layer 91 may be coupled to... Figure 3 The intermediate layer 35 or the intermediate layers 65A, 65B and 65' of Figure 6 are located in the manner of... Figure 3The insulating layer 93 is located on the intermediate layer 35 or the intermediate layers 65A, 65B, and 65' of FIG. 6. The insulating layer 93 may have a cylindrical shape with a hollow body, such as an inverted cup. The insulating layer 93 may have a top portion disposed thereon on the top portion of the electrode layer 91 and a side portion located between the electrode layers 91 and 92. The electrode layer 92 may have a cylindrical shape with a hollow body, such as an upright cup. The electrode layer 92 may have a side portion located on the side portion of the insulating layer 93. The electrode layer 92 may have a bottom portion not covered by the insulating layer 93. In some embodiments, the bottom portion of the electrode layer 92 may be coupled to the electrode layer 92. Figure 3 The conductive layer 34 (e.g., conductive layer 0) or the conductive layers 64A, 64B, 64'A, and 64'B (e.g., conductive layer 0) of FIG. 6 are located in such a manner that... Figure 3 The capacitor element 90 may further include a liner 94. The liner 94 may have a columnar shape. The liner 94 may cover the inner surface of the electrode layer 92. The top portion of the liner 94 may be covered by the top portion of the insulating layer 93.

[0048] In some embodiments, electrode layers 91 and 92 may comprise, for example, titanium nitride (TiN). In some embodiments, insulating layer 93 may comprise a high-k material having a high relative capacitance. For example, the high-k material may comprise an oxide containing, for example, any one of yttrium (Y), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), and aluminum (Al). Insulating layer 93 may further comprise other elements, such as silicon and nitrogen. Liner 94 may comprise a conductive material, such as polycrystalline silicon.

[0049] Figure 10A This is a vertical cross-sectional view showing a schematic structure of a capacitor element 100 according to an embodiment of the present disclosure. Figure 10B This is a horizontal cross-sectional view illustrating a schematic structure of a capacitor element 100 according to an embodiment of the present disclosure. In some embodiments, the capacitor element 100 may be... Figure 3 Any one of the capacitor elements 31 in Figure 6 or any one of the capacitor elements 61A, 61B, 61'A and 61'B in Figure 6.

[0050] Capacitor element 100 may include electrode layers 101 and 102 and an insulating layer 103 located between electrode layers 101 and 102. Electrode layer 102 may have a cylindrical shape with a hollow body, such as an upright cup. Electrode layer 102 may have a side portion and a bottom portion. The side portion of electrode layer 102 may have an inner surface and an outer surface covered by insulating layer 103. The bottom portion of electrode layer 102 may have an inner surface covered by insulating layer 103 on top and an outer surface not covered by insulating layer 103. In some embodiments, the outer surface of electrode layer 102 may be coupled to... Figure 3 The conductive layer 34 (e.g., conductive layer 0) or the conductive layers 64A, 64B, 64'A, and 64'B (e.g., conductive layer 0) of FIG. 6 are located in such a manner that... Figure 3 The conductive layer 34 (e.g., conductive layer 0) or the conductive layers 64A, 64B, 64'A, and 64'B (e.g., conductive layer 0) of FIG. 6. As previously mentioned, the insulating layer 103 may cover the inner and outer surfaces of the electrode layer 102. The electrode layer 101 may cover the insulating layer 103. For example, the electrode layer 101 may fill the hollow body of the electrode layer 102 above the insulating layer 103. Thus, the electrode layer 101 may cover the inner and outer surfaces of the electrode layer 102 through the insulating layer 103, and the insulating layer 103 may insulate the electrode layer 101 from the electrode layer 102. The electrode layer 101 may be coupled to Figure 3 The intermediate layer 35 or the intermediate layers 65A, 65B and 65' of Figure 6 are located in a manner that allows them to be situated in a position ... Figure 3 The top surface on the intermediate layer 35 or the intermediate layers 65A, 65B and 65' of Figure 6.

[0051] In some embodiments, electrode layers 101 and 102 may comprise, for example, titanium nitride (TiN). In some embodiments, insulating layer 103 may comprise a high-k material having a high relative capacitance. For example, the high-k material may comprise an oxide containing, for example, any one of yttrium (Y), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), and aluminum (Al). Insulating layer 103 may further comprise other elements, such as silicon and nitrogen.

[0052] Although various embodiments of this disclosure have been disclosed, those skilled in the art will understand that the embodiments extend beyond the particular disclosed embodiments to other alternative embodiments and / or uses of the embodiments, as well as their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form variations of the disclosed embodiments. Therefore, it is intended that the scope of at least some of this disclosure should not be limited to the particular disclosed embodiments described above.

Claims

1. A semiconductor device comprising: A first conductive layer includes an electrical portion and an intermediate portion, the electrical portion being configured to provide a power supply voltage; Second conductive layer; A third conductive layer is located between the first conductive layer and the second conductive layer; A contact located between the first conductive layer and the third conductive layer, the contact comprising one end coupled to the middle portion of the first conductive layer and the other end coupled to the third conductive layer; as well as One or more capacitor elements, wherein each of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer. The power component is included in the first power node, and the power supply voltage is the first power supply voltage. The intermediate portion is contained in an intermediate node, which provides an intermediate voltage to the intermediate portion. The intermediate voltage is the average of the first power supply voltage of the first power supply node and the second power supply voltage of the second power supply node, which is different from the first power supply node.

2. The device according to claim 1, wherein the third conductive layer comprises polycrystalline silicon.

3. The device according to claim 1, wherein at least one of the one or more capacitor elements comprises: A first electrode layer, which includes a top portion coupled to the third conductive layer; The second electrode layer includes a bottom portion coupled to the second conductive layer; as well as An insulating layer is located between the first electrode layer and the second electrode layer and is configured to insulate the first electrode layer from the second electrode layer.

4. The device of claim 3, wherein the first electrode layer comprises a cylindrical shape having a hollow body and further comprises the top portion and the side portion. The insulating layer includes a top portion and a side portion located on the top portion and the side portion of the first electrode layer, respectively.

5. The device of claim 4, wherein the second electrode layer comprises a column shape, the column shape comprising a top surface and a side surface respectively located on the top portion and the side portion of the insulating layer, and further comprising a bottom surface located on the second conductive layer.

6. A semiconductor device comprising: A first conductive layer includes a first electrical portion, a second electrical portion, a first intermediate portion, and a second intermediate portion; An intermediate line located in the first conductive layer, wherein the intermediate line is configured to couple the first intermediate portion to the second intermediate portion; The second conductive layer comprises a first portion and a second portion; A third conductive layer is located between the first conductive layer and the second conductive layer, and the third conductive layer includes a first portion and a second portion respectively coupled to the first intermediate portion and the second intermediate portion of the first conductive layer. The first capacitor includes: One or more first capacitor elements, each comprising one end and another end, the one end being coupled to a first portion of the third conductive layer and the other end being coupled to a first portion of the second conductive layer; A first electrical contact, comprising one end coupled to the first portion of the second conductive layer and the other end coupled to the first electrical portion of the first conductive layer; and A first contact, comprising one end coupled to the first portion of the third conductive layer and the other end coupled to the first intermediate portion of the first conductive layer; and The second capacitor includes: One or more second capacitor elements, each comprising one end and another end, the one end being coupled to the second portion of the third conductive layer and the other end being coupled to the second portion of the second conductive layer; A second electrical contact, comprising one end coupled to a second portion of the second conductive layer and the other end coupled to a second electrical portion of the first conductive layer; and The second contact includes one end coupled to the second portion of the third conductive layer and the other end coupled to the second intermediate portion of the first conductive layer. The first power component is configured to provide a first power supply voltage, and the second power component is configured to provide a second power supply voltage different from the first power supply voltage. The intermediate line is contained in an intermediate node, which provides an intermediate voltage to the intermediate line, and the intermediate voltage is the average of the first power supply voltage and the second power supply voltage.

7. The device of claim 6, wherein the first capacitor and the second capacitor comprise constant capacitance.

8. The device according to claim 6, wherein the first capacitor and the second capacitor are disposed separately from each other.

9. The device of claim 6, wherein the first portion of the second conductive layer comprises one side and the other side, and Each of the one or more first capacitor elements further includes a plurality of first power contacts, the plurality of first power contacts including a first power contact coupled to a first portion of the second conductive layer on one side and another first power contact coupled to a first portion of the second conductive layer on the other side.

10. The device of claim 6, wherein the third conductive layer further comprises a third portion, and The device further includes a pair of capacitors, the pair of capacitors comprising: The third capacitor comprises: One or more third capacitor elements, each comprising one end coupled to the third portion of the third conductive layer and the other end coupled to the first electrical portion; and The fourth capacitor comprises: One or more fourth capacitor elements, comprising one end coupled to the third portion of the third conductive layer and the other end coupled to the second electrical portion.

11. A semiconductor device comprising: A first capacitor, which is coupled to a first electric field line; A second capacitor, which is coupled to a second electric field line; A middle line configured to couple the first capacitor to the second capacitor, wherein the first power line, the second power line, and the middle line are contained in a first layer; The intermediate line is contained in an intermediate node, which provides an intermediate voltage to the intermediate line, and the intermediate voltage is the average of the voltages of the first electric field line and the second electric field line.

12. The device of claim 11, wherein the device further comprises: A first contact is configured to couple a node of the first capacitor in the second layer to the first electric field line in the first layer. as well as The second contact is configured to couple another node of the first capacitor in the intermediate layer between the first layer and the second layer to the intermediate line in the first layer.

13. The device of claim 12, wherein the first capacitor is disposed in the first region and the second capacitor is disposed in a second region away from the first region.

14. The device according to claim 13, further comprising: The third and fourth capacitors are located in the third region. The third and fourth capacitors are coupled to the intermediate layer, which is contained within the intermediate node. The first region is smaller than the third region.

15. The device of claim 11, wherein at least one of the first capacitor or the second capacitor is a compensation capacitor configured to stabilize the power supply voltage from at least one of the first power line or the second power line.

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