Power supply and its operation method

Abstract

The present technology relates to a power supply and an operating method thereof. The power supply includes a main power supply configured to receive external power and output a charging voltage and main power; and an auxiliary power supply including a capacitor array configured to charge the auxiliary power using the charging voltage and output the auxiliary power. The auxiliary power supply is configured to periodically repeat a discharge operation and an additional charge operation on the capacitor array when charging the capacitor array begins.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0030310, filed on March 8, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a power supply and an operating method thereof, and more particularly, to a power supply including an auxiliary power supply and an operating method thereof. Background Art

[0004] The memory system may include a memory device that stores data therein, a controller that controls the memory device, and a power supply (power supply device) that supplies power to the controller and the memory device.

[0005] The power supply may include a main power supply configured to receive external power and supply internal power to the controller and the memory device, and an auxiliary power supply configured to supply auxiliary power when the main power supply cannot output the internal power. For example, when the supply of external power is temporarily stopped, the auxiliary power supply may temporarily supply auxiliary power to the controller and the memory device.

[0006] Since the auxiliary power source is required to supply the auxiliary power when the supply of the external power is stopped, the auxiliary power source may include a plurality of capacitors configured to be charged with the external power when the external power is supplied.

[0007] A capacitor can be formed with a structure including a dielectric between two electrodes. Depending on the type of dielectric, capacitors can be classified into air capacitors, vacuum capacitors, gas capacitors, liquid capacitors, mica capacitors, ceramic capacitors, paper capacitors, plastic film capacitors, electrolyte capacitors, etc. Summary of the Invention

[0008] Embodiments of the present disclosure provide a power supply capable of increasing the charging speed of a capacitor array in an auxiliary power supply and an operating method thereof.

[0009] According to an embodiment of the present disclosure, a power supply includes: a main power supply configured to receive external power and output a charging voltage and main power; and an auxiliary power supply including a capacitor array configured to charge and output the auxiliary power. The auxiliary power supply is configured to periodically repeat a discharge operation and a sub-charge operation on the capacitor array when starting to charge the capacitor array.

[0010] According to an embodiment of the present disclosure, a power supply includes: a main power supply configured to receive external power and output a charging voltage and main power; and an auxiliary power supply including a capacitor array configured to charge and output the auxiliary power. The auxiliary power supply is configured to check a detection voltage charged in the capacitor array until the charge level of the capacitor array reaches a target level, and to periodically repeat a discharge operation and an additional charge operation on the capacitor array.

[0011] According to an embodiment of the present disclosure, a method for operating a power supply includes supplying a charging voltage to a plurality of capacitors via a charging line, and periodically monitoring the charging line when the charge levels of the plurality of capacitors increase to a target level. The monitoring operation includes reducing the voltage of the charging line and charging the charging line.

[0012] Since the present technology can quickly charge the auxiliary power source, data stored in the memory system can be protected by using the auxiliary power source when the external power supply is temporarily stopped. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0014] Figure 2 is a diagram illustrating a power supply according to an embodiment of the present disclosure.

[0015] Figure 3 It shows Figure 2 A diagram of a capacitor array is shown.

[0016] Figure 4 The present invention is shown in the embodiment of the present invention. Figure 2 A diagram of the charge controller is shown.

[0017] Figure 5 The present invention is shown in the embodiment of the present invention. Figure 4 The diagram of the discharge circuit is shown.

[0018] Figure 6 The present invention is shown in FIG. Figure 2 Schematic diagram of the computing device shown.

[0019] Figure 7 is a flowchart illustrating a method of operating an auxiliary power supply according to an embodiment of the present disclosure.

[0020] Figure 8 is a diagram illustrating a monitoring operation and a main charge check operation according to time according to an embodiment of the present disclosure.

[0021] Figure 9is a diagram illustrating a principle of temperature increase of a capacitor array according to an embodiment of the present disclosure.

[0022] Figure 10A and Figure 10B is a graph illustrating changes in auxiliary power with temperature during a monitoring operation according to an embodiment of the present disclosure.

[0023] Figure 11 is a diagram illustrating a charging speed of auxiliary power according to an embodiment of the present disclosure.

[0024] Figure 12 is a diagram illustrating a memory card system to which a power supply according to an embodiment of the present disclosure is applied.

[0025] Figure 13 is a diagram illustrating a solid-state drive (SSD) system to which a power supply according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0026] The specific structural or functional descriptions of the embodiments of the concepts disclosed in this specification or this application are only shown to describe the embodiments of the concepts of the present disclosure. The embodiments of the concepts of the present disclosure can be implemented in various forms and should not be interpreted as limited to the embodiments described in this specification.

[0027] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , the memory system 1000 may include a memory device 1100 , a memory controller 1200 , and a power supply 2000 .

[0029] The memory device 1100 may be configured to store data. For example, the memory device 1100 may be configured as a nonvolatile memory device or a volatile memory device.

[0030] The memory controller 1200 may be configured to communicate between the host and the memory device 1100. For example, when receiving a request output from the host, the memory controller 1200 may be configured to control the memory device 1100 according to the received request.

[0031] The power supply 2000 may be configured to receive external power PWR_E from an external device and supply main power PWR_M or auxiliary power PWR_A to the memory controller 1200 and the memory device 1100. The external device supplying the external power PWR_E may be a host transmitting a request to the memory controller 1200 or a power supply that only supplies the external power PWR_E regardless of the host.

[0032] When receiving external power PWR_E, the power supply 2000 can output the main power PWR_M. When the supply of external power PWR_E stops abnormally, because the main power PWR_M cannot be output, the power supply 2000 can output the auxiliary power PWR_A. The main power PWR_M can be a voltage for causing the memory controller 1200 and the memory device 1100 to perform conventional operations (e.g., programming operations, read operations, or erase operations). The auxiliary power PWR_A can be a voltage temporarily supplied to the memory controller 1200 and the memory device 1100 so that the memory controller 1200 and the memory device 1100 can stably store data when the supply of the main power PWR_M is temporarily stopped. For example, the power supply 2000 can charge the auxiliary power PWR_A when receiving the external power PWR_E and output the main power PWR_M, and can output the auxiliary power PWR_A instead of the main power PWR_M when the supply of the external power PWR_E stops abnormally. Since the auxiliary power PWR_A is a voltage charged in the power supply 2000 , when the supply of the external power PWR_E is interrupted, the auxiliary power PWR_A may be temporarily used only for a safe storage operation of the memory controller 1200 and the memory device 1100 .

[0033] Figure 2 is a diagram illustrating a power supply according to an embodiment of the present disclosure.

[0034] Reference Figure 2 The power supply 2000 may include a main power supply 2100 , an auxiliary power supply 2200 and a switching circuit 2300 .

[0035] The main power supply 2100 may receive external power PWR_E, convert the external power PWR_E into main power PWR_M, and output the main power PWR_M. For example, the main power supply 2100 may be configured according to Figure 1 The memory system 1000 converts the voltage level of the external power PWR_E and outputs the converted voltage as the main power PWR_M.

[0036] The auxiliary power supply 2200 may be configured to charge the voltage of the auxiliary power supply 2200 using the charging voltage Vcg when the charging voltage Vcg is supplied from the main power supply 2100. The auxiliary power supply 2200 may output the charged voltage as the auxiliary power PWR_A. The auxiliary power supply 2200 may be configured to output a charging completion signal CS when the charged voltage of the auxiliary power supply 2200 is charged to a target voltage level.

[0037] The switching circuit 2300 can be configured to monitor the level of the main power PWR_M output from the main power source 2100 and output the auxiliary power PWR_A instead of the main power PWR_M when the output of the main power PWR_M stops or the level drops rapidly. For example, the switching circuit 2300 can output the auxiliary power PWR_A instead of the main power PWR_M after receiving the charge completion signal CS. Since the auxiliary power PWR_A is not fully charged to the target voltage until the charge completion signal CS is received, the switching circuit 2300 does not output the auxiliary power PWR_A even if the supply of the main power PWR_M stops when the charge completion signal CS is inactive.

[0038] The auxiliary power supply 2200 is described in more detail as follows.

[0039] The auxiliary power supply 2200 may include a capacitor array 210 , a charging controller 220 , and an operating device 230 (ie, a processor).

[0040] The capacitor array 210 may be configured to charge a voltage of the capacitor array 210 using a charging voltage Vcg supplied through a charging line CHL. The capacitor array 210 may output the charged voltage as auxiliary power PWR_A.

[0041] When the charging voltage Vcg is supplied from the main power supply 2100, the charging controller 220 can transmit the charging voltage Vcg to the capacitor array 210 via the charging line CHL. The charging controller 220 can detect the voltage charged in the capacitor array 210 (i.e., the detection voltage Vcgd) via the charging line CHL. During the charging operation, the charging controller 220 can transmit the detection voltage Vcgd to the computing device 230 via the first transmission line TRL1 or the second transmission line TRL2. The charging line CHL is coupled to the capacitor array 210, so the detection voltage Vcgd can indicate the amount of charge charged in the capacitor array 210. The charging operation of charging the capacitor array 210 using the charging voltage Vcg and the detection operation of detecting the detection voltage Vcgd can be performed alternately and repeatedly.

[0042] For example, when charging is performed in capacitor array 210, charge controller 220 may periodically check a detection voltage Vcgd of capacitor array 210 detected via charge line CHL and transmit the detection voltage Vcgd to computing device 230 via first transmission line TL1. Furthermore, when the charging rate (i.e., charging level) of capacitor array 210 increases to a target rate (i.e., target level) during the charging operation, charge controller 220 may transmit the detection voltage Vcgd detected from charge line CHL to computing device 230 via second transmission line TRL2. That is, when charging of capacitor array 210 begins, charge controller 220 may independently perform a monitoring operation for increasing the charging speed of capacitor array 210 and a main charge check operation for checking whether charging of capacitor array 210 is complete. Because the monitoring operation and the main charge check operation are performed independently of each other, charge controller 220 may include a counter for the monitoring operation and a counter for the main charge check operation, respectively.

[0043] The operation device 230 may convert the detection voltage Vcgd received through the first transmission line TRL1 or the second transmission line TRL2 into a digital value, compare the digital value with a reference value, and output the comparison result to the charge controller 220 through the first transmission line TRL1 or the second transmission line TRL2.

[0044] For example, during a monitoring operation, the operation device 230 may compare the digital value of the detection voltage Vcgd received via the first transmission line TRL1 with a reference value and output the comparison result to the charging controller 220. When the digital value of the detection voltage Vcgd received via the first transmission line TRL1 is greater than or equal to the reference value, the operation device 230 may output a monitoring completion signal having a logic high value. When the digital value is less than the reference value, the operation device 230 may output a monitoring completion signal having a logic low value. In other words, the operation device 230 may not activate the monitoring completion signal when charging of the capacitor array 210 is not complete, and activate the monitoring completion signal when charging of the capacitor array 210 is complete.

[0045] During the main charge check operation, the operation device 230 may compare the digital value of the detection voltage Vcgd received via the second transmission line TRL2 with a reference value and output the comparison result to the charge controller 220. The reference value used in the monitoring operation and the main charge check operation may be set to be identical. When the digital value of the detection voltage Vcgd received via the second transmission line TRL2 is greater than or equal to the reference value, the operation device 230 may output a check completion signal having a logic high value. When the digital value is less than the reference value, the operation device 230 may output a check completion signal having a logic low value. In other words, the operation device 230 may not activate the check completion signal when charging of the capacitor array 210 is not complete, and may activate the check completion signal when charging of the capacitor array 210 is complete.

[0046] During the monitoring operation, the charging controller 220 may receive the monitoring completion signal MTC (see FIG. Figure 4 ) checks the detection voltage Vcgd of the charging line CHL every predetermined period, and ends the monitoring operation when receiving the monitoring completion signal MTC having a logic high value. During the monitoring operation, when there is no detection voltage Vcgd of the charging line CHL for the second set time amount 2Tset (see Figure 7 ), when the charging controller 220 receives the monitoring completion signal MTC having a logic high value within 1: 100 ms, the charging controller 220 may process the monitoring operation as a failure.

[0047] During the main charge check operation, when the third set time amount 3Tset (see Figure 7 ) receives a check completion signal PGS with a logic high value (see Figure 4 ), the charge controller 220 may output the charge completion signal CS having a logic high value. During the main charge check operation, when the check completion signal PGS having a logic high value is not received within the third set time amount 3Tset, the charge controller 220 may output the charge completion signal CS having a logic low value and process the main charge check operation as a failure.

[0048] Figure 3 The present invention is shown in the embodiment of the present invention. Figure 2 A diagram of capacitor array 210 is shown.

[0049] Reference Figure 3 , the capacitor array 210 may include a first capacitor group 41 and a second capacitor group 42 that can be charged with a charging voltage Vcg supplied through the charging line CHL. Figure 3 A first capacitor group 41 and a second capacitor group 42 are shown in FIG. 4 , but the number of capacitor groups is not limited to the number disclosed in the drawing.

[0050] The first capacitor group 41 and the second capacitor group 42 can be configured identically and connected in parallel between the charging line CHL and the ground terminal GND. For example, the first capacitor group 41 can include multiple capacitors CP connected in parallel between a first line L1 and a second line L2. The first line L1 can be connected to the charging line CHL, while the second line L2 can be connected to the ground terminal GND. The multiple capacitors CP can include two electrodes and a dielectric interposed between the electrodes. For example, depending on the type of dielectric, the multiple capacitors can be composed of air capacitors, vacuum capacitors, gas capacitors, liquid capacitors, mica capacitors, ceramic capacitors, paper capacitors, plastic film capacitors, or electrolytic capacitors. Among these, electrolytic capacitors can include polymer-tantalum capacitors. Polymer-tantalum capacitors refer to capacitors whose dielectric is formed of tantalum and are primarily used for charging high-capacity voltages. The charging speed of the multiple capacitors can be affected by temperature. For example, the charging speed can increase as the temperature increases. The second capacitor group 42 can include multiple capacitors CP connected in parallel between a third line L3 and a fourth line L4. The third line L3 can be connected to the charging line CHL via the first line L1, while the fourth line L4 can be connected to the ground terminal GND. The plurality of capacitors CP included in the second capacitor group 42 may be formed in the same structure as the plurality of capacitors CP included in the first capacitor group 41 .

[0051] Figure 4 The present invention is shown in the embodiment of the present invention. Figure 2 A diagram of the charge controller 220 is shown.

[0052] Reference Figure 4 , the charging controller 220 may include a power transmission circuit 510 , a monitoring circuit 520 , and a pass detector 530 .

[0053] The power transfer circuit 510 may be configured to receive power from Figure 2 The main power source 2100 outputs a charging voltage Vcg and transmits the charging voltage Vcg to a charging line CHL coupled to the capacitor array 210.

[0054] The monitoring circuit 520 may be configured to monitor a voltage level on the charging line CHL. The monitoring circuit 520 may include a first counter 520_1 and a discharge circuit 520_2.

[0055] The first counter 520_1 may be configured to count the amount of time during the monitoring operation to output the discharge signal DIS every predetermined period when receiving the count end signal FIN having a logic low level, and may not output the discharge signal DIS when receiving the count end signal FIN having a logic high level. For example, the first counter 520_1 may start the counting operation when the charging voltage Vcg of a positive voltage is applied to the charging line CHL, and output the discharge signal DIS every predetermined period after the counting operation is started. The first counter 520_1 may be configured to output the discharge signal DIS from the start of the counting operation, or may be configured to output the discharge signal DIS after a first set amount of time 1Tset (see FIG. 1 ) has passed since the start time of the counting operation. Figure 7 ) and then outputs a discharge signal DIS.

[0056] The discharge circuit 520_2 can discharge the charging line CHL (i.e., the capacitor array 210) in response to receiving a discharge signal DIS at predetermined intervals, detect a detection voltage Vcgd, and transmit the detection voltage Vcgd received from the charging line TRL1 to the first transmission line TRL1 after a predetermined amount of time has passed since the discharge of the charging line CHL. In an embodiment, the discharge circuit 520_2 can alternately discharge and charge the charging line CHL (i.e., the capacitor array 210) in response to the discharge signal DIS. The discharge operation can be performed much more quickly than the charge operation. For example, the discharge operation can be performed for 70 milliseconds, while the charge operation can be performed for 1 second. In an embodiment, the discharge circuit 520_2 can include at least one resistor. The discharge circuit 520_2 can use the at least one resistor to discharge the voltage of the capacitor array 210. Because the charge voltage Vcg is continuously supplied to the charging line CHL, even if the discharge circuit 520_2 discharges the charging line CHL, the voltage of the charging line CHL may not decrease rapidly, but may temporarily decrease and then increase again. The discharge circuit 520_2 can transmit the detection voltage Vcgd detected at the following time point to the first transmission line TRL1. Figure 2 The computing device 230 of FIG. At this point in time, the voltage of the charging line CHL begins to increase after temporarily decreasing. Furthermore, when the discharge circuit 520_2 receives the monitoring completion signal MTC having a logic low value from the computing device 230, the discharge circuit 520_2 may output the count end signal FIN having a logic low value. When the discharge circuit 520_2 receives the monitoring completion signal MTC having a logic high value, the discharge circuit 520_2 may output the count end signal FIN having a logic high value.

[0057] When the first counter 520_1 receives a count end signal FIN having a logic low value from the discharge circuit 520_2, the first counter 520_1 may output the discharge signal DIS every predetermined period. When the first counter 520_1 receives a count end signal FIN having a logic high value, the first counter 520_1 may not output the discharge signal DIS. Furthermore, if the count end signal FIN having a logic high value is not received until the maximum charging time after the monitoring operation begins, the first counter 520_1 may output a fail signal FA. The fail signal FA may be a signal indicating a failure in the charging operation and may be transmitted to the pass detector 530.

[0058] The pass detector 530 can be configured to check the detection voltage Vcgd of the charging line CHL when the charging voltage Vcg is supplied to the charging line CHL. The pass detector 530 can perform a check operation to determine whether charging is proceeding normally when the detection voltage Vcgd increases to a target voltage (i.e., a sub-target level). In an embodiment, the check operation can be an operation of discharging the voltage of the capacitor array 210 and checking the charged voltage of the capacitor array 210. In an embodiment, the check operation can be an operation of discharging the voltage of the capacitor array 210 using the time required to reduce the voltage by a preset level (e.g., -5%) and checking the capacitance of the capacitor array 210. To perform the check operation, the pass detector 530 can include a charging detector 530_1 and a second counter 530_2.

[0059] The charging detector 530_1 may start checking the detection voltage Vcgd of the charging line CHL when the charging voltage Vcg starts to be applied to the charging line CHL. For example, the charging detector 530_1 may perform a checking operation for determining whether the detection voltage Vcgd detected by the charging line CHL increases to an additional target level. The additional target level may be set to be lower than the target level of the auxiliary power (i.e., the final target level). For example, the additional target level may be set to a voltage that is 5% to 15% lower than the final target level of the auxiliary power. The charging detector 530_1 may perform a checking operation for determining when the detection voltage Vcgd increases to the additional target level. The checking operation may be performed in the same manner as the discharge operation performed by the discharge circuit 520_2. The detection voltage Vcgd may be detected only for a predetermined amount of time (e.g., Figure 10A After performing the checking operation during the predetermined amount of time, the charge detector 530_1 may output the detection voltage Vcgd received from the charge line CHL through the second transmission line TRL2.

[0060] Next, when receiving the check completion signal PGS having a logic low value through the second transmission line TRL2, the charge detector 530_1 may determine Figure 2 The capacitor array 210 is not sufficiently charged, and the counting signal CNT is output to the second counter 530_2.

[0061] When receiving a detection signal DET having a logic high value from the second counter 530_2, the charge detector 530_1 may recheck the detection voltage Vcgd of the charge line CHL. When receiving a detection signal DET having a logic low value from the second counter 530_2, the charge detector 530_1 may determine that the charging operation is abnormal and treat the charging operation as a failure. For example, the charge detector 530_1 may output a charge completion signal CS having a logic low value in response to the detection signal DET having a logic low value. Furthermore, the charge detector 530_1 may output a charge completion signal CS having a logic low value even when receiving the failure signal FA.

[0062] The second counter 530_2 may be configured to compare the current amount of time with the third set amount of time 3Tset (see Figure 7 ) to output a detection signal DET. The current time refers to the time from the start of the charging operation to the present, and the third set time 3Tset refers to the maximum charging time. Therefore, the third set time 3Tset may be pre-stored in the second counter 530_2. The second counter 530_2 may output a detection signal DET having a logic high value when the current time is less than the third set time 3Tset, and may output a detection signal DET having a logic low value when the current time is greater than or equal to the third set time 3Tset.

[0063] Figure 5 The present invention is shown in the embodiment of the present invention. Figure 4 Schematic diagram of discharge circuit 520_2 shown.

[0064] Reference Figure 5 The discharge circuit 520_2 may include a discharge switch group 61 , a delay circuit 62 , a voltage switch 63 and a monitoring detector 64 .

[0065] The discharge switch group 61 may include a plurality of discharge switches 61_1 connected in parallel between the charge line CHL and the ground terminal GND. The plurality of discharge switches 61_1 may be implemented using NMOS transistors that are turned on or off in response to a discharge signal DIS. For example, the plurality of discharge switches 61_1 may be turned on in response to a discharge signal DIS having a logic high value. When the plurality of discharge switches 61_1 are turned on, the voltage of the charge line CHL may decrease due to current flowing between the charge line CHL and the ground terminal GND. After a preset amount of time has passed since the plurality of discharge switches 61_1 were turned on, the plurality of discharge switches 61_1 may be turned off again when a discharge signal DIS having a logic low value is input.

[0066] The delay circuit 62 may be configured to output an inverted discharge signal DISb obtained by inverting the discharge signal DIS after a predetermined time delay when the discharge signal DIS is input. Although not shown in the drawing, the delay circuit 62 may include an odd number of inverters.

[0067] The voltage switch 63 can transmit the detection voltage Vcgd of the charge line CHL to the first transmission line TRL1 in response to the inverted discharge signal DISb. For example, during a discharge operation, when the discharge signal DIS has a logic high level and the inverted discharge signal DISb having a logic low value is input to the voltage switch 63, the voltage switch 63 can block the charge line CHL and the first transmission line TRL1 from each other. Therefore, during the discharge operation, the charge line CHL can be discharged. After the discharge operation is completed, when the discharge signal DIS has a logic low level and the inverted discharge signal DISb having a logic high value is input to the voltage switch 63, the voltage switch 63 can connect the charge line CHL and the first transmission line TRL1 to each other. Therefore, after the discharge operation is completed, the charge line CHL can be charged again with the charge voltage Vcg, and the detection voltage Vcgd can be provided through the first transmission line TRL1. A predetermined amount of time after connecting the charge line CHL and the first transmission line TRL1, the voltage switch 63 can again block the charge line CHL and the first transmission line TRL1. When the voltage switch 63 outputs the detection voltage Vcgd to the first transmission line TRL1 , the monitoring detector 64 sharing the first transmission line TRL1 does not receive the detection voltage Vcgd.

[0068] The monitoring detector 64 may be configured to output a count end signal FIN according to the logic value of the monitoring completion signal MTC when the monitoring completion signal MTC is input through the first transmission line TRL1. For example, when the monitoring completion signal MTC having a logic low value is input, the monitoring detector 64 may output a count end signal FIN having a logic low value, and when the monitoring completion signal MTC having a logic high value is input, the monitoring detector 64 may output a count end signal FIN having a logic high value. That is, when the detection voltage Vcgd is greater than the reference value, the monitoring completion signal MTC has a logic high value, which means that Figure 2 Therefore, the monitoring detector 64 can output the count end signal FIN having a logic high value to make the capacitor array 210 charged. Figure 4 The first counter 520_1 may end the counting operation.

[0069] Figure 6 The present invention is shown in the embodiment of the present invention. Figure 2 A diagram of the computing device 230 is shown.

[0070] Reference Figure 6 , the operation device 230 may include a first voltage operator 710 and a second voltage operator 720 .

[0071] The first voltage operator 710 can be configured to generate a digital value according to the level of the detection voltage Vcgd when the detection voltage Vcgd is input through the first transmission line TRL1, and perform an operation of comparing the digital value with a reference value. The reference value can be preset in the first voltage operator 710 and can be a value corresponding to the additional target level of the detection voltage Vcgd. The additional target level can be set according to the final target level of the auxiliary power. For example, the reference value can be set to a value corresponding to the final target level of the auxiliary power, or can be set to a value corresponding to a level that is 5% to 15% lower than the final target level. The first voltage operator 710 can output a monitoring completion signal MTC with a logic high value when the digital value of the detection voltage Vcgd is greater than or equal to the reference value, and output a monitoring completion signal MTC with a logic low value when the digital value is less than the reference value. That is, the first voltage operator can Figure 2 The monitoring completion signal MTC is not activated when the capacitor array 210 is not fully charged, and is activated when the capacitor array 210 is fully charged.

[0072] When the detection voltage Vcgd is input through the second transmission line TRL2, the second voltage operator 720 may compare the digital value of the detection voltage Vcgd with the reference value and output the result value to the charge controller 220 according to the comparison result. The reference value may be preset in the second voltage operator 720 and may be the same as the reference value stored in the first voltage operator 710. The second voltage operator 720 may output a check completion signal PGS having a logic high value when the digital value of the detection voltage Vcgd received through the second transmission line TRL2 is greater than or equal to the reference value, and output a check completion signal PGS having a logic low value when the digital value is less than the reference value. That is, the second voltage operator may Figure 2 The inspection completion signal PGS is not activated when the capacitor array 210 is not sufficiently charged, and is activated when the capacitor array 210 is sufficiently charged.

[0073] Figure 7 is a flowchart illustrating a method of operating an auxiliary power supply according to an embodiment of the present disclosure.

[0074] Reference Figure 4 and Figure 7 , when the charging voltage Vcg is supplied to the auxiliary power supply and charging starts, the auxiliary power supply may perform the monitoring operation S810 and the main charging check operation S820 independently of each other. The monitoring operation S810 is periodically performed at the start of the charging operation to increase Figure 2 The charging speed of the capacitor array 210 is determined, and the main charging check operation S820 is performed to check Figure 2 The capacitor array 210 is charged normally. When the charging voltage Vcg is applied to Figure 2 When the auxiliary power source 2200 is supplied, the charging operation may be started, and when the charging operation is started, the monitoring operation S810 and the main charging check operation S820 may be performed independently of each other. Each of the monitoring operation S810 and the main charging check operation S820 is described as follows.

[0075] When monitoring operation S810 begins, operation S11 may be performed to determine whether a first set time 1Tset has elapsed after the charging operation begins. For example, the first counter 520_1 may count the time from when voltage begins to be applied to the charging line CHL and compare the counted time with the first set time 1Tset. If the counted time differs from the first set time 1Tset (no) as a result of the comparison, the first counter 520_1 may continue counting time.

[0076] When the amount of time counted in operation S11 reaches the first set time amount 1Tset (yes), operation S12 of discharging the charging line CHL and detecting the detection voltage Vcgd can be performed by the discharge circuit 520_2. For example, in operation S12, a discharge operation can be performed to temporarily discharge the charging line CHL that supplies the charging voltage Vcg, and an additional charging operation can be performed in which the voltage level of the charging line CHL is increased again by the charging voltage Vcg after the discharge is completed. Subsequently, the detection voltage Vcgd of the charging line CHL in which the additional charging operation is performed can be detected. Alternatively, when operation S12 starts, the discharge operation can be performed after the additional charging operation in which the charging voltage Vcg is continuously applied to the charging line CHL. Since the discharge operation is completed within a predetermined time, when the discharge operation is completed, the detection voltage Vcgd of the charging line CHL can be increased again by the charging voltage Vcg.

[0077] Next, the first voltage operator 710 may perform operation S13 of comparing the level of the detection voltage Vcgd with the additional target level Vt. For example, if the level of the detection voltage Vcgd is lower than the additional target level Vt (No), operation S14 of comparing the current time Tc with the second set time 2Tset may be performed. The current time Tc refers to the amount of time since the charging operation, while the second set time 2Tset refers to the maximum charging time. In other words, if the current time Tc is equal to or greater than the second set time 2Tset, the charging operation will not proceed normally until the maximum charging time after the charging operation begins. For example, if a leak occurs in some of the devices charging the auxiliary power, the charging operation may not be completed within the maximum charging time. Therefore, in this case, the charging operation may be processed as a failure (S15). That is, in operation S14, if the current time Tc is greater than or equal to the second set time 2Tset (No), the charging operation may be processed as a failure (S15).

[0078] In operation S13 , when the level of the detection voltage Vcgd is higher than or equal to the target level (Yes), the charging operation may be ended.

[0079] In operation S14 , when the current amount of time Tc is less than the second set amount of time 2Test (Yes), operation S16 of counting the amount of time for monitoring the detection voltage Vcgd according to the predetermined period Tpr may be performed.

[0080] In operation S16, when the amount of time corresponding to the period Tpr has passed, operation S12 may be performed again. Operations S12 to S16 may be repeated until the level of the detection voltage Vcgd is higher than or equal to the additional target level Vt (Yes) in operation S13.

[0081] When the level of the detection voltage Vcgd is higher than or equal to the additional target level Vt in operation S13 (Yes), since the charging operation of the auxiliary power is completed, the charging operation may be ended.

[0082] The main charge checking operation S820 is described as follows.

[0083] When the main charging check operation S820 starts, the operation S21 of determining whether the check completion signal PGS has a logic high value 1 may be performed at the start of the charging operation. Figure 2 When the charging rate of the capacitor array 210 increases to the target rate, the charging detector 530_1 can transmit the detection voltage Vcgd detected from the charging line CHL to the operation device 230 through the second transmission line TRL2. For example, when the main charging check operation S820 starts, the charging detector 530_1 can perform the detection voltage Vcgd of the charging line CHL and Figure 2 The checking operation is a checking operation of temporarily lowering the voltage level of the charging line CHL when the charging rate of the capacitor array 210 increases to the target rate. The checking operation can be performed in the same way as the discharge operation performed by the discharge circuit 520_2. The checking operation can be performed for a predetermined amount of time (e.g., Figure 10A The inspection operation is performed during the predetermined time period (the time between time points T2 and T3), and when the predetermined time period has passed, the charge detector 530_1 may output the detection voltage Vcgd of the charge line CHL through the second transmission line TRL2. Then, it may be determined whether the inspection completion signal PGS having a logic high value 1 is received through the second transmission line TRL2.

[0084] In operation S21, when the check completion signal PGS has a logic low value of 0 (No), operation S22 may be performed to compare the current time amount Tc with the third set time amount 3Tset. The current time amount Tc refers to the time from the start of the charging operation to the present, and the third set time amount 3Tset refers to the maximum charging time. Therefore, the third set time amount 3Tset may be set to the same time as the second set time amount 2Tset.

[0085] When the current time amount Tc is less than the third set time amount 3Tset (Yes) in operation S22, operation S21 may be performed again. When the check completion signal PGS has a logic high value 1 (Yes) in operation S21, the charging operation may be ended.

[0086] In operation S22 , when the current amount of time Tc is greater than or equal to the third set amount of time 3Tset (No), the charging operation may be processed as a failure ( S23 ).

[0087] Figure 8 is a diagram illustrating a monitoring operation and a main charge check operation according to time according to an embodiment of the present disclosure.

[0088] Reference Figure 8 , when the charging operation starts ( T1 ), the monitoring operation S810 and the main charging check operation S820 may be independently performed.

[0089] In the monitoring operation S810, the monitoring operation may be performed every predetermined period Tpr. Figure 7 For detection Figure 4 In the main charging check operation S820, when the monitoring operation S810 is performed, the check operation S820 may be performed. Figure 4 The voltage of the charging line CHL is operated and can be quickly performed Figure 7 Operation S21 for determining an inspection completion signal.

[0090] For example, since the charging operation and the discharging operation are periodically repeated in the monitoring operation S810, Figure 2 The temperature of the capacitor array 210 can be gradually increased. As the temperature of the capacitor array 210 increases, the charging speed of the capacitor array 210 increases, thereby shortening the time required to complete the charging operation of the auxiliary power supply (81).

[0091] Figure 9 is a diagram illustrating a principle of temperature increase of a capacitor array according to an embodiment of the present disclosure.

[0092] Reference Figure 9 The capacitor array 210 includes a plurality of capacitors CP. When a voltage is applied to the charging line CHL (91) and when the charging line CHL (92) is discharged, the direction of current flow is different. Therefore, when the charging operation and the discharging operation are periodically performed, the direction of current flow in the plurality of capacitors CP periodically changes, and thus the temperature of the plurality of capacitors CP also periodically increases. Since the charging speed also increases with the increase in the temperature of the plurality of capacitors CP, the time required to increase the auxiliary power to the final target level can be shortened.

[0093] Figure 10A and Figure 10B is a graph illustrating a change in auxiliary power with temperature during a monitoring operation according to an embodiment of the present disclosure.

[0094] Reference Figure 10A , the voltage charged into the capacitor at room temperature without monitoring operation is referred to as room temperature auxiliary power PWR_As, and the voltage charged into the capacitor at a temperature lower than room temperature is referred to as the first low temperature auxiliary power PWR_Alow1. Figure 2 The voltage charged in the capacitor when the discharge operation T2 to T3 and the additional charging operation T3 to T4 according to the present embodiment are performed in a state where the capacitor array 210 is not leaked is referred to as the second low-temperature auxiliary power PWR_Alow2. Here, the additional charging operation T3 to T4 is for Figure 2 The term "full charging operation" is used to distinguish the complete charging operation performed on the capacitor array 210 and refers to the charging operation performed immediately after the discharge operation in the monitoring operation. Therefore, in the additional charging operation, the charging operation can be continuously performed without time division. Figure 2 The voltage charged in the capacitor when the discharge operations T2 to T3 and the additional charge operations T3 to T4 according to the present embodiment are performed in a state where a defect such as leakage exists in the capacitor array 210 is referred to as a third low-temperature auxiliary power PWR_Alow3 .

[0095] When the discharging operations T2 to T3 and the additional charging operations T3 to T4 according to the present embodiment are not performed, the first low-temperature auxiliary power PWR_Alow1 may increase slower than the room-temperature auxiliary power PWR_As.

[0096] When performing the discharge operation T2 to T3 and the additional charging operation T3 to T4 according to this embodiment, the second low-temperature auxiliary power PWR_Alow2 temporarily decreases during the discharge operation T2 to T3, and when performing the additional charging operation T3-T4, the second low-temperature auxiliary power PWR_Alow2 increases faster than the first low-temperature auxiliary power PWR_Alow1. At this time, the direction of the current changes due to the discharge operation T2 to T3 and the additional charging operation T3 to T4, and the charging operation can be performed quickly as the temperature rises.

[0097] When performing the discharge operations T2 to T3 and the additional charging operations T3 to T4 according to this embodiment, the third low-temperature auxiliary power PWR_Alow3 may increase more slowly from the start of the charging operation (T1) than the first low-temperature auxiliary power PWR_Alow1 due to defects such as leakage. In a defective capacitor array, even if the temperature rises, the level of the third low-temperature auxiliary power PWR_Alow3 may increase more slowly than the level of the first low-temperature auxiliary power PWR_Alow1 due to reasons such as leakage. In such an auxiliary power supply, since the third low-temperature auxiliary power PWR_Alow3 does not increase to the target voltage, or even if it does increase to the target voltage, it increases very slowly, the charging operation may be processed as a failure.

[0098] Reference Figure 10B , an additional charging operation may be performed before the discharging operation in the period T2-T4. Figure 10AIn the described embodiment, after the discharge operation is performed during the period T2 to T3, the additional charge operation is performed during the period T3 to T4, but Figure 10B In the embodiment, the discharge operation may be performed after the additional charge operation is performed. For example, the additional charge operation may be performed in the period T2 to T3. The discharge operation may be performed and then the additional charge operation may be performed in the period T3 to T4.

[0099] Figure 11 is a diagram illustrating a charging speed of auxiliary power according to an embodiment of the present disclosure.

[0100] Refer to Figure 10 and Figure 11 The first low-temperature auxiliary power PWR_Alow1 is not applied in this embodiment. Figure 7 The second low-temperature auxiliary power PWR_Alow2 is a voltage of the monitoring operation S12 of the present embodiment, and the second low-temperature auxiliary power PWR_Alow2 is a voltage of the monitoring operation S12 of the present embodiment. In the graph, the T axis indicates an increase in time, and the V axis indicates an increase in voltage.

[0101] When the charging operation begins (T1), the first low-temperature auxiliary power PWR_Alow1 can increase at a slower rate than the room-temperature auxiliary power PWR_As. However, when the monitoring operation S12 according to this embodiment is applied, the charging speed can be gradually increased each time the monitoring operation S21 is performed, as with the second low-temperature auxiliary power PWR_Alow2. Therefore, the second low-temperature auxiliary power PWR_Alow2 can reach the target rate PER faster than the room-temperature auxiliary power PWR_As, thereby quickly completing the charging operation.

[0102] Figure 12 is a diagram illustrating a memory card system 3000 to which a power supply according to an embodiment of the present disclosure is applied.

[0103] Reference Figure 12 , the memory card system 3000 includes a power supply 2000 , a controller 3100 , a memory device 3200 , and a connector 3300 .

[0104] Power Supply 2000 can be used with Figure 2 The illustrated power supply 2000 is identically configured and can supply main power or auxiliary power to the controller 3100 and the memory device 3200 .

[0105] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control a program operation, a read operation, or an erase operation of the memory device 3200 or to control background operations. The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0106] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device through at least one of the following various communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards or interfaces mentioned above.

[0107] For example, the memory device 3200 may be constructed from various nonvolatile memory elements such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0108] The controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure memory cards such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (e.g., MMC, RS-MMC, micro MMC, or eMMC), a Secure Digital (SD) card (e.g., SD, mini SD, micro SD, or SDHC), and a Universal Flash Storage (UFS).

[0109] Figure 13is a diagram illustrating a solid-state drive (SSD) system 4000 to which a power supply according to an embodiment of the present disclosure is applied.

[0110] Reference Figure 13 , an SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges a signal SIG with the host 4100 via a signal connector 4001 and receives power PWR via a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of flash memories 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0111] The controller 4210 may control the plurality of flash memories 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of the following communication standards or interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0112] Auxiliary power supply 4230 can be used with reference Figure 2 The auxiliary power supply 4230 may be implemented similarly to the auxiliary power supply 2200 described above. For example, the auxiliary power supply 4230 may be connected to the host 4100 via the power connector 4002 and may be charged by receiving power from the host 4100. When the power supply from the host 4100 is unstable, the auxiliary power supply 4230 may provide power to the SSD 4200. For example, the auxiliary power supply 4230 may be located within the SSD 4200 or may be located external to the SSD 4200. For example, the auxiliary power supply 4230 may be located on the motherboard and may provide auxiliary power to the SSD 4200.

[0113] The buffer memory 4240 operates as a buffer memory of the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from the plurality of flash memories 4221 to 422n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 4221 to 422n. The buffer memory 4240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0114] In the above-described embodiments, all operations may be selectively performed or skipped. In addition, the operations in each embodiment may not always be performed sequentially in a given order, and the operations in each embodiment may be performed randomly. In addition, the embodiments and drawings disclosed in this specification are intended to help those of ordinary skill in the art to understand the present disclosure more clearly, and are not intended to limit the scope of the present disclosure. In other words, those of ordinary skill in the art to which the present disclosure belongs will be able to easily understand that, based on the technical scope of the present disclosure and the appended claims, various modifications may be made. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A power supply comprising: a main power supply that receives external power and outputs a charging voltage and main power; as well as an auxiliary power supply including a capacitor array that charges auxiliary power using the charging voltage and outputs the auxiliary power, wherein the auxiliary power supply periodically repeats a discharge operation and an additional charging operation on the capacitor array when starting to charge the capacitor array, The auxiliary power supply further includes: a charging controller for controlling the discharging operation and the additional charging operation of the charging line; and an operation device for comparing the voltage detected on the charging line with a reference value and outputting a monitoring completion signal according to the comparison result, and The charge controller further periodically repeats the discharge operation and the additional charge operation when the monitoring completion signal has a logic low value, and stops the discharge operation when the monitoring completion signal has a logic high value.

2. The power supply according to claim 1, wherein The charge controller is connected to the capacitor array through a charging line and transmits the charging voltage to the capacitor array through the charging line.

3. The power supply according to claim 2, wherein the capacitor array comprises a plurality of capacitor banks connected in parallel between the charging line and a ground terminal, and Each of the capacitor banks includes a plurality of capacitors.

4. The power supply of claim 1 , wherein a plurality of capacitors in the capacitor array are comprised of polymer-tantalum capacitors.

5. The power supply of claim 2, wherein the charge controller comprises: a power transmission circuit for transmitting the charging voltage to the charging line; as well as A monitoring circuit performs the discharging operation on the charging line. 6 . The power supply of claim 5 , wherein the monitoring circuit further performs the additional charging operation before or after performing the discharging operation.

7. The power supply according to claim 2, The computing device further generates a digital value according to the voltage level on the charging line. wherein the operation means compares the voltage with the reference value by comparing the digital value with the reference value, and The operation device outputs a monitoring completion signal having a logic low value when the digital value is less than the reference value, and outputs a monitoring completion signal having a logic high value when the digital value is greater than or equal to the reference value.

8. The power supply according to claim 1 , further comprising a switching circuit that is activated after the auxiliary power charged in the auxiliary power supply increases to a target level and, after activation, outputs the auxiliary power instead of the main power when the supply of the external power is cut off.

9. A power supply comprising: a main power supply that receives external power and outputs a charging voltage and main power; as well as an auxiliary power supply including a capacitor array that charges auxiliary power using the charging voltage and outputs the auxiliary power, wherein the auxiliary power supply checks the detection voltage charged in the capacitor array until the charge level of the capacitor array reaches a target level, and periodically repeats the discharge operation and the additional charge operation on the capacitor array, The auxiliary power supply further includes: a charging controller that controls the discharging operation and the additional charging operation of the charging line; and an operation device that compares the detection voltage charged in the capacitor array with a reference value to output a monitoring completion signal, and compares the detection voltage charged in the capacitor array with the reference value to output an inspection completion signal, and The charge controller further periodically repeats the discharge operation and the additional charge operation when the monitoring completion signal has a logic low value, and stops the discharge operation when the monitoring completion signal has a logic high value.

10. The power supply according to claim 9, wherein The charge controller is connected to the capacitor array through a charge line and transmits the charge voltage to the capacitor array through the charge line, and outputs the detection voltage charged in the capacitor array when the charge level of the capacitor array reaches the target level.

11. The power supply of claim 10, wherein the charge controller comprises: a power transmission circuit for transmitting the charging voltage to the charging line; a monitoring circuit, configured to perform the discharging operation on the charging line; as well as The charge level of the detection voltage charged in the capacitor array is compared with the target level by the detector, and the detection voltage is transmitted to the operation device when the charge level reaches the target level.

12. The power supply of claim 11 , wherein the monitoring circuit comprises: a first counter that periodically outputs a discharge signal when charging of the capacitor array is started; as well as The discharge circuit discharges the charge line for a predetermined time period each time the discharge signal is output. 13 . The power supply according to claim 12 , wherein the first counter further stops outputting the discharge signal when the detection voltage charged in the capacitor array increases to the reference value.

14. The power supply of claim 11 , wherein the passage detector comprises: Charge detector: When charging of the capacitor array is started, the charge level of the detection voltage charged in the capacitor array is compared with the target level, outputting a count signal when the charge level is lower than the target level, and When the charge level increases to the target level, transmitting the detection voltage to the computing device; as well as Second counter: comparing a current amount of time with a set amount of time in response to the count signal, and A detection signal is output to the charge detector based on a result of comparison of the current amount of time with the set amount of time.

15. The power supply of claim 14, wherein the second counter: When the current amount of time is less than the set amount of time, outputting a detection signal having a logic high value, and When the current amount of time is greater than or equal to the set amount of time, a detection signal having a logic low value is output. 16 . The power supply according to claim 15 , wherein the charge detector further detects the detection voltage again when the detection signal has a logic high value.

17. A method of operating a power supply according to any one of claims 1 to 8, the method comprising: supplying auxiliary power to the plurality of capacitors via charging lines; as well as periodically performing a monitoring operation on the charging line when the charging levels of the plurality of capacitors increase to a target level, The monitoring operations include: reducing the voltage of the charging line; as well as The charging cable is charged. 18 . The method of claim 17 , wherein the reducing the voltage of the charging line comprises discharging the charging line that supplies the auxiliary power. 19 . The method of claim 18 , wherein charging the charging line again comprises supplying the auxiliary power to the plurality of capacitors through the charging line by stopping the discharging operation.

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