Voltage regulator without compensating capacitor

Abstract

The present invention provides a voltage regulator without a compensation capacitor, which includes a MOS transistor MNHV3, a current replication circuit, a first current source, a second current source, and a power supply path. The input end of the first current source is connected to the power supply end, and its output end is connected to the first node; the first connection end of the MOS transistor MNHV3 is connected to the first node, its control end is connected to the first node, and its second connection end is connected to the input end of the current replication circuit; the output end of the current replication circuit is connected to the second node; the input end of the second current source is connected to the second node, and its output end is grounded; the power supply path includes MOS transistors MNHV4 and MPHV5. The first connection end of the MOS transistor MNHV4 is connected to the power supply end, its control end is connected to the first connection node, and its second connection end is connected to the voltage output end of the power supply path; the first connection end of the MOS transistor MPHV5 is connected to the power supply end, its control end is connected to the second node, and its second connection end is connected to the voltage output end of the power supply path. Compared with the prior art, the present invention can save chip area and reduce costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supplies, and particularly relates to a voltage regulator without a compensation capacitor.

Background Art

[0002] Voltage regulators are widely used in chips to supply power to various circuits in the system. In some high-voltage circuit designs, it is often necessary to generate a low-voltage output powered by a high-voltage input voltage to supply power to the internal control circuit. For example, here the high voltage refers to higher than 5V, and the low voltage refers to lower than 5V. In another case, here the high voltage refers to higher than 3.3V, and the low voltage refers to lower than 3.3V. Generally, voltage regulators in the prior art need to be provided with compensation capacitors to ensure stability, which requires a large chip area. If this compensation capacitor is not required, the chip area can be saved and the cost can be reduced.

[0003] Therefore, it is necessary to provide a voltage regulator without a compensation capacitor.

Summary of the Invention

[0004] The purpose of the present invention is to provide a voltage regulator without a compensation capacitor, which can save the chip area and reduce the cost.

[0005] According to one aspect of the present invention, the present invention provides a voltage regulator without a compensation capacitor, which includes an MOS transistor MNHV3, a current replication circuit, a first current source I1, a second current source I2, and one or more power supply paths. The input end of the first current source I1 is connected to the power supply terminal VDD, and its output end is connected to the first connection node A; the first connection end of the MOS transistor MNHV3 is connected to the first connection node A, its control end is connected to the first connection node A, and its second connection end is connected to the input end of the current replication circuit; the output end of the current replication circuit is connected to the second connection point B, and the current replication circuit proportionally replicates the current input at the first connection end of the MOS transistor MNHV3 and outputs the replicated current at its output end; the input end of the second current source I2 is connected to the second connection node B, and its output end is grounded; the power supply path includes an MOS transistor MNHV4 and an MPHV5. The first connection end of the MOS transistor MNHV4 is connected to the power supply terminal VDD, its control end is connected to the first connection node A, and its second connection end is connected to the voltage output terminal VO of the power supply path; the first connection end of the MOS transistor MPHV5 is connected to the power supply terminal VDD, its control end is connected to the second connection node B, and its second connection end is connected to the voltage output terminal VO of the power supply path.

[0006] Further, the current replication circuit includes MOS transistors MPHV7, MPHV6, MN5, and MN1. The first connection end of the MOS transistor MN1 is connected to the second connection end of the MOS transistor MNHV3, its control end is connected to its first connection end, and its second connection end is grounded; the control end of the MOS transistor MN5 is connected to the control end of the MOS transistor MN1, and its second connection end is grounded; the first connection end of the MOS transistor MPHV6 is connected to the power supply terminal VDD, its second connection end is connected to the first connection end of the MOS transistor MN5, and its control end is connected to its second connection end; the first connection end of the MOS transistor MPHV7 is connected to the power supply terminal VDD, its control end is connected to the control end of the MOS transistor MPHV6, and its second connection end is connected to the second connection node B.

[0007] Further, the MOS transistors MPHV7, MPHV6, and MPHV5 are all PMOS transistors. The first connection end, the second connection end, and the control end of the MOS transistors MPHV7, MPHV6, and MPHV5 are respectively the source, drain, and gate of the PMOS transistor; the MOS transistors MN5, MN1, MNHV3, and MNHV4 are all NMOS transistors. The first connection end, the second connection end, and the control end of the MOS transistors MN5, MN1, MNHV3, and MNHV4 are respectively the drain, source, and gate of the NMOS transistor.

[0008] Further, the body terminal of the MOS transistor MNHV3 is grounded; the MOS transistors MNHV3 and MNHV4 are of the same type; the MOS transistors MNHV3 and MNHV4 form a differential amplifier.

[0009] Further, when the replicated current output by the output end of the current replication circuit is greater than the current of the second current source I2, the second connection node B is at a high level, which controls the MOS transistor MPHV5 to turn off. At this time, the MOS transistor MNHV4 supplies power to the voltage output terminal VO; when the replicated current output by the output end of the current replication circuit is less than the current of the second current source I2, the second connection node B is at a low level, which controls the MOS transistor MPHV5 to turn on.

[0010] Further, the voltage regulator without a compensation capacitor further includes a clamping circuit. The clamping circuit is connected between the power supply terminal VDD and the second connection node B, and is used to clamp the minimum value of the voltage of the second connection node B to a predetermined voltage threshold.

[0011] Further, the current value of the second current source is less than that of the first current source. The MOS transistors MN5 and MN1 form a current mirror, and the ratio of the width-to-length ratios of the MOS transistors MN5 and MN1 is 1:1. The MOS transistors MPHV7 and MPHV6 form a current mirror, and the ratio of the width-to-length ratios of the MOS transistors MPHV7 and MPHV6 is 1:1.

[0012] Further, the current value of the second current source is equal to half of the current value of the first current source.

[0013] Further, the clamping circuit includes a plurality of MOS transistors connected in series between the power supply terminal VDD and the second connection node B. Among them, each MOS transistor in the clamping circuit is configured in a diode-connected manner.

[0014] Further, the clamping circuit includes PMOS transistors MP3 and MP2. The source of the PMOS transistor MP3 is connected to the power supply terminal VDD, and its gate is connected to its drain. The source of the PMOS transistor MP2 is connected to the drain of the PMOS transistor MP3, and its gate and drain are both connected to the second connection node B.

[0015] Further, the voltage regulator without a compensation capacitor further includes a voltage boosting circuit. The voltage boosting circuit is connected between the second connection end of the MOS transistor MNHV3 and the input end of the current replication circuit, and is used to boost the voltage of the second connection end of the MOS transistor MNHV3.

[0016] Further, the voltage boosting circuit includes a plurality of MOS transistors, and the plurality of MOS transistors are connected in series between the second connection end of the MOS transistor MNHV3 and the input end of the current replication circuit. Each MOS transistor in the voltage boosting circuit is configured in a diode-connected manner.

[0017] Further, the voltage boosting circuit includes a PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the second connection end of the MOS transistor MNHV3, its drain is connected to the input end of the current replication circuit, and its gate is connected to its drain.

[0018] Further, the voltage boosting circuit further includes an NMOS transistor MN2. The drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP1, its source is connected to the input end of the current replication circuit, and its gate is connected to its drain.

[0019] Compared with the prior art, the voltage regulator of the present invention can dispense with a compensation capacitor through reasonable circuit design, thereby saving chip area and reducing costs.

Description of the Drawings

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. Among them:

[0021] Figure 1 It is a schematic circuit diagram of a voltage regulator without a compensation capacitor in the first embodiment of the present invention;

[0022] Figure 2 It is a schematic circuit diagram of a voltage regulator without a compensation capacitor in the second embodiment of the present invention;

[0023] Figure 3 It is a schematic circuit diagram of a voltage regulator without a compensation capacitor in the third embodiment of the present invention.

Specific Embodiments

[0024] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0025] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words indicating electrical connection, such as "connected", "coupled", and "joined", in this article all mean directly or indirectly electrically connected.

[0026] Please refer to Figure 1 As shown, it is a schematic circuit diagram of a voltage regulator without a compensation capacitor in the first embodiment of the present invention. Figure 1 The voltage regulator without a compensation capacitor shown includes a clamping circuit 110, a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube MNHV3, a first current source I1, a second current source I2, a power supply path 120, a current replication circuit 130, and a voltage boosting circuit 140.

[0027] Among them, the input end of the first current source I1 is connected to the power supply terminal VDD, and its output end is connected to the first connection node A; the first connection end of the MOS transistor MNHV3 is connected to the first connection node A, its control end is connected to the first connection node A, its second connection end is connected to the input end of the current replication circuit 130 through the voltage boosting circuit 140, and its body end is grounded; the output end of the current replication circuit 130 is connected to the second connection point B, and the current replication circuit 130 proportionally replicates the current input at the first connection end of the MOS transistor MNHV3 and outputs the replicated current at its output end; the input end of the second current source I2 is connected to the second connection node B, and its output end is grounded.

[0028] In Figure 1 the illustrated embodiment, the current replication circuit 130 includes MOS transistors MPHV7, MPHV6, MN5, and MN1. Among them, the first connection end of the MOS transistor MN1 is connected to the second connection end of the MOS transistor MNHV3 through the voltage boosting circuit 140 (it can also be said that the first connection end of the MOS transistor MN1 is the input end of the current replication circuit 130), its control end is connected to its first connection end, its second connection end is grounded, and its body end is connected to its second connection end; the control end of the MOS transistor MN5 is connected to the control end of the MOS transistor MN1, its second connection end is grounded, and its body end is connected to its second connection end; the first connection end of the MOS transistor MPHV6 is connected to the power supply terminal VDD, its second connection end is connected to the first connection end of the MOS transistor MN5, its control end is connected to its second connection end, and its body end is connected to its first connection end; the first connection end of the MOS transistor MPHV7 is connected to the power supply terminal VDD, its control end is connected to the control end of the MOS transistor MPHV6, its second connection end is connected to the second connection node B (it can also be said that the second connection end of the MOS transistor MPHV7 is the output end of the current replication circuit 130), and its body end is connected to its first connection end.

[0029] The voltage boosting circuit 140 is connected between the second connection end of the MOS transistor MNHV3 and the input end of the current replication circuit 130 (or the first connection end of the MOS transistor MN1), and it is used to boost the voltage of the second connection end of the MOS transistor MNHV3. In Figure 1 the illustrated specific embodiment, the voltage boosting circuit 140 includes a PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the second connection end of the MOS transistor MNHV3, its drain is connected to the input end of the current replication circuit 130 (or the first connection end of the MOS transistor MN1), its gate is connected to its drain, and its body end is connected to its source, that is, the PMOS transistor MP1 is configured in a diode connection mode.

[0030] The clamping circuit 110 is connected between the power supply terminal VDD and the second connection node B. The clamping circuit 110 is used to clamp the minimum value of the voltage of the second connection node B to a predetermined voltage threshold. The clamping circuit 110 includes a plurality of MOS transistors connected in series between the power supply terminal VDD and the second connection node B, and each MOS transistor in the clamping circuit 110 is configured in a diode connection mode; the body terminal of each MOS transistor in the clamping circuit 110 is connected to the power supply terminal VDD. In Figure 1 In the specific embodiment shown, the clamping circuit 110 includes PMOS transistors MP3 and MP2. Among them, the source of the PMOS transistor MP3 is connected to the power supply terminal VDD, and its gate is connected to its drain; the source of the PMOS transistor MP2 is connected to the drain of the PMOS transistor MP3, and its gate and drain are both connected to the second connection node B; the body terminals of the PMOS transistors MP3 and MP2 are both connected to the power supply terminal VDD, that is, the PMOS transistor MP3 is configured in a diode connection mode, and the PMOS transistor MP2 is configured in a diode connection mode.

[0031] The power supply path 120 includes MOS transistors MNHV4 and MPHV5. The first connection terminal of the MOS transistor MNHV4 is connected to the power supply terminal VDD, its control terminal is connected to the first connection node A, its second connection terminal is connected to the voltage output terminal VO1 of the power supply path 120, and its body terminal is connected to its second connection terminal; the first connection terminal of the MOS transistor MPHV5 is connected to the power supply terminal VDD, its control terminal is connected to the second connection node B, its second connection terminal is connected to the voltage output terminal VO1 of the power supply path 120, and its body terminal is connected to its first connection terminal.

[0032] In Figure 1 In the specific embodiment shown, the MOS transistors MPHV7, MPHV6, and MPHV5 are all PMOS (positive channel Metal Oxide Semiconductor) transistors, and the first connection terminal, second connection terminal, and control terminal of the MOS transistors MPHV7, MPHV6, and MPHV5 are the source, drain, and gate of the PMOS transistor respectively; the MOS transistors MN5, MN1, MNHV3, and MNHV4 are all NMOS (negative channel Metal Oxide Semiconductor) transistors, and the first connection terminal, second connection terminal, and control terminal of the MOS transistors MN5, MN1, MNHV3, and MNHV4 are the drain, source, and gate of the NMOS transistor respectively.

[0033] Among them, the current value of the second current source I2 is less than the current value of the first current source I1. In a preferred embodiment, the current value of the second current source I2 is designed to be equal to half of the current value of the first current source I1.

[0034] MOS transistors MPHV7 and MPHV6 form a current mirror; MOS transistors MN5 and MN1 form a current mirror.

[0035] In a preferred embodiment, the ratio of the width-to-length ratio of MOS transistors MN5 and MN1 is 1:1, that is, MOS transistor MN5 replicates the current of MOS transistor MN1 at a ratio of 1:1; the ratio of the width-to-length ratio of MOS transistors MPHV7 and MPHV6 is 1:1, that is, PMOS transistor MPHV7 replicates the current of MOS transistor MPHV6 at a ratio of 1:1.

[0036] When the current of PMOS transistor MPHV7 (or the replicated current output from the output terminal of current replication circuit 130) is greater than the current of second current source I2, second connection node B is at a high level, which controls PMOS transistor MPHV5 to be open (or turned off). At this time, mainly NMOS transistor MNHV4 supplies current to voltage output terminal VO1. The source voltage of NMOS transistor MNHV3 is equal to |Vgs_MP1| + Vgs_MN1, where Vgs_MP1 is the gate-source voltage of PMOS transistor MP1, and Vgs_MN1 is the gate-source voltage of NMOS transistor MN1. NMOS transistors MNHV3 and MNHV4 are NMOS transistors of the same type, here they are high-voltage NMOS transistors. NMOS transistors MNHV3 and MNHV4 form a differential amplifier with source input to adjust the source voltage of NMOS transistor MNHV4 to be close to equal to the source voltage of NMOS transistor MNHV3. Therefore, the voltage of voltage output terminal VO1 is close to equal to |Vgs_MP1| + Vgs_MN1. Generally, the subsequent powered circuit is composed of PMOS and NMOS transistors, and such a voltage can generally ensure being high enough to enable the subsequent circuit to work stably.

[0037] When the voltage of the power supply terminal VDD drops below |Vgs_MP1| + Vgs_MN1 + Vgs_MNHV3, the current of the NMOS transistor MN1 decreases, resulting in a decrease in the current of the PMOS transistor MPHV7. Here, Vgs_MP1 is the gate-source voltage of the PMOS transistor MP1, Vgs_MN1 is the gate-source voltage of the NMOS transistor MN1, and Vgs_MNHV3 is the gate-source voltage of the NMOS transistor MNHV3. When the current of the PMOS transistor MPHV7 (or the replicated current output from the output terminal of the current replication circuit 130) drops below the current of the second current source I2, the voltage of the second connection node B becomes low (or at a low level). However, the PMOS transistors MP3 and MP2 in the clamping circuit 110 are connected in a diode configuration, which can clamp the voltage of the second connection node B from dropping too much below |Vgs_MP3| + |Vgs_MP2|. Here, Vgs_MP3 is the gate-source voltage of the PMOS transistor MP3, and Vgs_MP2 is the gate-source voltage of the PMOS transistor MP2. This can protect the gate of the PMOS transistor MPHV5 (because in many processes, such high-voltage transistors use a thin gate oxide structure, and their Vgs withstand voltage is not high. Of course, some processes support a thick gate oxide structure with high voltage resistance, and the clamping circuit 110 like PMOS transistors MP3 and MP2 may not be needed). When the voltage of the second connection node B becomes low, the PMOS transistor MPHV5 conducts, making the voltage of the voltage output terminal VO1 close to the voltage of the power supply terminal VDD. At this time, the voltage of the power supply terminal VDD is already very low and can directly supply power to the subsequent output voltage without damaging the subsequent powered circuit. This circuit can provide a relatively stable output voltage to supply power to the subsequent circuit and does not generally require a compensation capacitor that occupies a large chip area.

[0038] Please refer to Figure 2 shown, which is a circuit schematic diagram of a voltage regulator without a compensation capacitor in the second embodiment of the present invention. Figure 2 is basically the same as the circuit structure of the voltage regulator without a compensation capacitor shown in Figure 1 The main difference between it and the voltage regulator without a compensation capacitor shown in Figure 1 is that Figure 2 According to needs, an NMOS transistor MN2 or more MOS transistors are connected in series below the NMOS transistor MNHV3 to increase the voltage value of the voltage output terminal VO1. It can also be said that the voltage boosting circuit 140 includes several MOS transistors, and these several MOS transistors are connected in series between the second connection end of the MOS transistor MNHV3 and the input terminal of the current replication circuit 130 (or the first connection end of the MOS transistor MN1). Among them, each MOS transistor in the voltage boosting circuit 140 is connected in a diode configuration. In Figure 2In the illustrated embodiment, the voltage boosting circuit 140 includes a PMOS transistor MP1 and an NMOS transistor MN2 connected in series between the second connection terminal of the MOS transistor MNHV3 and the input terminal of the current replication circuit 130 (or the first connection terminal of the MOS transistor MN1). The source of the PMOS transistor MP1 is connected to the second connection terminal of the MOS transistor MNHV3, its gate is connected to its drain, and its body terminal is connected to its source. The drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP1, its source is connected to the input terminal of the current replication circuit 130 (or the first connection terminal of the MOS transistor MN1), its gate is connected to its drain, and its body terminal is grounded. After the NMOS transistor MN2 is connected in series, when the voltage of the power supply terminal VDD is relatively high (higher than |Vgs_MP1| + Vgs_MN1 + Vgs_MN2 + Vgs_MNHV3), the voltage of the voltage output terminal VO1 is approximately equal to |Vgs_MP1| + Vgs_MN1 + Vgs_MN2, where Vgs_MP1 is the gate-source voltage of the PMOS transistor MP1, Vgs_MN1 is the gate-source voltage of the NMOS transistor MN1, and Vgs_MN2 is the gate-source voltage of the NMOS transistor MN2.

[0039] Please refer to Figure 3 as shown, which is a schematic circuit diagram of a voltage regulator without a compensation capacitor in the third embodiment of the present invention. Figure 3 is basically the same as Figure 1 the circuit structure of the voltage regulator without a compensation capacitor shown, and the main difference between it and Figure 1 the voltage regulator without a compensation capacitor shown is that Figure 3 a power supply path 150 is added. The circuit structure of the power supply path 150 is the same as that of the power supply path 120. The power supply path 150 includes a MOS transistor MNHV6 and a MPHV8. The first connection terminal of the MOS transistor MNHV6 is connected to the power supply terminal VDD, its control terminal is connected to the first connection node A, and its second connection terminal is connected to the voltage output terminal VO2 of the power supply path 150. The first connection terminal of the MOS transistor MPHV8 is connected to the power supply terminal VDD, its control terminal is connected to the second connection node B, and its second connection terminal is connected to the voltage output terminal VO2 of the power supply path 150. Thus, in Figure 3In the illustrated embodiment, two output voltages VO1 and VO2 can be generated. In many application examples, two or more power supply paths need to be generated in a chip to avoid affecting the operation of another powered circuit due to the fluctuation of the output voltage shared when the current of one powered circuit fluctuates. If more output power supply paths need to be expanded, similar NMOS transistors MNHV6 and PMOS transistors MPHV8 can be added to achieve this. The gates of the expanded (or added) NMOS transistors are connected to the first connection node A, the drains are connected to the power supply terminal VDD, and the sources are connected to the voltage output terminal of this power supply path. The gates of the expanded (or added) PMOS transistors are connected to the second connection node B, the sources are connected to the power supply terminal VDD, and the drains are connected to the voltage output terminal of this power supply path. That is to say, the voltage regulator of the present invention without a compensation capacitor includes one or more power supply paths 120 and 150.

[0040] In summary, the voltage regulator of the present invention can dispense with a compensation capacitor through reasonable circuit design, thereby saving chip area and reducing costs.

[0041] In the present invention, terms indicating electrical connection such as "connected", "linked", "joined", and "connected to", unless otherwise specified, mean direct or indirect electrical connection. The direct electrical connection means a direct connection between two or more objects without any intervening objects, and the indirect electrical connection means a connection between two or more objects with one or more intervening objects (such as electrical components or electrical units like resistors, capacitors, inductors, switches, filters, etc.).

[0042] It should be noted that any modification made by those skilled in the art to the specific embodiments of the present invention does not depart from the scope of the claims of the present invention. Correspondingly, the scope of the claims of the present invention is not limited solely to the foregoing specific embodiments.

Claims

1. A voltage regulator without a compensating capacitor, characterized in that It includes MOS transistor MNHV3, a current replication circuit, a first current source I1, a second current source I2, and one or more power supply paths. The input terminal of the first current source I1 is connected to the power supply terminal VDD, and its output terminal is connected to the first connection node A; the first connection terminal of the MOS transistor MNHV3 is connected to the first connection node A, its control terminal is connected to the first connection node A, and its second connection terminal is connected to the input terminal of the current replication circuit; the output terminal of the current replication circuit is connected to the second connection node B, and the current replication circuit proportionally replicates the current input at the first connection terminal of the MOS transistor MNHV3 and outputs the replicated current at its output terminal; the input terminal of the second current source I2 is connected to the second connection node B, and its output terminal is grounded. The power supply path includes MOS transistors MNHV4 and MPHV5. The first connection terminal of the MOS transistor MNHV4 is connected to the power supply terminal VDD, its control terminal is connected to the first connection node A, and its second connection terminal is connected to the voltage output terminal VO of the power supply path; the first connection terminal of the MOS transistor MPHV5 is connected to the power supply terminal VDD, its control terminal is connected to the second connection node B, and its second connection terminal is connected to the voltage output terminal VO of the power supply path.

2. The voltage regulator without a compensation capacitor according to claim 1, characterized in that the current replication circuit includes MOS transistors MPHV7, MPHV6, MN5, and MN1. The first connection terminal of the MOS transistor MN1 is connected to the second connection terminal of the MOS transistor MNHV3, its control terminal is connected to its first connection terminal, and its second connection terminal is grounded; the control terminal of the MOS transistor MN5 is connected to the control terminal of the MOS transistor MN1, and its second connection terminal is grounded; the first connection terminal of the MOS transistor MPHV6 is connected to the power supply terminal VDD, its second connection terminal is connected to the first connection terminal of the MOS transistor MN5, and its control terminal is connected to its second connection terminal; the first connection terminal of the MOS transistor MPHV7 is connected to the power supply terminal VDD, its control terminal is connected to the control terminal of the MOS transistor MPHV6, and its second connection terminal is connected to the second connection node B.

3. The voltage regulator without a compensation capacitor according to claim 2, characterized in that the MOS transistors MPHV7, MPHV6, and MPHV5 are all PMOS transistors, and the first connection terminal, the second connection terminal, and the control terminal of the MOS transistors MPHV7, MPHV6, and MPHV5 are respectively the source, drain, and gate of the PMOS transistor; the MOS transistors MN5, MN1, MNHV3, and MNHV4 are all NMOS transistors, and the first connection terminal, the second connection terminal, and the control terminal of the MOS transistors MN5, MN1, MNHV3, and MNHV4 are respectively the drain, source, and gate of the NMOS transistor.

4. The voltage regulator without a compensation capacitor according to claim 3, characterized in that the body terminal of the MOS transistor MNHV3 is grounded. The MOS transistors MNHV3 and MNHV4 are of the same type; The MOS transistors MNHV3 and MNHV4 form a differential amplifier.

5. The voltage regulator without a compensation capacitor according to claim 1, wherein When the replicated current output from the output terminal of the current replication circuit is greater than the current of the second current source I2, the second connection node B is at a high level, which controls the MOS transistor MPHV5 to turn off. At this time, the MOS transistor MNHV4 supplies power to the voltage output terminal VO; When the replicated current output from the output terminal of the current replication circuit is less than the current of the second current source I2, the second connection node B is at a low level, which controls the MOS transistor MPHV5 to turn on.

6. The voltage regulator without a compensating capacitor according to claim 1, characterized in that It further includes a clamping circuit, The clamping circuit is connected between the power supply terminal VDD and the second connection node B, and is used to clamp the minimum value of the voltage of the second connection node B to a predetermined voltage threshold.

7. The voltage regulator without a compensation capacitor according to claim 2, wherein The current value of the second current source is less than the current value of the first current source, The MOS transistors MN5 and MN1 form a current mirror, and the ratio of the width-to-length ratio of the MOS transistors MN5 and MN1 is 1:1; The MOS transistors MPHV7 and MPHV6 form a current mirror, and the ratio of the width-to-length ratio of the MOS transistors MPHV7 and MPHV6 is 1:

1.

8. The voltage regulator without a compensation capacitor according to claim 7, wherein The current value of the second current source is equal to half of the current value of the first current source.

9. The voltage regulator without a compensation capacitor according to claim 6, wherein The clamping circuit includes a plurality of MOS transistors connected in series between the power supply terminal VDD and the second connection node B. Among them, each MOS transistor in the clamping circuit is in a diode connection mode.

10. The voltage regulator without a compensation capacitor according to claim 9, wherein The clamping circuit includes PMOS transistors MP3 and MP2, The source of the PMOS transistor MP3 is connected to the power supply terminal VDD, and its gate is connected to its drain; The source of the PMOS transistor MP2 is connected to the drain of the PMOS transistor MP3, and its gate and drain are both connected to the second connection node B.

11. The voltage regulator without a compensating capacitor according to claim 1, characterized in that, It further includes a voltage boosting circuit, The voltage boosting circuit is connected between the second connection end of the MOS transistor MNHV3 and the input end of the current replication circuit, and is used to boost the voltage of the second connection end of the MOS transistor MNHV3.

12. The voltage regulator without a compensation capacitor according to claim 11, wherein The voltage boosting circuit includes a plurality of MOS transistors, The plurality of MOS transistors are connected in series between the second connection end of the MOS transistor MNHV3 and the input end of the current replication circuit; Each MOS transistor in the voltage boosting circuit is in a diode connection mode.

13. The voltage regulator without a compensation capacitor according to claim 12, wherein The voltage boosting circuit includes a PMOS transistor MP1, The source of the PMOS transistor MP1 is connected to the second connection end of the MOS transistor MNHV3, its drain is connected to the input end of the current replication circuit, and its gate is connected to its drain.

14. The voltage regulator without a compensation capacitor according to claim 13, wherein the voltage boost circuit further includes an NMOS transistor MN2, the drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP1, its source is connected to the input end of the current replication circuit, and its gate is connected to its drain.

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