Rectifier circuit and power control device

Abstract

A rectifier circuit and a power receiving control device. The rectifier circuit includes: a first input line supplied with a first AC voltage and routed along a first direction; a second input line supplied with a second AC voltage and routed along the first direction on a second direction side of the first input line; a first output line outputting a first rectified voltage and routed along a second direction; a second output line outputting a second rectified voltage and routed along the second direction on a first direction side of the first output line; a first rectifier element disposed at the intersection of the first input line and the first output line; a second rectifier element disposed at the intersection of the second input line and the first output line; a third rectifier element disposed at the intersection of the first input line and the second output line; and a fourth rectifier element disposed at the intersection of the second input line and the second output line.

Description

Technical Field

[0001] This invention relates to rectifier circuits and power receiving control devices, etc. Background Technology

[0002] Rectifier circuits that rectify alternating current voltage and output a rectified voltage have been known for a long time. As prior art for such rectifier circuits, for example, the circuit disclosed in Patent Document 1 is known. In the rectifier circuit of Patent Document 1, a Schottky diode is used as the rectifier element on the upper side (high potential side), and an N-type transistor is used as the rectifier element on the lower side (low potential side).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2013-255392

[0004] However, Patent Document 1 discloses the circuit structure of the rectifier circuit, but does not disclose the layout configuration of the rectifier circuit. In particular, it does not propose a layout configuration that can reduce power loss during power reception. Summary of the Invention

[0005] One aspect of the present invention relates to a rectifier circuit that receives a first AC voltage and a second AC voltage inversely opposite to the first AC voltage, and outputs a first rectified voltage on a high potential side and a second rectified voltage on a low potential side. The rectifier circuit includes: a first input line supplied with the first AC voltage and routed along a first direction; a second input line supplied with the second AC voltage, routed along the first direction on the second direction side of the first input line when the direction perpendicular to the first direction is defined as the second direction; a first output line, which is the output line of the first rectified voltage and routed along the second direction; and a second output line, which is the output line of the second rectified voltage, routed along the first direction on the first output line. The second direction wiring; a first rectifier element, which, when viewed from above, is configured corresponding to the intersection of the first input line and the first output line, and connected between the first input line and the first output line; a second rectifier element, which, when viewed from above, is configured corresponding to the intersection of the second input line and the first output line, and connected between the second input line and the first output line; a third rectifier element, which, when viewed from above, is configured corresponding to the intersection of the first input line and the second output line, and connected between the first input line and the second output line; and a fourth rectifier element, which, when viewed from above, is configured corresponding to the intersection of the second input line and the second output line, and connected between the second input line and the second output line.

[0006] Furthermore, one aspect of the present invention relates to a power receiving control device comprising: a power receiving circuit including the aforementioned rectifier circuit; and a power supply circuit that supplies power according to the power received by the power receiving circuit. Attached Figure Description

[0007] Figure 1 This is an example of the structure of the rectifier circuit in this embodiment.

[0008] Figure 2 This is an example of the layout configuration of the rectifier circuit in this embodiment.

[0009] Figure 3 This is a detailed layout example of the rectifier circuit in this embodiment.

[0010] Figure 4 This is the first structural example of the rectifier circuit in this embodiment.

[0011] Figure 5 This is the second structural example of the rectifier circuit in this embodiment.

[0012] Figure 6 This is the third structural example of the rectifier circuit in this embodiment.

[0013] Figure 7 This is an operational diagram illustrating the rectifier circuit of the first structural example.

[0014] Figure 8 This is an operational diagram illustrating the rectifier circuit of the first structural example.

[0015] Figure 9 This is a signal waveform diagram illustrating the operation of the rectifier circuit in the second structural example.

[0016] Figure 10 This is a signal waveform diagram illustrating the operation of the rectifier circuit in the third structural example.

[0017] Figure 11 This is a detailed layout example of the rectifier circuit in this embodiment.

[0018] Figure 12 This is a detailed layout example of the rectifier circuit in this embodiment.

[0019] Figure 13 This is a cross-sectional view of the rectifier circuit.

[0020] Figure 14 These are cross-sectional views of different types of rectifier circuits.

[0021] Figure 15 These are diagrams illustrating the operation of different types of rectifier circuits.

[0022] Figure 16 This is a structural example of the power receiving control device in this embodiment.

[0023] Figure 17 This is a structural example of the power receiving control device in this embodiment.

[0024] Label Explanation

[0025] 10: Rectifier circuit; 12: AC power supply; 14: Load; 15: Battery; 16: Capacitor; 20: P-type well; 22: N-type well; 24: N-type well; 26: N-type diffusion layer; 27: N-type diffusion region; 30: Metal layer; 32: Diffusion layer; 34: Embedding layer; 40: Power receiving control device; 50: Power receiving circuit; 60: Power supply circuit; 70: Power transmission device; ALA~ALD: Metal layer; ANi: Anode; ANj: Anode; ANp; ANq: Anode; CA1, CA2, CA3, CA4: Cathode; CCAi, CCAj, CCAp, CCAq: Common cathode; D1, D2, D3, D4: Diode; DP1, DP2: Parasitic diode; DR1, DR2, DR3, DR4: Direction; Di: Diode; Dj, Dp: Diode; Dq: Diode; GD1, GD2, GD3, GD4: Diode group; GI1, GI2: Input line group; GQ1: Output line group; GQ2: Output line group; GRF1, GRF2, GRF3, GRF4: Rectifier element group; I1, I2: Input line; ID1: Current; ID2: Current; L: Coil; L1: Primary coil; L2: Secondary coil; Q1, Q2: Output line; RF1, RF2, RF3; RF4: Rectifier element; T1, T2: Transistor; VC1, VC2: AC voltage; VCC, VSS: Rectified voltage; VF: Forward voltage. Detailed Implementation

[0026] The preferred embodiments of the present invention will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the invention as defined in the claims, and not all structures described in these embodiments are necessary to achieve the desired solution.

[0027] 1. Rectifier circuit

[0028] Figure 1 An example of the structure of the rectifier circuit 10 in this embodiment is shown. The rectifier circuit 10 receives AC voltages VC1 and VC2 as inputs and outputs rectified voltages VCC and VSS. AC voltage VC1 is a first AC voltage, and AC voltage VC2 is a second AC voltage that is inversely phase to AC voltage VC1. Rectified voltage VCC is the first rectified voltage on the high-potential side, and rectified voltage VSS is the second rectified voltage on the low-potential side. That is, the rectifier circuit 10 receives VC1 as the first AC voltage and VC2 as the inverse of VC1 as the second AC voltage, and, for example, through full-wave rectification, outputs VCC as the first rectified voltage on the high-potential side and VSS as the second rectified voltage on the low-potential side. Figure 1 AC voltages VC1 and VC2 are supplied from AC power source 12.

[0029] The rectifier circuit 10 includes rectifier elements RF1, RF2, RF3, and RF4. RF1 is the first rectifier element, RF2 is the second rectifier element, RF3 is the third rectifier element, and RF4 is the fourth rectifier element. As described later, diodes can be used as rectifier elements, and Schottky diodes are more preferred. Alternatively, transistors can also be used as rectifier elements. Rectifier element RF1 is positioned between the input node N1 of AC voltage VC1 and the output node NH of rectified voltage VCC, and is a forward rectifier element moving from node N1 towards node NH. "Forward" refers to the rectification direction. Rectifier element RF2 is positioned between the input node N2 of AC voltage VC2 and node NH, and is a forward rectifier element moving from node N2 towards node NH. Rectifier element RF3 is positioned between the output node NL of rectified voltage VSS and node N1, and is a forward rectifier element moving from node NL towards node N1. The rectifier element RF4 is disposed between node NL and node N2, and its direction from node NL to node N2 is considered positive. Furthermore, the rectifier circuit 10 in this embodiment is not limited to... Figure 1 The structure allows for deformations such as adding other structural elements.

[0030] Figure 2 An example layout of the rectifier circuit 10 in this embodiment is shown. Figure 2 The layout of circuit elements and wiring is shown when viewed from above in a direction perpendicular to the semiconductor substrate on which the rectifier circuit 10 is formed. Figure 2 In this context, the direction perpendicular to direction DR1 is designated as direction DR2, the opposite direction of direction DR1 is designated as direction DR3, and the opposite direction of direction DR2 is designated as direction DR4. Directions DR1, DR2, DR3, and DR4 are respectively the first, second, third, and fourth directions. Furthermore, in... Figure 2 In this embodiment, directions DR1, DR2, DR3, and DR4 are respectively right, down, left, and up on the paper, but this embodiment is not limited to this. For example, various modifications can be implemented, such as directions DR1 and DR3 being left and right respectively, or directions DR2 and DR4 being up and down respectively.

[0031] The rectifier circuit 10 includes Figure 1 The rectifier components RF1, RF2, RF3, and RF4, input lines I1 and I2, and output lines Q1 and Q2 are described in the diagram. Input line I1 is the first input line, input line I2 is the second input line, output line Q1 is the first output line, and output line Q2 is the second output line.

[0032] Input line I1, serving as the first input line, is supplied with the first AC voltage VC1 and is routed along direction DR1. That is, input line I1 is routed along direction DR1 as its length direction. Direction DR1 is the first direction. When the direction perpendicular to direction DR1 is designated as direction DR2, a second input line, i.e., input line I2, is routed along direction DR1 on the direction DR2 side of input line I1. That is, input line I2 is located on the direction DR2 side of input line I1, and direction DR1 is routed as its length direction. Direction DR2 is the second direction. Output line Q1, serving as the first output line, is the output line of the first rectified voltage VCC on the high-potential side and is routed along direction DR2. That is, output line Q1 is routed along direction DR2 as its length direction, outputting the rectified voltage VCC after rectification by rectifier circuit 10. Output line Q2, i.e., output line of the second rectified voltage VSS on the low-potential side, is routed along direction DR2 on the direction DR1 side of output line Q1. That is, the output line Q2 is configured on the side of the direction DR1 of the output line Q1, and the direction DR2 is used as the length direction for wiring, and the output is the rectified voltage VSS after being rectified by the rectifier circuit 10.

[0033] RF1, as the first rectifier element, is positioned at the intersection of input line I1 and output line Q1 when viewed from above, and is connected between input line I1 and output line Q1. That is, as Figure 1 As shown, the rectifier element RF1 is connected between the input line I1 of the AC voltage VC1 corresponding to node N1 and the output line Q1 of the rectified voltage VCC corresponding to node NH, performing a positive rectification operation from the input line I1 to the output line Q1. Furthermore, the rectifier element RF1 is, for example, positioned in a region corresponding to the intersection of the input line I1 and the output line Q1. Additionally, the top view is, for example, a view perpendicular to the semiconductor substrate on which the rectifier circuit 10 is formed.

[0034] RF2, as the second rectifier element, is positioned at the intersection of input line I2 and output line Q1 when viewed from above, and is connected between input line I2 and output line Q1. That is, as Figure 1 As shown, rectifier element RF2 is connected between the input line I2 of AC voltage VC2 corresponding to node N2 and the output line Q1 of rectified voltage VCC corresponding to node NH, performing a positive rectification operation from input line I2 to output line Q1. Furthermore, rectifier element RF2 is, for example, positioned in the region corresponding to the intersection of input line I2 and output line Q1.

[0035] RF3, as the third rectifier element, is positioned at the intersection of input line I1 and output line Q2 when viewed from above, and is connected between input line I1 and output line Q2. That is, as Figure 1As shown, rectifier element RF3 is connected between the input line I1 of AC voltage VC1 corresponding to node N1 and the output line Q2 of rectified voltage VSS corresponding to node NL, performing a positive rectification operation from output line Q2 to input line I1. Furthermore, rectifier element RF3 is, for example, positioned in the region corresponding to the intersection of input line I1 and output line Q2.

[0036] RF4, as the fourth rectifier element, is positioned at the intersection of input line I2 and output line Q2 when viewed from above, and is connected between input line I2 and output line Q2. That is, as Figure 1 As shown, rectifier element RF4 is connected between the input line I2 of AC voltage VC2 corresponding to node N2 and the output line Q2 of rectified voltage VSS corresponding to node NL, performing a positive rectification operation from output line Q2 to input line I2. Furthermore, rectifier element RF4 is, for example, positioned in the region corresponding to the intersection of input line I2 and output line Q2.

[0037] Thus, in this embodiment, input lines I1 and I2 for AC voltages VC1 and VC2 are arranged along direction DR1, and output lines Q1 and Q2 for rectified voltages VCC and VSS are arranged along direction DR2, which is perpendicular to direction DR1. Furthermore, rectifier elements RF1 and RF2 are positioned in regions corresponding to the intersections of input lines I1 and I2 and output line Q1, and rectifier elements RF3 and RF4 are positioned in regions corresponding to the intersections of input lines I1 and I2 and output line Q2. Therefore, the parasitic resistance between input line I1 and one end of rectifier element RF1, and between the other end of rectifier element RF1 and output line Q1, can be reduced, as can the parasitic resistance between input line I2 and one end of rectifier element RF2, and between the other end of rectifier element RF2 and output line Q1. Similarly, the parasitic resistance between input line I1 and one end of rectifier element RF3, and between the other end of rectifier element RF3 and output line Q2, can be reduced. The parasitic resistance between input line I2 and one end of rectifier element RF4, and between the other end of rectifier element RF4 and output line Q2, can also be reduced. By reducing parasitic resistance in this way, low impedance can be achieved during rectification operation, thus reducing power loss in rectifier circuit 10. Furthermore, efficient layout and configuration of rectifier elements RF1, RF2, RF3, and RF4, efficient layout and routing of input lines I1 and I2, and output lines Q1 and Q2 can also be achieved, resulting in a smaller layout area for rectifier circuit 10.

[0038] Figure 3 A detailed layout example of the rectifier circuit 10 in this embodiment is shown. Figure 3In the rectifier circuit 10, there are: input line group GI1, which includes input line I1; input line group GI2, which includes input line I2; output line group GQ1, which includes output line Q1; and output line group GQ2, which includes output line Q2. Input line group GI1 is the first input line group, input line group GI2 is the second input line group, output line group GQ1 is the first output line group, and output line group GQ2 is the second output line group.

[0039] Moreover, such as Figure 3 As shown, each input line of input line group GI1 is arranged along direction DR1, and each input line of input line group GI2 is arranged along direction DR1 on the direction DR2 side of input line group GI1. Similarly, each output line of output line group GQ1 is arranged along direction DR2, which is perpendicular to direction DR1, and each output line of output line group GQ2 is routed along direction DR2 on the direction DR1 side of output line group GQ1. For example, output line group GQ1 is routed in a manner that intersects with input line groups GI1 and GI2, and output line group GQ2 is routed in a manner that intersects with input line groups GI1 and GI2 on the direction DR1 side of output line group GQ1. Therefore, AC voltages VC1 and VC2 can be input to rectifier circuit 10 through multiple input lines of input line groups GI1 and GI2, and rectified voltages VCC and VSS can be output from rectifier circuit 10 through multiple output lines of output line groups GQ1 and GQ2. This allows for, for example, reduction of power loss due to reduced parasitic resistance and appropriate layout and routing.

[0040] In addition, Figure 3In the rectifier circuit 10, there are two rectifier element groups: rectifier element group GRF1, which includes rectifier element RF1; and rectifier element group GRF2, which includes rectifier element RF2. Rectifier element group GRF1 is a first rectifier element group, and rectifier element group GRF2 is a second rectifier element group. Furthermore, rectifier element group GRF1 is configured at the intersection of input line group GI1 and output line group GQ1, and rectifier element group GRF2 is configured at the intersection of input line group GI2 and output line group GQ1. For example, rectifier element group GRF1 is configured in a region corresponding to the intersection area of ​​input line group GI1 and output line group GQ1, and rectifier element group GRF2 is configured in a region corresponding to the intersection area of ​​input line group GI2 and output line group GQ1. Specifically, rectifier element group GRF1 may include, for example, a plurality of rectifier elements arranged in parallel, and rectifier element group GRF2 may include, for example, a plurality of rectifier elements arranged in parallel. Furthermore, for example, each rectifier element of rectifier element group GRF1 is arranged in the region corresponding to the intersection region of each input line of input line group GI1 and each output line of output line group GQ1. Similarly, each rectifier element of rectifier element group GRF2 is arranged in the region corresponding to the intersection region of each input line of input line group GI2 and each output line of output line group GQ1. Thus, for example, the rectification operation of rectifier circuit 10 can be performed by rectifier element group GRF1, which contains multiple rectifier elements, and rectifier element group GRF2, which also contains multiple rectifier elements. Therefore, the power loss of rectifier circuit 10 can be further reduced, achieving efficient rectification operation.

[0041] Furthermore, the rectifier circuit 10 includes: a rectifier element group GRF3, which includes rectifier element RF3; and a rectifier element group GRF4, which includes rectifier element RF4. The rectifier element group GRF3 is the third rectifier element group, and the rectifier element group GRF4 is the fourth rectifier element group. Moreover, the rectifier element group GRF3 is configured corresponding to the intersection of the input line group GI1 and the output line group GQ2, and the rectifier element group GRF4 is configured corresponding to the intersection of the input line group GI2 and the output line group GQ2. For example, the rectifier element group GRF3 is configured in the region corresponding to the intersection area of ​​the input line group GI1 and the output line group GQ2, and the rectifier element group GRF4 is configured in the region corresponding to the intersection area of ​​the input line group GI2 and the output line group GQ2. Specifically, the rectifier element group GRF3, for example, includes a plurality of rectifier elements arranged in parallel, and the rectifier element group GRF4, for example, includes a plurality of rectifier elements arranged in parallel. Furthermore, for example, each rectifier element of rectifier element group GRF3 is arranged in the region corresponding to the intersection region of each input line of input line group GI1 and each output line of output line group GQ2. In addition, each rectifier element of rectifier element group GRF4 is arranged in the region corresponding to the intersection region of each input line of input line group GI2 and each output line of output line group GQ2.

[0042] 2. Detailed structural example of a rectifier circuit

[0043] Figure 4 The first structural example of the rectifier circuit 10 is shown. Figure 4 In the middle, diodes D1 and D2 are set as Figure 1 The rectifier components are RF1 and RF2. Diode D1 is the first diode, specifically the first Schottky barrier diode. Diode D2 is the second diode, specifically the second Schottky barrier diode. Furthermore, in... Figure 4 In this configuration, diodes D3 and D4 are used as rectifier elements RF3 and RF4. Diode D3 is the third diode, specifically the third Schottky barrier diode. Diode D4 is the fourth diode, specifically the fourth Schottky barrier diode. A Schottky barrier diode utilizes a Schottky barrier formed by the junction of a metal and a semiconductor. Due to its operation based on multiple charge carriers, a Schottky barrier diode exhibits a smaller forward voltage drop and faster switching speed compared to a PN junction diode. Furthermore, variations using PN junction diodes as diodes D1, D2, D3, and D4 can be implemented. A PN junction diode is a diode formed by the junction of a P-type semiconductor region and an N-type semiconductor region.

[0044] In diodes D1 and D2, the output node (node ​​NH) of the rectified voltage VCC is the cathode. Furthermore, in diode D1, the input node (node ​​N1) of the AC voltage VC1 is the anode, and in diode D2, the input node (node ​​N2) of the AC voltage VC2 is the anode. In diodes D3 and D4, the output node (node ​​NL) of the rectified voltage VSS is the anode. Furthermore, in diode D3, node N1 is the cathode, and in diode D4, node N2 is the cathode. Additionally, in… Figure 4 The following Figure 5 , Figure 6 In this circuit, AC voltage VC1 is output from one end of the coil L that receives power, and AC voltage VC2 is output from the other end of the coil L. As an example, coil L will be described later. Figure 17 The secondary coil L2 in the contactless power transmission receives the power transmitted by the power transmission device 70.

[0045] Figure 5 The second structural example of the rectifier circuit 10 is shown. Figure 5 In this configuration, diodes D1 and D2 are set as rectifier elements RF1 and RF2, and transistors T1 and T2 are set as rectifier elements RF3 and RF4. Figure 5In this configuration, diodes D1 and D2 are Schottky barrier diodes, but variations using PN junction diodes are also possible. Transistor T1 is the first transistor, and transistor T2 is the second transistor. Transistors T1 and T2 are, for example, N-type transistors, such as N-type transistors of a MOS transistor. Furthermore, the gate of transistor T1 is connected to the input node N2 of AC voltage VC2, and the gate of transistor T2 is connected to the input node N1 of AC voltage VC1. That is, in Figure 2 , Figure 3 In transistor T1, the gate of transistor T1 is connected to the second input line, input line I2. The gate of transistor T2 is connected to the first input line, input line I1. Furthermore, in transistor T1, a parasitic diode DP1 is formed between the drain and source, which also functions as a rectifier element RF3. Similarly, in transistor T2, a parasitic diode DP2 is formed between the drain and source, which also functions as a rectifier element RF4. The parasitic diodes DP1 and DP2 are formed by the PN junction between the drain and source of transistors T1 and T2, and are also called body diodes.

[0046] Figure 6 The third structural example of the rectifier circuit 10 is shown. Figure 6 In this configuration, diodes D1 and D2 are used as rectifier elements RF1 and RF2. Furthermore, transistor T1 is used as rectifier element RF3, and diode D3 is connected in parallel with transistor T1. Diode D3 is the third Schottky barrier diode. Additionally, transistor T2 is used as rectifier element RF4, and diode D4 is connected in parallel with transistor T2. Diode D4 is the fourth Schottky barrier diode. The gate of transistor T1 is connected to node N2. Figure 2 , Figure 3 In the middle, it is connected to the input line I2. The gate of transistor T2 is connected to node N1, in Figure 2 , Figure 3 In the middle, it is connected to the input line I1. In addition, it is also possible to implement the setting of PN junction diodes as variations of diodes D1, D2, D3, and D4.

[0047] Figure 7 , Figure 8 yes Figure 4 The first structural example shows the operation diagram of the rectifier circuit 10. (See diagram for example.) Figure 7As shown, the current ID1 from node N1 of AC voltage VC1 flows through load 14 via diode D1, and from load 14 flows through node N2 of AC voltage VC2 via diode D4. The current ID2 from node N2 of AC voltage VC2 flows through load 14 via diode D2, and from load 14 flows through node N1 of AC voltage VC1 via diode D3. Regarding the paths of these currents ID1 and ID2, in... Figure 5 , Figure 6 The same applies to the rectifier circuit 10 in the second and third structural examples. Furthermore, in... Figure 7 In the process, a capacitor 16 for smoothing the rectified voltages VCC and VSS is provided between node NH of rectified voltage VCC and node NL of rectified voltage VSS.

[0048] Figure 8 Show Figure 7 The waveforms of the forward voltage VF and current ID1 of diode D1 are shown. Figure 8 As shown in B1, when diode D1 is a Schottky barrier diode, the forward voltage VF when a forward current ID1 flows through diode D1 can be reduced, for example, to about 0.4V. On the other hand, as shown in B2, when diode D1 is a PN junction diode, the forward voltage VF when a forward current ID1 flows through diode D1 becomes higher than that of a Schottky barrier diode, for example, to about 0.7V. Furthermore, in a Schottky barrier diode, the power loss when a reverse voltage is applied to diode D1 can be reduced, as shown in B3, but in a PN junction diode, as shown in B4, the power loss increases. Thus, using Schottky barrier diodes as diodes D1 to D4 is advantageous in that it reduces the forward voltage VF and the power loss compared to using PN junction diodes.

[0049] Figure 9 This is an explanation Figure 5 The signal waveform diagram of the operation of the rectifier circuit 10 in the second structural example. Figure 9 The period shown in E1 is as follows: when a forward voltage is applied to diode D1, transistor T2 turns on, and when a reverse voltage is applied to diode D2, transistor T1 turns off. Specifically, when the AC voltage VC1 exceeds the threshold voltage of transistor T2, transistor T2 turns on; when the AC voltage VC1 exceeds the rectified voltage VCC, a forward current flows through diode D1. Therefore, with... Figure 7Similarly, the current ID1 from node N1 of AC voltage VC1 flows through diode D1, load 14, and transistor T2 to node N2 of AC voltage VC2. At this time, because the forward voltage VF of the Schottky barrier diode is small, AC voltage VC1 is clamped to a voltage lower than the rectified voltage VCC, as shown in E2. Furthermore, even during the period when AC voltage VC1 is lower than the threshold voltage of transistor T2 and transistor T2 is still off, a forward current flows in parasitic diode DP2. Therefore, as shown in E3, AC voltage VC2 becomes a voltage that is lower than the rectified voltage VSS by the forward voltage VF of parasitic diode DP2. The regions exceeding the rectified voltage VCC shown in E2 and below the rectified voltage VSS shown in E3 become power loss regions.

[0050] also, Figure 9 The period shown in E4 is as follows: when a reverse voltage is applied to diode D1, transistor T2 is off; and when a forward voltage is applied to diode D2, transistor T1 is on. Specifically, when the AC voltage VC2 exceeds the threshold voltage of transistor T1, transistor T1 is on; and when the AC voltage VC2 exceeds the rectified voltage VCC, a forward current flows through diode D2. Therefore, with... Figure 7 Similarly, the current ID2 from node N2 of AC voltage VC2 flows through diode D2, load 14, and transistor T1 through node N1 of AC voltage VC1. In this case, the areas shown in E5 and E6 also become areas of power loss.

[0051] Figure 10 This is an explanation Figure 6 The signal waveform diagram of the operation of the rectifier circuit 10 in the third structural example. Figure 10 The period indicated by F1 is as follows: when a forward voltage is applied to diodes D1 and D4, transistor T2 conducts; and when a reverse voltage is applied to diodes D2 and D3, transistor T1 is turned off. Specifically, when the AC voltage VC1 exceeds the threshold voltage of transistor T2, transistor T2 conducts; and when the AC voltage VC1 exceeds the rectified voltage VCC, a forward current flows through diode D1. Therefore, with... Figure 7Similarly, the current ID1 from node N1 of AC voltage VC1 flows through node N2 of AC voltage VC2 via diode D1, load 14, transistor T2, and diode D4. At this time, the forward voltage VF of the Schottky barrier diode is small; therefore, as shown in F2, AC voltage VC1 is clamped to a voltage lower than the rectified voltage VCC. Furthermore, even during the period when AC voltage VC1 is lower than the threshold voltage of transistor T2 and transistor T2 is still off, current flows in diode D4, which is connected in parallel with transistor T2. Thus, as shown in F3, AC voltage VC2 becomes a voltage lower than the forward voltage VF of diode D4 by an amount lower than the rectified voltage VSS. In this case, diode D4 is a Schottky barrier diode with a low forward voltage VF; therefore, with… Figure 9 Compared to the E3, in Figure 10 In F3, the voltage drop relative to the rectified voltage VSS is relatively small. Therefore, according to Figure 6 , Figure 10 The rectifier circuit 10 in the third structural example, and Figure 5 , Figure 9 Compared to the rectifier circuit 10 in the second structural example, power loss can be reduced.

[0052] also, Figure 10 The period shown in F4 is as follows: when a reverse voltage is applied to diodes D1 and D4, transistor T2 is off; and when a forward voltage is applied to diodes D2 and D3, transistor T1 is on. Specifically, when the AC voltage VC2 exceeds the threshold voltage of transistor T1, transistor T1 turns on; when the AC voltage VC2 exceeds the rectified voltage VCC, a forward current flows through diode D2. Therefore, with... Figure 7 Similarly, the current ID2 from node N2 of AC voltage VC2 flows through diode D2, load 14, transistor T1, and diode D3 through node N1 of AC voltage VC1. In this case, the areas shown in F5 and F6 also become power loss areas, however, compared to... Figure 9 Compared to the regions shown in E5 and E6, the power loss is smaller. Therefore, according to Figure 6 , Figure 10 The rectifier circuit 10 in the third structural example, and Figure 5 , Figure 9 Compared to the rectifier circuit 10 in the second structural example, power loss can be reduced.

[0053] As mentioned above, in Figure 4 , Figure 5 , Figure 6 In the rectifier circuit 10, the first diode, namely diode D1, is set as... Figure 1The rectifier circuit 10 uses a second diode, D2, as rectifier element RF2, instead of a first diode RF1. This allows the rectifier circuit 10 to operate at a higher speed compared to using transistors as rectifier elements RF1 and RF2. Therefore, even when the frequencies of AC voltages VC1 and VC2 are high, the AC voltages VC1 and VC2 can be appropriately rectified to output rectified voltages VCC and VSS. In other words, when transistors are used as rectifier elements RF1 and RF2, feedback control of the transistor gate is required. Furthermore, such feedback control introduces a delay time, making it difficult for the rectifier circuit 10 to operate at high speed, especially when the frequencies of AC voltages VC1 and VC2 are high. In contrast, if diodes D1 and D2 are used as rectifier elements RF1 and RF2, such feedback control is not required, thus enabling the rectifier circuit 10 to operate at high speed, even when the frequencies of AC voltages VC1 and VC2 are high.

[0054] In addition, Figure 4 , Figure 5 , Figure 6 In the diagram, diode D1 is a Schottky barrier diode, and diode D2 is also a Schottky barrier diode. If Schottky barrier diodes are used as diodes D1 and D2 in this manner, then... Figure 8 As explained in B1 and B2, the forward voltage VF can be reduced compared to the case of using a PN junction diode. Thus, the forward voltage VF can be reduced, for example, as... Figure 9 E2, E5, Figure 10 As shown in F2 and F5, the regions where AC voltages VC1 and VC2 exceed the rectified voltage VCC can be reduced. Therefore, compared with PN junction diodes, power loss can be reduced and the power collection efficiency of rectifier circuit 10 can be improved.

[0055] In addition, Figure 5 , Figure 6In this design, transistor T1, whose gate is connected to the input line I2 of AC voltage VC2, is configured as rectifier element RF3, and transistor T2, whose gate is also connected to the input line I1 of AC voltage VC1, is configured as rectifier element RF4. Thus, AC voltage VC2 from input line I2 can be input to the gate of transistor T1, causing transistor T1 to turn on and off, thereby enabling transistor T1 to operate as rectifier element RF3. Similarly, AC voltage VC1 from input line I1 can be input to the gate of transistor T2, causing transistor T2 to turn on and off, thereby enabling transistor T2 to operate as rectifier element RF4. That is, even without a gate control circuit to control the transistor gates, transistors T1 and T2 can operate as rectifier elements RF3 and RF4. Furthermore, since the drain-source voltage when transistors T1 and T2 are turned on is smaller than the forward voltage VF of the diode, it also has the advantage of reducing forward losses.

[0056] In addition, Figure 6 In addition, a third Schottky barrier diode, namely diode D3, connected in parallel with transistor T1 is provided as a rectifier element RF3, and a fourth Schottky barrier diode, namely diode D4, connected in parallel with transistor T2 is provided as a rectifier element RF4. Therefore, with... Figure 5 Compared to the structure of diodes D3 and D4 without a Schottky barrier diode, such as Figure 10 As explained in F3 and F6, this can reduce power loss. That is, in Figure 5 In the structure, such as Figure 9 As shown in E3 and E6, the AC voltages VC1 and VC2 are lower than the rectified voltage VSS by the forward voltage VF of the PN junction diodes, i.e., the parasitic diodes DP1 and DP2. In contrast, through... Figure 6 The diodes D3 and D4 of the Schottky barrier diode are configured in that way, such as Figure 10 As shown in F3 and F6, the region where the AC voltages VC1 and VC2 are lower than the rectified voltage VSS can be reduced, thus reducing power loss. This enables efficient rectification operation.

[0057] In addition, Figure 4 , Figure 6 In this configuration, a third Schottky barrier diode, namely diode D3, is used as rectifier element RF3, and a fourth Schottky barrier diode, namely diode D4, is used as rectifier element RF4. By using diodes D3 and D4 as Schottky barrier diodes, compared to using PN junction diodes, the forward voltage VF can be reduced, power loss can be decreased, and thus, efficient rectification operation can be achieved.

[0058] 3. Detailed layout configuration

[0059] Figure 11 , Figure 12 A detailed layout example of the rectifier circuit 10 in this embodiment is shown. Figure 11 , Figure 12 yes Figure 3 More detailed layout configuration examples are provided below. Specifically, Figure 11 , Figure 12 yes Figure 6 The layout configuration example of the rectifier circuit 10 in the third structural example.

[0060] exist Figure 11 , Figure 12 In the rectifier circuit 10, there are: an input line group GI1, in which each input line is arranged along direction DR1; and an input line group GI2, in which each input line is arranged along direction DR1 on the direction DR2 side of the input line group GI1. Furthermore, as... Figure 12 As shown, the rectifier circuit 10 includes: an output line group GQ1, which has output lines arranged along a direction DR2 perpendicular to the direction DR1; and an output line group GQ2, which has output lines arranged along the direction DR2 on the direction DR1 side of the output line group GQ1. Figure 12 It is relative to Figure 11 The layout configuration diagram includes output line groups GQ1 and GQ2.

[0061] In addition, Figure 11 , Figure 12 In the rectifier circuit 10, a first diode group, namely diode group GD1, is provided as... Figure 3 The rectifier element group GRF1 includes a second diode group, namely diode group GD2, as the rectifier element group GRF2. Furthermore, a third diode group, namely diode group GD3, and a fourth diode group, namely diode group GD4, are also included as the rectifier element group GRF4. Diode group GD1 is positioned at the intersection of input line group GI1 and output line group GQ1, diode group GD2 is positioned at the intersection of input line group GI2 and output line group GQ1, diode group GD3 is positioned at the intersection of input line group GI1 and output line group GQ2, and diode group GD4 is positioned at the intersection of input line group GI2 and output line group GQ2. For example, diode group GD1 is positioned at the intersection of input line group GI1 and output line group GQ1, and diode group GD2 is positioned at the intersection of input line group GI2 and output line group GQ1. Furthermore, diode group GD3 is positioned at the intersection of input line group GI1 and output line group GQ2, and diode group GD4 is positioned at the intersection of input line group GI2 and output line group GQ2. Additionally, regarding the number of wires and the number of diodes... Figure 11 , Figure 12This is just an example; in reality, the number of wires and diodes can be further increased.

[0062] Specifically, in Figure 11 , Figure 12 In this diode array, diodes Di, Di+1, and Di+2 are configured as diode group GD1, and diodes Dj, Dj+1, and Dj+2 are configured as diode group GD2. Diodes Di, Di+1, and Di+2 are the i-th, i+1-th, and i+2-th diodes, respectively, and diodes Dj, Dj+1, and Dj+2 are the j-th, j+1-th, and j+2-th diodes, respectively. Furthermore, diodes Dp, Dp+1, and Dp+2 are configured as diode group GD3, and diodes Dq, Dq+1, and Dq+2 are configured as diode group GD4. Diodes Dp, Dp+1, and Dp+2 are the p-th, p+1-th, and p+2-th diodes, respectively, and diodes Dq, Dq+1, and Dq+2 are the q-th, q+1-th, and q+2-th diodes, respectively. Additionally, i, j, p, and q are, for example, different integers greater than or equal to 1.

[0063] Specifically, diode group GD1 includes: diode Di; and diode Di+1, which is adjacent to diode Di in direction DR2. Diode Di, as the i-th diode, and diode Di+1, as the (i+1)-th diode, are arranged, for example, along direction DR2 with direction DR1 as the length direction. In addition, diode group GD1 also includes diode Di+2, which is adjacent to diode Di+1 in direction DR2.

[0064] Furthermore, diode group GD2 includes: diode Dj; and diode Dj+1, which is adjacent to diode Dj in direction DR2. Diode Dj, as the j-th diode, and diode Dj+1, as the (j+1)-th diode, are arranged, for example, along direction DR2 with direction DR1 as the length direction. Additionally, diode group GD2 also includes diode Dj+2, which is adjacent to diode Dj+1 in direction DR2.

[0065] Therefore, diode Di is positioned below the input line corresponding to diode Di in input line group GI1, and diode Di+1 is positioned below the input line corresponding to diode Di+1 in input line group GI1. For example, by positioning diodes Di and Di+1 below each corresponding input line in a manner that follows the length direction of each input line, an AC voltage VC1 can be supplied from each input line. Furthermore, the direction below is from the circuit formation area of ​​the semiconductor substrate toward the semiconductor substrate. Additionally, diode Dj is positioned below the input line corresponding to diode Dj in input line group GI2, and diode Dj+1 is positioned below the input line corresponding to diode Dj+1 in input line group GI2. For example, by positioning diodes Dj and Dj+1 below each corresponding input line in a manner that follows the length direction of each input line, an AC voltage VC2 can be supplied from each input line. Therefore, by efficiently configuring multiple diodes of diode group GD1 in the intersection area of ​​input line group GI1 and output line group GQ1, and by efficiently configuring multiple diodes of diode group GD2 in the intersection area of ​​input line group GI2 and output line group GQ1, the area of ​​the rectifier circuit 10 layout can be reduced. Furthermore, since multiple diodes are connected in parallel between input line group GI1 and output line group GQ1, and multiple diodes are connected in parallel between input line group GI2 and output line group GQ1, the current flowing through the rectifier elements can be increased, thereby achieving efficient rectification operation of the rectifier circuit 10.

[0066] In addition, Figure 11 , Figure 12 In this configuration, a common cathode CCAi, shared by anodes ANi and ANi+1, is disposed between the anodes of diode Di and Di+1. Furthermore, a common cathode CCAi+1, shared by anodes ANi+1 and ANi+2, is disposed between anodes ANi+1 and Di+2. Anodes ANi, ANi+1, and ANi+2 are the i-th, i+1-th, and i+2-th anodes, respectively. Common cathodes CCAi and CCAi+1 are the i-th and i+1-th common cathodes, respectively.

[0067] In addition, Figure 11 , Figure 12In this configuration, a common cathode CCAj shared by anodes ANj and ANj+1 is disposed between the anodes ANj and ANj+1 of diode Dj. Furthermore, a common cathode CCAj+1 shared by anodes ANj+1 and ANj+2 is disposed between anode ANj+1 and the anode ANj+2 of diode Dj+2. Anodes ANj, ANj+1, and ANj+2 are the j-th, j+1-th, and j+2-th anodes, respectively. Common cathodes CCAj and CCAj+1 are the j-th and j+1-th common cathodes, respectively.

[0068] Therefore, among the two anodes arranged along direction DR2, the cathode disposed between the two anodes can be used as a common cathode for the two anodes. Thus, the rectified current of each diode can be maintained and the length of the region of each diode group along direction DR2 can be reduced. Therefore, the efficiency of the rectifier circuit 10 and its area can be reduced simultaneously.

[0069] In addition, Figure 11 , Figure 12 In the rectifier circuit 10, cathode CA1 is positioned to surround the anodes Ani, Ani+1, and Ani+2, respectively, and cathode CA2 is positioned to surround the anodes ANj, ANj+1, and ANj+2, respectively. Thus, current flows from the anodes Ani, Ani+1, and Ani+2 in the up-down and left-right directions to cathode CA1, and current flows from the anodes ANj, ANj+1, and ANj+2 in the up-down and left-right directions to cathode CA2. Therefore, the current flowing from the anodes to the cathodes can be efficiently transmitted, enabling efficient rectification operation of the rectifier circuit 10.

[0070] In addition, Figure 11 , Figure 12 In the rectifier circuit 10, diode group GD3 is provided as rectifier element group GRF3, and diode group GD4 is provided as rectifier element group GRF4. Furthermore, diode group GD3, as the third diode group, includes: diode Dp; and diode Dp+1, which is adjacent to diode Dp in direction DR2. Diode Dp, as the p-th diode, and diode Dp+1, as the (p+1)-th diode, are arranged, for example, along direction DR2 with direction DR1 as the length direction. In addition, diode group GD3 also includes diode Dp+2, which is adjacent to diode Dp+1 in direction DR2.

[0071] Furthermore, diode group GD4 includes: diode Dq; and diode Dq+1, which is adjacent to diode Dq in direction DR2. Diode Dq, as the q-th diode, and diode Dq+1, as the (q+1)-th diode, are arranged, for example, along direction DR2 with direction DR1 as the length direction. Additionally, diode group GD4 also includes diode Dq+2, which is adjacent to diode Dq+1 in direction DR2.

[0072] Therefore, diodes Dp and Dp+1 are placed below each input line corresponding to diodes Dp and Dp+1 in input line group GI1 to supply AC voltage VC1. Similarly, diodes Dq and Dq+1 are placed below each input line corresponding to diodes Dq and Dq+1 in input line group GI2 to supply AC voltage VC2. Thus, multiple diodes of diode group GD3 can be efficiently arranged in the intersection area of ​​input line group GI1 and output line group GQ2, and multiple diodes of diode group GD4 can be efficiently arranged in the intersection area of ​​input line group GI2 and output line group GQ2, enabling a smaller layout area for the rectifier circuit 10. Furthermore, the presence of multiple diodes connected in parallel between input line group GI1 and output line group GQ2, and between input line group GI2 and output line group GQ2, increases the current flowing through the rectifier elements, thereby achieving efficient rectification operation of the rectifier circuit 10.

[0073] In addition, Figure 11 , Figure 12 In this configuration, a common cathode CCAp shared by anodes ANp and ANp+1 is disposed between the anodes ANp and ANp+1 of diode Dp. Furthermore, a common cathode CCAp+1 shared by anodes ANp+1 and ANp+2 is disposed between anode ANp+1 and anode ANp+2 of diode Dp+2. Anodes ANp, ANp+1, and ANp+2 are the p-th, p+1-th, and p+2-th anodes, respectively. Common cathodes CCAp and CCAp+1 are the p-th and p+1-th common cathodes, respectively.

[0074] In addition, Figure 11 , Figure 12In this design, a common cathode CCAq, shared by anodes ANq and ANq+1, is disposed between the anodes ANq and ANq+1 of diode Dq. Furthermore, a common cathode CCAq+1, shared by anodes ANq+1 and ANq+2, is disposed between anode ANq+1 and ANq+2 of diode Dq+2. Anodes ANq, ANq+1, and ANq+2 are respectively the q-th, q+1-th, and q+2-th anodes. The common cathodes CCAq and CCAq+1 are clearly the q-th and q+1-th common cathodes, respectively.

[0075] Therefore, among the two anodes arranged along direction DR2, the cathode arranged between the two anodes can be used as a common cathode for the two anodes. Thus, the efficiency of the rectification operation of the rectifier circuit 10 can be improved and the area reduced at the same time.

[0076] In addition, Figure 11 , Figure 12 In the rectifier circuit 10, a cathode CA3 is positioned to surround the anodes ANp, ANp+1, and ANp+2, respectively. A cathode CA4 is positioned to surround the anodes ANq, ANq+1, and ANq+2, respectively. Thus, current flows from the anodes ANp, ANp+1, and ANp+2 to the cathode CA3 in the up-down and left-right directions, and current flows from the anodes ANq, ANq+1, and ANq+2 to the cathode CA4 in the up-down and left-right directions, respectively. Therefore, the current flowing from the anodes to the cathodes can be efficiently transmitted, enabling efficient rectification operation of the rectifier circuit 10.

[0077] Moreover, in Figure 11 , Figure 12 In the configuration, the anode ANi and the common cathode CCAp are arranged along the direction DR1, and the anode ANj and the common cathode CCAq are arranged along the direction DR1.

[0078] That is, the anodes Ani of diode Di in diode group GD1 and the common cathode CCAp of the anodes ANp of diode Dp and ANp+1 of diode Dp+1 in diode group GD3 are arranged along direction DR1. Similarly, the anodes Ani+1 of diode group GD1 and the common cathode CCAp+1 of diode group GD3 are arranged along direction DR1.

[0079] Furthermore, the anodes ANj of diode Dj in diode group GD3 and the common cathode CCAq of the anodes ANq and ANq+1 of diode Dq in diode group GD4 are arranged along direction DR1. Similarly, the anodes ANj+1 of diode group GD2 and the common cathode CCAq+1 of diode group GD4 are arranged along direction DR1.

[0080] For example, Figure 11 , Figure 12 Anode ANi and Figure 6 The anode of diode D1 corresponds to the common cathode CCAp, which corresponds to the cathode of diode D3. Furthermore, a contact is provided at the position where the anode ANi and the corresponding input line overlap when viewed from above. The anode ANi is connected to the input line via this contact, thus connecting node N1 of AC voltage VC1 to the anode of diode D1, i.e., the anode ANi. Similarly, a contact is provided at the position where the common cathode CCAp overlaps with the input line when viewed from above. The common cathode CCAp is connected to the input line via this contact, thus connecting node N1 of AC voltage VC1 to the common cathode CCAp, which is the cathode of diode D3. Therefore, by arranging the anode ANi and the common cathode CCAp along direction DR1, a connection can be made using the shortest possible path via the input line and the contact. Figure 6 The anode of diode D1 and the cathode of diode D3 are connected. Therefore, parasitic resistance in the connection path can be reduced, and power loss caused by parasitic resistance can be reduced.

[0081] also, Figure 11 , Figure 12 The anode ANj and Figure 6 The anode of diode D2 corresponds to the common cathode CCAq, and the cathode of diode D4 corresponds to the common cathode CCAq. Furthermore, a contact is provided at the position where the anode ANj and the corresponding input line overlap when viewed from above. The anode ANj is connected to the input line via the contact, thereby connecting node N2 of AC voltage VC2 to the anode ANj, which is the anode of diode D2. Similarly, a contact is provided at the position where the common cathode CCAq overlaps with the input line when viewed from above. The common cathode CCAq is connected to the input line via the contact, thereby connecting node N2 of AC voltage VC2 to the common cathode CCAq, which is the cathode of diode D4. Therefore, by arranging the anode ANj and the common cathode CCAq along direction DR1, a connection can be made using the shortest connection path via the input line and the contact. Figure 6 The anode of diode D2 and the cathode of diode D4 are connected. Therefore, parasitic resistance in the connection path can be reduced, and power loss caused by parasitic resistance can be reduced.

[0082] In addition, Figure 11 , Figure 12In this configuration, transistor T1 is arranged on the DR1 side of diode group GD3. For example, transistor T1 is arranged adjacent to the DR1 side of diode group GD3 with its source S, gate G, and drain D arranged along the DR2 direction. Similarly, transistor T2 is arranged on the DR1 side of diode group GD4. For example, transistor T2 is arranged adjacent to the DR1 side of diode group GD4 with its source S, gate G, and drain D arranged along the DR2 direction. Thus, not only diode groups GD1, GD2, GD3, and GD4, but also transistors T1 and T2 can be efficiently configured with a compact layout. Furthermore, the AC voltage VC2 from input line group GI2 is transmitted through… Figure 11 The wiring shown in H1 supplies power to the gate G of transistor T1. Furthermore, the AC voltage VC1 from input line group GI1 is supplied to the gate G of transistor T2 via the wiring shown in H2.

[0083] Furthermore, the layout of the rectifier circuit 10 in this embodiment is not limited to... Figure 11 , Figure 12 It can be modified in various ways. For example, in Figure 4 In the case of the rectifier circuit 10 in the first structural example, it is not necessary Figure 11 , Figure 12 The layout configuration of transistors T1 and T2. Furthermore, in Figure 5 In the case of the rectifier circuit 10 in the second structural example, it is not necessary Figure 11 , Figure 12 The layout configuration of diode groups GD3 and GD4.

[0084] Figure 13 yes Figure 12 The dashed line of the Y-shape shows a cross-sectional view of the rectifier circuit 10. (See figure.) Figure 13 As shown, each input line of input line groups GI1 and GI2 is formed by metal layers ALB and ALC, and each output line of output line groups GQ1 and GQ2 is formed by metal layers ALD and ALE, which are located above metal layers ALB and ALC. Therefore, output line groups GQ1 and GQ2 can be arranged to intersect with input line groups GI1 and GI2 along direction DR1. Furthermore, a metal layer ALA for connecting to diodes, etc., is provided below metal layer ALB. Moreover, metal layers ALA to ALE are formed of metals such as aluminum.

[0085] In addition, Figure 13In this design, a P-type well 20 and an N-type well 22 are formed on a semiconductor substrate, and an N-type well 24 is formed on the N-type well 22. The N-type well 22 is, for example, a high-voltage N-type well with high withstand voltage, and the N-type well 24 is, for example, a low-voltage N-type well with low withstand voltage. Furthermore, the N-type diffusion layer 26 formed on the N-type well 24 serves as the cathode electrode of the Schottky barrier diode. Additionally, a P-type embedding layer 34 is formed on the N-type well 22, a P-type diffusion layer 32 is formed on the P-type embedding layer 34, and a metal layer 30 is formed on the P-type diffusion layer 32. This metal layer 30 serves as the anode electrode of the Schottky barrier diode. For example, cobalt or a cobalt alloy is used as the metal layer 30. Specifically, cobalt silicide is used. However, titanium or a titanium alloy can also be used as the metal layer 30. For example, a Schottky barrier diode is realized by the Schottky barrier generated by the bonding of this metal layer 30 to the N-type well 22. Furthermore, in... Figure 13 In the above, the relationship P+>P>P- holds for impurity concentrations in P-type diodes, and the relationship N+>N>N- holds for impurity concentrations in N-type diodes. Furthermore, the structure of Schottky barrier diodes is not limited to... Figure 13 The structure allows for various modifications. For example, it can also be structured such that multiple P-type diffusion layers and electrodes are arranged in a segmented manner on the N-type well. Furthermore, in this embodiment, Schottky barrier diodes are preferably used as diodes D1 to D4, but modifications using PN junction diodes are also possible. In this case, for example, it is sufficient to form a P-type diffusion layer serving as the anode of the PN junction diode and an N-type diffusion layer serving as the cathode of the PN junction diode on the N-type well. The diffusion layer is an impurity layer.

[0086] Figure 14 These are cross-sectional views of the rectifier circuit 10 in different configurations, and... Figure 13 correspond.

[0087] exist Figure 13 In a diode structure, it is also possible to place it between two N-type wells 24, such as Figure 14 The N-type diffusion region 27 is configured as shown. The N-type diffusion region 27 is a region with increased impurity concentration and is configured to connect two N-type wells 24. The impurity concentration in the N-type diffusion region 27 is higher than the impurity concentration in the N-type well region 22, therefore, the resistance is reduced. In a preferred embodiment, the impurity concentration in the N-type diffusion region 27 is the same as the impurity concentration N+ of the N-type diffusion layer 26. However, this impurity concentration is not limited to this; it is acceptable as long as the impurity concentration is higher than that of the N-type well region 22 of the base (impurity concentration N-).

[0088] Figure 15 This is a graph showing the relationship between the diode's forward voltage VF and current ID1. Figure 8 correspond.

[0089] According to the settings Figure 14The diode structure of the N-type diffusion region 27, and Figure 13 Compared to the previous structure, the connection resistance between the two N-type wells 24 is reduced, thus lowering the forward voltage VF. Specifically, as... Figure 15 As shown, it can be set as a ratio representation. Figure 13 The forward voltage VF of the diode is lower than the voltage B1 by B5. Furthermore, it can be set to be lower than the voltage B5 indicated by... Figure 13 The reverse current ID1 of the diode is lower than the current B3 and the current B6. That is, according to Figure 14 The diode structure can further reduce power loss.

[0090] 4. Power receiving control device

[0091] Figure 16 An example of the structure of the power receiving control device 40 in this embodiment is shown. For example... Figure 16 As shown, the power receiving control device 40 of this embodiment includes: a power receiving circuit 50, which includes the rectifier circuit 10 of this embodiment; and a power supply circuit 60, which supplies power according to the power received by the power receiving circuit 50. For example, the power receiving circuit 50 rectifies the AC voltage from the AC power source 12 through the rectifier circuit 10, thereby generating rectified voltages VCC and VSS, and supplies the power received based on the rectified voltages VCC and VSS as power to the power supply circuit 60. The power supply circuit 60 supplies power to the load 14 according to the power received by the power receiving circuit 50. The AC power source 12 may be, for example, an AC power source, or an AC power source with a secondary coil for contactless power transmission.

[0092] Figure 17 Another structural example of the power receiving control device 40 of this embodiment is shown. Figure 17 In this system, the power receiving control device 40 receives power through contactless power transmission. Specifically, the power receiving circuit 50 of the power receiving control device 40 receives power from the power transmitting device 70 without contact. That is, it receives power wirelessly. For example, a primary coil L1 is provided on the power transmitting device 70 side, and a secondary coil L2 is provided on the power receiving control device 40 side. Moreover, the power transmission driver of the power transmitting device 70 applies an AC voltage to the primary coil L1, thereby transmitting power from the primary coil L1 to the secondary coil L2. The power receiving circuit 50 receives power from the power transmitting device 70. Specifically, the power receiving circuit 50 converts the AC induced voltage of the secondary coil L2 into a DC rectified voltage VCC through the rectifier circuit 10. The power supply circuit 60 charges the battery 15, which serves as a load 14, according to the power received voltage based on the rectified voltage VCC.

[0093] Furthermore, the power receiving control device 40 of this embodiment can be assembled into an electronic device. Examples of electronic devices incorporating the power receiving control device 40 include, for example, earphones or wearable devices, but this embodiment is not limited to these. For example, various devices such as head-mounted displays, smartphones, mobile phones and other portable communication terminals, watches, biometric measurement devices, shavers, electric toothbrushes, wrist computers, handheld terminals, or in-vehicle systems in automobiles can be envisioned as electronic devices.

[0094] As explained above, the rectifier circuit of this embodiment receives a first AC voltage and a second AC voltage that is inversely phase to the first AC voltage, and outputs a first rectified voltage on the high-potential side and a second rectified voltage on the low-potential side. The rectifier circuit includes: a first input line supplied with the first AC voltage, routed along a first direction; and a second input line supplied with the second AC voltage, routed along the first direction on the second direction side of the first input line when the direction perpendicular to the first direction is defined as the second direction. Furthermore, the rectifier circuit includes: a first output line, which is the output line of the first rectified voltage, routed along the second direction; and a second output line, which is the output line of the second rectified voltage, routed along the second direction on the first direction side of the first output line. The rectifier circuit includes: a first rectifier element, which, when viewed from above, is configured corresponding to the intersection of the first input line and the first output line, and connected between the first input line and the first output line; a second rectifier element, which, when viewed from above, is configured corresponding to the intersection of the second input line and the first output line, and connected between the second input line and the first output line. The rectifier circuit also includes: a third rectifier element, which, when viewed from above, is configured corresponding to the intersection of the first input line and the second output line, and connected between the first input line and the second output line; and a fourth rectifier element, which, when viewed from above, is configured corresponding to the intersection of the second input line and the second output line, and connected between the second input line and the second output line.

[0095] According to this embodiment, a first input line for a first AC voltage and a second input line for a second AC voltage are arranged along a first direction, and a first output line for a first rectified voltage and a second output line for a second rectified voltage are arranged along a second direction perpendicular to the first direction. Furthermore, the first and second rectified elements are positioned at the intersections of the first and second input lines with the first output line, and the third and fourth rectified elements are positioned at the intersections of the first and second input lines with the second output line. This reduces parasitic resistance between each rectified element and each input and output line, thereby reducing power loss in the rectifier circuit. In addition, it enables efficient layout and arrangement of rectified elements, efficient layout and wiring of input and output lines, and minimizes the area of ​​the rectifier circuit layout.

[0096] Furthermore, this embodiment may also include: a first input line group comprising a first input line; a second input line group comprising a second input line; a first output line group comprising a first output line; and a second output line group comprising a second output line. Each input line of the first input line group is routed along a first direction, each input line of the second input line group is routed along the first direction on the second direction side of the first input line group, each output line of the first output line group is routed along the second direction, and each output line of the second output line group is routed along the second direction on the first direction side of the first output line group.

[0097] Therefore, the first AC voltage and the second AC voltage can be input to the rectifier circuit through multiple input lines of the first input line group and the second input line group, and the first rectified voltage and the second rectified voltage can be output from the rectifier circuit through multiple output lines of the first output line group and the second output line group. This, for example, can reduce power loss due to the reduction of parasitic resistance.

[0098] Alternatively, in this embodiment, it may include: a first rectifier element group containing a first rectifier element; and a second rectifier element group containing a second rectifier element. The first rectifier element group is configured at the intersection of the first input line group and the first output line group, and the second rectifier element group is configured at the intersection of the second input line group and the first output line group.

[0099] Thus, for example, rectification of the rectifier circuit can be performed using a first rectifier element group containing multiple rectifier elements and a second rectifier element group containing multiple rectifier elements, thereby further reducing the power loss of the rectifier circuit and achieving efficient rectification operation.

[0100] In addition, in this embodiment, a first diode group may be provided as a first rectifier element group, and a second diode group may be provided as a second rectifier element group. The first diode group includes: an i-th diode; and an i+1-th diode, which is adjacent to the i-th diode in the second direction. The second diode group includes: a j-th diode; and a j+1-th diode, which is adjacent to the j-th diode in the second direction.

[0101] Therefore, diodes of the i-th diode and the (i+1)-th diode can be configured at the positions of corresponding input lines in the first input line group, and diodes of the j-th diode and the (j+1)-th diode can be configured at the positions of corresponding input lines in the second input line group. Consequently, multiple diodes of the first diode group can be efficiently configured at the intersections of the first input line group and the first output line group, and multiple diodes of the second diode group can be efficiently configured at the intersections of the second input line group and the first output line group.

[0102] In addition, in this embodiment, a common cathode shared by the i-th anode and the i+1-th anode of the i-th diode may be disposed between the i-th anode and the i+1-th anode of the i-th diode, and a common cathode shared by the j-th anode and the j+1-th anode of the j-th diode may be disposed between the j-th anode and the j+1-th anode of the j-th diode.

[0103] Therefore, in the two anodes arranged along the second direction, the cathode arranged between the two anodes can be used as a common cathode for the two anodes.

[0104] In addition, in this embodiment, a third diode group may be provided as a third rectifier element group, and a fourth diode group may be provided as a fourth rectifier element group. The third diode group includes: a p-th diode; and a p+1-th diode, which is adjacent to the p-th diode in the second direction. The fourth diode group includes: a q-th diode; and a q+1-th diode, which is adjacent to the q-th diode in the second direction.

[0105] Therefore, diodes of the p-th diode and the (p+1)-th diode can be configured at the positions of the corresponding input lines of the first input line group, and diodes of the q-th diode and the (q+1)-th diode can be configured at the positions of the corresponding input lines of the second input line group. Consequently, multiple diodes of the third diode group can be efficiently configured at the intersection of the first input line group and the second output line group, and multiple diodes of the fourth diode group can be efficiently configured at the intersection of the second input line group and the second output line group.

[0106] Furthermore, in this embodiment, a common cathode shared by the p-th anode and the p+1-th anode of the p-th diode may be disposed between the p-th anode and the p+1-th anode of the p-th diode, and a common cathode shared by the q-th anode and the q+1-th anode of the q-th diode may be disposed between the q-th anode and the q+1-th anode of the q-th diode. The i-th anode and the p-th common cathode are arranged along the first direction, and the j-th anode and the q-th common cathode are arranged along the first direction.

[0107] Therefore, among the two anodes arranged along the second direction, the cathode disposed between the two anodes can be used as a common cathode for the two anodes. Furthermore, in this embodiment, the i-th anode and the p-th common cathode are arranged along the first direction, and the j-th anode and the q-th common cathode are also arranged along the first direction. Thus, the anode of the i-th diode and the cathode of the p-th diode can be connected via the shortest possible signal line, and the anode of the j-th diode and the cathode of the q-th diode can be connected via the shortest possible signal line.

[0108] In addition, in this embodiment, a first diode may be provided as a first rectifier element, and a second diode may be provided as a second rectifier element.

[0109] Therefore, compared with the case where transistors are used as the first rectifier element and the second rectifier element, the rectifier circuit can operate at high speed. For example, when the frequency of the first AC voltage and the second AC voltage is high, the first AC voltage and the second AC voltage can be rectified appropriately to output the first rectified voltage and the second rectified voltage.

[0110] Alternatively, in this embodiment, the first diode may be a first Schottky barrier diode, and the second diode may be a second Schottky barrier diode.

[0111] Using Schottky barrier diodes in this way reduces the forward voltage compared to using PN junction diodes, thereby reducing power loss and improving the power receiving efficiency of the rectifier circuit.

[0112] In addition, in this embodiment, a first transistor with its gate connected to the second input line may be provided as a third rectifier element, and a second transistor with its gate connected to the first input line may be provided as a fourth rectifier element.

[0113] Therefore, by inputting a second AC voltage from the second input line to the gate of the first transistor, the first transistor is turned on and off, thereby enabling the first transistor to operate as a third rectifier element. Furthermore, by inputting a first AC voltage from the first input line to the gate of the second transistor, the second transistor is turned on and off, thereby enabling the second transistor to operate as a fourth rectifier element.

[0114] In addition, in this embodiment, a third Schottky barrier diode connected in parallel with the first transistor may also be provided as a third rectifier element, and a fourth Schottky barrier diode connected in parallel with the second transistor may also be provided as a fourth rectifier element.

[0115] Therefore, compared with the structure without the third and fourth Schottky barrier diodes, power loss can be reduced.

[0116] Alternatively, in this embodiment, a third Schottky barrier diode may be provided as a third rectifier element, and a fourth Schottky barrier diode may be provided as a fourth rectifier element.

[0117] By using Schottky barrier diodes in this way, the forward voltage can be reduced, thus reducing power loss compared to using PN junction diodes.

[0118] Furthermore, this embodiment relates to a power receiving control device, which includes: a power receiving circuit including the aforementioned rectifier circuit; and a power supply circuit that supplies power according to the power received by the power receiving circuit.

[0119] Furthermore, although this embodiment has been described in detail above, those skilled in the art should readily understand that various modifications can be made without substantially departing from the invention and its effects. Therefore, all such modifications are included within the scope of this invention. For example, a term described at least once in the specification or drawings, along with a broader or synonymous term, can be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this invention. Moreover, the structure and operation of the rectifier circuit, the power-controlled device, etc., are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A rectifier circuit which is inputted with a first alternating voltage and a second alternating voltage which is opposite to the first alternating voltage, and outputs a first rectified voltage on a high potential side and a second rectified voltage on a low potential side, characterized in that, The rectifier circuit includes: a first input line to which the first AC voltage is supplied and which is routed in a first direction; a second input line to which the second AC voltage is supplied and which is routed in the first direction on a second direction side of the first input line, the second direction being perpendicular to the first direction; a first output line which is an output line of the first rectified voltage and which is routed in the second direction; a second output line which is an output line of the second rectified voltage and which is routed in the second direction on a first direction side of the first output line; a first rectifying element which is disposed at a crossing of the first input line and the first output line when viewed in plan and which is connected between the first input line and the first output line; a second rectifying element which is disposed at a crossing of the second input line and the first output line when viewed in plan and which is connected between the second input line and the first output line; a third rectifying element which is disposed at a crossing of the first input line and the second output line when viewed in plan and which is connected between the first input line and the second output line; a fourth rectifying element which is disposed at a crossing of the second input line and the second output line when viewed in plan and which is connected between the second input line and the second output line; a first input line group including the first input line; a second input line group including the second input line; a first output line group including the first output line; and a second output line group including the second output line; each input line of the first input line group is routed in the first direction, each input line of the second input line group is routed in the first direction on the second direction side of the first input line group, each output line of the first output line group is routed in the second direction, and each output line of the second output line group is routed in the second direction on the first direction side of the first output line group; the rectifier circuit includes: a first rectifying element group including the first rectifying element; and a second rectifying element group including the second rectifying element, the first rectifying element group is disposed at crossings of the first input line group and the first output line group, and the second rectifying element group is disposed at crossings of the second input line group and the first output line group; a first diode group is provided as the first rectifying element group in the rectifier circuit, a second diode group is provided as the second rectifying element group in the rectifier circuit, the first diode group includes: a first diode; and a second diode adjacent to the first diode in the second direction, and the second diode group includes: a third diode; and a fourth diode adjacent to the third diode in the second direction. ​ 2. The rectifier circuit of claim 1, wherein A first common cathode shared by cathodes of the first diode and the second diode is arranged between an anode of the first diode and an anode of the second diode, and a second common cathode shared by cathodes of the third diode and the fourth diode is arranged between an anode of the third diode and an anode of the fourth diode.

3. The rectifier circuit of claim 2, wherein The rectifier circuit includes a third rectifying element group including the third rectifying element, and a fourth rectifying element group including the fourth rectifying element, a third diode group including a fifth diode and a sixth diode adjacent to the fifth diode in the second direction is provided as the third rectifying element group in the rectifier circuit, and a fourth diode group including a seventh diode and an eighth diode adjacent to the seventh diode in the second direction is provided as the fourth rectifying element group in the rectifier circuit.

4. The rectifier circuit of claim 3, wherein A third common cathode shared by cathodes of the fifth diode and the sixth diode is arranged between an anode of the fifth diode and an anode of the sixth diode, and a fourth common cathode shared by cathodes of the seventh diode and the eighth diode is arranged between an anode of the seventh diode and an anode of the eighth diode, the anode of the first diode and the third common cathode are arranged in the first direction, and the anode of the second diode and the fourth common cathode are arranged in the first direction.

5. The rectifier circuit of claim 1, wherein The first diode, the second diode, the third diode, and the fourth diode are first Schottky barrier diodes.

6. The rectifier circuit of claim 5, wherein A first transistor having a gate connected to the second input line is provided as the third rectifying element in the rectifier circuit, and a second transistor having a gate connected to the first input line is provided as the fourth rectifying element in the rectifier circuit.

7. The rectifier circuit of claim 6, wherein A Schottky barrier diode connected in parallel to the first transistor is further provided as the third rectifying element in the rectifier circuit, and a Schottky barrier diode connected in parallel to the second transistor is further provided as the fourth rectifying element in the rectifier circuit.

8. The rectifier circuit of claim 1, wherein The third rectifying element and the fourth rectifying element are Schottky barrier diodes.

9. A power reception control device characterized by comprising: It includes a power receiving circuit including the rectifier circuit according to any one of claims 1 to 8, and a power supply circuit that supplies power in accordance with power received by the power receiving circuit.

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