Clock calibration device, equipment and method

Abstract

The present invention provides a clock calibration device, equipment and method. The clock calibration device is applied to a clock circuit, the clock circuit is used to provide a clock signal, the clock calibration device includes a receiving module and a calibration module, the receiving module is used to receive calibration data, the calibration data includes at least one of the number of added pulses and the number of subtracted pulses, and calibration cycle information; the calibration module is connected to the receiving module and is used to connect to the clock circuit, the calibration module is used to perform pulse calibration on the clock signal within the calibration cycle according to the clock signal and the calibration data, so that the frequency of the calibrated clock signal reaches the nominal frequency, wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses, so that the clock calibration device can realize the increase and decrease of the clock signal pulses, thereby achieving the purpose of increasing and decreasing the clock signal frequency.

Description

Technical Field

[0001] The present application relates to the technical field of clock circuits, and in particular to a clock calibration device, equipment and method. Background Art

[0002] In order to ensure the normal operation of electronic equipment, it is often necessary to set up a clock circuit inside to provide a clock signal.

[0003] A crystal oscillator or an oscillator is usually set in the clock circuit. Due to its working characteristics, the actual frequency of the output clock signal has some deviation from the nominal frequency, so it needs to be calibrated. The existing calibration technology can only achieve unidirectional frequency calibration, for example, it can only increase or decrease the frequency, but cannot achieve bidirectional calibration. Summary of the invention

[0004] The present application provides a clock calibration device, equipment and method capable of implementing bidirectional calibration.

[0005] A clock calibration device is applied to a clock circuit, wherein the clock circuit is used to provide a clock signal, and the clock calibration device comprises:

[0006] A receiving module, configured to receive calibration data, wherein the calibration data includes at least one of the number of plus pulses and the number of minus pulses, and calibration cycle information;

[0007] a calibration module connected to the receiving module and used to be connected to the clock circuit, the calibration module being used to perform pulse calibration on the clock signal within a calibration period according to the clock signal and the calibration data so that the frequency of the calibrated clock signal reaches the nominal frequency;

[0008] The number of added pulses is used to indicate the number of increased pulses, and the number of reduced pulses is used to indicate the number of reduced pulses.

[0009] In one embodiment, the calibration module comprises:

[0010] A generating control unit connected to the receiving module, configured to generate a pulse-adding enable signal according to the calibration cycle information and the number of pulse-adding, and to generate a pulse-subtracting enable signal according to the calibration cycle information and the number of pulse-subtracting;

[0011] A pulse compensation unit is connected to the generation control unit and is used to connect to the clock circuit, and is used to increase the pulse of the clock signal within the calibration period according to the clock signal and the pulse increase enable signal; and to reduce the pulse of the clock signal within the calibration period according to the clock signal and the pulse reduction enable signal.

[0012] In one embodiment, the calibration period is characterized by 2 n The number of pulses is expressed as:

[0013]

[0014] Wherein, D is the number of pulses, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n;

[0015] The generation control unit is also used for:

[0016] If D j The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. j the first triggering moment, the front splitting point is a splitting point set before the front wheel is split;

[0017] At each of the first trigger moments, a pulse with a width equal to one clock cycle of the clock signal is generated to obtain the pulse reduction enable signal.

[0018] In one embodiment, the calibration period is characterized by 2 n The number of pulses is represented by:

[0019]

[0020] Wherein, A is the number of pulses added, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n;

[0021] The generation control unit is also used for:

[0022] If A i The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. i the second triggering moment, the front splitting point is a splitting point set before the front wheel is split;

[0023] Based on each of the second trigger moments, a pulse with a width of one clock cycle of the clock signal is generated to obtain the pulse enable signal.

[0024] In one embodiment, the generation control unit is further configured to:

[0025] At each of the second trigger moments, a pulse having a width of one clock cycle of the clock signal is generated by delaying the preset time length to obtain the pulse enable signal; wherein the preset time length is an integer multiple of the clock cycle.

[0026] In one embodiment, the pulse compensation unit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first trigger, a second trigger, a third trigger, an AND gate, a NAND gate, an OR gate, a buffer circuit and a two-way selector;

[0027] Wherein, the input end of the first NOT gate is connected to the generation control unit, and the input end of the second NOT gate is connected to the clock circuit;

[0028] The input terminal of the first trigger is connected to the output terminal of the first NOT gate, the clock terminal of the first trigger is connected to the output terminal of the second NOT gate, and the output terminal of the first trigger is connected to the first input terminal of the AND gate;

[0029] The second input terminal of the AND gate is connected to the clock circuit, and the output terminal of the AND gate is connected to the first input terminal of the two-way selector;

[0030] The input end of the second trigger is connected to the generation control unit, and the output end of the second trigger is respectively connected to the input end of the third trigger and the first input end of the NAND gate;

[0031] The input end of the third NOT gate and the clock end of the third flip-flop are respectively connected to the clock circuit, and the output end of the third NOT gate is respectively connected to the first input end of the OR gate and the clock end of the second flip-flop;

[0032] The output end of the third trigger is connected to the second input end of the NAND gate, and the output end of the NAND gate is connected to the second input end of the OR gate and the input end of the buffer circuit respectively;

[0033] The output end of the buffer circuit is connected to the control end of the two-way selector, and the output end of the OR gate is connected to the second input end of the two-way selector.

[0034] In one embodiment, the buffer circuit includes a plurality of buffers connected in series.

[0035] In one of the embodiments, the generation control unit is further used to control the receiving module to stop receiving the next set of calibration data after the receiving module receives a set of calibration data until the pulse compensation unit completes the pulse increase or decrease action.

[0036] A clock calibration device, comprising:

[0037] Clock circuit;

[0038] And a clock calibration device as described in any of the above items.

[0039] In one embodiment, the clock calibration device further includes:

[0040] The terminal is connected to the receiving module and is used to obtain the number of added pulses and the number of subtracted pulses according to the calibration cycle information, the frequency of the clock signal and the nominal frequency, and send them to the receiving module.

[0041] A clock calibration method is applied to a clock circuit, wherein the clock circuit is used to provide a clock signal, and the clock calibration method comprises:

[0042] receiving calibration data, wherein the calibration data includes at least one of the number of up pulses and the number of down pulses, and calibration cycle information;

[0043] Performing pulse calibration on the clock signal within a calibration period according to the clock signal and the calibration data, so that the frequency of the calibrated clock signal reaches the nominal frequency;

[0044] The number of added pulses is used to indicate the number of increased pulses, and the number of reduced pulses is used to indicate the number of reduced pulses.

[0045] The above-mentioned clock calibration device is applied to a clock circuit, and the clock circuit is used to provide a clock signal. The clock calibration device includes a receiving module and a calibration module. The receiving module is used to receive calibration data, and the calibration data includes at least one of the number of added pulses and the number of subtracted pulses, as well as calibration cycle information; the calibration module is connected to the receiving module and is used to connect to the clock circuit. The calibration module is used to perform pulse calibration on the clock signal within the calibration cycle according to the clock signal and the calibration data, so that the frequency of the calibrated clock signal reaches the nominal frequency, wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses. In this way, the clock calibration device can realize the increase and decrease of the clock signal pulses, thereby achieving the purpose of increasing and reducing the clock signal frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a structural block diagram of a clock calibration device according to an embodiment of the present application;

[0047] Figure 2 This is a structural block diagram of a clock calibration device according to another embodiment of the present application;

[0048] Figure 3 This is a circuit structure diagram of a pulse compensation unit according to an embodiment of the present application;

[0049] Figure 4A waveform diagram of each signal according to an embodiment of the present application;

[0050] Figure 5 This is a flow chart of a clock calibration method according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0054] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0055] Figure 1 1 is a block diagram of a clock calibration device according to an embodiment of the present invention. The clock calibration device is applied to a clock circuit 100. The clock circuit 100 is used to provide a clock signal, such as Figure 1As shown, the clock calibration device includes a receiving module 101 and a calibration module 102, the receiving module 101 is used to receive calibration data, the calibration data includes at least one of the number of added pulses and the number of subtracted pulses, and calibration cycle information; the calibration module 102 is connected to the receiving module 101, and is used to connect to the clock circuit 100, the calibration module 102 is used to perform pulse calibration on the clock signal within the calibration cycle according to the clock signal and the calibration data, so that the frequency of the calibrated clock signal reaches the nominal frequency; wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses.

[0056] The calibration data may include the number of pulses added and calibration cycle information, the number of pulses subtracted and calibration cycle information, or the number of pulses added, the number of pulses subtracted and calibration cycle information. The calibration cycle information, the number of pulses added and the number of pulses subtracted may be preset information, which may be sent to the receiving module 101 through an external terminal. The receiving module 101 may include a configuration interface, so that the terminal may be connected via a wire to receive the calibration cycle information, the number of pulses added and the number of pulses subtracted sent by the terminal; the receiving module 101 may also include a wireless transmission component, so that the calibration cycle information, the number of pulses added and the number of pulses subtracted may be received via a wireless connection to the terminal.

[0057] It can be understood that the calibration period information is used to characterize the calibration period, that is, the duration required for pulse calibration. The calibration period can be an integer multiple of the clock period of the clock signal, that is, when performing pulse calibration, pulse calibration is performed on the clock signal within each integer multiple of the clock period.

[0058] In one embodiment, when performing pulse calibration, since the number of added pulses and the number of subtracted pulses are known, pulse increase and decrease operations can be performed in the clock signal within the current calibration cycle; in another embodiment, a clock signal with a specific number of pulses can be regenerated within the current calibration cycle based on the number of added pulses and the number of subtracted pulses to replace the original clock signal, and finally a clock signal with a nominal frequency is obtained.

[0059] The clock calibration device of the above-mentioned embodiment is applied to a clock circuit, and receives calibration data through a receiving module, the calibration data including at least one of the number of added pulses and the number of subtracted pulses, and calibration cycle information. Then, the calibration module performs pulse calibration on the clock signal within the calibration cycle according to the clock signal and the calibration data, so that the frequency of the calibrated clock signal reaches the nominal frequency, wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses. In this way, the clock calibration device can realize the increase and decrease of the clock signal pulses, thereby achieving the purpose of increasing and decreasing the clock signal frequency.

[0060] In one embodiment, the calibration module 102 includes a generation control unit 1021 and a pulse compensation unit 1022. The generation control unit 1021 is connected to the receiving module 101, and is used to generate a pulse-adding enable signal according to the calibration cycle information and the number of pulse-adding, and to generate a pulse-reducing enable signal according to the calibration cycle information and the number of pulse-reducing; the pulse compensation unit 1022 is connected to the generation control unit 1021, and is used to connect to the clock circuit 100, and is used to increase the pulse of the clock signal within the calibration cycle according to the clock signal and the pulse-adding enable signal; and to reduce the pulse of the clock signal within the calibration cycle according to the clock signal and the pulse-reducing enable signal.

[0061] Among them, the generation control unit 1021 may be provided with a signal generator to generate an enable signal. The pulse-adding enable signal generated according to the calibration cycle information and the number of pulses added may carry the time information and quantity information of the added pulses, which may be used to indicate that a preset number of pulses are added at a preset time within the calibration cycle of the clock signal. Similarly, the pulse-reducing enable signal generated according to the calibration cycle information and the number of pulses reduced may carry the time information and quantity information of the reduced pulses, which may be used to indicate that a preset number of pulses are reduced at a preset time within the calibration cycle of the clock signal.

[0062] It can be understood that the number of added pulses and the number of subtracted pulses can be greater than or equal to 0 respectively. When the number of added pulses and the number of subtracted pulses are both 0, the generated added pulse enable signal and subtracted pulse enable signal indicate that the number of increased and decreased pulses is 0. At this time, the pulse compensation unit 1022 does not perform increase or decrease pulse operations on the clock signal; when the number of added pulses is 0 and the number of subtracted pulses is not 0, the number of increased pulses indicated by the added pulse enable signal is 0, while the number of reduced pulses indicated by the subtracted pulse enable signal is not 0. At this time, combined with the clock signal, the pulse compensation unit 1022 only performs a subtracted pulse operation on the clock signal; when the number of added pulses is not 0 and the number of subtracted pulses is 0, the number of increased pulses indicated by the added pulse enable signal is not 0, while the number of reduced pulses indicated by the subtracted pulse enable signal is 0. At this time, combined with the clock signal, the pulse compensation unit 1022 only performs a added pulse operation on the clock signal.

[0063] This embodiment generates corresponding enable signals by increasing the number of pulses and decreasing the number of pulses, and then combines the clock signal to increase or decrease the pulses of the clock signal within the calibration period. The method is simple, does not require the regeneration of a new clock signal, has low performance requirements for the device, and simplifies the device structure.

[0064] In one embodiment, the calibration period is characterized by 2 n The clock cycle of a clock signal, the number of pulses is represented by:

[0065]

[0066] Where D is the number of pulses, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n;

[0067] The generation control unit 1021 is further configured to: j If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. j A first trigger moment, the front segmentation point is a segmentation point set before the current round of segmentation; then a pulse with a width of a clock cycle of a clock signal is generated at each first trigger moment to obtain a pulse reduction enable signal.

[0068] It can be understood that when the calibration period is preset, the calibration period should satisfy the value of the clock period of the clock signal whose value is equal to the exponential power of 2. The number of subtraction pulses is an integer, which can be represented as the sum of multiple different exponential powers of 2. When generating the subtraction pulse enable signal, for any exponential power of 2, at least one round of segmentation can be performed, wherein in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point dividing the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until the first trigger moment equal to the exponential power of 2 is obtained, and then a pulse with a width of one clock period of the clock signal is generated at each first trigger moment. For example, if the calibration period is 2 5 =32, D is equal to 12, that is, D is represented as equal to 2 2 and 2 3 The sum of, on the one hand, for 2 2 =4, that is, 4 segmentation points are to be obtained as the first triggering moment; at least one round of segmentation is performed, wherein in the first round of segmentation, since there is only one interval of the calibration period at this time, the number of segmentation points set in this round of segmentation is 1, which is located at the 16th clock cycle. Since the number of segmentation points in this round does not reach 4, the segmentation is continued; in the second round of segmentation, since there are two intervals of the 0th to 16th clock cycle and the 16th to 32nd clock cycle after the first round of segmentation, the number of segmentation points set in this round of segmentation is 2, which are located at the 8th clock cycle and the 16th to 32nd clock cycle, respectively. The first and second rounds of segmentation have four intervals, namely the 0th to 8th clock cycle, the 8th to 16th clock cycle, the 16th to 24th clock cycle, and the 24th to 32nd clock cycle. Therefore, the number of segmentation points set for this round of segmentation is 4, which are located at the 4th, 12th, 20th, and 28th clock cycles respectively. At this time, the 4 first triggering moments are the 4th, 12th, 20th, and 28th clock cycles respectively. 2 The segmentation is completed; on the other hand, for 2 3=8, that is, to obtain 8 segmentation points as the first triggering moment, the above segmentation steps are also performed. It can be seen from the above that the third round of segmentation only obtains 4 first triggering moments, which does not reach 8, so the fourth round of segmentation is continued on this basis. When performing the fourth round of segmentation, since there are eight intervals of the 0th to 4th clock cycle, the 4th to 8th clock cycle, the 8th to 12th clock cycle, the 12th to 16th clock cycle, the 16th to 20th clock cycle, the 20th to 24th clock cycle, the 24th to 28th clock cycle, and the 28th to 32nd clock cycle after the first, second, and third rounds of segmentation, the number of segmentation points set in this round of segmentation is 8, which are located at the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, and 30th clock cycles respectively. At this time, the 8 first triggering moments are the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, and 30th clock cycles respectively. So far, for 2 3 After obtaining the first triggering moment, a pulse is generated at each first triggering moment, thereby obtaining a pulse reduction enable signal.

[0069] In one embodiment, the clock cycle can be counted by a counter to determine the first triggering moment. The counter can use a binary counting method to start counting from 0. For example, assuming n=20, p=8, that is, the calibration cycle is 2 20 , The corresponding relationship between the valid bit DEL[j] of DEL[8:0] and the clock cycle count of the clock signal can be shown in Table 1.

[0070] Table 1

[0071] Clock cycle count DEL[j] Number of generated pulses 1000_0000_0000_0000_0000 DEL[0] 1 ？100_0000_0000_0000_0000 DEL[1] 2 ？？10_0000_0000_0000_0000 DEL[2] 4 ？？？1_0000_0000_0000_0000 DEL[3] 8 ？？？？_1000_0000_0000_0000 DEL[4] 16 ？？？？_？100_0000_0000_0000 DEL[5] 32 ？？？？_？？10_0000_0000_0000 DEL[6] 64 ？？？？_？？？1_0000_0000_0000 DEL[7] 128 ？？？？_？？？？_1000_0000_0000 DEL[8] 256

[0072] Among them, the symbol "?" is "0" or "1", indicating that a pulse will be generated regardless of whether the bit is "0" or "1".

[0073] The number of subtraction pulses is represented as the sum of multiple different exponential powers of 2, and then at least one round of segmentation is performed for any exponential power of 2, wherein in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point dividing the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until the first trigger moments equal to the exponential power of 2 are obtained, and then pulses with a width of a clock period of a clock signal are generated at the first trigger moments corresponding to each exponential power of 2, so that the pulse uniformity of the subtraction pulse enable signal can be achieved, and then the pulses in the clock signal can be uniformly erased, so that the pulses of the calibrated clock signal are uniform.

[0074] In one embodiment, the calibration period is characterized by 2 n The clock cycle of a clock signal plus the number of pulses is represented by:

[0075]

[0076] Among them, A is the number of pulses added, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n; the generation control unit 1021 is also used for: if A i If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. i second triggering moments, the former segmentation point is the segmentation point set before the current round of segmentation; then based on each second triggering moment, a pulse with a width of one clock cycle of the clock signal is generated to obtain a pulse-adding enable signal. It can be understood that when the calibration period is preset, the calibration period should satisfy the value of the clock cycle of the clock signal whose value is equal to the exponential power of 2. The number of pulses added is an integer, which can be characterized as the sum of multiple different exponential powers of 2. When generating the pulse-adding enable signal, for any exponential power of 2, at least one round of segmentation can be performed, wherein in each round of segmentation, a segmentation point is set to divide the interval formed by the former segmentation point on the calibration period into two, and the moment at which the segmentation point is located is used as the second triggering moment until a second triggering moment equal to the exponential power of 2 is obtained. Among them, the specific segmentation action performed in the process of generating the pulse-adding enable signal can refer to the segmentation action performed on the generation of the pulse-subtracting enable signal in the above embodiment, which will not be repeated here.

[0077] Then, a pulse with a width of one clock cycle of the clock signal is generated based on each second trigger moment. In this way, the pulse uniformity of the pulse enable signal can be achieved, and then the pulses in the clock signal can be uniformly increased, so that the pulses of the calibrated clock signal are uniform. Among them, the second trigger moment can be used to stimulate the pulse to be generated immediately at the current moment, that is, the pulse is generated at the second trigger moment; in addition, the second trigger moment can also be used to stimulate the pulse to be generated at a specific moment, that is, the pulse is not generated at the second trigger moment.

[0078] In one embodiment, each second triggering moment may be delayed by a preset time length to generate a pulse with a width of one clock cycle of the clock signal, thereby obtaining a pulse enable signal; wherein the preset time length is an integer multiple of the clock cycle.

[0079] It can be understood that after performing at least one round of segmentation for any exponential power of 2 to obtain a number of second trigger moments equal to each exponential power of 2, a pulse can be generated after a delay of a preset time length based on each second trigger moment, so that the pulse uniformity of the pulse enable signal can still be achieved.

[0080] In one embodiment, both the pulse add enable signal and the pulse subtraction enable signal can be obtained by obtaining a number of trigger moments equal to the exponential power of each 2, and then based on the pulses generated at the trigger moments, wherein the pulse add enable signal can be obtained by generating a pulse at the second trigger moment, or by generating a pulse after delaying the second trigger moment for a preset time period. Among them, for the method of generating a pulse after delaying the second trigger moment for a preset time period to obtain the pulse add enable signal, the pulse add enable signal can be offset by a preset time period, thereby avoiding conflicts in the increase and decrease moments of the pulses due to the same number of pulses added and pulses subtracted.

[0081] The preset time length is an integer multiple of the clock cycle, for example, it can be 1 clock cycle, or 2 clock cycles. The specific value of the preset time length can be determined according to the calibration cycle, the number of added pulses and the number of subtracted pulses.

[0082] In summary, through the above increase and decrease actions, in 2 n Within the clock cycle of a clock signal, a maximum of 2 0 +2 1 +2 2 +……+2 m =2 m+1 -1 pulse, similarly, up to 2 p+1 -1 pulse, the calibration range of the system is (-2 p+1 -1, 2 m+1 -1) clock cycles, the calibration resolution is 1 / 2 n The clock signal is calibrated directly according to the number of added pulses and the number of subtracted pulses, and there is no need to sample the clock signal. The method is simple to implement, thereby simplifying the system structure.

[0083] In one embodiment, Figure 3 As shown, the pulse compensation unit 1022 includes: a first NOT gate 311, a second NOT gate 312, a third NOT gate 313, a first trigger 321, a second trigger 322, a third trigger 323, an AND gate 331, a NAND gate 332, an OR gate 341, a buffer circuit 351 and a two-way selector 361. Among them, the input end of the first NOT gate 311 is connected to the generation control unit 1021 ( Figure 3 The input terminal of the second NOT gate 312 is connected to the clock circuit 100 ( Figure 3The input end of the first trigger 321 is connected to the output end of the first NOT gate 311, the clock end of the first trigger 321 is connected to the output end of the second NOT gate 312, and the output end of the first trigger 321 is connected to the first input end of the AND gate 331; the second input end of the AND gate 331 is connected to the clock circuit 100, and the output end of the AND gate 331 is connected to the first input end of the two-way selector 361; the input end of the second trigger 322 is connected to the generation control unit 1021, and the output end of the second trigger 322 is respectively connected to the input end of the third trigger 323 and the first input end of the AND gate 332. The input end of the third NOT gate 313 and the clock end of the third trigger 323 are respectively connected to the clock circuit 100, and the output end of the third NOT gate 313 is respectively connected to the first input end of the OR gate 341 and the clock end of the second trigger 322; the output end of the third trigger 323 is connected to the second input end of the NAND gate 332, and the output end of the NAND gate 332 is respectively connected to the second input end of the OR gate 341 and the input end of the buffer circuit 351; the output end of the buffer circuit 351 is connected to the control end of the two-way selector 361, and the output end of the OR gate 341 is connected to the second input end of the two-way selector 361.

[0084] Specific, combined Figure 4 As shown, on the one hand, the input end of the first NOT gate 311 receives the subtraction pulse enable signal del_en (taking one pulse as an example in the figure) output by the generation control unit 1021, and after flipping, the reverse subtraction pulse enable signal del_en_n is obtained, and then sent to the input end of the first trigger 321, and the input end of the second NOT gate 312 receives the clock signal src_clk provided by the clock circuit 100, and after flipping, it is sent to the clock end of the first trigger 321, so as to realize the falling edge synchronization of the reverse subtraction pulse enable signal del_en_n with the falling edge of the clock signal src_clk, and obtain the reverse subtraction pulse falling edge synchronization signal del_en_neg. The first input terminal of the AND gate 331 receives the reverse subtraction pulse falling edge synchronization signal del_en_neg, and the second input terminal of the AND gate 331 receives the clock signal src_clk. The AND gate 331 ANDs the reverse subtraction pulse falling edge synchronization signal del_en_neg with the clock signal src_clk to obtain the subtraction pulse output signal clk_del_calr, and outputs it to the first input terminal of the two-way selector 361. It should be understood that due to the influence of the system structure, there may be a delay (for example, 100% delay) between the subtraction pulse enable signal del_en and the clock signal src_clk, and between the reverse subtraction pulse falling edge synchronization signal del_en_neg and the clock signal src_clk. Figure 4In the embodiment, there is a delay between the pulse generation time of the subtraction pulse enable signal del_en and the rising edge of the corresponding clock signal src_clk, and there is a delay between the falling edge of the reverse subtraction pulse falling edge synchronization signal del_en_neg and the falling edge of the corresponding clock signal src_clk).

[0085] On the other hand, the input end of the second flip-flop 322 receives the pulse enable signal add_en (including one pulse in the figure as an example) output by the generation control unit 1021, and the input end of the third NOT gate 313 receives the clock signal src_clk, which is flipped to obtain the reverse clock signal src_clk_n, which is then sent to the clock end of the second flip-flop 322 and the first input end of the OR gate 341. The second flip-flop 322 implements the falling edge synchronization of the pulse enable signal with the falling edge of the clock signal according to the reverse clock signal src_clk_n and add_en, and obtains the pulse falling edge synchronization signal add_en_neg. The input end of the third trigger 323 receives the pulse falling edge synchronization signal add_en_neg, and the clock end of the third trigger 323 receives the clock signal src_clk, so as to realize the rising edge synchronization of the pulse falling edge synchronization signal add_en_neg using the rising edge of the clock signal src_clk to obtain the pulse rising edge synchronization add_en_pos, and the NAND gate 332 performs NAND operation on the pulse falling edge synchronization signal add_en_neg and the pulse rising edge synchronization add_en_pos to obtain the pre-pulse selection signal add_en_sel_pre. The buffer circuit 351 delays the pre-adding pulse selection signal add_en_sel_pre to obtain the adding pulse selection signal add_en_sel, and provides it to the control end of the two-way selector 361. The OR gate 341 performs an OR operation on the pre-adding pulse selection signal add_en_sel_pre and the reverse clock signal src_clk_n to obtain the additional clock signal ext_clk, and sends it to the second input end of the two-way selector 361. The first input end of the two-way selector 361 can be a high level end 1, and the second input end of the two-way selector 361 can be a low level end 0. Under the drive of the adding pulse selection signal add_en_sel, the calibration output signal clk_calr is finally output. Similarly, it should be understood that due to the influence of the system structure, there may be a delay between the adding pulse enable signal add_en and the clock signal src_clk, between the adding pulse falling edge synchronization signal add_en_neg and the clock signal src_clk, and between the adding pulse rising edge synchronization add_en_pos and the clock signal src_clk.

[0086] In one embodiment, the buffer circuit 351 may include a plurality of buffers connected in series.

[0087] like Figure 3 As shown, taking three buffers as an example, buffer 01, buffer 02 and buffer 03 are connected in series in sequence to delay the pre-add pulse selection signal add_en_sel_pre. The number of buffers can be set as needed to adjust the delay time, so that the added pulse finally reaches the desired width.

[0088] In one embodiment, the generation control unit 1021 is further used to control the receiving module 101 to stop receiving the next set of calibration data after the receiving module 101 receives a set of calibration data until the pulse compensation unit 1022 completes the pulse increase or decrease action.

[0089] It can be understood that when an external terminal sends calibration data to the receiving module 101, the receiving module 101 will forward the calibration data to the generation control unit 1021. If the pulse compensation unit 1022 has not completed the increase or decrease action of the signal, and the receiving module 101 continues to receive the calibration data of the terminal and forward it to the generation control unit 1021, it may further affect the current increase or decrease action of the pulse compensation unit 1022. Therefore, after receiving a set of calibration data, the generation control unit 1021 can control the receiving module 101 to stop receiving the next set of calibration data until the pulse compensation unit 1022 completes the increase or decrease action of the pulse.

[0090] In one embodiment, after receiving a set of calibration data, the generation control unit 1021 may send a shielding signal to the receiving module 101, thereby instructing the receiving module 101 to stop receiving the calibration data of the terminal until the pulse increase and decrease action is completed, and then control the receiving module 101 to start receiving new calibration data.

[0091] An embodiment of the present invention further provides a clock calibration device, comprising a clock circuit 100 and a clock calibration apparatus according to any one of the above embodiments.

[0092] In one embodiment, the clock calibration device further includes a terminal connected to the receiving module 101 , and configured to obtain the number of added pulses and the number of subtracted pulses according to the calibration cycle information, the frequency of the clock signal and the nominal frequency, and send the obtained numbers to the receiving module 101 .

[0093] Among them, the calibration cycle information can be used to characterize the calibration cycle, and the terminal can obtain the number of plus pulses and the number of minus pulses according to the following formula:

[0094]

[0095] Among them, f calr is the nominal frequency, f src is the frequency of the clock signal, A is the number of add pulses, D is the number of subtract pulses, and T is the calibration period, which can be represented as 2 nIt can be understood that, when the nominal frequency and the frequency of the clock signal are known, by adjusting the values ​​of A and D respectively, both sides of the final equation are equal, a matching set of values ​​of A and D is obtained.

[0096] In one embodiment, the calibration period information received by the receiving module 101 may be sent by the terminal.

[0097] An embodiment of the present invention further provides a clock calibration method, which is applied to a clock circuit. The clock circuit is used to provide a clock signal. The clock calibration method includes steps S110 to S120.

[0098] Step S110, receiving calibration data, the calibration data including at least one of the number of plus pulses and the number of minus pulses, and calibration cycle information;

[0099] Step S120, pulse calibration is performed on the clock signal within the calibration period according to the clock signal and the calibration data, so that the frequency of the calibrated clock signal reaches the nominal frequency; wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses.

[0100] The working principle and beneficial effects of the clock calibration method according to the embodiment of the present invention have been specifically described in the above-mentioned clock calibration device, and will not be described in detail here.

[0101] In one embodiment, the step of pulse calibrating the clock signal within the calibration cycle according to the clock signal and the calibration data also includes: generating a pulse add enable signal according to the calibration cycle information and the number of pulse add pulses, and generating a pulse subtraction enable signal according to the calibration cycle information and the number of pulse subtraction pulses; increasing the pulse of the clock signal within the calibration cycle according to the clock signal and the pulse add enable signal; and reducing the pulse of the clock signal within the calibration cycle according to the clock signal and the pulse subtraction enable signal.

[0102] In one embodiment, the calibration period is characterized by 2 n The clock cycle of a clock signal, the number of pulses is represented by:

[0103]

[0104] Where D is the number of pulses, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n; the step of generating a pulse reduction enable signal according to the calibration cycle information and the number of pulse reductions includes: if D j The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. jA first trigger moment, the front segmentation point is a segmentation point set before the current round of segmentation; a pulse with a width of one clock cycle of the clock signal is generated at each first trigger moment to obtain a pulse reduction enable signal.

[0105] In one embodiment, the calibration period is characterized by 2 n The clock cycle of a clock signal plus the number of pulses is represented by:

[0106]

[0107] Among them, A is the number of pulses added, A i The value of i is 0 or 1, i, m and n are natural numbers, and m is less than n; the step of generating a pulse enable signal according to the calibration cycle information and the number of pulses includes: if A i If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. i A second trigger moment, the front segmentation point is a segmentation point set before the current round of segmentation; based on each second trigger moment, a pulse with a width of one clock cycle of the clock signal is generated to obtain a pulse enable signal.

[0108] In one embodiment, based on each second trigger moment, a pulse with a width of one clock cycle of the clock signal is generated, and the step of obtaining a pulse enable signal includes: delaying a preset time length at each second trigger moment to generate a pulse with a width of one clock cycle of the clock signal, and obtaining a pulse enable signal; wherein the preset time length is an integer multiple of the clock cycle.

[0109] In one embodiment, the clock calibration method further includes: after receiving a set of calibration data, stopping receiving the next set of calibration data until the pulse increase and decrease actions are completed.

[0110] In one embodiment, the clock calibration method further includes: acquiring and sending the number of plus pulses and the number of minus pulses according to the calibration cycle information, the frequency of the clock circuit and the nominal frequency.

[0111] The present invention also provides a clock calibration method, comprising the following steps:

[0112] Step (a1): Obtain and send the number of plus pulses and the number of minus pulses according to the calibration cycle information, the frequency of the clock circuit and the nominal frequency.

[0113] Step (a2): receiving calibration data, the calibration data including at least one of the number of plus pulses and the number of minus pulses, and calibration cycle information.

[0114] Step (a3): After receiving a set of calibration data, stop receiving the next set of calibration data until the pulse increase and decrease action is completed.

[0115] Step (a4): The calibration cycle is characterized as 2 n The clock cycle of a clock signal, the number of pulses is represented by:

[0116]

[0117] Where D is the number of pulses, D j The value of D is 0 or 1, j, p and n are natural numbers, and p is less than n; if D j If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. j A first trigger moment, the front segmentation point is a segmentation point set before the current round of segmentation; then, a pulse with a width of one clock cycle of the clock signal is generated at each first trigger moment to obtain a pulse reduction enable signal.

[0118] Step (a5): The calibration cycle is characterized as 2 n The clock cycle of a clock signal plus the number of pulses is represented by:

[0119]

[0120] Among them, A is the number of pulses added, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n; if A i If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. i a second trigger moment, the front segmentation point is the segmentation point set before the current round of segmentation; then, at each second trigger moment, a preset time length is delayed to generate a pulse with a width of one clock cycle of the clock signal, to obtain a pulse enable signal; wherein the preset time length is an integer multiple of the clock cycle.

[0121] Step (a6): increasing the pulse of the clock signal within the calibration period according to the clock signal and the pulse increase enable signal; and decreasing the pulse of the clock signal within the calibration period according to the clock signal and the pulse decrease enable signal.

[0122] It should be understood that although the above Figure 5In the flowchart, each step is shown in sequence as indicated by the arrows, and each step in step (a1) to step (a6) is shown in sequence as indicated by the numbers, but these steps are not necessarily performed in the order indicated by the arrows or numbers. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be performed in other orders. Moreover, Figure 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternating with other steps or at least part of the steps or stages in other steps.

[0123] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A clock calibration device, characterized in that: Applied to a clock circuit, the clock circuit is used to provide a clock signal, and the clock calibration device includes: A receiving module, configured to receive calibration data, wherein the calibration data includes at least one of the number of added pulses and the number of subtracted pulses, and calibration cycle information; wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses; and the calibration cycle information is used to characterize the calibration cycle, and the calibration cycle is characterized as 2 n The number of pulses is expressed as: Wherein, D is the number of pulses, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n; A generating control unit is connected to the receiving module and is used for: Generate a pulse adding enable signal according to the calibration cycle information and the pulse adding quantity; If D j The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. j the first triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation; At each of the first triggering moments, a pulse having a width of one clock cycle of the clock signal is generated to obtain a pulse reduction enable signal; A pulse compensation unit is connected to the generation control unit and is used to connect to the clock circuit, and is used to increase the pulse of the clock signal within the calibration period according to the clock signal and the pulse increase enable signal; and to reduce the pulse of the clock signal within the calibration period according to the clock signal and the pulse reduction enable signal.

2. The clock calibration device according to claim 1, characterized in that: The number of pulses added is characterized by: Wherein, A is the number of pulses added, A i The value of is 0 or 1, i and m are natural numbers, and m is less than n; The generation control unit is also used for: If A i The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. i the second triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation; Based on each of the second trigger moments, a pulse with a width of one clock cycle of the clock signal is generated to obtain the pulse enable signal.

3. The clock calibration device according to claim 2, characterized in that: The generation control unit is also used for: At each of the second trigger moments, a pulse having a width of one clock cycle of the clock signal is generated by delaying the preset time length to obtain the pulse enable signal; wherein the preset time length is an integer multiple of the clock cycle.

4. The clock calibration device according to claim 1, characterized in that: The pulse compensation unit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first trigger, a second trigger, a third trigger, an AND gate, a NAND gate, an OR gate, a buffer circuit and a two-way selector; Wherein, the input end of the first NOT gate is connected to the generation control unit, and the input end of the second NOT gate is connected to the clock circuit; The input terminal of the first trigger is connected to the output terminal of the first NOT gate, the clock terminal of the first trigger is connected to the output terminal of the second NOT gate, and the output terminal of the first trigger is connected to the first input terminal of the AND gate; The second input terminal of the AND gate is connected to the clock circuit, and the output terminal of the AND gate is connected to the first input terminal of the two-way selector; The input end of the second trigger is connected to the generation control unit, and the output end of the second trigger is respectively connected to the input end of the third trigger and the first input end of the NAND gate; The input end of the third NOT gate and the clock end of the third flip-flop are respectively connected to the clock circuit, and the output end of the third NOT gate is respectively connected to the first input end of the OR gate and the clock end of the second flip-flop; The output end of the third trigger is connected to the second input end of the NAND gate, and the output end of the NAND gate is connected to the second input end of the OR gate and the input end of the buffer circuit respectively; The output end of the buffer circuit is connected to the control end of the two-way selector, and the output end of the OR gate is connected to the second input end of the two-way selector.

5. The clock calibration device according to claim 4, characterized in that: The buffer circuit includes a plurality of buffers connected in series.

6. The clock calibration device according to claim 1, characterized in that: The generation control unit is further used to control the receiving module to stop receiving the next set of calibration data after the receiving module receives a set of calibration data until the pulse compensation unit completes the pulse increase or decrease action.

7. A clock calibration device, characterized in that: include: Clock circuit; And the clock calibration device according to any one of claims 1 to 6.

8. The clock calibration device according to claim 7, characterized in that: The clock calibration device also includes: The terminal is connected to the receiving module and is used to obtain the number of added pulses and the number of subtracted pulses according to the calibration cycle information, the frequency of the clock signal and the nominal frequency, and send them to the receiving module.

9. A clock calibration method, characterized in that: Applied to a clock circuit, the clock circuit is used to provide a clock signal, and the clock calibration method includes: Receive calibration data, the calibration data including at least one of the number of added pulses and the number of subtracted pulses, and calibration cycle information; wherein the number of added pulses is used to indicate the number of increased pulses, and the number of subtracted pulses is used to indicate the number of reduced pulses; Generate a pulse adding enable signal according to the calibration cycle information and the pulse adding quantity; The calibration cycle information is used to characterize the calibration cycle, and the calibration cycle is characterized as 2 n The number of pulses is expressed as: Wherein, D is the number of pulses, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n; The clock calibration method further comprises: If D j The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. j the first triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation; At each of the first triggering moments, a pulse having a width of one clock cycle of the clock signal is generated to obtain a pulse reduction enable signal; The pulse of the clock signal in the calibration period is increased according to the clock signal and the pulse-adding enable signal; and the pulse of the clock signal in the calibration period is decreased according to the clock signal and the pulse-subtracting enable signal.

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