Delay pulse generation device, method and electronic equipment based on FPGA chip

Abstract

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of timing control, and in particular to a delay pulse generation device, method and electronic equipment based on an FPGA chip. BACKGROUND

[0002] A sub-nanosecond delay pulse generation device is widely used in micro-magnetic resonance, such as NMR (Nuclear Magnetic Resonance), ESR (Electron Spin-resonance), ODMR (Optical Detected Magnetic Resonance), ultrasound, radar, medical imaging and many other aspects, and provides accurate timing control functions. The device is used to provide accurate working timing for key components of the machine, so the performance index of the delay device is crucial.

[0003] In the related art, the delay pulse generation device mostly uses a high-precision DAC (Digital to Analog Converter) chip to generate a high-precision pulse sequence or uses a capacitor charging and discharging to realize output pulse delay. The former needs a DAC chip with a sampling rate of 1GSps or more for sub-nanosecond delay pulse, and has the disadvantages of high cost, complex structure and troublesome configuration. The latter has the problems of large output jitter and low delay precision. SUMMARY

[0004] The present application aims to at least solve one of the technical problems in the related art. To this end, one object of the present application is to provide a delay pulse generation device based on an FPGA chip, which realizes sub-nanosecond delay adjustment based on the internal logic of the FPGA chip, generates a sub-nanosecond delay pulse sequence, has low requirements for the peripheral circuit, and has the advantages of low cost, simple structure and easy implementation.

[0005] A second object of the present application is to provide an electronic equipment.

[0006] A third object of the present application is to provide a delay pulse generation method based on an FPGA chip.

[0007] To achieve the above object, the first aspect of the present application provides a delay pulse generation device based on an FPGA chip, the field programmable gate array (FPGA) chip having M delay units, the device comprising: a clock generation module configured to generate a reference clock, an output clock and a delay clock; a pulse generation module configured to generate a first output pulse according to the reference clock; a delay adjustment module configured to perform delay adjustment on the first output pulse according to the delay clock to obtain a second output pulse, wherein the delay adjustment module comprises N delay units, N being a positive integer less than or equal to M; and a parallel-to-serial conversion module configured to perform parallel-to-serial conversion on the second output pulse according to the reference clock and the output clock to output a delay pulse sequence.

[0008] The delay pulse generation device based on the FPGA chip according to the embodiment of the present application, the clock generation module generates the clocks required by the pulse generation module, the delay adjustment module and the parallel-to-serial conversion module, the reference clock, the output clock and the delay clock. The pulse generation module generates the first output pulse according to the reference clock, the delay adjustment module performs delay adjustment on the first output pulse according to the delay clock to generate the second output pulse, and the parallel-to-serial conversion module performs parallel-to-serial conversion on the second output pulse generated by the delay adjustment module according to the reference clock and the output clock to output the delay pulse sequence. The device realizes sub-nanosecond delay adjustment based on the internal logic of the FPGA chip, generates a sub-nanosecond delay pulse sequence, has low requirements on the peripheral circuit, and has the advantages of low cost, simple structure and easy implementation.

[0009] In addition, the delay pulse generation device based on the FPGA chip according to the above embodiment of the present application can have the following additional technical features:

[0010] According to an embodiment of the present application, the pulse generation module is specifically configured to determine the delay precision of the first output pulse according to the frequency of the reference clock, and output the first output pulse with the delay precision.

[0011] According to an embodiment of the present application, the N delay units are connected in cascade, each delay unit receives the delay clock, the first delay unit receives the first output pulse and performs delay adjustment on the first output pulse according to the delay clock, the next delay unit receives the delay pulse output by the previous delay unit and performs delay adjustment on the delay pulse output by the previous delay unit according to the delay clock, and the last delay unit outputs the second output pulse.

[0012] According to one embodiment of the present application, the parallel-to-serial conversion module is specifically configured to determine a parallel data bit width according to clock frequencies provided by the reference clock and the output clock, and convert the second output pulse into the delay pulse sequence according to the parallel data bit width.

[0013] According to one embodiment of the present application, a delay range of the delay adjustment module is positively related to a number of cascaded delay units in the delay adjustment module.

[0014] According to one embodiment of the present application, a delay precision of the delay adjustment module is positively related to a frequency of the delay clock received by the delay adjustment module.

[0015] According to one embodiment of the present application, when the frequency of the output clock is twice the frequency of the reference clock, the parallel data bit width is 4.

[0016] According to one embodiment of the present application, the delay adjustment module is specifically configured to perform sub-nanosecond level delay adjustment on the first output pulse.

[0017] To achieve the above object, a second aspect of the present application provides an electronic device comprising the delay pulse generation apparatus.

[0018] To achieve the above object, a third aspect of the present application provides a delay pulse generation method based on an FPGA chip, which is used in the delay pulse generation apparatus based on an FPGA chip and comprises the following steps: generating a reference clock, an output clock and a delay clock; generating a first output pulse according to the reference clock; performing delay adjustment on the first output pulse according to the delay clock to obtain a second output pulse; and performing parallel-to-serial conversion on the second output pulse according to the reference clock and the output clock to output a delay pulse sequence.

[0019] Additional aspects and advantages of the present application will be given in part in the following description, become apparent from the following description, or be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 FIG. 1 is a structural schematic diagram of a delay pulse generation apparatus based on an FPGA chip according to one embodiment of the present application;

[0021] Figure 2 FIG. 2 is a structural schematic diagram of a delay adjustment module according to one embodiment of the present application;

[0022] Figure 3 FIG. 3 is a structural schematic diagram of an electronic device according to one embodiment of the present application;

[0023] Figure 4is a flow chart of a delay pulse generation method based on an FPGA chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] Embodiments of the present application will be described in detail below with reference to drawings, examples of which are shown in the accompanying drawings, in which the same or similar components have the same or similar designations throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and are not to be understood as limiting the present application.

[0025] The embodiments of the present application will be described below in detail with reference to the accompanying drawings and specific embodiments of the present application. Figures 1-4 The delay pulse generation device, method and electronic equipment based on an FPGA chip according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Figure 1 is a structural schematic diagram of a delay pulse generation device based on an FPGA chip according to an embodiment of the present application. The field programmable gate array (FPGA) chip in the embodiment of the present application has M delay units. As shown in Figure 1 The delay pulse generation device 100 based on an FPGA chip includes a clock generation module 10, a pulse generation module 20, a delay adjustment module 30 and a parallel-serial conversion module 40. The clock generation module 10 is configured to generate a reference clock CLK_DATA, an output clock CLK_OUT and a delay clock CLK_IDELAY. The pulse generation module 20 is configured to generate a first output pulse according to the reference clock CLK_DATA. The delay adjustment module 30 is configured to delay and adjust the first output pulse according to the delay clock CLK_IDELAY to obtain a second output pulse. The delay adjustment module 30 includes N delay units, and N is a positive integer less than or equal to M. The parallel-serial conversion module 40 is configured to perform parallel-serial conversion on the second output pulse according to the reference clock CLK_DATA and the output clock CLK_OUT, and output a delay pulse sequence.

[0027] Specifically, the clock generation module 10 can generate the reference clock CLK_DATA, the delay clock CLK_IDELAY and the output clock CLK_OUT, and connect the pulse generation module 20, the delay adjustment module 30 and the parallel-serial conversion module 40 respectively, and provide the pulse generation module 20 with the reference clock CLK_DATA, the delay adjustment module 30 with the delay clock CLK_IDELAY, and the parallel-serial conversion module 40 with the reference clock CLK_DATA and the output clock CLK_OUT.

[0028] Further specifically, the pulse generation module 20 generates the first output pulse under the reference clock CLK_DATA clock domain, and transmits the first output pulse to the delay adjustment module 30. The delay adjustment module 30 performs delay adjustment on the first output pulse under the delay clock CLK_IDELAY clock domain, and outputs the second output pulse after delay adjustment. The parallel-serial conversion module 40 receives the second output pulse, performs parallel-serial conversion on the second output pulse under the reference clock CLK_DATA and output clock CLK_OUT clock domains, and outputs the delay pulse sequence.

[0029] In the embodiment of the present application, the FPGA chip has M delay units, and the delay adjustment module 30 can use N delay units in the FPGA chip, N being less than or equal to M, to perform sub-nanosecond delay adjustment on the first output pulse under the delay clock CLK_IDELAY clock domain, so that the delay pulse generation device 100 realizes sub-nanosecond delay adjustment based on the internal logic of the FPGA chip, and generates the sub-nanosecond delay pulse sequence.

[0030] As an example, the FPGA chip of model XC7K325TFFG901-2l has 500 delay units, and when the delay pulse generation device 100 in the embodiment of the present application uses the FPGA chip of model XC7K325TFFG901-2l, the delay adjustment module 30 can use delay units less than or equal to 500 to perform sub-nanosecond delay adjustment on the first output pulse under the delay clock CLK_IDELAY clock domain.

[0031] It should be noted that the model of the field programmable gate array FPGA chip in the embodiment of the present application can be XC7K325TFFG901-2l. The present application does not limit the model of the FPGA chip.

[0032] In the embodiment of the present application, the pulse generation module 20 is specifically configured to determine the pulse precision of the first output pulse according to the frequency of the reference clock CLK_DATA, and output the first output pulse with the pulse precision.

[0033] Specifically, the pulse generation module 20 can determine the pulse precision of the first output pulse as 1 / f according to the frequency f of the reference clock CLK_DATA, and generate the first output pulse with the pulse precision of 1 / f. As an example, when the clock generation module 10 generates the reference clock CLK_DATA of 250MHz, the pulse generation module 20 can generate the first output pulse with the pulse precision of 4ns (nanoseconds).

[0034] In the embodiment of the present application, as Figure 3As shown, the N delay units IDELAY are connected in series, and each delay unit IDELAY receives a delay clock CLK_IDELAY, the first delay unit IDELAY1 receives a first output pulse and adjusts the first output pulse according to the delay clock CLK_IDELAY, the next delay unit (IDELAY2, IDELAY3, … IDELAYn) receives a delay pulse output by the previous delay unit and adjusts the delay pulse output by the previous delay unit according to the delay clock CLK_IDELAY, and the last delay unit IDELAYn outputs a second output pulse.

[0035] Specifically, as shown, Figure 3 As shown, the N delay units IDELAY are connected in series, and each delay unit IDELAY receives a delay clock CLK_IDELAY, the first delay unit IDELAY1 receives a first output pulse and adjusts the first output pulse according to the delay clock CLK_IDELAY, the next delay unit (IDELAY2, IDELAY3, … IDELAYn) receives a delay pulse output by the previous delay unit and adjusts the delay pulse output by the previous delay unit according to the delay clock CLK_IDELAY, and the last delay unit IDELAYn outputs a second output pulse.

[0036] It should be noted that the delay unit IDELAY is a programmable delay unit in the I / O (Input / Output) module of the FPGA chip, which can be applied to combinational logic, timing logic or both. In addition, it can be directly accessed by the logic of the FPGA chip. The delay unit IDELAY allows the incoming signal to be delayed on the respective input pin, and the delay is controlled by the IDELAYCTRL original sentence according to the delay clock CLK_IDELAY frequency provided for the IDELAYCTRL. The delay precision of the second output pulse is different. The number of delay units IDELAY2 connected in series in the delay adjustment module 30 is different, and the delay range of the second output pulse can be adjusted.

[0037] In the embodiment of the application, the delay precision of the second output pulse is positively correlated with the frequency of the delay clock CLK_IDELAY.

[0038] Specifically, the higher the frequency of the delay clock CLK IDELAY received by the delay units IDELAY connected in cascade in the delay adjustment module 30, the higher the delay precision of the second output pulse output by the delay adjustment module 30. For example, when the number of delay units IDELAY connected in cascade in the delay adjustment module 30 is consistent, and the frequency of the delay clock CLK IDELAY received by each delay unit IDELAY connected in cascade in the delay adjustment module 30 is 400 MHz, the delay precision of the second output pulse output by the delay adjustment module 30 is 39 ps (picoseconds). When the frequency of the delay clock CLK IDELAY received by each delay unit IDELAY connected in cascade in the delay adjustment module 30 is 300 MHz, the delay precision of the second output pulse output by the delay adjustment module 30 is 52 ps. When the frequency of the delay clock CLK IDELAY received by each delay unit IDELAY connected in cascade in the delay adjustment module 30 is 200 MHz, the delay precision of the second output pulse output by the delay adjustment module 30 is 78 ps.

[0039] In the embodiment of the present application, the delay range of the second output pulse is positively correlated with the number of stages of the delay units.

[0040] Specifically, the more the number of delay units connected in cascade in the delay adjustment module 30, the greater the delay range that can be adjusted by the second output pulse output by the delay adjustment module 30. For example, when the frequency of the delay units IDELAY connected in cascade in the delay adjustment module 30 is 300 MHz, and the number of delay units IDELAY connected in cascade in the delay adjustment module 30 is 16, i.e., there are 16 stages of delay units IDELAY connected in cascade in the delay adjustment module 30, each delay unit IDELAY has 31 taps that can be adjusted, and each tap represents a delay precision of 52 ps, thus each delay unit IDELAY can provide a delay adjustment range of 31 x 52 ps, i.e., 1612 ps, and the delay adjustment range of 16 stages of delay units IDELAY is 16 x 1612 ps, i.e., 25792 ps. It can be seen that the more the number of delay units IDELAY connected in cascade in the delay adjustment module 30, the greater the adjustable delay range of the delay adjustment module 30.

[0041] As an example, when the delay pulse generation device 100 in the embodiment of the present application uses an FPGA chip with a model number of XC7K325TFFG901-2l to generate a sub-nanosecond delay pulse sequence, since the FPGA chip has as many as 500 delay units IDELAY, the delay range that can be achieved by the delay pulse generation device 100 can reach the microsecond level when the delay precision is 78 ps.

[0042] In embodiments of the present invention, the frequency of the delay clock CLK_IDELAY input to the delay adjustment module 30 can be adjusted according to the pulse precision of the delay pulse sequence. The number of cascaded delay units IDELAY in the delay adjustment module 30 can be adjusted according to the adjustable delay range of the delay pulse sequence.

[0043] In an embodiment of the present invention, the parallel-to-serial conversion module 40 is specifically used to determine the parallel data bit width according to the clock frequency provided by the reference clock CLK_DATA and the output clock CLK_OUT, and to convert the second output pulse into a delayed pulse sequence according to the parallel data bit width.

[0044] Specifically, the main unit of the parallel-to-serial conversion module 40 is the output parallel-to-serial converter OSERDES2. OSERDES2 is one of the main Select IO logic resources of the FPGA chip. Its main function is to realize the parallel-to-serial conversion of high-speed source-synchronous output data. Depending on the different clock frequencies provided by the reference clock CLK_DATA and the output clock CLK_OUT provided by the clock generation module 10, OSERDES2 can provide parallel-to-serial conversion with parallel data bit widths of 2-8, 10, and 14. The OSERDES2 unit in the parallel-to-serial conversion module 40 performs parallel-to-serial conversion on the second output pulse, converting the parallel data into serial data, and finally outputting a serial delayed pulse sequence.

[0045] In an embodiment of the present invention, when the frequency of the output clock CLK_OUT is twice that of the reference clock CLK_DATA, the parallel data bit width is 4.

[0046] As an example, when the reference clock CLK_DATA frequency is 250MHz and the output clock CLK_OUT is 500MHz, OSERDES2 can provide a parallel data bit width of 4. More specifically, when the first output pulse with a pulse precision of 4ns is delayed by the delay adjustment module 30, OSERDES2 with a parallel data bit width of 4 can convert the second output pulse into a delayed pulse sequence with a pulse precision of 1ns.

[0047] In this embodiment of the invention, the delay adjustment module 30 is specifically used to perform sub-nanosecond level delay adjustment on the first output pulse.

[0048] Taking the clock generation module 10 generating a 250MHz reference clock CLK_DATA, a 500MHz output clock CLK_OUT, and a 300MHz delay clock CLK_IDELAY, and the delay adjustment module 30 having a delay pulse generation device 100 consisting of 16 cascaded delay units IDELAY, as an example, the generation of sub-nanosecond level delay pulse sequences by the delay pulse generation device 100 will be explained:

[0049] The pulse generation module 20 generates a first output pulse with a pulse accuracy of 4ns in the time domain of the reference clock CLK_DATA at a frequency of 250MHz. The delay adjustment module 30, with a delay accuracy of 52ps and an adjustable delay range of 25792ps, performs sub-nanosecond level delay adjustment on the first output pulse with an accuracy of 4ns and outputs a second output pulse. The parallel-to-serial conversion module 40, with a parallel data bit width of 4, can convert the second output pulse into a delayed pulse sequence with a pulse accuracy of 1ns.

[0050] As can be seen from the embodiments provided by the present invention above, the clock generation module 10 is used to generate the relevant clocks for the pulse generation module 20, the delay adjustment module 30, and the parallel-to-serial conversion module 40. Under the action of the reference clock CLK_DATA, the pulse generation module 20 generates a first output pulse. Under the action of the delay clock CLK_IDELAY, the delay adjustment module 30 performs delay adjustment on the first output pulse to generate a second output pulse. The delayed pulse sequence is generated by the parallel-to-serial conversion module 40 converting the second output pulse into a parallel-to-serial sequence within the clock domains of the reference clock CLK_DATA and the output clock CLK_OUT. In the embodiments of the present invention, the pulse delay adjustment is performed after the first output pulse is generated and before the parallel-to-serial conversion, achieving sub-nanosecond-level delay adjustment of the first output pulse.

[0051] The FPGA-based delay pulse generation device of this invention generates a delay pulse sequence and adjusts the sub-nanosecond delay of the first output pulse through internal logic of the FPGA chip. This reduces the requirements for external circuitry and offers advantages such as low cost, simple structure, and easy implementation. The number of cascaded delay units (IDELAY) in the delay adjustment module 30 is adjustable, and the frequency of the delay clock received by the cascaded delay units in the delay adjustment module 30 is also adjustable. Furthermore, the FPGA chip has a large number of usable delay units (IDELAY), giving the delay adjustment module 30 the advantages of high delay accuracy, a large delay range, and flexible adjustment of the delay range.

[0052] The present invention also proposes an electronic device.

[0053] In embodiments of the present invention, such as Figure 4 As shown, the electronic device 1000 includes the FPGA chip-based delay pulse generation device 100 as described above.

[0054] Based on the aforementioned FPGA chip-based delay pulse generation device, this invention also proposes an FPGA chip-based delay pulse generation method.

[0055] Figure 4This is a flowchart of a delay pulse generation method based on an FPGA chip according to an embodiment of the present invention. Figure 4 As shown, a delay pulse generation method based on an FPGA chip may include:

[0056] S1 generates the reference clock, output clock, and delay clock.

[0057] S2 generates the first output pulse based on the reference clock.

[0058] S3, according to the delayed clock, the first output pulse is delayed to obtain the second output pulse.

[0059] S4 performs parallel-to-serial conversion on the second output pulse based on the reference clock and the output clock, and outputs a delayed pulse sequence.

[0060] Specifically, the clock generation module 10 can be used to generate a reference clock CLK_DATA, an output clock CLK_OUT, and a delay clock CLK_IDELAY. The pulse generation module 20 can be used to generate a first output pulse based on the reference clock CLK_DATA. The delay adjustment module 30 can be used to adjust the delay of the first output pulse based on the delay clock CLK_IDELAY to obtain a second output pulse. The parallel-to-serial conversion module 40 can be used to convert the second output pulse from parallel to serial based on the reference clock CLK_DATA and the output clock CLK_OUT to output a delayed pulse sequence.

[0061] It should be noted that other specific embodiments of the delay pulse generation method based on FPGA chip in the present invention can be found in the specific embodiments of the delay pulse generation device based on FPGA chip in the above embodiments of the present invention.

[0062] The FPGA-based delay pulse generation method and electronic device of this invention can achieve sub-nanosecond delay adjustment based on the internal logic of the FPGA chip, and generate a sub-nanosecond delay pulse sequence. It has low requirements for peripheral circuits and has the advantages of low cost, simple structure and convenient implementation.

[0063] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0064] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0065] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0066] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0068] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0069] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0070] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A delay pulse generation device based on an FPGA chip, characterized in that, The field-programmable gate array (FPGA) chip has M delay units, and the device includes: The clock generation module is used to generate the reference clock, output clock, and delay clock. A pulse generation module is used to generate a first output pulse according to the reference clock; A delay adjustment module is used to adjust the delay of the first output pulse according to the delay clock to obtain a second output pulse, wherein the delay adjustment module includes N delay units, and N is a positive integer less than or equal to M; Parallel-to-serial conversion module, used to convert the second output pulse into a parallel-to-serial converter according to the reference clock and the output clock, and output a delayed pulse sequence; N delay units are cascaded together, and each delay unit receives the delay clock. The first-stage delay unit receives the first output pulse and adjusts the delay of the first output pulse according to the delay clock. The next-stage delay unit receives the delay pulse output by the previous-stage delay unit and adjusts the delay of the delay pulse output by the previous-stage delay unit according to the delay clock. The last-stage delay unit outputs the second output pulse.

2. The delay pulse generation device based on an FPGA chip according to claim 1, characterized in that, The pulse generation module is specifically used to determine the pulse precision of the first output pulse based on the frequency of the reference clock, and output the first output pulse with the specified pulse precision.

3. The delay pulse generation device based on an FPGA chip according to claim 1, characterized in that, The parallel-to-serial conversion module is specifically used to determine the parallel data bit width based on the clock frequency provided by the reference clock and the output clock, and to convert the second output pulse into the delayed pulse sequence based on the parallel data bit width.

4. The delay pulse generation device based on an FPGA chip according to claim 1, characterized in that, The delay range of the delay adjustment module is positively correlated with the number of stages of the cascaded delay units in the delay adjustment module.

5. The delay pulse generation device based on an FPGA chip according to claim 1, characterized in that, The delay accuracy of the delay adjustment module is positively correlated with the frequency of the delay clock received by the delay adjustment module.

6. The delay pulse generation device based on an FPGA chip according to claim 3, characterized in that, When the frequency of the output clock is twice that of the reference clock, the parallel data bit width is 4.

7. The delay pulse generation device based on an FPGA chip according to claim 1, characterized in that, The delay adjustment module is specifically used to adjust the delay of the first output pulse at the sub-nanosecond level.

8. An electronic device, characterized in that, Includes a delay pulse generation device based on an FPGA chip as described in any one of claims 1-7.

9. A method for generating delay pulses based on an FPGA chip, characterized in that, The method is used in any one of the FPGA chip-based delay pulse generation devices as described in any one of claims 1-7, the method comprising: Generate a reference clock, an output clock, and a delay clock; A first output pulse is generated according to the reference clock; The first output pulse is delayed according to the delay clock to obtain the second output pulse; Based on the reference clock and the output clock, the second output pulse is converted from parallel to serial to output a delayed pulse sequence.

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