Phase-locked loop, signal processing device and signal processing method
Through the parallel design and weighted calculation of multiple reference clock signals, the influence of reference clock noise on power consumption in the phase-locked loop is solved, the low power consumption optimization of the phase-locked loop is achieved, and the influence of in-band phase noise on the phase-locked loop is reduced.
Patent Information
- Application Number
- CN202210634606.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-06
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2042-06-06
AI Technical Summary
The phase noise and power consumption of the phase-locked loop are difficult to further optimize. Limited by the in-band phase noise of the reference clock, existing technologies find it difficult to balance the ratio of in-band and out-of-band phase noise.
The system adopts a parallel design of multiple reference clock signals, determines the error signal through the phase detection unit, and performs weighted calculation through the weighting unit to achieve phase domain averaging of the reference clock noise and reduce the power consumption of the phase-locked loop.
By averaging the reference clock noise in the phase domain, the power consumption of the phase-locked loop is reduced, the influence of the in-band phase noise on the power consumption is avoided, and the performance of the phase-locked loop is optimized.
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Figure CN115037294B_ABST
Abstract
Description
Technical Field
[0001] This article relates to but is not limited to integrated circuit technology, and in particular to a phase-locked loop, a signal processing device, and a signal processing method. Background Art
[0002] In recent years, the continuous advancement of wireless communication technology has placed increasingly higher requirements on the phase noise of the frequency sources used. Lower phase noise often requires higher power consumption. In the design of phase-locked loops (PLLs), the balance between phase noise and power consumption has become an increasingly important issue.
[0003] The phase noise of a phase-locked loop can be roughly divided into two parts: in-band and out-of-band. Among them, the out-of-band phase noise is mainly determined by the voltage-controlled oscillator (VCO), and the in-band phase noise is mainly determined by the reference clock. In order to minimize the phase noise of the phase-locked loop, the bandwidth of the phase-locked loop is generally adjusted to balance the ratio of in-band phase noise and out-of-band phase noise. The modulation result is generally that the contribution ratio of in-band phase noise and out-of-band phase noise to the total noise is roughly the same. In related technologies, the theoretical limit (lower limit) of in-band phase noise is reference clock noise + log(N div )dBc / Hz; where N div This value represents the ratio of the phase-locked loop (PLL) output frequency to the reference clock frequency; dBc is the difference in decibels (dB) between the power at that frequency and the power at the reference clock. To reduce the phase noise of the PLL, a smaller bandwidth is required to reduce the in-band phase noise contributed by the reference clock. This leads to the need for a lower-noise VCO to avoid excessive out-of-band phase noise. In VCO design, phase noise and power consumption are traded off: achieving lower phase noise requires more power.
[0004] In summary, due to the limitation of the in-band phase noise of the reference clock, the phase noise and power consumption of the phase-locked loop are difficult to further modulate and optimize. Summary of the Invention
[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0006] The embodiments of the present invention provide a phase-locked loop, a signal processing device, and a signal processing method, which can avoid the influence of in-band phase noise on the power consumption of the phase-locked loop.
[0007] The embodiment of the present invention provides a phase-locked loop, comprising: a reference clock unit, a feedback unit, a correction unit, a phase detection unit and a weighting unit; wherein,
[0008] The reference clock unit is configured to output two or more frequency-adjustable reference clock signals to the phase detector unit, wherein the two or more reference clock signals are synchronized;
[0009] The feedback unit is configured to: perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal;
[0010] The phase detector unit is configured to determine, for each reference clock signal, a corresponding error signal for correcting the output voltage signal according to a phase difference between the reference clock signal and the feedback signal;
[0011] The weighting unit is configured to: perform weighted calculation on the determined error signal to obtain a weighted error signal;
[0012] The correction unit is configured to correct the output voltage signal of the second period according to the weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
[0013] The first period and the second period are two adjacent periods for outputting the output voltage signal.
[0014] In an exemplary embodiment, the phase-locked loop further includes a filter configured to:
[0015] Perform filtering processing on the weighted error signal obtained by the weighting unit.
[0016] In an exemplary embodiment, the reference clock unit includes two or more first crystal oscillators; wherein,
[0017] The first crystal oscillator is configured to output the reference clock signal.
[0018] In an exemplary embodiment, the reference clock unit includes a second crystal oscillator and one or more third crystal oscillators; wherein,
[0019] The second crystal oscillator is configured to: output a reference clock signal;
[0020] The third crystal oscillator is configured to: output the reference clock signal;
[0021] The frequency of the reference clock signal output by the second crystal oscillator is greater than the frequency of the reference clock signal output by the third crystal oscillator.
[0022] In an exemplary embodiment, the number of the third crystal oscillators is 8 or 16.
[0023] In an exemplary embodiment, the frequency of the third crystal oscillator is 0.1n kHz;
[0024] Wherein, n is a positive integer.
[0025] On the other hand, an embodiment of the present invention further provides a signal processing device, which includes the phase-locked loop according to the above.
[0026] In another aspect, an embodiment of the present invention further provides a method for implementing signal processing, comprising:
[0027] Performing frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal;
[0028] For each of the two or more frequency-adjustable reference clock signals, determining a corresponding error signal based on a phase difference between the reference clock signal and a feedback signal;
[0029] performing weighted calculation on the determined error signal to obtain a weighted error signal;
[0030] Correcting the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
[0031] The first period and the second period are two adjacent periods for outputting the output voltage signal; and the two or more reference clock signals are synchronized.
[0032] In an exemplary embodiment, before correcting the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal, the method further includes:
[0033] The obtained weighted error signal is filtered.
[0034] In an exemplary embodiment, before determining the corresponding error signal according to the phase difference between the reference clock signal and the feedback signal, the method further includes:
[0035] The two or more frequency-adjustable reference clock signals are generated by using two or more first crystal oscillators.
[0036] The technical solution of the present application includes: a reference clock unit, a feedback unit, a correction unit, a phase detector unit, and a weighting unit; wherein the reference clock unit is configured to output two or more frequency-adjustable reference clock signals to the phase detector unit, and the two or more reference clock signals are synchronized; the feedback unit is configured to perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal; the phase detector unit is configured to determine, for each reference clock signal, a corresponding error signal for correcting the output voltage signal based on the phase difference between the reference clock signal and the feedback signal; the weighting unit is configured to perform weighted calculation on the determined error signal to obtain a weighted error signal; and the correction unit is configured to correct the output voltage signal in the second cycle based on the weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second cycle; wherein the first cycle and the second cycle are two adjacent cycles in which the output voltage signal is output. In this embodiment of the present invention, multiple error signals are determined using two or more reference clock signals, and by weighting the error signals, phase-domain averaging of the reference clock noise of the phase-locked loop is achieved, thereby avoiding the impact of the in-band phase noise of the reference clock on the power consumption of the phase-locked loop and reducing the power consumption of the phase-locked loop.
[0037] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.
[0039] Figure 1 This is a flow chart of a phase-locked loop according to an embodiment of the present invention;
[0040] Figure 2 This is an example diagram of a phase-locked loop according to an embodiment of the present invention;
[0041] Figure 3 The present invention is a flowchart of a method for implementing signal processing according to an embodiment of the present invention. DETAILED DESCRIPTION
[0042] To make the purpose, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application can be combined with each other in any manner.
[0043] The steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. Also, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be performed in an order different from that shown here.
[0044] Figure 1 : is a structural block diagram of a phase-locked loop according to an embodiment of the present invention, as shown in FIG. Figure 1 As shown, it includes: a reference clock unit, a feedback unit, a correction unit, a phase detection unit and a weighting unit; wherein,
[0045] The reference clock unit is configured to output two or more frequency-adjustable reference clock signals to the phase detector unit, wherein the two or more reference clock signals are synchronized;
[0046] The feedback unit is configured to: perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal;
[0047] The phase detector unit is configured to determine, for each reference clock signal, a corresponding error signal for correcting the output voltage signal according to a phase difference between the reference clock signal and the feedback signal;
[0048] The weighting unit is configured to: perform weighted calculation on the determined error signal to obtain a weighted error signal;
[0049] The correction unit is configured to correct the output voltage signal of the second period according to the weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
[0050] The first period and the second period are two adjacent periods for outputting the output voltage signal.
[0051] In an exemplary embodiment, the feedback signal of the embodiment of the present invention includes: the frequency and / or phase of the output voltage signal.
[0052] It should be noted that the output voltage signal in the initial stage of the embodiment of the present invention can be set to 0; other auxiliary circuits are included, and other voltage signals provided by the auxiliary circuits can also be output with reference to related technologies.
[0053] The embodiment of the present invention determines multiple error signals through two or more reference clock signals and achieves phase domain averaging of the reference clock noise of the phase-locked loop by weighting the error signals, thereby avoiding the influence of the in-band phase noise of the reference clock on the power consumption of the phase-locked loop and reducing the power consumption of the phase-locked loop.
[0054] In an exemplary embodiment, the phase-locked loop of the embodiment of the present invention further includes a filter, which is configured as follows:
[0055] The weighted error signal obtained by the weighting unit is filtered.
[0056] It should be noted that the error signal in the embodiment of the present invention is of the same type as the signal output by the phase detector in the related art, and can be a digital signal or a voltage signal.
[0057] In an exemplary embodiment, the reference clock unit of the embodiment of the present invention includes two or more first crystal oscillators; wherein,
[0058] The first crystal oscillator is configured to output a reference clock signal.
[0059] In an exemplary embodiment, the reference clock unit of the embodiment of the present invention includes: a synchronization circuit for synchronizing a reference clock signal.
[0060] In an exemplary embodiment, the synchronization circuit of the embodiment of the present invention can be designed and implemented with reference to related technologies, which will not be described in detail here.
[0061] In an exemplary embodiment, the embodiment of the present invention numbers two first crystal oscillators, namely, first crystal oscillator 1, first crystal oscillator 2, first crystal oscillator 3, ..., first crystal oscillator n. After determining the reference clock signal of first crystal oscillator 1 as the standard reference clock, a group of phase detectors and filters for synchronizing the reference clock signal are connected to the output end of first crystal oscillator 1, the output of the filter is connected to the input of first crystal oscillator 2, and the output of first crystal oscillator 2 is connected to the input end of the phase detector for synchronizing the reference clock signal. The reference clock signals output by first crystal oscillator 1 and first crystal oscillator 2 are synchronized through the connected phase detectors and filters for synchronizing the reference clock signal. Similarly, a group of phase detectors and filters for synchronizing the reference clock signal are connected between first crystal oscillator 1 and first crystal oscillator 3 in accordance with the above principle, so that the reference clock signals output by first crystal oscillator 1 and first crystal oscillator 3 can be synchronized. A group of phase detectors and filters for synchronizing the reference clock signal are connected between first crystal oscillator 1 and first crystal oscillator n in accordance with the above principle, so that the reference clock signals output by first crystal oscillator 1 and first crystal oscillator n can be synchronized. For ease of description, the phase detector and filter for synchronizing the reference clock signal are defined as a synchronization module. The synchronization module can be understood as a narrowband phase-locked loop in the related art. In an exemplary embodiment, the phase detector unit of the embodiment of the present invention is a phase detector or a phase frequency detector.
[0062] In an exemplary embodiment, the weighting unit of the embodiment of the present invention is an adder.
[0063] In an exemplary embodiment, the reference clock unit includes a second crystal oscillator and one or more third crystal oscillators; wherein the second crystal oscillator is configured to: output a reference clock signal; the third crystal oscillator is configured to: output a reference clock signal;
[0064] The frequency of the reference clock signal output by the second crystal oscillator is greater than the frequency of the reference clock signal output by the third crystal oscillator.
[0065] The number of the third crystal oscillator in the embodiment of the application is 8.
[0066] In an exemplary example, the number of the third crystal oscillator in the embodiment of the application is 16.
[0067] In an exemplary example, the third crystal oscillator in the embodiment of the application is numbered as the third crystal oscillator 1, the third crystal oscillator 2, …, and the third crystal oscillator m. After the reference clock signal of the second crystal oscillator is determined as the standard reference clock, a set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator 1 to synchronize the reference clock signals output by the second crystal oscillator and the third crystal oscillator 1. Similarly, a set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator 2, a set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator 2, and a set of synchronization modules is connected between the second crystal oscillator and the third crystal oscillator m to realize the synchronization of the reference clock signals output by the reference clock unit. In an exemplary example, the phase discriminator unit in the embodiment of the application includes a number of phase discriminators (or frequency and phase discriminators) equal to the number of the reference clock signals. Each phase discriminator (or frequency and phase discriminator) is configured to determine an error signal corresponding to one of the reference clock signals according to the phase difference between the reference clock signal and the feedback signal. In other words, when the phase-locked loop includes N crystal oscillators, the phase discriminator unit includes N phase discriminators (or frequency and phase discriminators). According to a one-to-one correspondence, each crystal oscillator is connected to a phase discriminator (or frequency and phase discriminator). The phase discriminator (or frequency and phase discriminator) determines the error signal corresponding to the reference clock signal from the crystal oscillator connected to the phase discriminator (or frequency and phase discriminator) according to the phase difference between the reference clock signal and the feedback signal.
[0068] In an exemplary example, the frequency of the third crystal oscillator in the embodiment of the application is 0.1n kilohertz, where n is a positive integer.
[0069] In an exemplary example, the correction unit in the phase-locked loop in the embodiment of the application can be an oscillator. In an exemplary example, the feedback unit in the phase-locked loop in the embodiment of the application can be a frequency divider.
[0070] When the correction unit in the phase-locked loop is an oscillator and the feedback unit is a frequency divider, the processing performed by the filter, the oscillator, and the frequency divider in the embodiment of the application is exactly the same as the processing performed by the filter, the oscillator, and the frequency divider in the related art, except that the input is changed.
[0071] In an exemplary example, the oscillator in the embodiment of the application can be a voltage-controlled oscillator.
[0072] It should be noted that the correction unit and the feedback unit in the embodiment of the present invention can be replaced with other components according to the results of the phase-locked loop in the relevant technology, and the embodiment of the present invention does not limit this.
[0073] In an exemplary embodiment, the first crystal oscillator in the embodiment of the present invention can be a voltage-controlled crystal oscillator (VCXO) or a digitally controlled crystal oscillator; in an exemplary embodiment, the second crystal oscillator in the embodiment of the present invention can be a voltage-controlled crystal oscillator or a digitally controlled crystal oscillator; in an exemplary embodiment, the third crystal oscillator in the embodiment of the present invention can be a voltage-controlled crystal oscillator or a digitally controlled crystal oscillator.
[0074] The following example illustrates that the first, second, and third crystal oscillators are all voltage-controlled crystal oscillators. A voltage-controlled crystal oscillator is referred to as a first VCXO, a voltage-controlled crystal oscillator is referred to as a second VCXO, and a voltage-controlled crystal oscillator is referred to as a third VCXO. This example illustrates that a reference clock unit includes one second VCXO and one or more third VCXOs for outputting N reference clock signals, a phase detector unit includes N phase detectors, a weighting unit is an adder, and a filter, a correction unit, and a feedback unit in a phase-locked loop are connected in sequence. Figure 2 This is an example diagram of a phase-locked loop according to an embodiment of the present invention. Figure 2 As shown, in the embodiment of the present invention, when the VCXO is the second VCXO, it can be determined as the master crystal oscillator (Master VCXO). When the VCXO is the third VCXO, N-1 third VCXOs can be considered as N-1 slave crystal oscillators (Slave VCXOs). Each slave crystal oscillator is controlled by a synchronization module to synchronize with the master crystal oscillator. The phase-locked loop in the embodiment of the present invention includes one master phase-locked loop and N-1 (N-1 is greater than or equal to 1, and can be 8 or 16) synchronous phase-locked loops. The bandwidth of the synchronous phase-locked loop is much smaller than that of the master phase-locked loop. Because the phase noise of each crystal oscillator is uncorrelated within the frequency range above the synchronous phase-locked loop bandwidth, the output of each crystal oscillator in the embodiment of the present invention is phase-detected with the output of the feedback unit, resulting in a total of N phase detectors. The outputs of the phase detectors are averaged to achieve phase-domain averaging of the reference clock noise, thereby achieving an equivalent reference clock with an equivalent noise of 1 / (N) of a single crystal oscillator. It achieves noise averaging in the phase domain, reduces the noise of the equivalent reference clock of the phase-locked loop, avoids the noise and power consumption limitations of the traditional phase-locked loop, and is beneficial to reducing the overall noise and power consumption of the phase-locked loop.
[0075] An embodiment of the present invention further provides a signal processing device, which includes the above-mentioned phase-locked loop.
[0076] In an exemplary embodiment, the signal processing device according to the embodiment of the present invention may include a receiver, a clock circuit, a frequency sweep circuit, or a local oscillator circuit.
[0077] Figure 3 Flowchart of a method for implementing signal processing according to an embodiment of the present invention, such as Figure 3 Shown, including:
[0078] Step 301: Perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal;
[0079] Step 302: for each of the two or more frequency-adjustable reference clock signals, determine a corresponding error signal based on a phase difference between the reference clock signal and the feedback signal;
[0080] Step 303: Perform weighted calculation on the determined error signal to obtain a weighted error signal;
[0081] Step 304: Correct the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period;
[0082] The first period and the second period are two adjacent periods of the output voltage signal; and the two or more reference clock signals are synchronized.
[0083] The embodiment of the present invention determines multiple error signals through two or more reference clock signals and achieves phase domain averaging of the reference clock noise of the phase-locked loop by weighting the error signals, thereby avoiding the influence of the in-band phase noise of the reference clock on the power consumption of the phase-locked loop and reducing the power consumption of the phase-locked loop.
[0084] In an exemplary embodiment, before correcting the output voltage signal generated by the oscillator according to the obtained weighted error signal, the method of the embodiment of the present invention further includes:
[0085] The obtained weighted error signal is filtered.
[0086] In an exemplary embodiment, before determining the corresponding error signal based on the phase difference between each reference clock signal and the feedback signal, the method of the embodiment of the present invention further includes:
[0087] More than two reference clock signals are generated by using more than two first crystal oscillators.
[0088] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is common and well understood by those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.
Claims
1. A phase-locked loop, comprising: Reference clock unit, feedback unit, correction unit, phase detection unit and weighting unit; wherein, The reference clock unit includes a synchronization circuit for synchronizing a reference clock signal, and is configured to: output two or more frequency-adjustable reference clock signals to the phase detector unit, wherein the two or more reference clock signals are synchronized; The feedback unit is configured to: perform frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal; The phase detector unit is configured to determine, for each reference clock signal, a corresponding error signal for correcting the output voltage signal according to a phase difference between the reference clock signal and the feedback signal; The weighting unit is configured to: perform weighted calculation on the determined error signal to obtain a weighted error signal; The correction unit is configured to correct the output voltage signal of the second period according to the weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period; The first period and the second period are two adjacent periods for outputting the output voltage signal.
2. The phase-locked loop according to claim 1, wherein: The phase-locked loop further includes a filter configured to: Perform filtering processing on the weighted error signal obtained by the weighting unit.
3. The phase-locked loop according to claim 1 or 2, characterized in that: The reference clock unit includes two or more first crystal oscillators; wherein, The first crystal oscillator is configured to output the reference clock signal.
4. The phase-locked loop according to claim 1 or 2, characterized in that: The reference clock unit includes a second crystal oscillator and one or more third crystal oscillators; wherein, The second crystal oscillator is configured to: output a reference clock signal; The third crystal oscillator is configured to: output the reference clock signal; The frequency of the reference clock signal output by the second crystal oscillator is greater than the frequency of the reference clock signal output by the third crystal oscillator.
5. The phase-locked loop according to claim 4, wherein: The number of the third crystal oscillators is 8 or 16.
6. The phase-locked loop according to claim 4, wherein: The frequency of the third crystal oscillator is 0.1n kilohertz; Wherein, n is a positive integer.
7. A signal processing device, characterized in that The signal processing device includes a phase-locked loop according to any one of claims 1 to 6.
8. A method for implementing signal processing, comprising: Performing frequency division processing on the output voltage signal output by the phase-locked loop in the first cycle to obtain a feedback signal; For each of the two or more frequency-adjustable reference clock signals, determining a corresponding error signal based on a phase difference between the reference clock signal and a feedback signal; performing weighted calculation on the determined error signal to obtain a weighted error signal; Correcting the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal to obtain the output voltage signal output by the phase-locked loop in the second period; The first period and the second period are two adjacent periods for outputting the output voltage signal; and the two or more reference clock signals are synchronized through a synchronization circuit.
9. The method according to claim 8, characterized in that Before correcting the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal, the method further includes: The obtained weighted error signal is filtered.
10. The method according to claim 8 or 9, characterized in that Before determining the corresponding error signal according to the phase difference between the reference clock signal and the feedback signal, the method further includes: The two or more frequency-adjustable reference clock signals are generated by using two or more first crystal oscillators.
Citation Information
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High-stability low-phase-noise standard frequency processing method and system
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