Analog-to-digital conversion circuit, chip, control method and electronic device

Abstract

The present application provides an analog-to-digital conversion circuit, a chip, a control method and an electronic device, which belong to the field of signal processing technology. The analog-to-digital conversion circuit includes: a Flash analog-to-digital conversion module, which is configured to sample the analog input signal and generate a first set of code values; a plurality of SAR analog-to-digital conversion modules, which are configured to alternately sample the analog input signal together with the Flash analog-to-digital conversion module; each SAR analog-to-digital conversion module is configured to generate a second set of code values ​​based on the first set of code values ​​after its own sampling is completed, so as to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first set of code values ​​and the second set of code values. The chip includes the analog-to-digital conversion circuit. The solution of the present application can improve the performance of the analog-to-digital conversion circuit.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an analog-to-digital conversion circuit, chip, control method and electronic device. Background Art

[0002] There are many types of analog-to-digital converters, such as ∑-Δ (sigma-delta) ADC, pipeline ADC, Flash ADC (also known as full parallel analog-to-digital converter, flash analog-to-digital converter), SAR ADC (Successive Approximation Register ADC). Among them, sigma-delta ADC has high accuracy and low speed; Pipeline ADC has medium resolution and speed, and high static power consumption; Flash ADC has high speed and high power consumption; SAR ADC has simple structure, small area, low power consumption, and low speed. Summary of the invention

[0003] In view of this, embodiments of the present application provide an analog-to-digital conversion circuit, a chip, a control method, and an electronic device to improve the performance of the analog-to-digital conversion circuit.

[0004] According to one aspect of the present application, there is provided an analog-to-digital conversion circuit, comprising:

[0005] A Flash analog-to-digital conversion module configured to sample an analog input signal and generate a first set of code values;

[0006] A plurality of SAR analog-to-digital conversion modules are configured to alternately sample analog input signals together with the Flash analog-to-digital conversion module;

[0007] Each SAR analog-to-digital conversion module is configured to generate a second set of code values ​​based on the first set of code values ​​after completing its own sampling, so as to output a digital output signal corresponding to the analog input signal; wherein the digital output signal includes the first set of code values ​​and the second set of code values;

[0008] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal.

[0009] According to another aspect of the present application, there is provided an analog-to-digital conversion method, comprising:

[0010] The Flash analog-to-digital conversion module samples the analog input signal and generates a first set of code values;

[0011] Multiple SAR analog-to-digital conversion modules are used to sample analog input signals alternately with the Flash analog-to-digital conversion module;

[0012] Each SAR analog-to-digital conversion module generates a second set of code values ​​based on the first set of code values ​​after completing its own sampling, so as to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first set of code values ​​and the second set of code values;

[0013] Among them, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, and the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal.

[0014] According to another aspect of the present application, a control method of an analog-to-digital conversion circuit is provided, the analog-to-digital conversion circuit comprising a Flash analog-to-digital conversion module and a plurality of SAR analog-to-digital conversion modules, the control method comprising:

[0015] Providing a signal defining a sampling period of the Flash analog-to-digital conversion module to the Flash analog-to-digital conversion module, wherein the Flash analog-to-digital conversion module is configured to sample the analog input signal during the sampling period and generate a first set of code values;

[0016] Providing a plurality of first sampling control signals to a plurality of SAR analog-to-digital conversion modules, wherein the plurality of first sampling control signals correspond to the plurality of SAR analog-to-digital conversion modules, wherein each SAR analog-to-digital conversion module is configured to sample an analog input signal when the first sampling control signal corresponding to itself is at a first level, and after the sampling itself is completed, generate a second group of code values ​​based on the first group of code values ​​to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values;

[0017] in:

[0018] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal;

[0019] In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the others are at the second level; in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the others are at the second level.

[0020] According to another aspect of the present application, a control device for an analog-to-digital conversion circuit is provided, the analog-to-digital conversion circuit comprising a Flash analog-to-digital conversion module and a plurality of SAR analog-to-digital conversion modules, the control device comprising:

[0021] A first providing module, configured to provide a signal defining a sampling period of the Flash analog-to-digital conversion module to the Flash analog-to-digital conversion module, wherein the Flash analog-to-digital conversion module is configured to sample the analog input signal during the sampling period and generate a first set of code values;

[0022] a second providing module, configured to provide a plurality of first sampling control signals to a plurality of SAR analog-to-digital conversion modules, wherein the plurality of first sampling control signals correspond to the plurality of SAR analog-to-digital conversion modules, wherein each SAR analog-to-digital conversion module is configured to sample the analog input signal when the first sampling control signal corresponding to itself is at a first level, and after the sampling itself is completed, generate a second group of code values ​​based on the first group of code values ​​to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values;

[0023] in:

[0024] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal;

[0025] In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the rest are at the second level; in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

[0026] According to another aspect of the present application, a chip is provided, comprising the analog-to-digital conversion circuit of the present application.

[0027] According to another aspect of the present application, an electronic device is provided, comprising: the analog-to-digital conversion circuit or chip of the present application.

[0028] One or more technical solutions provided in the embodiments of the present application, the Flash analog-to-digital conversion module samples the analog input signal and generates a first set of code values, and multiple SAR analog-to-digital conversion modules alternately sample the analog input signal together with the Flash analog-to-digital conversion module, and each SAR analog-to-digital conversion module generates a second set of code values ​​based on the first set of code values ​​after completing its own sampling, so as to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first set of code values ​​and the second set of code values. During the period when some SAR analog-to-digital conversion modules generate the current digital output signal, the Flash analog-to-digital conversion module and another SAR analog-to-digital conversion module can perform the next analog-to-digital conversion to generate the next digital output signal. Since the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the duration of an analog-to-digital conversion of the analog-to-digital conversion circuit, the time interval between two analog-to-digital conversions can be shortened, and the digital output signal can be output faster. And since multiple SAR analog-to-digital conversion modules share the Flash analog-to-digital conversion module, the circuit area is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 A schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0031] Figure 2 Shows Figure 1 A schematic timing diagram of a sampling control signal of the analog-to-digital conversion circuit shown;

[0032] Figure 3 Shows Figure 1 A schematic timing diagram of the analog-to-digital conversion process of the analog-to-digital conversion circuit shown;

[0033] Figure 4 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0034] Figure 5 Shows Figure 4 A schematic timing diagram of a sampling control signal of the analog-to-digital conversion circuit shown;

[0035] Figure 6 Shows Figure 4 A schematic timing diagram of the analog-to-digital conversion process of the analog-to-digital conversion circuit shown;

[0036] Figure 7 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0037] Figure 8A schematic block diagram showing a circuit system in which sampling control is outside an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

[0038] Fig. 9 A schematic diagram showing an analog-to-digital conversion circuit including a selection circuit according to an exemplary embodiment of the present application is shown;

[0039] Fig.10 A schematic timing diagram of a selection enable signal of an exemplary embodiment of the present application is shown;

[0040] Fig.11 A schematic block diagram of a selection circuit according to an exemplary embodiment of the present application is shown;

[0041] Fig.12 A schematic diagram of an analog-to-digital conversion circuit including a receiving module according to an exemplary embodiment of the present application is shown;

[0042] Fig.13 A schematic timing diagram of a reception enable signal of an exemplary embodiment of the present application is shown;

[0043] Fig.14 A schematic block diagram of a receiving module of an exemplary embodiment of the present application is shown;

[0044] Fig.15 A schematic block diagram of a single-ended input analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0045] Fig.16 A schematic block diagram of a differential input analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0046] Fig.17 A structural block diagram of a differential analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0047] Fig.18 A schematic block diagram of a differential analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown;

[0048] Fig.19 A flow chart showing an analog-to-digital conversion method according to an exemplary embodiment of the present application is shown;

[0049] Fig. 20 A flow chart showing a control method of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application; and

[0050] Fig.21 A schematic block diagram of a control device of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0051] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

[0052] It should be understood that the various steps described in the method implementation of the present application can be performed in different orders and / or performed in parallel. In addition, the method implementation may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this respect.

[0053] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] It should be noted that the modifications of "one" and "plurality" mentioned in the present application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0056] In order to improve the working speed of SAR ADC, a hybrid structure SAR ADC is proposed in the related art. Among them, the Pipelined-SARADC in the related art can improve the speed of SAR ADC by combining the working mode of pipeline structure pipeline. However, the Pipelined-SARADC still has problems such as the difficulty of residual amplifier design and high power consumption. The Flash-SAR ADC in the related art can improve the speed of SAR ADC by combining the full parallel working mode of flash structure, and does not need to design a difficult amplifier. An N-bit SAR ADC can obtain the comparison result of K bits through 1 clock cycle by adding a K-bit Flash ADC, and the remaining M bits require M clock cycles (where M=NK). Then for the N=K+M bit SAR ADC, a total of N-K+2 clock cycles are required to obtain a complete result. Compared with the SAR ADC, K-1 clock cycles are saved, the overall speed is improved, and no amplifier module with difficult design is introduced.

[0057] Analysis shows that the speed of the Flash-SAR ADC in the related art is positively correlated with the number of bits of the Flash ADC. Increasing the number of bits of the Flash ADC can increase the speed of the Flash-SAR ADC, but it will increase a lot of circuits and power consumption.

[0058] An exemplary embodiment of the present application provides an analog-to-digital conversion circuit, including: a Flash analog-to-digital conversion module and a plurality of SAR analog-to-digital conversion modules.

[0059] The Flash analog-to-digital conversion module can sample the analog input signal and generate a first set of code values. The multiple SAR analog-to-digital conversion modules can alternately sample the analog input signal together with the Flash analog-to-digital conversion module. Each SAR analog-to-digital conversion module can generate a second set of code values ​​based on the first set of code values ​​after completing its own sampling to output a digital output signal corresponding to the analog input signal. As an embodiment, the digital output signal includes N digital bits, the first set of code values ​​are the high K digital bits of the digital output signal, and the second set of code values ​​are the low M digital bits of the digital output signal, wherein N=K+M, and N, K, and M are positive integers.

[0060] Through the analog-to-digital conversion circuit, each time the analog input signal is sampled, a corresponding digital output signal is generated, and the second group of code values ​​of the digital output signal corresponding to different samplings are generated by different SAR analog-to-digital conversion modules. For example, the second group of code values ​​of the digital output signal corresponding to the current sampling is generated by one SAR analog-to-digital conversion module, and the second group of code values ​​of the digital output signal corresponding to the next sampling is generated by another SAR analog-to-digital conversion module. In the process of generating the digital output signal corresponding to the current sampling by one SAR analog-to-digital conversion module, another SAR analog-to-digital conversion module and the Flash analog-to-digital conversion module can perform the next sampling and generate the corresponding digital output signal.

[0061] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the duration of an analog-to-digital conversion of the analog-to-digital conversion circuit, wherein the duration of the analog-to-digital conversion is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal. Because the duration of an analog-to-digital conversion of the analog-to-digital conversion circuit is less than the duration from sampling the analog input signal to generating the corresponding digital output signal, the speed of the analog-to-digital conversion circuit is improved. And because multiple SAR analog-to-digital conversion modules share the Flash analog-to-digital conversion module, the circuit area is smaller.

[0062] Exemplarily, the Flash analog-to-digital conversion module can use c (minimum value is 1) clock cycles for one sampling, and it can use f (minimum value is 1) clock cycles to complete the conversion, and the SAR analog-to-digital conversion module can use m (minimum value is M) clock cycles to complete the conversion. The analog-to-digital conversion time length T of the analog-to-digital conversion circuit can be expressed as: T=c+f+m, and the minimum value of T is M+2 (also expressed as N-K+2, N is M+K) clock cycles. The time interval between two adjacent sampling periods can be set to be less than T. Taking the sampling process as 1 clock cycle, the time length of the Flash analog-to-digital conversion module to generate the first group of code values ​​is at least 1 clock cycle, and the corresponding SAR analog-to-digital conversion module to generate the second group of code values ​​based on the first group of code values ​​can be at least M clock cycles. For example, the analog-to-digital conversion time length of the digital output signal can be at least M+2 clock cycles, and the time interval between two adjacent sampling periods can be set to be less than M+2 clock cycles. In this way, the time interval for the analog-to-digital conversion circuit to generate a digital output signal can be shortened.

[0063] In some embodiments, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than the time duration for the Flash analog-to-digital conversion module to sample the analog input signal and generate the corresponding first group of code values.

[0064] In some possible implementations, in order to make the time intervals between each analog-to-digital conversion equal, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module may be greater than or equal to the ratio of one analog-to-digital conversion duration to the number of SAR analog-to-digital conversion modules (expressed as p), that is, T / p.

[0065] Exemplarily, referring to the above example, the analog-to-digital conversion duration of the digital output signal of K+M digital bits can be at least M+2 clock cycles. In the case where the analog-to-digital conversion circuit includes two 8-bit (i.e., M equals 8) SAR analog-to-digital conversion modules, the time interval between two adjacent sampling periods can be greater than or equal to 5 (i.e., (8+2) / 2). Further, in order to shorten the time interval, the time interval can be set to be less than one analog-to-digital conversion duration, that is, the time interval can be greater than or equal to 5 and less than 10 (i.e., 8+2).

[0066] In some possible implementations, each SAR analog-to-digital conversion module can sample the analog input signal when the first sampling control signal corresponding to itself is at the first level (e.g., high level). Wherein, each SAR analog-to-digital conversion module corresponds to one first sampling control signal, and multiple SAR analog-to-digital conversion modules correspond to multiple first sampling control signals. In the first sampling period of the Flash analog-to-digital conversion module (e.g., one or more clock cycles lasting from the rising edge to the falling edge), any one of the multiple first sampling control signals is at the first level, and the rest are at the second level (e.g., low level), so that one of the multiple SAR analog-to-digital conversion modules and the Flash analog-to-digital conversion module simultaneously samples the analog input signal. In the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level, so that in the second sampling period, another SAR analog-to-digital conversion module and the Flash analog-to-digital conversion module simultaneously sample the analog input signal.

[0067] When any SAR analog-to-digital conversion module is in the conversion period, the first sampling control signal corresponding to the SAR analog-to-digital conversion module is at the second level, so that the SAR analog-to-digital conversion module does not sample the analog input signal.

[0068] In some possible implementations, the analog-to-digital conversion circuit may further include a sampling control module coupled to the plurality of SAR analog-to-digital conversion modules. The sampling control module may generate the above-mentioned multiple first sampling control signals based on the second sampling control signal corresponding to the Flash analog-to-digital conversion module, wherein the second sampling control signal defines the sampling period of the Flash analog-to-digital conversion module, that is, in which clock cycles the Flash analog-to-digital conversion module performs sampling, and the time interval between two adjacent samplings.

[0069] The sampling control module can make any one of the multiple first sampling control signals be at the first level (e.g., high level) and the rest be at the second level (e.g., low level) during the first sampling period of the Flash analog-to-digital conversion module; it can also make another one of the multiple first sampling control signals be at the first level and the rest be at the second level during the second sampling period of the Flash analog-to-digital conversion module. Through this implementation, the generation of control signals can be realized inside the analog-to-digital conversion circuit, simplifying the signal control logic of its peripheral circuits (e.g., CPU). Exemplarily, in the current sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level and the rest are at the second level; in the next sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level and the rest are at the second level. Thus, multiple SAR analog-to-digital conversion modules alternately sample the analog input signal simultaneously with the Flash analog-to-digital conversion module.

[0070] In some possible implementations, the sampling control module may also generate the second sampling control signal based on a third sampling control signal (e.g., input by a CPU) input to the analog-to-digital conversion circuit. The sampling period defined by the second sampling control signal may match the third sampling control signal, for example, by keeping the same or performing frequency division, frequency multiplication, delay, and the like.

[0071] The Flash analog-to-digital conversion module samples the analog input signal to obtain a sampling signal, and generates a first group of code values ​​(e.g., high K-bit digital bits) of a digital output signal corresponding to the sampling signal. The SAR analog-to-digital conversion module that performs sampling together with the Flash analog-to-digital conversion module generates the remaining second group of code values ​​(e.g., low M-bit digital bits) of the corresponding digital output signal based on the first group of code values. In order to provide the first group of code values ​​to the corresponding SAR analog-to-digital conversion module, in some possible implementations, the analog-to-digital conversion circuit may also include: a selection module, which may be set in the Flash analog-to-digital conversion module or may be independent of the Flash analog-to-digital conversion module. The selection module may provide the corresponding first group of code values ​​to the SAR analog-to-digital conversion module that performs sampling simultaneously with the Flash analog-to-digital conversion module based on the above-mentioned multiple first sampling control signals. The corresponding first group of code values ​​are not provided to the remaining SAR analog-to-digital conversion modules.

[0072] In some possible implementations, the selection module may delay the above-mentioned multiple first sampling control signals by at least one clock cycle, and when the first sampling control signal after the delay is at the first level, provide the corresponding first group of code values ​​to the SAR analog-to-digital conversion module corresponding to the first sampling control signal. When the first sampling control signal after the delay is at the second level, do not provide the corresponding first group of code values ​​to the SAR analog-to-digital conversion module corresponding to the first sampling control signal. Exemplarily, the first level duration of the first sampling control signal is consistent with the sampling period of the Flash analog-to-digital conversion module, and the Flash analog-to-digital conversion module can generate the corresponding first group of code values ​​within at least 1 clock cycle, and thus may be delayed by one clock cycle, so that after the Flash analog-to-digital conversion module outputs the corresponding first group of code values, the corresponding first group of code values ​​are provided to the corresponding SAR analog-to-digital conversion module.

[0073] In order to provide the first group of code values ​​to the corresponding SAR analog-to-digital conversion module, in some possible implementations, the analog-to-digital conversion circuit may include: multiple receiving modules, each receiving module is coupled to a SAR analog-to-digital conversion module. Each receiving module may select whether to provide the corresponding first group of code values ​​to the SAR analog-to-digital conversion module coupled to itself based on the first sampling control signal corresponding to the SAR analog-to-digital conversion module coupled to itself. In some possible implementations, each receiving module may delay the first sampling control signal corresponding to the SAR analog-to-digital conversion module coupled to itself by at least one clock cycle, and provide the corresponding first group of code values ​​to the SAR analog-to-digital conversion module coupled to itself when the first sampling control signal after the delay is a first level. When the first sampling control signal after the delay is a second level, the corresponding first group of code values ​​are not provided to the SAR analog-to-digital conversion module coupled to itself.

[0074] In some possible implementations, it also includes: multiple receiving modules, each receiving module is coupled to a SAR analog-to-digital conversion module; wherein each receiving module is configured to: based on the first sampling control signal corresponding to the SAR analog-to-digital conversion module coupled to itself, select whether to provide the first group of code values ​​to the SAR analog-to-digital conversion module coupled to itself.

[0075] In some possible implementations, each receiving module is configured to delay the first sampling control signal corresponding to the SAR analog-to-digital conversion module coupled to itself by at least one clock cycle, and provide a first group of code values ​​to the SAR analog-to-digital conversion module coupled to itself when the first sampling control signal after the delay is at a first level.

[0076] The scheme of the present application is described below with reference to the accompanying drawings.

[0077] Figure 1 A schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. Figure 1The exemplary embodiment shown is described by taking two SAR analog-to-digital conversion modules as an example. Figure 1 As shown, the analog-to-digital conversion circuit 100 includes: a Flash analog-to-digital conversion module 101, and SAR analog-to-digital conversion modules 1021 and 1022. Among them, the Flash analog-to-digital conversion module 101, the SAR analog-to-digital conversion modules 1021 and 1022 receive an analog input signal 103, sample and convert the analog input signal 103, and generate a corresponding digital output signal, which corresponds to the analog input signal. The Flash analog-to-digital conversion module 101 can receive a sampling control signal 104 and a clock signal CLK. The sampling control signal 104 defines the sampling period of the Flash analog-to-digital conversion module 101, and the Flash analog-to-digital conversion module 101 samples the analog input signal 103 in the corresponding clock cycle. The SAR analog-to-digital conversion modules 1021 and 1022 receive the clock signal CLK respectively, and can also receive sampling control signals 1051 and 1052 respectively. The SAR analog-to-digital conversion modules 1021 and 1022 are controlled by the sampling control signals 1051 and 1052 to alternately sample together with the Flash analog-to-digital conversion module 101. After the sampling is completed, the Flash analog-to-digital conversion module 101 generates the high K bits of the corresponding digital output signal. After the sampling is completed, the SAR analog-to-digital conversion module 1021 or 1022 generates the low M bits of the corresponding digital output signal based on the corresponding high K bits generated by the Flash analog-to-digital conversion module 101, wherein the digital output signal includes N bits, N=M+K.

[0078] Figure 2 Shows Figure 1 The schematic timing diagram of the sampling control signal of the analog-to-digital conversion circuit shown in FIG. Figure 3 Shows Figure 1 The schematic timing diagram of the analog-to-digital conversion process of the analog-to-digital conversion circuit shown is non-limiting, and the following is combined with Figures 1 to 3 right Figure 1 The analog-to-digital conversion circuit 100 is shown for illustration.

[0079] Combination Figures 1 to 3As shown, in the first sampling period, the sampling control signal 104 and the sampling control signal 1051 are at a high level, and the Flash analog-to-digital conversion module 101 and the SAR analog-to-digital conversion module 1021 simultaneously sample the analog input signal 103 in the corresponding clock cycle (for example, 1 clock cycle) (referred to as sampling 1). In the first sampling period, the sampling control signal 1052 is at a low level, and the SAR analog-to-digital conversion module 1022 does not perform sampling. The Flash analog-to-digital conversion module 101 can use at least one clock cycle to convert its sampled signal into the high K-bit digital bits TP[K-1:0] of the digital output signal corresponding to sampling 1. The SAR analog-to-digital conversion module 1021 receives TP[K-1:0], and based on the high K-bit digital bits, successively outputs the low M-bit digital bits of the digital output signal, and obtains the digital output signal D1[N-1:0] corresponding to sampling 1, where N=M+K.

[0080] Continue to combine Figures 1 to 3 As shown, during the process of the SAR analog-to-digital conversion module 1021 converting its sampled signal, the second sampling period can be entered. In the second sampling period, the sampling control signal 104 and the sampling control signal 1052 are high level, and the Flash analog-to-digital conversion module 101 and the SAR analog-to-digital conversion module 1022 sample the analog input signal 103 together in the corresponding clock cycle (referred to as sampling 2); at this time, the sampling control signal 1051 is low level, and the SAR analog-to-digital conversion module 1021 does not perform sampling. The Flash analog-to-digital conversion module 101 can use one clock cycle to convert its sampled signal into the high K-bit digital bits TP[K-1:0] of the corresponding digital output signal. The SAR analog-to-digital conversion module 1022 receives TP[K-1:0], and based on the high K-bit digital bits, successively outputs the low M-bit digital bits of the digital signal to obtain the digital output signal D2[N-1:0] corresponding to sampling 2, where N=M+K.

[0081] Continue to combine Figures 1 to 3 As shown, after the SAR analog-to-digital conversion module 1021 generates the digital output signal corresponding to the first sampling period, the third sampling period can be entered. In the third sampling period, the sampling control signal 104 and the sampling control signal 1051 are high level, and the Flash analog-to-digital conversion module 101 and the SAR analog-to-digital conversion module 1021 simultaneously sample the analog input signal 103 in the corresponding clock cycle (referred to as sampling 3); at this time, the sampling control signal 1052 is low level, and the SAR analog-to-digital conversion module 1022 does not perform sampling, but converts the sampling signal corresponding to sampling 2.

[0082] Combination Figures 1 to 3As shown, a sampling can use c (minimum value is 1) clock cycles, the Flash analog-to-digital conversion module 101 can use f (minimum value is 1) clock cycles to complete the conversion, and the SAR analog-to-digital conversion module 1021 or 1022 can use m (minimum value is M) clock cycles to complete the conversion. The analog-to-digital conversion time length T of the analog-to-digital conversion circuit can be expressed as: T=c+f+m, and the minimum value of T is M+2 (also expressed as N-K+2) clock cycles. The SAR analog-to-digital conversion modules 1021 and 1022 reuse the Flash analog-to-digital conversion module 101 to alternately perform sampling and conversion. The time interval between two adjacent sampling periods can be less than T and greater than c+f. In addition, in order to uniformly generate digital output signals, that is, the time intervals between sampling periods are equal, T can be greater than or equal to T / 2. Exemplarily, when T takes the minimum value M+2, if M is 8, at this time, in order to uniformly and quickly generate digital output signals, T can be set to be greater than or equal to 5 and less than 10.

[0083] Figure 4 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. Figure 4 The exemplary embodiment shown is described by taking three SAR analog-to-digital conversion modules as an example. Figure 4 As shown, the analog-to-digital conversion circuit 200 includes: a Flash analog-to-digital conversion module 201, SAR analog-to-digital conversion modules 2021, 2022 and 2023. Among them, the Flash analog-to-digital conversion module 201 and the SAR analog-to-digital conversion modules 2021 to 2023 can receive an analog input signal 203, sample and convert the analog input signal 203, and generate a corresponding digital output signal. The Flash analog-to-digital conversion module 201 can receive a sampling control signal 204 and a clock signal CLK. The sampling control signal 204 defines the sampling period of the Flash analog-to-digital conversion module 201, and the Flash analog-to-digital conversion module 201 samples the analog input signal 203 in the corresponding clock cycle. The SAR analog-to-digital conversion modules 2021 to 2023 can receive the clock signal CLK respectively, and can also receive the sampling control signals 2051, 2052 and 2053 respectively, and control the SAR analog-to-digital conversion modules 2021 to 2023 to perform sampling alternately with the Flash analog-to-digital conversion module 201 through the sampling control signals 2051 to 2053. After the sampling is completed, the Flash analog-to-digital conversion module 201 generates the high K bits of the digital output signal. After the sampling is completed, the SAR analog-to-digital conversion modules 2021, 2022 and 2023 generate the low M bits of the corresponding digital output signal based on the corresponding high K bits generated by the Flash analog-to-digital conversion module 201, wherein the digital output signal includes N bits, N=K+M.

[0084] Figure 5 Shows Figure 4 The schematic timing diagram of the sampling control signal of the analog-to-digital conversion circuit shown in FIG. Figure 6 Shows Figure 4 The schematic timing diagram of the analog-to-digital conversion process of the analog-to-digital conversion circuit shown is non-limiting, combined with Figures 4 to 6 As shown, Figure 4 The analog-to-digital conversion circuit 200 is shown for illustration.

[0085] Combination Figures 4 to 6 As shown, in the first sampling period, the sampling control signal 204 and the sampling control signal 2051 are at a high level, and the Flash analog-to-digital conversion module 201 and the SAR analog-to-digital conversion module 2021 sample the analog input signal 203 together in the corresponding clock cycle (referred to as sampling 1); at this time, the sampling control signals 2052 and 2053 are at a low level, and the SAR analog-to-digital conversion modules 2022 and 2023 do not sample. The Flash analog-to-digital conversion module 201 can convert its sampled signal into the high K-bit digital bits TP[K-1:0] of the corresponding digital output signal. The SAR analog-to-digital conversion module 2021 receives TP[K-1:0], and based on the high K-bit digital bits, successively outputs the low M-bit digital bits of the corresponding digital output signal to obtain the corresponding digital output signal D1[N-1:0], where N=M+K.

[0086] Continue to combine Figures 4 to 6 As shown, during the conversion process of the SAR analog-to-digital conversion module 2021, the second sampling period can be entered. In the second sampling period, the sampling control signal 204 and the sampling control signal 2052 are high, and the Flash analog-to-digital conversion module 201 and the SAR analog-to-digital conversion module 2022 sample the analog input signal 203 together in the corresponding clock cycle (referred to as sampling 2); at this time, the sampling control signals 2051 and 2053 are low, and the SAR analog-to-digital conversion modules 2021 and 2023 do not sample. The Flash analog-to-digital conversion module 201 converts its sampled signal into the high K-bit digital bits TP[K-1:0] of the corresponding digital output signal. The SAR analog-to-digital conversion module 2022 receives the corresponding TP[K-1:0], and outputs the low M-bit digital bits of the corresponding digital output signal based on the high K-bit digital bits, and obtains the corresponding digital output signal D2[N-1:0].

[0087] Continue to combine Figures 4 to 6As shown, during the conversion process of the SAR analog-to-digital conversion module 2021 and / or 2022, the third sampling period can be entered. In the third sampling period, the sampling control signal 204 and the sampling control signal 2053 are at a high level, and the Flash analog-to-digital conversion module 201 and the SAR analog-to-digital conversion module 2023 sample the analog input signal 203 together in the corresponding clock cycle (referred to as sampling 3); at this time, the sampling control signals 2051 and 2052 are at a low level, and the SAR analog-to-digital conversion modules 2021 and 2022 do not perform sampling, but perform conversions corresponding to sampling 1 and sampling 2, respectively. Accordingly, the Flash analog-to-digital conversion module 201 generates the high K bits of the corresponding digital output signal, and the SAR analog-to-digital conversion module 2023 outputs the low M bits of the corresponding digital output signal based on the high K bits, and obtains the digital output signal D3[N-1:0].

[0088] Continue to combine Figures 4 to 6 As shown, after the SAR analog-to-digital conversion module 2021 generates a digital output signal corresponding to sampling 1, the fourth sampling period may be entered.

[0089] Combination Figures 4 to 6 As shown, the analog-to-digital conversion time length T of the analog-to-digital conversion circuit can be expressed as mentioned above: T=c+f+m, and the minimum value of T is M+2 (also expressed as N-K+2) clock cycles. The SAR analog-to-digital conversion modules 2021 to 2023 reuse the Flash analog-to-digital conversion module 201 to alternately perform sampling and conversion, and the time interval between two adjacent sampling periods may be less than T and greater than c+f. In addition, in order to uniformly generate the corresponding digital output signals, that is, the time intervals between the sampling periods are equal, T may be greater than or equal to T / 3. Exemplarily, when T takes the minimum value M+2, if M is 10, at this time, in order to uniformly and quickly generate the digital output signal, T can be set to be greater than or equal to 4 and less than 12.

[0090] It should be understood that Figure 1 and Figure 4 Exemplary analog-to-digital conversion circuits including two and three SAR analog-to-digital conversion modules are shown respectively, but the present application does not limit the number of SAR analog-to-digital conversion modules. In practical applications, two, three or more SAR analog-to-digital conversion modules can be set as needed. These SAR analog-to-digital conversion modules can reuse Flash analog-to-digital conversion modules to alternately perform sampling and conversion, which can improve the performance of analog-to-digital conversion.

[0091] Figure 7 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. Figure 7 In the exemplary embodiment shown, sampling control is implemented inside the analog-to-digital conversion circuit, and the analog-to-digital conversion circuit receives a sampling control signal input from the outside, such as Figure 7 As shown, the analog-to-digital conversion circuit 700 includes: a Flash analog-to-digital conversion module 701, SAR analog-to-digital conversion modules 7021 and 7022, and a sampling control module 706. Among them, the Flash analog-to-digital conversion module 701, the SAR analog-to-digital conversion modules 7021 and 7022 can receive an analog input signal 703, sample and convert the analog input signal 703, and generate a corresponding digital output signal. The Flash analog-to-digital conversion module 701 can receive a sampling control signal 704 and a clock signal CLK, and sample the analog input signal 703 in a corresponding clock cycle. The sampling control signal 704 defines the sampling period of the Flash analog-to-digital conversion module 701.

[0092] In some examples, the sampling control signal 707 (eg, input by the CPU) may be directly provided to the Flash analog-to-digital conversion module 701 as the sampling control signal 704. In other examples, such as Figure 7 As shown, sampling control module 706 receives sampling control signal 707 and then provides sampling control signal 704 to Flash analog-to-digital conversion module 701. The sampling period defined by sampling control signal 704 can match sampling control signal 707, for example, keep consistent or perform frequency division, frequency multiplication, delay and other processing.

[0093] Combination Figure 7 As shown, the sampling control module 706 can generate sampling control signals 7051 and 7052 based on the sampling control signal 704, and provide the sampling control signals 7051 and 7052 to the SAR analog-to-digital conversion modules 7021 and 7022 respectively. The SAR analog-to-digital conversion modules 7021 and 7022 can receive the clock signal CLK respectively, and can also receive the sampling control signals 7051 and 7052 respectively. In the first sampling period of the Flash analog-to-digital conversion module 701, one of the sampling control signals 7051 and 7052 is a first level (e.g., a high level), and the other is a second level (e.g., a low level); in the second sampling period of the Flash analog-to-digital conversion module 701, the levels of the sampling control signals 7051 and 7052 are reversed. This allows the SAR analog-to-digital conversion modules 7021 and 7022 to alternately sample with the Flash analog-to-digital conversion module 701.

[0094] It should be understood that Figure 7 An exemplary analog-to-digital conversion circuit including two SAR analog-to-digital conversion modules is shown, and analog-to-digital conversion circuits including more SAR analog-to-digital conversion modules are not described in detail here.

[0095] Figure 8 A schematic block diagram of a circuit system of an exemplary embodiment of the present application in which sampling control is outside an analog-to-digital conversion circuit is shown. Figure 8In the exemplary embodiment shown, sampling control is implemented outside the analog-to-digital conversion circuit. Figure 8 As shown, the circuit system 800 includes: a sampling control module 810 and an analog-to-digital conversion circuit 820 . The sampling control module 810 receives a sampling control signal 811 , and provides a sampling control signal 821 , sampling control signals 8221 and 8222 to the analog-to-digital conversion circuit 820 based on the sampling control signal 811 .

[0096] The sampling control signal 821 is used by the Flash analog-to-digital conversion module in the analog-to-digital conversion circuit 820, and defines the sampling period of the Flash analog-to-digital conversion module. The sampling control signals 8221 and 8222 respectively control the two SAR analog-to-digital conversion modules in the analog-to-digital conversion circuit 820. The sampling control module 810 can make, in the first sampling period of the Flash analog-to-digital conversion module, any one of the sampling control signals 8221 and 8222 is a first level (e.g., a high level), and the rest are a second level (e.g., a low level). The sampling control module 810 can make, in the second sampling period of the Flash analog-to-digital conversion module, another one of the sampling control signals 8221 and 8222 is a first level, and the rest are a second level, so that multiple SAR analog-to-digital conversion modules are alternately sampled with the Flash analog-to-digital conversion module.

[0097] Combine the following Fig. 9 , Fig.10 and Fig.11 The analog-to-digital conversion circuit including the selection module is described. In this exemplary embodiment, the corresponding high-K digital bits generated by the Flash analog-to-digital conversion module are provided to the corresponding SAR analog-to-digital conversion module through the selection module.

[0098] Fig. 9 A schematic diagram of an analog-to-digital conversion circuit including a selection module according to an exemplary embodiment of the present application is shown. Fig. 9As shown, the analog-to-digital conversion circuit 900 includes: a Flash analog-to-digital conversion module 901, SAR analog-to-digital conversion modules 9021 and 9022, and a selection module 906. The Flash analog-to-digital conversion module 901 receives a sampling control signal 904 and a clock signal CLK, and samples an analog input signal 903 in a corresponding clock cycle. The SAR analog-to-digital conversion modules 9021 and 9022 receive the clock signal CLK respectively, and can also receive sampling control signals 9051 and 9052 respectively. The SAR analog-to-digital conversion modules 9021 and 9022 are controlled by the sampling control signals 9051 and 9052 to alternately sample together with the Flash analog-to-digital conversion module 901. After sampling, the Flash analog-to-digital conversion module 901 generates the high K bits of the corresponding digital output signal. After sampling itself, the SAR analog-to-digital conversion module 9021 or 9022 generates the remaining low M bits of the corresponding digital output signal based on the corresponding high K bits generated by the Flash analog-to-digital conversion module 901.

[0099] Combination Fig. 9 As shown, the selection module 906 can provide the corresponding high K bits to the SAR analog-to-digital conversion module (e.g., the SAR analog-to-digital conversion module 9021) that performs sampling together with the Flash analog-to-digital conversion module 901 based on the sampling control signals 9051 and 9052, but does not provide the corresponding high K bits to the remaining SAR analog-to-digital conversion modules (e.g., the SAR analog-to-digital conversion module 9022).

[0100] In some examples, reference Fig.10 As shown, the selection module 906 can delay the sampling control signals 9051 and 9052 by at least one clock cycle, and the delayed sampling control signals 9051 and 9052 are respectively represented as selection enable signals 9071 and 9072. Fig.10 As shown, during the period when the sampling control signal 9051 is at a high level, the SAR analog-to-digital conversion module 9021 and the Flash analog-to-digital conversion module 901 perform sampling together; at this time, the sampling control signal 9052 is at a low level, and the SAR analog-to-digital conversion module 9022 does not perform sampling. When the sampling control signal 9051 becomes a low level, this sampling is completed. The Flash analog-to-digital conversion module 901 can use one clock cycle to generate the high K bits of the corresponding digital output signal. Due to the delay processing of the selection module 906, at this time, the selection enable signal 9071 is selected to be at a high level, and the selection module 906 provides the high K bits to the SAR analog-to-digital conversion module 9021. The SAR analog-to-digital conversion module 9021 generates the remaining low M bits of the corresponding digital output signal based on the high K bits. When the selection enable signal 9072 is at a low level, the selection module 906 does not provide the high K bits to the SAR analog-to-digital conversion module 9022.

[0101] Fig.11 A schematic block diagram of a selection module of an exemplary embodiment of the present application is shown. Fig.11 In the example, two SAR analog-to-digital conversion modules are used for explanation. Fig.11 As shown, the selection module 1100 includes: low trigger circuits 11010 and 11020, which respectively generate selection enable signals 9071 and 9072 that are at least one clock cycle wider than the sampling corresponding clock cycle; and AND gate circuits 11031 and 11032.

[0102] Combination Fig.11 As shown, the low trigger circuit 11010 includes a NOT gate 11011 and a D flip-flop 11012, the NAND gate 11011 receives the sampling control signal 9051, the NOT gate 11011 is coupled to the D terminal of the D flip-flop 11012, the reset terminal of the D flip-flop 11012 receives the sampling control signal 9051, and the QN terminal of the D flip-flop 11012 outputs the selection enable signal 9071. The low trigger circuit 11020 includes a NOT gate 11021 and a D flip-flop 11022, the NOT gate 11021 receives the sampling control signal 9052, the NOT gate 11021 is coupled to the D terminal of the D flip-flop 11022, the reset terminal of the D flip-flop 11022 receives the sampling control signal 9052, and the QN terminal of the D flip-flop 11022 outputs the selection enable signal 9072.

[0103] Continue to combine Fig.11 As shown, gate circuits 11031 and 11032 respectively include AND gates corresponding to the number of bits of the Flash analog-to-digital conversion module, represented as 11031[K-1:0] and 11032[K-1:0], one input end of each AND gate is coupled to a digital bit of the first digital signal TP[K-1:0] of the Flash analog-to-digital conversion module, the other input end of each AND gate receives a corresponding selection enable signal, and the output end of each AND gate is coupled to the corresponding SAR analog-to-digital conversion module. Fig.11 As shown, the output of gate circuit 11031 is represented as TP1[K-1:0], and the output of gate circuit 11031 is represented as TP2[K-1:0].

[0104] Combine the following Fig.12 , Fig.13 and Fig.14 The analog-to-digital conversion circuit including the receiving module is described. In this exemplary embodiment, the receiving module determines whether to receive the corresponding high-K digital bits generated by the Flash analog-to-digital conversion module.

[0105] Fig.12 A schematic diagram of an analog-to-digital conversion circuit including a receiving module according to an exemplary embodiment of the present application is shown. Fig.12 As shown, the analog-to-digital conversion circuit 1200 includes: a Flash analog-to-digital conversion module 1201, SAR analog-to-digital conversion modules 12021 and 12022, and receiving modules 12061 and 12062. The receiving modules 12061 and 12062 are respectively coupled to the Flash analog-to-digital conversion module 1201, and are respectively coupled to the SAR analog-to-digital conversion modules 12021 and 12022.

[0106] The Flash analog-to-digital conversion module 1201 receives a sampling control signal 1204 and a clock signal CLK, and samples the analog input signal 1203 in the corresponding clock cycle. The SAR analog-to-digital conversion modules 12021 and 12022 receive the clock signal CLK respectively, and can also receive sampling control signals 12051 and 12052 respectively. The SAR analog-to-digital conversion modules 12021 and 12022 are controlled by the sampling control signals 12051 and 12052 to alternately perform sampling in synchronization with the Flash analog-to-digital conversion module 1201. After sampling, the Flash analog-to-digital conversion module 1201 generates the high K bits of the corresponding digital output signal. After completing its own sampling, the SAR analog-to-digital conversion module 12021 or 12022 generates the remaining low M bits of the corresponding digital output signal based on the high K bits generated by the Flash analog-to-digital conversion module 1201.

[0107] Combination Fig.12 As shown, the receiving module 12061 can determine whether to receive the high K bits generated by the Flash analog-to-digital conversion module 1201 based on the sampling control signal 12051. The receiving module 12062 can determine whether to receive the high K bits generated by the Flash analog-to-digital conversion module 1201 based on the sampling control signal 12052.

[0108] Take receiving module 12061 as an example, refer to Fig.13 As shown, the receiving module 12061 can delay the sampling control signal 12051 by at least one clock cycle, and the delayed sampling control signal 12051 is represented as the receiving enable signal 12071. The following is an example of an output process. Fig.13As shown, during the period when the sampling control signal 12051 is at a high level, the SAR analog-to-digital conversion module 12021 and the Flash analog-to-digital conversion module 1201 perform sampling together; at this time, the sampling control signal 12052 is at a low level, and the SAR analog-to-digital conversion module 12022 does not perform sampling. When the sampling control signal 12051 becomes a low level, this sampling is completed. The Flash analog-to-digital conversion module 1201 can use one clock cycle to generate the high K bits of the corresponding digital output signal. Due to the delay processing of the receiving module 12061, at this time, the receiving enable signal 12071 is at a high level, and the receiving module 12061 provides the high K bits to the SAR analog-to-digital conversion module 12021. The SAR analog-to-digital conversion module 12021 generates the remaining low M bits of the corresponding digital output signal based on the high K bits. The selection enable signal corresponding to the receiving module 12062 is at a low level, and the receiving module 12062 does not provide the high K bits to the SAR analog-to-digital conversion module 12022.

[0109] Fig.14 A schematic block diagram of a receiving module of an exemplary embodiment of the present application is shown. Fig.14 As shown, the receiving module 12061 includes a low trigger circuit 1210 and an AND gate circuit 1220. Fig.14 As shown, the low trigger circuit 1210 includes a NOT gate 1211 and a D trigger 1212, the NOT gate 1211 receives the sampling control signal 12051, the NOT gate 1211 is coupled to the D end of the D trigger 1212, the reset end of the D trigger 1212 receives the sampling control signal 12051, and the QN end of the D trigger 1212 outputs a reception enable signal 12071.

[0110] Continue to combine Fig.14 As shown, the gate circuit 1220 includes an AND gate corresponding to the number of bits of the Flash analog-to-digital conversion module, represented as 1220[K-1:0], one input end of each AND gate is coupled to a digital bit of the high K bits TP[K-1:0] of the Flash analog-to-digital conversion module 1201, and the other input end of each AND gate receives the receiving enable signal 12071. When the receiving enable signal 12071 is at a high level, TP[K-1:0] is received through the output end of the AND gate circuit 1220, and the first digital signal received by the SAR analog-to-digital conversion module 12021 is represented as TPD[K-1:0]. When the receiving enable signal 12071 is at a low level, TP[K-1:0] is not received.

[0111] The following describes exemplary embodiments of analog-to-digital conversion circuits for processing different analog input signals in conjunction with the accompanying drawings, wherein the Flash ADC circuit corresponds to the above-mentioned Flash analog-to-digital conversion module, the SAR ADC circuit corresponds to the above-mentioned SAR analog-to-digital conversion module, and the receiving circuit corresponds to the above-mentioned receiving module.

[0112] In some examples, the analog-to-digital conversion circuit of the present application is a single-ended input. Fig.15 A schematic block diagram of a single-ended input analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. Fig.15 As shown, the analog-to-digital conversion circuit 1500 includes a Flash ADC circuit 1510, and SAR ADC circuits 1521 and 1522. The Flash ADC circuit 1510, the SAR ADC circuit 1521 and 1522 receive a single-ended input signal V IN , for a single-ended input signal V IN Take samples and output the digital representation corresponding to the samples.

[0113] Combination Fig.15 As shown, the Flash ADC circuit 1510 includes: a sampling and holding circuit 1511, which is not limited to a sampling and holding circuit 1511 including a switch and a capacitor (CS1); a comparison circuit 1512, which is not limited to a comparison circuit 1512 including a series of comparators, each of which compares an input signal with a reference voltage; an encoding circuit 1513, which is coupled to an output terminal of the comparison circuit 1512, which is not limited to a coding circuit 1513, which may include a K-bit (bit) thermometer code conversion binary code circuit, and converts the output TP[2 K -1:0] is converted to a K-bit binary output TP[K-1:0].

[0114] Non-limitingly, the encoding circuit 1513 can integrate the selection module mentioned above in the present application, combined with Fig.15 As shown, the selection module integrated in the encoding circuit 1513 receives the sampling control signals corresponding to the SAR ADC circuits 1521 and 1522 (respectively represented as sample 1 and sample 2). The selection module selectively outputs the K-bit binary output TP[K-1:0] to the corresponding SAR ADC circuits based on the sampling control signals corresponding to the SAR ADC circuits 1521 and 1522. Fig.15 In FIG. 1 , the K-bit binary output to the SAR ADC circuit 1521 is represented as TP1[K-1:0], and the K-bit binary output to the SAR ADC circuit 1522 is represented as TP2[K-1:0].

[0115] In some examples, the analog-to-digital conversion circuit of the present application has a differential input. Fig.16 A schematic block diagram of a differential input analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. Fig.16 As shown, the analog-to-digital conversion circuit 1600 includes a Flash ADC circuit 1610, and SAR ADC circuits 1621 and 1622. The Flash ADC circuit 1610, the SAR ADC circuits 1621 and 1622 all receive a differential input signal V IN + 、V IN - , for the differential input signal V IN + 、V IN - Take samples and output the digital representation corresponding to the samples.

[0116] Combination Fig.16 As shown, the Flash ADC circuit 1610 includes: a sampling and holding circuit 1611, which is not limited to a sampling and holding circuit 1611 including a switch and capacitors CS1 and CS2; a comparison circuit 1612, which is not limited to a comparison circuit 1612 including a series of comparators, each of which compares an input signal with a unique reference voltage; an encoding circuit 1613, which is coupled to an output terminal of the comparison circuit 1612, and which is not limited to a coding circuit 1613, which may include a K-bit (bit) thermometer code conversion binary code circuit, and converts the output TP[2 K -1:0], TN[2 K -1:0] is converted to K-bit binary output TP[K-1:0], TN[K-1:0], where TP[2 K -1:0] and TP[K-1:0] correspond to V IN + ,TN[2 K -1:0] and TN[K-1:0] correspond to V IN - .

[0117] Non-restrictive, combined Fig.16 As shown, the encoding circuit 1613 outputs the binary outputs TP[K-1:0] and TN[K-1:0] to the SAR ADC circuits 1621 and 1622 at the same time. The SAR ADC circuits 1621 and 1622 may integrate receiving circuits 16211 and 16222, which receive sampling control signals of the corresponding SAR ADC circuits and selectively receive the binary outputs TP[K-1:0] and TN[K-1:0] based on the sampling control signals.

[0118] Fig.17The structure block diagram of the differential analog-to-digital conversion circuit of the exemplary embodiment of the present application is shown. Fig.17 The analog-to-digital conversion circuit 1700 shown in the figure shows a Flash-SAR hybrid structure ADC, including a K-bit differential Flash ADC circuit 1710 and N-bit differential SAR ADC circuits 1721 and 1722 .

[0119] Non-limiting, Flash ADC circuit 1710, including sampling capacitors 1711 (CS1 and CS2), comparison circuit 1712 (non-limiting, may include K-bit resistor string, 2*(2 K -1) comparator). The SAR ADC circuits 1721 and 1722 respectively include an N-bit digital analog conversion (DAC) differential capacitor array, a comparator (COMP), an M-bit SAR logic, etc. The DAC capacitor array is not limited to a binary weighted DAC capacitor array, a bridge DAC capacitor array, or a capacitor-resistor hybrid DAC structure.

[0120] refer to Fig.17 As shown, after the encoding circuit feeds back the binary encoding result of the Flash ADC circuit 1710 to the high K-bit capacitor array in the SAR ADC circuit 1721 or 1722, the corresponding SAR ADC circuit starts the comparison of the M-1th bit, and compares M times in total. The lowest capacitance CP(0) in the high K bit of the DAC capacitor array is twice the highest capacitance CP(MK-1) in the low MK bit. The encoding circuit 2 in the SAR ADC circuits 1721 and 1722 accumulates the K-bit binary code result T[K-1:0] of the Flash ADC circuit and the M-bit binary result D[M-1:0] of the SAR ADC to obtain the N-bit binary code result D[N-1:0].

[0121] The multiple sampling is described below.

[0122] In the sampling 1 stage, the Flash ADC circuit 1710 and the SAR ADC circuit 1721 sample simultaneously. After the sampling is completed, the Flash ADC circuit 1710 can use one clock cycle to obtain the temperature code result TP1 corresponding to the differential signal [2 K -1:0] and TN1[2 K -1:0], and then obtain the K-bit binary code results TP1[K-1:0] and TN1[K-1:0] through the encoding circuit 1. The binary result of the Flash ADC circuit 1710 is fed back to the SAR ADC circuit 1721.

[0123] In the sampling 2 phase, the Flash ADC circuit 1710 and the SAR ADC circuit 1722 sample simultaneously. After the sampling is completed, the Flash ADC circuit 1710 can use one clock cycle to obtain the temperature code result TP2 corresponding to the differential signal [2 K -1:0] and TN2[2 K -1:0], and then obtain the K-bit binary code results TP2[K-1:0] and TN2[K-1:0] through the encoding circuit 1. The binary result of the Flash ADC circuit 1710 is fed back to the SAR ADC circuit 1722.

[0124] Exemplarily, the encoding circuit 1 may include a thermometer code to binary code circuit, two low triggers, and two sets of AND gate logic circuits to generate TP1[K-1:0] and TN1[K-1:0] signals corresponding to the SAR ADC circuit 1721, and generate TP2[K-1:0] and TN2[K-1:0] signals corresponding to the SAR ADC circuit 1722. The two low trigger circuits are used to generate selection enable signals that are one clock cycle wider than the corresponding sampling control signals (respectively represented as sample 1 and sample 2) of the SAR ADC circuit 1721, respectively represented as sample1_en and sample2_en. It can be achieved that when the SAR ADC circuit 1721 and the Flash ADC circuit 1710 are sampled simultaneously, the binary output of the Flash ADC circuit 1710 is provided to the SAR ADC circuit 1721; when the SAR ADC circuit 1722 and the Flash ADC circuit 1710 are sampled simultaneously, the binary output of the Flash ADC circuit 1710 is provided to the SAR ADC circuit 1722.

[0125] Fig.18 A schematic block diagram of a differential analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. Fig.18 The analog-to-digital conversion circuit 1800 shown in the figure includes a K-bit Flash ADC circuit 1810, and N-bit SAR ADC circuits 1821, 1822, and 1823. The Flash ADC circuit 1810 includes sampling capacitors 1811 (CS1 and CS2), a comparison circuit 1812 (which may include a K-bit resistor string, 2*(2 K -1) comparator).

[0126] Combination Fig.18As shown, the encoding circuit 1 can receive sampling control signals (represented as sample 1, sample 2 and sample 3, respectively) of the SAR ADC circuits 1821, 1822 and 1823, generate a selection enable signal based on sample 1, sample 2 and sample 3, and provide the binary output of the Flash ADC circuit 1810 to the corresponding SAR ADC circuit.

[0127] The multiple sampling is described below.

[0128] In the sampling 1 stage, the Flash ADC circuit 1810 and the SAR ADC circuit 1821 sample simultaneously. After the sampling is completed, the Flash ADC circuit 1810 can use one clock cycle to obtain the temperature code result TP1 corresponding to the differential signal [2 K -1:0] and TN1[2 K -1:0], and then obtain the K-bit binary code results TP1[K-1:0] and TN1[K-1:0] through the encoding circuit 1. The binary result of the Flash ADC circuit 1810 is fed back to the SAR ADC circuit 1821.

[0129] In the sampling 2 phase, the Flash ADC circuit 1810 and the SAR ADC circuit 1822 sample simultaneously. After the sampling is completed, the Flash ADC circuit 1810 can use one clock cycle to obtain the temperature code result TP2 corresponding to the differential signal [2 K -1:0] and TN2[2 K -1:0], and then obtain the K-bit binary code results TP2[K-1:0] and TN2[K-1:0] through the encoding circuit 1. The binary result of the Flash ADC circuit 1810 is fed back to the SAR ADC circuit 1822.

[0130] In the sampling 3 stage, the Flash ADC circuit 1810 and the SAR ADC circuit 1823 sample simultaneously. After the sampling is completed, the Flash ADC circuit 1810 can use one clock cycle to obtain the temperature code result TP3 corresponding to the differential signal [2 K -1:0] and TN3[2 K -1:0], and then obtain the K-bit binary code results TP3[K-1:0] and TN3[K-1:0] through the encoding circuit 1. The binary result of the Flash ADC circuit 1810 is fed back to the SAR ADC circuit 1823.

[0131] The exemplary embodiment of the present application also provides an analog-to-digital conversion method.

[0132] Fig.19A flowchart of an analog-to-digital conversion method according to an exemplary embodiment of the present application is shown. Fig.19 As shown, the method includes steps S1901 to S1903.

[0133] In step S1901, the Flash analog-to-digital conversion module samples the analog input signal and generates a first set of code values.

[0134] In step S1902, multiple SAR analog-to-digital conversion modules alternately sample the analog input signal together with the Flash analog-to-digital conversion module.

[0135] In step S1903, after completing its own sampling, each SAR analog-to-digital conversion module generates a second set of code values ​​based on the first set of code values ​​to output a digital output signal corresponding to the analog input signal.

[0136] The digital output signal includes a first set of code values ​​and a second set of code values.

[0137] Among them, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal.

[0138] Through the method of this embodiment, during the period when some SAR analog-to-digital conversion modules generate the current digital output signal, the Flash analog-to-digital conversion module and another SAR analog-to-digital conversion module can perform the next analog-to-digital conversion to generate the next digital output signal. Since the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the duration of one analog-to-digital conversion of the analog-to-digital conversion circuit, the time interval between two analog-to-digital conversions can be shortened, thereby outputting the digital output signal more quickly. In addition, since multiple SAR analog-to-digital conversion modules share the Flash analog-to-digital conversion module, the circuit area is small.

[0139] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than the time length for the Flash analog-to-digital conversion module to sample the analog input signal and generate a first group of code values ​​corresponding to the analog input signal.

[0140] Exemplarily, a sampling may use c (minimum value is 1) clock cycles, the Flash analog-to-digital conversion module may use f (minimum value is 1) clock cycles to complete the conversion, the SAR analog-to-digital conversion module may use m (minimum value is M) clock cycles to complete the conversion, and the analog-to-digital conversion time length T of the analog-to-digital conversion circuit may be expressed as: T=c+f+m, and the minimum value of T is M+2 (also expressed as N-K+2) clock cycles. Multiple SAR analog-to-digital conversion modules reuse the Flash analog-to-digital conversion module to alternately perform sampling and conversion, and the time interval between two adjacent sampling periods may be less than T and greater than c+f.

[0141] In some possible implementations, in order to uniformly generate the corresponding digital output signal, that is, the time intervals between the sampling periods are equal, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module may be greater than or equal to the ratio of an analog-to-digital conversion duration to the number of SAR analog-to-digital conversion modules (expressed as p). As mentioned above, T may be greater than or equal to T / p. Exemplarily, when T takes the minimum value M+2, if M is 8 and p is 2, at this time, in order to uniformly and quickly generate the digital output signal, T may be set to be greater than or equal to 5 and less than 10.

[0142] In some possible implementations, the multiple first sampling control signals correspond to the multiple SAR analog-to-digital conversion modules, and step S1902 specifically includes: each SAR analog-to-digital conversion module samples the analog input signal when the first sampling control signal corresponding to itself is at the first level (for example, a high level); wherein, in the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals corresponding to the multiple SAR analog-to-digital conversion modules is at the first level, and the rest are at the second level (for example, a low level); in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

[0143] In some possible implementations, in step S1902, the above-mentioned multiple first sampling control signals may be generated based on the second sampling control signal corresponding to the Flash analog-to-digital conversion module, wherein the second sampling control signal defines the sampling period of the Flash analog-to-digital conversion module, that is, in which clock cycles the sampling is performed, and the time interval between two adjacent samplings. In step S1902, in the sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals may be at the first level (e.g., high level), and the rest may be at the second level (e.g., level). In step S1902, in the next sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals may be at the first level, and the rest may be at the second level.

[0144] In some possible implementations, in step S1901, the second sampling control signal may be generated based on a third sampling control signal (e.g., input by a CPU) input to the analog-to-digital conversion circuit. The sampling period defined by the second sampling control signal may match the third sampling control signal, for example, by keeping the same or performing frequency division, frequency multiplication, delay, and the like.

[0145] In some possible implementations, when any SAR analog-to-digital conversion module is in a conversion period, the first sampling control signal corresponding to the SAR analog-to-digital conversion module is at a second level, so that the SAR analog-to-digital conversion module does not sample the analog input signal.

[0146] In some possible implementations, in the above step S1901, based on the above multiple first sampling control signals, the first set of code values ​​may be provided to the SAR analog-to-digital conversion module that performs sampling together with the Flash analog-to-digital conversion module, while the first set of code values ​​may not be provided to the remaining SAR analog-to-digital conversion modules.

[0147] Further, in step S1901, the above-mentioned multiple first sampling control signals may be delayed by at least one clock cycle, and when the delayed first sampling control signal is at the first level, the first group of code values ​​are provided to the SAR analog-to-digital conversion module corresponding to the first sampling control signal. When the delayed first sampling control signal is at the second level, the first group of code values ​​are not provided to the SAR analog-to-digital conversion module corresponding to the first sampling control signal.

[0148] In some possible implementations, in the above step S1903, each SAR analog-to-digital conversion module may select whether to receive the first group code value based on the first sampling control signal corresponding to itself. In some possible implementations, each SAR analog-to-digital conversion module may delay the first sampling control signal corresponding to itself by at least one clock cycle, and receive the first group code value when the first sampling control signal after the delay is at the first level. When the first sampling control signal after the delay is at the second level, the first group code value is not received.

[0149] As an implementation, the digital output signal includes N digital bits, the first group of code values ​​are the high K digital bits of the digital output signal, and the second group of code values ​​are the low M digital bits of the digital output signal, where N=K+M, and N, K and M are positive integers.

[0150] The exemplary embodiment of the present application also provides a control method for an analog-to-digital conversion circuit, which can be applied to a CPU or a circuit. Fig. 20 A flow chart of a control method of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. The control method includes step S2001 and step S2002.

[0151] In step S2001, a signal defining a sampling period of the Flash analog-to-digital conversion module is provided to the Flash analog-to-digital conversion module.

[0152] The Flash analog-to-digital conversion module is configured to sample the analog input signal during a sampling period and generate a first set of code values.

[0153] In step S2002, multiple channels of first sampling control signals are provided to multiple SAR analog-to-digital conversion modules.

[0154] Among them, multiple first sampling control signals correspond to multiple SAR analog-to-digital conversion modules, wherein each SAR analog-to-digital conversion module is configured to sample the analog input signal when the first sampling control signal corresponding to itself is at the first level, and after its own sampling is completed, generate a second group of code values ​​based on the first group of code values ​​to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values.

[0155] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal.

[0156] Through the method of this embodiment, during the period when some SAR analog-to-digital conversion modules generate the current digital output signal, the Flash analog-to-digital conversion module and another SAR analog-to-digital conversion module can perform the next analog-to-digital conversion to generate the next digital output signal. Since the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the duration of one analog-to-digital conversion of the analog-to-digital conversion circuit, the time interval between two analog-to-digital conversions can be shortened, thereby outputting the digital output signal more quickly. And since multiple SAR analog-to-digital conversion modules share the Flash analog-to-digital conversion module, the circuit area is smaller.

[0157] In some possible implementations, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than the time duration for the Flash analog-to-digital conversion module to sample the analog input signal and generate the corresponding first group of code values.

[0158] In some possible implementations, in the above step S2001, the time interval between two adjacent sampling periods is greater than or equal to the ratio of an analog-to-digital conversion duration to the number of SAR analog-to-digital conversion modules.

[0159] In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the rest are at the second level; in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

[0160] When any SAR analog-to-digital conversion module is in the conversion period, the first sampling control signal corresponding to the SAR analog-to-digital conversion module is at the second level, so that the SAR analog-to-digital conversion module does not sample the analog input signal.

[0161] The exemplary embodiment of the present application further provides a control device for an analog-to-digital conversion circuit, the device being a computer program instruction or a circuit, Fig.21 A schematic block diagram of a control device of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application is shown. The control device includes: a first providing module 2101 and a second providing module 2102 .

[0162] The first providing module 2101 is used to provide a signal defining a sampling period of the Flash analog-to-digital conversion module to the Flash analog-to-digital conversion module, wherein the Flash analog-to-digital conversion module is configured to sample the analog input signal during the sampling period and generate a first set of code values.

[0163] The second providing module 2102 is used to provide multiple first sampling control signals to multiple SAR analog-to-digital conversion modules, wherein the multiple first sampling control signals correspond to the multiple SAR analog-to-digital conversion modules, wherein each SAR analog-to-digital conversion module is configured to sample the analog input signal when the first sampling control signal corresponding to itself is at the first level, and after its own sampling is completed, generate a second group of code values ​​based on the first group of code values ​​to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values.

[0164] in:

[0165] The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal;

[0166] In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the rest are at the second level; in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

[0167] Through the device of this embodiment, during the period when some SAR analog-to-digital conversion modules generate the current digital output signal, the Flash analog-to-digital conversion module and another SAR analog-to-digital conversion module can perform the next analog-to-digital conversion to generate the next digital output signal. Since the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the duration of one analog-to-digital conversion of the analog-to-digital conversion circuit, the time interval between two analog-to-digital conversions can be shortened, thereby outputting the digital output signal more quickly. In addition, since multiple SAR analog-to-digital conversion modules share the Flash analog-to-digital conversion module, the circuit area is smaller.

[0168] In some possible implementations, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than the time duration for the Flash analog-to-digital conversion module to sample the analog input signal and generate the corresponding first group of code values.

[0169] In some possible implementations, the time interval between two adjacent sampling periods is greater than or equal to a ratio of the analog-to-digital conversion duration to the number of SAR analog-to-digital conversion modules.

[0170] In some possible implementations, when any SAR analog-to-digital conversion module is in a conversion period, the first sampling control signal corresponding to the SAR analog-to-digital conversion module is at a second level, so that the SAR analog-to-digital conversion module does not sample the analog input signal.

[0171] In some possible implementations, the digital output signal includes N digital bits, the first group of code values ​​are the high K digital bits of the digital output signal, and the second group of code values ​​are the low M digital bits of the digital output signal, where N=K+M, and N, K and M are positive integers.

[0172] The embodiment of the present application also provides a chip, which includes the above-mentioned analog-to-digital conversion circuit. The chip (Integrated Circuit, IC) is also called a chip, and the chip can be but is not limited to a SOC (System on Chip) chip or a SIP (system in package) chip. The chip samples the analog input signal alternately with the Flash analog-to-digital conversion module through multiple SAR analog-to-digital conversion modules. The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the analog-to-digital conversion time of the analog-to-digital conversion circuit, which can improve the analog-to-digital conversion speed.

[0173] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device subject. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charging charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. The electronic device samples the analog input signal alternately with the Flash analog-to-digital conversion module through multiple SAR analog-to-digital conversion modules. The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than the analog-to-digital conversion time of an analog-to-digital conversion circuit, which can improve the analog-to-digital conversion speed.

[0174] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that: include: Flash analog-to-digital conversion module, multiple SAR analog-to-digital conversion modules and sampling control module; The sampling control module is configured to: generate a second sampling control signal corresponding to the Flash analog-to-digital conversion module based on a third sampling control signal input to the analog-to-digital conversion circuit, and generate a plurality of first sampling control signals based on the second sampling control signal, wherein the second sampling control signal defines a sampling period of the Flash analog-to-digital conversion module, and the plurality of first sampling control signals correspond to the plurality of SAR analog-to-digital conversion modules; The Flash analog-to-digital conversion module is configured to sample the analog input signal based on the second sampling control signal and generate a first set of code values; The multiple SAR analog-to-digital conversion modules are configured to alternately sample the analog input signal together with the Flash analog-to-digital conversion module; wherein each of the SAR analog-to-digital conversion modules samples the analog input signal when the first sampling control signal corresponding to itself is at the first level, and after completing its own sampling, generates a second group of code values ​​based on the first group of code values ​​to output a digital output signal corresponding to the analog input signal; wherein the digital output signal includes the first group of code values ​​and the second group of code values; The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit; wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating the digital output signal corresponding to the analog input signal.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than the time duration for the Flash analog-to-digital conversion module to sample the analog input signal and generate the first group of code values ​​corresponding to the analog input signal.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than or equal to the ratio of the analog-to-digital conversion duration to the number of SAR analog-to-digital conversion modules.

4. The analog-to-digital conversion circuit according to claim 1, characterized in that: In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the others are at the second level; In the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

5. The analog-to-digital conversion circuit according to claim 4, characterized in that: When any of the SAR analog-to-digital conversion modules is in a conversion period, the first sampling control signal corresponding to the SAR analog-to-digital conversion module is the second level, so that the SAR analog-to-digital conversion module does not sample the analog input signal.

6. The analog-to-digital conversion circuit according to claim 4, characterized in that: In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the others are at the second level; In the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the others are at the second level.

7. The analog-to-digital conversion circuit according to claim 4, characterized in that: Also includes: The selection module is configured to provide the first set of corresponding code values ​​to the SAR analog-to-digital conversion module that performs sampling together with the Flash analog-to-digital conversion module based on the multiple first sampling control signals.

8. The analog-to-digital conversion circuit according to claim 7, characterized in that: The selection module is configured to: The multiple first sampling control signals are delayed by at least one clock cycle, and when the delayed first sampling control signals are at the first level, the corresponding first group code values ​​are provided to the SAR analog-to-digital conversion module corresponding to the first sampling control signals.

9. The analog-to-digital conversion circuit according to claim 4, characterized in that: Also includes: A plurality of receiving modules, each receiving module is coupled to a SAR analog-to-digital conversion module; Each receiving module is configured to select whether to provide the first group of code values ​​to the SAR analog-to-digital conversion module coupled to itself based on a first sampling control signal corresponding to the SAR analog-to-digital conversion module coupled to itself.

10. The analog-to-digital conversion circuit according to claim 9, characterized in that: Each receiving module is configured as follows: The first sampling control signal corresponding to the SAR analog-to-digital conversion module coupled to itself is delayed by at least one clock cycle, and when the delayed first sampling control signal is at the first level, the first group of code values ​​is provided to the SAR analog-to-digital conversion module coupled to itself.

11. The analog-to-digital conversion circuit according to any one of claims 1 to 10, characterized in that: The digital output signal includes N digital bits, the first group of code values ​​are the high K digital bits of the digital output signal, and the second group of code values ​​are the low M digital bits of the digital output signal, wherein N=K+M, and N, K and M are positive integers.

12. An analog-to-digital conversion method of an analog-to-digital conversion circuit, characterized in that: include: The sampling control module generates a second sampling control signal corresponding to the Flash analog-to-digital conversion module based on the third sampling control signal input to the analog-to-digital conversion circuit, and generates a plurality of first sampling control signals based on the second sampling control signal, wherein the second sampling control signal defines a sampling period of the Flash analog-to-digital conversion module, and the plurality of first sampling control signals correspond to a plurality of SAR analog-to-digital conversion modules; The Flash analog-to-digital conversion module samples the analog input signal based on the second sampling control signal and generates a first group of code values; The multiple SAR analog-to-digital conversion modules alternately sample the analog input signal together with the Flash analog-to-digital conversion module; wherein each of the SAR analog-to-digital conversion modules samples the analog input signal when the first sampling control signal corresponding to itself is at the first level; Each of the SAR analog-to-digital conversion modules generates a second group of code values ​​based on the first group of code values ​​after completing its own sampling, so as to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values; Among them, the time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, and the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating a digital output signal corresponding to the analog input signal.

13. The analog-to-digital conversion method according to claim 12, characterized in that: The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than the time duration for the Flash analog-to-digital conversion module to sample the analog input signal and generate the first group of code values ​​corresponding to the analog input signal.

14. The analog-to-digital conversion method according to claim 12, characterized in that: The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is greater than or equal to the ratio of the analog-to-digital conversion duration to the number of SAR analog-to-digital conversion modules.

15. The analog-to-digital conversion method according to claim 12, characterized in that: In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals corresponding to the multiple SAR analog-to-digital conversion modules is at the first level, and the others are at the second level; In the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

16. The analog-to-digital conversion method according to claim 15, characterized in that: When any of the SAR analog-to-digital conversion modules is in a conversion period, the first sampling control signal corresponding to the SAR analog-to-digital conversion module is the second level, so that the SAR analog-to-digital conversion module does not sample the analog input signal.

17. The analog-to-digital conversion method according to any one of claims 12 to 16, characterized in that: The digital output signal includes N digital bits, the first group of code values ​​are the high K digital bits of the digital output signal, and the second group of code values ​​are the low M digital bits of the digital output signal, wherein N=K+M, and N, K and M are positive integers.

18. A control method for an analog-to-digital conversion circuit, characterized in that: The analog-to-digital conversion circuit includes a Flash analog-to-digital conversion module and a plurality of SAR analog-to-digital conversion modules, and the control method includes: Providing a second sampling control signal defining a sampling period of the Flash analog-to-digital conversion module to the Flash analog-to-digital conversion module based on a third sampling control signal input to the analog-to-digital conversion circuit, wherein the Flash analog-to-digital conversion module is configured to sample the analog input signal during the sampling period and generate a first set of code values; Generate a plurality of first sampling control signals based on the second sampling control signal, and provide the plurality of first sampling control signals to the plurality of SAR analog-to-digital conversion modules, wherein the plurality of first sampling control signals correspond to the plurality of SAR analog-to-digital conversion modules, wherein each SAR analog-to-digital conversion module is configured to sample the analog input signal when the first sampling control signal corresponding to itself is at a first level, and after the sampling itself is completed, generate a second group of code values ​​based on the first group of code values ​​to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values; in: The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating the digital output signal corresponding to the analog input signal; In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the rest are at the second level; in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

19. A control device for an analog-to-digital conversion circuit, characterized in that: The analog-to-digital conversion circuit includes a Flash analog-to-digital conversion module and a plurality of SAR analog-to-digital conversion modules, and the control device includes: A first providing module, configured to provide the Flash analog-to-digital conversion module with a second sampling control signal defining a sampling period of the Flash analog-to-digital conversion module based on a third sampling control signal input to the analog-to-digital conversion circuit, wherein the Flash analog-to-digital conversion module is configured to sample the analog input signal during the sampling period and generate a first set of code values; a second providing module, configured to generate a plurality of first sampling control signals based on the second sampling control signal, and provide the plurality of first sampling control signals to the plurality of SAR analog-to-digital conversion modules, wherein the plurality of first sampling control signals correspond to the plurality of SAR analog-to-digital conversion modules, wherein each SAR analog-to-digital conversion module is configured to sample the analog input signal when the first sampling control signal corresponding to itself is at a first level, and after the sampling itself is completed, generate a second group of code values ​​based on the first group of code values, so as to output a digital output signal corresponding to the analog input signal; the digital output signal includes the first group of code values ​​and the second group of code values; in: The time interval between two adjacent sampling periods of the Flash analog-to-digital conversion module is less than an analog-to-digital conversion duration of the analog-to-digital conversion circuit, wherein the analog-to-digital conversion duration is the duration from sampling the analog input signal to generating the digital output signal corresponding to the analog input signal; In the first sampling period of the Flash analog-to-digital conversion module, any one of the multiple first sampling control signals is at the first level, and the rest are at the second level; in the second sampling period of the Flash analog-to-digital conversion module, another one of the multiple first sampling control signals is at the first level, and the rest are at the second level.

20. A chip, characterized in that: The method comprises the analog-to-digital conversion circuit according to any one of claims 1 to 11.

21. An electronic device, characterized in that: include: The analog-to-digital conversion circuit according to any one of claims 1 to 11 or the chip according to claim 20.

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