A round computing unit and corresponding encryption and decryption algorithm system

Abstract

The present invention relates to the technical field of encrypted communication, and provides a round computing unit and a corresponding encryption and decryption algorithm system. The round computing unit includes an input selection module, a reconfigurable S-box module, a reconfigurable shift module, a reconfigurable column mixing module and an output selection module, and each module is cascade-coupled in sequence, wherein a round key processing module is connected across the input selection module and the output selection module, and the above modules have two working modes, SM4 and AES. The present invention realizes the configurability of the mode during the circuit operation process, and reuses part of the circuit resources, and improves the utilization efficiency of the circuit resources while being compatible with the SM4 and AES encryption algorithms.

Description

[Technical field]

[0001] The present invention relates to the technical field of encryption communication, and in particular to a round calculation unit and a corresponding encryption and decryption algorithm system. [Background technology]

[0002] AES, or Advanced Encryption Standard, is an encryption standard released by the National Institute of Standards and Technology of the United States. It is one of the most popular symmetric block encryption algorithms today.

[0003] SM4 or SMS4.0 is a block cipher standard released by the China National Cryptography Administration on March 21, 2012. It is mainly used for data encryption in commercial cryptographic systems.

[0004] With the development of communication technology, the transmission rate of communication networks has gradually increased, and the security of communication networks has received more and more attention from the society. From IP encryption (IP Sec) at the L3 layer to MAC encryption (MAC Sec) at the L2 layer, the demand for encryption in communication networks has developed towards lower implementation complexity and cost, lower network latency and more diverse encryption methods. In particular, as the next-generation backbone transmission network, it is necessary to meet the diverse encryption needs of users with lower implementation complexity and latency.

[0005] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. [Summary of the invention]

[0006] The technical problem to be solved by the present invention is that the AES encryption and decryption algorithm and the SM4 encryption algorithm are relatively independent and compatible with different encryption modes, and different independent encryption circuits need to be used respectively; high throughput means that a parallel encryption algorithm is required, and the circuit scale of the encryption algorithm is large. Supporting multiple mode encryption functions increases the circuit scale exponentially.

[0007] The present invention adopts the following technical solution:

[0008] In the first aspect, the present invention provides a round computing unit, including an input selection module, a reconfigurable S-box module, a reconfigurable shift module, a reconfigurable column mixing module and an output selection module, wherein the modules are cascade-coupled in sequence, wherein a round key processing module is connected across the input selection module and the output selection module, and the above modules have two working modes: SM4 and AES.

[0009] Preferably, the input selection module specifically includes:

[0010] When working in SM4 mode, the result obtained by XORing the three groups of input X1, X2, X3 and the SM4 round key in the input selection module is output together with X1, X2 and X3;

[0011] When working in AES mode, the output of the input selection module is the same as the input, which are X0, X1, X2 and X3.

[0012] Preferably, the input selection module includes a selector and an input XOR module, wherein the selector includes input port 1 and input port 2, and output port 1 and output port 2, the input port 1 of the input XOR module is connected to the output port 1 of the selector, the input port 2, input port 3, and input port 4 of the input XOR module are used for inputting data X1, X2, and X3, respectively, the output port 2 of the selector is connected to the round key processing module, and is transmitted to the output selection module by the second group of input ports of the round key processing module and the output selection module, specifically:

[0013] When working in SM4 mode, the input port 1 of the selector is used to input X0, and the input port 2 of the selector is used for the SM4 round key; the output port 1 of the selector is used for the SM4 round key, and the output port 2 of the selector is used to output X0;

[0014] When working in AES mode, the input port 1 of the selector is used to input X0, and the input port 2 of the selector is used to input the AES round key; wherein, the output port 1 of the selector and the output port 2 of the selector are respectively used to transparently transmit the data of the input port 1 of the selector and the input port 2 of the selector.

[0015] Preferably, the reconfigurable S-box includes a first S-box, a second S-box, a third S-box and a fourth S-box, specifically:

[0016] When working in SM4 mode, the first S-box is configured as the S-box mode of SM4 mode, and the other three S-boxes, the second S-box, the third S-box and the fourth S-box, are configured as a linear relationship;

[0017] When working in the AES mode, the four S-box modules are all configured as the S-box mode of the AES mode.

[0018] Preferably, the reconfigurable shift module specifically includes:

[0019] When working in SM4 mode, corresponding to the data output by the first S-box, three shifted displacement data are obtained according to the preset displacement strategy, and the displacement data is XOR-processed with the output of the first S-box as a group of outputs of the shift module, wherein the three groups of data obtained from the second S-box, the third S-box and the fourth S-box are respectively transparently transmitted in the shift module;

[0020] When working in AES mode, after performing the corresponding AES shift operation, the shift operation result is output.

[0021] Preferably, the reconfigurable column mixing module specifically includes:

[0022] When working in SM4 mode, data is transparently transmitted from the column mixing module; when working in AES mode, the column mixing module is effective.

[0023] Preferably, in order to satisfy the XOR round key operation of AES and the XOR X0 operation at the output of SM4, the output selection module has two groups of input ports and one group of output ports; the first group of input ports of the output selection module is used to obtain the 4 channel data after the input selection module, the S-box module, the shift module and the column mixing module are sequentially cascaded, specifically:

[0024] When working in SM4 mode, the second group of input ports of the output selection module inputs the data X0 obtained by the round key processing module from the input selection module, and performs an XOR operation on the input ports of the two output selection modules; when working in AES mode, the second group of input ports of the output selection module inputs the AES round key obtained by the round key processing module.

[0025] The round computing unit proposed in the present invention can be compatible with both SM4 and AES encryption algorithms, realize mode configurability during circuit operation, and reuse part of the circuit resources, thereby improving the utilization efficiency of the circuit resources while being compatible with both SM4 and AES encryption algorithms.

[0026] In a second aspect, the present invention provides an encryption and decryption algorithm system, comprising 32 round calculation units as described in the first aspect, specifically comprising:

[0027] When used for AES encryption and decryption, each round computing unit is configured as the AES working mode, and the output of the 14th round computing unit is the output of AES encryption and decryption;

[0028] When used for SM4 encryption and decryption, each round computing unit is configured as the SM4 working mode, and the output of the 32nd round computing unit is the output of SM4 encryption and decryption.

[0029] The encryption and decryption algorithm system proposed in the present invention can be compatible with both SM4 and AES encryption algorithms, thereby achieving configurable modes during circuit operation and ensuring that the algorithm has high throughput.

[0030] In a third aspect, the present invention provides an encryption and decryption algorithm system, comprising 14 round calculation units as described in the first aspect, specifically comprising:

[0031] When used for AES encryption and decryption, each round computing unit is configured as the AES working mode, and the output of the 14th round computing unit is the output of AES encryption and decryption;

[0032] When used for SM4 encryption and decryption, each round computing unit is configured as the SM4 working mode, and the input of the first round computing unit needs to be selected, and the output of the eighth round computing unit also needs to be selected. After 4 pollings, the output of the eighth round computing unit is used as the output of SM4 encryption and decryption.

[0033] Preferably, the pulsation controller is arranged at the input port of the system, specifically:

[0034] If the current mode is SM4 mode, 8 consecutive beats are output every 32 clock cycles, which is the SM4 plaintext data window to be encrypted; if the current mode is AES mode, the pulsation controller is in a transparent transmission state.

[0035] The encryption and decryption algorithm system proposed in the present invention can be compatible with SM4 and AES encryption algorithms at the same time, realizing the configurable mode during circuit operation, and through the pipeline plus serialization design scheme, the SM4 encryption algorithm is realized while ensuring the throughput of the AES encryption algorithm, and has a higher throughput of encrypted data.

Brief Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a structural schematic diagram of a round calculation unit provided by an embodiment of the present invention;

[0038] Figure 2 is a structural schematic diagram of a round calculation unit provided by an embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram of the contents of an AES S-box provided by an embodiment of the present invention;

[0040] Figure 4 It is a schematic diagram of the contents of an S box of SM4 provided by an embodiment of the present invention;

[0041] Figure 5 is a schematic diagram of the contents of a linear relationship S-box provided by an embodiment of the present invention;

[0042] Figure 6It is a structural schematic diagram of a round calculation unit of SM4 encryption in the prior art provided by an embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of a full serial structure of an encryption and decryption algorithm system provided by an embodiment of the present invention;

[0044] Figure 8 It is a schematic diagram of the pipeline structure of an encryption and decryption algorithm system provided by an embodiment of the present invention;

[0045] Fig. 9 It is a pipeline + serial structure diagram of an encryption and decryption algorithm system provided by an embodiment of the present invention;

[0046] Fig.10 is a schematic flow chart of a round calculation process of a round calculation unit provided by an embodiment of the present invention;

[0047] Fig.11 is a flowchart of a round calculation process of a round calculation unit provided by an embodiment of the present invention;

[0048] Fig.12 It is a flowchart of a calculation process of an encryption and decryption algorithm system provided by an embodiment of the present invention;

[0049] Fig.13 It is a flowchart of a calculation process of an encryption and decryption algorithm system provided by an embodiment of the present invention;

[0050] Fig.14 It is a flowchart of a calculation process of an encryption and decryption algorithm system provided by an embodiment of the present invention. [Specific implementation method]

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] With the development of communication technology, the security of communication networks has received more and more attention. The AES encryption and decryption algorithm is an advanced encryption algorithm released by the National Institute of Standards and Technology of the United States, which is widely used in many fields; the SM4 encryption algorithm is an encryption algorithm released by the National Cryptography Administration, which is mainly used for the information security of products such as wireless LANs, and is increasingly used in China. Facing different communication devices, the communication network has diverse encryption requirements; the increase in communication network bandwidth has further increased the chip processing bandwidth, and the circuits that process encryption functions have become larger and more complex, which has increased the power consumption of the chip.

[0053] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0054] Embodiment 1:

[0055] Compared with the prior art, as shown in Example 1, the round calculation process in the encryption algorithm is redesigned in the embodiment of the present invention, a reconfigurable S-box module, a reconfigurable shift module and a reconfigurable column mixing module (referred to as S-box module, shift module and column mixing module in the embodiment of the present invention, respectively) are adopted, an input selection module is added, and an output XOR module is modified. The embodiment of the present invention proposes a round calculation unit, such as Figure 1 As shown, it includes an input selection module, a reconfigurable S-box module, a reconfigurable shift module, a reconfigurable column mixing module and an output selection module. The modules are cascade-coupled in sequence, wherein the round key processing module is connected across the input selection module and the output selection module. The above modules all have two working modes: SM4 and AES.

[0056] In various embodiments of the present invention, the working mode corresponding to the SM4 encryption algorithm is also referred to as the SM4 mode, and the working mode corresponding to the AES encryption algorithm is also referred to as the AES mode. Specifically:

[0057] For the four groups of input data X0, X1, X2, and X3, in the input selection module, when working in SM4 mode, the result obtained by XORing the three groups of input X1, X2, X3 and the SM4 round key in the input selection module is output together with X1, X2, and X3; when working in AES mode, the output of the input selection module is the same as the input, which are X0, X1, X2, and X3.

[0058] The reconfigurable S-box module includes a first S-box, a second S-box, a third S-box and a fourth S-box. When working in SM4 mode, the first S-box is configured as the S-box mode of SM4 mode, and the other three S-boxes, the second S-box, the third S-box and the fourth S-box, are configured in a linear relationship; when working in AES mode, the four S-box modules are all configured as the S-box mode of AES mode.

[0059] In the shift module, when working in SM4 mode, corresponding to the data output by the first S box, three shifted displacement data are obtained according to the preset displacement strategy, and the displacement data is XOR-processed with the data output by the first S box as a group of outputs of the shift module, wherein the three groups of data obtained from the second S box, the third S box and the fourth S box are respectively transmitted in the shift module.

[0060] When working in AES mode, after executing the corresponding AES shift operation, the shift operation result is output. Taking the input data of each S-box as 32 bits in length as an example, it is necessary to explain that when working in SM4 mode, the 32-bit output of the first S-box is shifted by 2 bits, 10 bits and 24 bits respectively (i.e., an example of the preset shift strategy), and a total of 4 groups of 32-bit data are XOR-operated, and the resulting 32 bits are used as a group of outputs of the shift module, which are not from the 32 bits output by the second S-box, the third S-box and the fourth S-box.

[0061] In the column mixing module, when working in the SM4 mode, data is transparently transmitted from the column mixing module; when working in the AES mode, the column mixing module is effective.

[0062] In the output selection module, in order to meet the XOR round key operation of AES and the XOR X0 operation at the output of SM4, the output selection module has two groups of input ports and one group of output ports; the first group of input ports of the output selection module is used to obtain 4 channel data after cascade processing by the input selection module, the reconfigurable S-box module, the shift module and the column mixing module in sequence; when working in the SM4 mode, the second group of input ports of the output selection module inputs the data X0 obtained by the round key processing module from the input selection module, and performs an XOR operation on the input ports of the two output selection modules; when working in the AES mode, the second group of input ports of the output selection module inputs the AES round key obtained by the round key processing module.

[0063] The round computing unit proposed in the embodiment of the present invention can be compatible with both SM4 and AES encryption algorithms, thereby realizing configurable modes during circuit operation. The newly designed round computing unit reuses part of the circuit resources, thereby improving the utilization efficiency of the circuit resources while being compatible with both SM4 and AES encryption algorithms.

[0064] In the embodiment of the present invention, Figure 2 As shown, the input selection module includes a selector and an input XOR module, wherein the selector includes input port 1 and input port 2, and output port 1 and output port 2, the input port 1 of the input XOR module is connected to the output port 1 of the selector, the input port 2, input port 3, and input port 4 of the input XOR module are used for inputting data X1, X2, and X3, respectively, the output port 2 of the selector is connected to the round key processing module, and is transmitted to the output selection module by the second group of input ports of the round key processing module and the output selection module, specifically:

[0065] When working in SM4 mode, the input port 1 of the selector is used to input X0, and the input port 2 of the selector is used for the SM4 round key; the output port 1 of the selector is used for the SM4 round key, and the output port 2 of the selector is used to output X0.

[0066] When working in AES mode, the input port 1 of the selector is used to input X0, and the input port 2 of the selector is used to input the AES round key; wherein, the output port 1 of the selector and the output port 2 of the selector are respectively used to transparently transmit the data of the input port 1 of the selector and the input port 2 of the selector.

[0067] In the embodiment of the present invention, the selector only works in SM4 mode; the input XOR module also only works in SM4. It is reasonable to describe both of them as input selection modules. In the example where X0 is 32-bit data, the selector implements the transposition operation of the input 32-bit data X0 and the 32-bit SM4 round key.

[0068] In combination with the embodiment of the present invention, during the implementation of the first S-box, the second S-box, the third S-box and the fourth S-box, a 32-bit length is taken as an example of the input data size of each S-box, and it is assumed that the 128-bit input of the S-box module is 4 groups of 32-bit Y0, Y1, Y2 and Y3, which correspond to the first S-box, the second S-box, the third S-box and the fourth S-box respectively, and the 128-bit output of the S-box module is 4 groups of 32-bit Z0, Z1, Z2 and Z3, wherein Y0, Y1, Y2 and Y3 correspond to the output data of the 4 output ports of the input selection module respectively, specifically:

[0069]

[0070]

[0071]

[0072]

[0073] Among them, τ sm.4 is the S-box mode conversion of the conventional SM4 mode; τ aes This is the S-box mode transformation of the conventional AES mode.

[0074] Similar to the S-box module described above, in the shift module of the embodiment of the present invention, the input data is Z0, Z1, Z2 and Z3, and the length of each group of data is 32 bits, then the intermediate variables are T0, T1, T2, T3, T4, T5 and T6, and the output of the shift module is M0, M1, M2, M3, specifically:

[0075] The AES shift operations include: T0=Z3, T1=Z3<<<2, T2=Z3<<<10, T3=Z3<<<24, T4=Z2<<<8, T5=Z1<<<16, T6=Z0<<<24; wherein the symbol <<< represents a shift operation, and the parameter value on the right side of the symbol <<< is the corresponding shift bit parameter value.

[0076]

[0077]

[0078]

[0079]

[0080] Similar to the S-box module described above, in the embodiment of the present invention, in the column mixing module involved, the input of the column mixing module is 4 groups of data M0, M1, M2, M3, and the output of the column mixing module is 4 groups of data N0, N1, N2, N3. When working in the SM4 mode, the data is transparently transmitted from the column mixing module; when working in the AES mode, the column mixing module takes effect, which is specifically manifested as follows:

[0081]

[0082]

[0083]

[0084]

[0085] Among them, σ aes This is the column mix block transform for the conventional AES mode.

[0086] In the embodiment of the present invention, in order to meet the operation of the XOR round key in the AES mode and the operation of the XOR X0 in the output of the SM4 mode, the output selection module has two groups of input interfaces, the input port 1 of the output selection module is a 128-bit data interface, and the input port 2 of the output selection module is a 128-bit round key interface; one group of output ports is a 128-bit data interface, specifically:

[0087] When working in SM4 mode, the first group of input ports of the output selection module is composed of 4 32-bit N0 / N1 / N2 / N3 data channels, and the second group of input ports of the output selection module inputs 32-bitX0 and 96-bit0; an XOR operation is performed on the input ports of the two output selection modules; when working in AES mode, the first group of input ports of the output selection module is composed of 4 32-bit N0 / N1 / N2 / N3 data channels, and the second group of input ports of the output selection module inputs 128-bit AES round keys.

[0088] Embodiment 2:

[0089] Embodiment 1 of the present invention provides a round calculation unit. Compared with embodiment 1, the embodiment of the present invention uses an instantiation, and the functional characteristics of each module included in the relatively complete device structure are described in detail (in the embodiment of the present invention, the corresponding Figure 2 In the embodiment of the present invention, the size of the input data X0, X1, X2, and X3 is directly set as 32 bits as an example to illustrate the corresponding technical content associated with Example 1. It is known to those skilled in the art that in the specific implementation process, the corresponding input data X0, X1, X2, and X3 include but are not limited to the above-mentioned 32-bit length.

[0090] Before entering the input XOR module, the input 32-bit X0 and 128-bit round key are selected and transformed according to the current encryption mode. Figure 2 As shown, the selector has two input ports and two output ports. Input port 1 is 32-bit X0 input, and input port 2 is 128-bit input; output port 1 is 32-bit output, and output port 2 is 128-bit output. The input and output relationship is shown in the following table:

[0091] Selector Port SM4 Mode AES Mode Input port 1 (32b) <![CDATA[32bit X0]]> <![CDATA[32bit X0]]> Input port 2 (128b) {32bit SM4.round key, 0, 0, 0} {128bit AES.round key} Output port 1 (32b) 32bit SM4.round key <![CDATA[32bit X0]]> Output port 2 (128b) <![CDATA[{32bit X0,0,0,0}]]> {128bit AES.round key}

[0092] The first step of SM4 encryption is to XOR the input, that is, to XOR the three sets of 32-bit input X1, X2, X3 and the 32-bit SM4 round key; for AES, this step does not exist.

[0093] When working in AES mode, the output of the input XOR module is equal to the input; when working in SM4 mode, assuming that the 128 bits of the input XOR module are 4 groups of 32 bits, that is Assume that the 128 bits output by the module is also 4 groups of 32 bits, which is It is worth noting that after passing through the selector module, X0 has become the round key SM4.rk of SM4, as shown in the following formula:

[0094]

[0095] Y2=X3

[0096] Y1=X2

[0097] Y0=X1

[0098] In the embodiment of the present invention, a reconfigurable S-box module is used to dynamically reconfigure the S-box through software according to the SM4 or AES mode; for example, the S-box can be reused. Figure 2 The round key processing module in the system is provided with the ability to interact with external control signals and to dynamically configure other reconfigurable modules.

[0099] When working in AES mode, all four S-boxes must be configured as AES S-boxes, such as Figure 3 As shown, in the specific implementation process, the data in the S box is expressed in hexadecimal. For example, if "ef" is input, the value after passing through the S box is the value of the e-th row and f-th column in the table, Sbox('ef')='df'.

[0100] When working in SM4 mode, the first S-box is configured as an S-box of SM4, such as Figure 4 As shown, in the specific implementation process, the data in the S box is expressed in hexadecimal. For example, if "ef" is input, the value after passing through the S box is the value of the eth row and fth column in the table, Sbox('ef')='84'.

[0101] The other three S-boxes, the second S-box, the third S-box, and the fourth S-box are configured in a linear relationship, such as Figure 5 shown.

[0102] Assume that the 128-bit input of the S-box module is 4 groups of 32 bits, namely (Y0, Y1, Y2, Y3), and the 128-bit output of the S-box module is also 4 groups of 32 bits, namely (Z0, Z1, Z2, Z3), as shown in the following formula:

[0103]

[0104]

[0105]

[0106]

[0107] A shift module is designed to be compatible with the row shift operation of AES and the 32-bit shift operation of SM4.

[0108] In the shift module, the input data is Z0, Z1, Z2 and Z3, and the length of each data group is 32 bits. Then, the intermediate variables are T0, T1, T2, T3, T4, T5 and T6, and the output of the shift module is M0, M1, M2, M3.

[0109] The AES shift operations include: T0=Z3, T1=Z3<<<2, T2=Z3<<<10, T3=Z3<<<24, T4=Z2<<<8, T5=Z1<<<16, T6=Z0<<<24; wherein the symbol <<< represents a shift operation, and the parameter value on the right side of the symbol <<< is the corresponding shift bit parameter value.

[0110]

[0111]

[0112]

[0113]

[0114] The column mixing module is used to meet the column mixing operation of AES. Compared with the column mixing operation in the AES encryption algorithm, it is unchanged. When working in AES mode, the module is effective; when working in SM4 mode, the module is invalid and data is transparently transmitted.

[0115] The output XOR module satisfies the XOR round key operation of the AES mode and the XOR X0 operation of the SM4 mode output. The output XOR module has two sets of input ports, input port 1 is a 128-bit data interface, and input port 2 is a 128-bit round key interface; one set of output ports is a 128-bit data interface. Under the action of the input selection module, in the AES mode, the input of input port 2 is a 128-bit AES round key; in the SM4 mode, the input of input port 2 is 32-bit X0 and 96-bit 0. After performing the XOR operation on the two input ports, the output result can meet the algorithm requirements.

[0116] Embodiment 3:

[0117] The embodiment of the present invention takes the corresponding round calculation unit in Example 2 working in AES mode as an example to illustrate the round calculation process in the redesigned encryption algorithm. In the embodiment of the present invention, the round calculation unit is also called an SM4+AES compatible round calculation unit. Correspondingly, in each module, the identification method of data input and output follows the corresponding method in Example 1 and Example 2. Figure 2 and Fig.10 As shown, including:

[0118] In step 201, the input 128-bit plaintext data is divided into 4 groups of 32-bit data, namely {X0, X1, X2, X3}, and input into the SM4+AES compatible round calculation unit input port (i.e., the input port of the input selection module in Example 1), and the current 128-bit AES.rk round key is input into the module (i.e., the input selection module in Example 1).

[0119] In step 202, the selector working mode is pre-configured as the AES mode, where the output port 1 of the selector is 32-bit X0, and the output port 2 is 128-bit AES round key AES.rk.

[0120] In the specific implementation process, 128 bits of data are usually input at a time, but the 128 bits of data are divided into 4 groups, among which the data of group X0 needs to enter this module.

[0121] In step 203, the input XOR module is pre-configured to AES mode. At this time, the input XOR module is transparently transmitted. The input of the input XOR module is {X0, X1, X2, X3}, and the output of the input XOR module is {Y0, Y1, Y2, Y3}. At this time, {Y0, Y1, Y2, Y3} is the same as {X0, X1, X2, X3}.

[0122] In step 204, all S-boxes in the S-box module are pre-configured as AES S-boxes. 128-bit data uses a total of 16 parallel S-boxes in units of 8 bits to perform a table lookup. Assuming that the input of the S-box module is {Y0, Y1, Y2, Y3}, the table lookup output is the module output {Z0, Z1, Z2, Z3}.

[0123] In step 205, the shift module is pre-configured to AES mode, and shifts four 32-bit data in sequence, cyclically shifting left by 0 bits, 8 bits, 16 bits, and 24 bits respectively. Assuming that the input of the module is {Z0, Z1, Z2, Z3} at this time, the output of the shift module is {M0, M1, M2, M3}.

[0124] In step 206, the row-column mixing module is pre-configured to the AES mode, and the input 4*32Bit data is column mixed according to the AES encryption algorithm. Assuming that the input of the module is {M0, M1, M2, M3}, the output of the shift module is {N0, N1, N2, N3}.

[0125] In step 207, output XOR processing is performed in the output selection module, and the input 4*32bit data {N0, N1, N2, N3} is bitwise XORed with the 128bit round key, and the calculation result is {P0, P1, P2, P3}. At this time, the output 4*32bit data {P0, P1, P2, P3} is the output of the round calculation result.

[0126] Embodiment 4:

[0127] The embodiment of the present invention takes the corresponding round calculation unit in Example 2 working in SM4 mode as an example to illustrate the round calculation process in the redesigned encryption algorithm. In the embodiment of the present invention, the round calculation unit is also called an SM4+AES compatible round calculation unit. Correspondingly, in each module, the identification method of data input and output follows the corresponding method in Example 1 and Example 2. Figure 2 and Fig.11 As shown, including:

[0128] In step 301, the input 128-bit plaintext data is divided into 4 groups of 32-bit data, which are {X0, X1, X2, X3} and input into the SM4+AES compatible round calculation unit input port. At the same time, the current 32-bit round key SM4.rk is modified, and 96-bit 0 is added as the low bit, and {SM4.rk, 0, 0, 0} is used as the round key input module.

[0129] In step 302, the selector working mode is pre-configured as SM4 mode. At this time, the output port 1 of the selection module is the 32-bit SM round key SM4.rk, and the output port 2 is the 128-bit {X0, 0, 0, 0}.

[0130] In step 303, the input XOR module is pre-configured to SM4 mode. At this time, the input of the input XOR module is {SM4.rk, X1, X2, X3}, and the output of the module is {Y0, Y1, Y2, Y3}, wherein the corresponding content of {Y0, Y1, Y2, Y3} is expressed as {Y, X1, X2, X3}, and Y is the result obtained by XORing the three groups of 32-bit inputs X1, X2, X3 and the 32-bit SM4 round key in the input selection module.

[0131] In step 304, the first S-box in the S-box module is pre-configured as an SM4 box, and the other three groups of variable S-boxes are input equal to output, and a table lookup is performed. Assuming that the input of the module is {Y0, Y1, Y2, Y3} at this time, the table lookup output is the output of the module {Z0, Z1, Z2, Z3}, where it can be deduced from the content in step 303 that Z1, Z2, Z3 correspond to X1, X2, X3 respectively, and the corresponding Z0 can be understood as the above-mentioned Y obtained by table lookup in the first S-box.

[0132] In step 305, the shift module is pre-configured to SM4 mode, and the highest 32 bits of data are shifted in sequence, cyclically shifting left by 0 bits, 2 bits, 10 bits, and 24 bits respectively. Assuming that the input of the module is {Z0, Z1, Z2, Z3} at this time, the output of the shift module is {M0, M1, M2, M3}, where M1, M2, and M3 correspond to X1, X2, and X3 respectively, and M0 is the result of cyclically shifting Z0 left by 0 bits, 2 bits, 10 bits, and 24 bits respectively.

[0133] In step 306, the row-column mixing module is pre-configured to SM4 mode. In SM4 mode, this column mixing mode is transparent. Assuming that the input of the module is {M0, M1, M2, M3}, the output of the shift module is {N0, N1, N2, N3}, where the contents of {N0, N1, N2, N3} and {M0, M1, M2, M3} are the same.

[0134] In step 307, output XOR processing is performed, and the input 4*32bit data {N0, N1, N2, N3} and 128bit {X0, 0, 0, 0} are bitwise XORed, and the calculation result is {P0, P1, P2, P3}. At this time, the output 4*32bit data {P0, P1, P2, P3} is the output result of one round of calculation.

[0135] Embodiment 5:

[0136] The present invention provides an encryption and decryption algorithm system based on the round calculation unit described in Embodiment 1 and Embodiment 2, which specifically includes:

[0137] The encryption and decryption system includes one or more round computing units as described in Example 1, and the number of round computing units is determined according to the computing structure adopted by the decryption system. In the embodiment of the present invention, the round computing unit is also called an SM4+AES compatible round computing unit.

[0138] The computing structures that can be adopted by the encryption and decryption algorithm system include serialized computing structure, pipeline computing structure, and pipeline plus serialized computing structure, etc. The specific computing structure to be used is determined by technical personnel in this field according to the needs of the encryption and decryption algorithm system in actual application scenarios.

[0139] Among them, a serialized computing structure is adopted, which has the characteristics of minimizing resources. In this case, based on a single round computing unit, the data is iteratively calculated, such as Figure 7 As shown; after the initial data is loaded into the SM4+AES round calculation unit, the output of the round calculation unit is used as the input of the round calculation unit for iterative calculation. After a certain number of rounds of iteration, the output of the round calculation unit is the encryption result. The algorithm and the number of iterations are shown in the following table:

[0140] Encryption Algorithm Iterations AES-128 10 AES-256 14 SM4 32

[0141] Serialized computing structures are used in application scenarios where circuit scale is strictly limited and throughput or processing power requirements are not high.

[0142] The pipeline computing structure has the characteristic of maximum throughput. By multiplexing the SM4+AES compatible round computing unit and the SM4 round computing unit, the data is encrypted. Figure 8 The AES encryption algorithm requires a maximum of 14 rounds of iterations, while the SM4 algorithm requires a fixed 32 rounds of iterations. To implement a fully pipelined encryption structure, 32 rounds of calculation units are required. Since the AES and SM4 share only the first 14 rounds of circuits, from the perspective of optimizing resources, the embodiment of the present invention also proposes a heterogeneous pipeline structure, in which the first 14 rounds use SM4+AES compatible round calculation units, and the last 18 rounds use SM4 round calculation units (such as Figure 6 The SM4 round calculation unit here is the prior art). The 14th round calculation result is output as the AES encrypted settlement result, and the 32nd round output is output as the SM4 encrypted calculation result.

[0143] The pipeline computing structure is used in scenarios where the throughput demand is greater than the circuit scale, that is, the processing capabilities of AES and SM4 must be prioritized.

[0144] The pipeline plus serialized computing structure has the characteristics of balanced circuit resources and throughput. By reusing the SM4+AES compatible round computing units, the last round of the pipeline outputs the AES encryption result and uses the first part of the round computing units for serialization; the pipeline structure uses an additional 18 rounds of SM4 round computing units. If the circuit works in AES mode, there is a waste of resources in this part of the circuit. From the perspective of balancing throughput and circuit scale, a pipeline plus serialized computing structure is proposed, such as using 14 SM4+AES compatible round computing units, or using 14 SM4+AES compatible round computing units plus 2 SM4 round computing units.

[0145] Take the example of using only 14 SM4+AES compatible round computing units. Fig. 9 When working in AES mode, for example, AES-256 encryption requires 14 rounds of calculations, so the output of the 14th round of calculations is the AES encryption output. When working in SM4 mode, a total of 32 rounds of calculations are required. The 8th round of calculation structure is iterated back to the first round of input. After a total of 4 iterations, the output of the 8th round of calculation structure is the SM4 encryption result output. An additional pulsation control circuit is also required to rectify the input data, and each output is output for 8 consecutive beats, with an output interval of 32 beats.

[0146] At this time, the processing throughput of AES is 100%, and the processing throughput of SM4 is 25%.

[0147] Take the example of using 14 SM4+AES compatible round calculation unit structures and 2 additional SM4 round calculation structures. When working in AES mode, for example, AES-256 encryption, a total of 14 rounds of calculation are required, so the 14th round calculation output is the AES encryption output. When working in SM4 mode, a total of 32 rounds of calculation are required. The 16th round calculation structure is iterated back to the first round input. After a total of 2 iterations, the output of the 16th round calculation structure is the SM4 encryption result output. The pulsation control circuit rectifies the input data, and each output is output for 16 consecutive beats, with an output interval of 32 beats.

[0148] At this time, the processing throughput of AES is 100%, and the processing throughput of SM4 is 50%.

[0149] If the requirements for throughput and circuit scale are relatively strict, this pipeline plus serialized computing structure can be considered for trade-off design.

[0150] Embodiment 6:

[0151] The embodiment of the present invention is to illustrate the serialized calculation process under the corresponding encryption and decryption algorithm system in Embodiment 5. Figure 7 and Fig.12As shown, including:

[0152] In step 401, the selector, the input XOR module, the content of the reconfigurable S-box, the reconfigurable shift module, the reconfigurable column mixing module and the output selection module are configured according to the current encryption mode.

[0153] In step 402, the 128-bit plaintext data to be encrypted and the corresponding round key are imported into the input selection module.

[0154] In step 403, the 128-bit data calculated and output by the output selection module is sent back to the selector and the input XOR module as input for the next round of calculation; and the round key calculated in the current round is updated and input to the selector.

[0155] In step 404, step 403 is repeated until the number of iterations is equal to the number of rounds in the encryption algorithm, at which point the output of the output selection module is output as the final encryption result.

[0156] Embodiment 7:

[0157] The embodiment of the present invention is to illustrate the pipeline calculation process under the corresponding encryption and decryption algorithm system in Example 5. In the embodiment of the present invention, the device compatible with the SM4 and AES encryption algorithms is referred to as the SM4+AES round calculation unit, where different individuals are presented in a corresponding numbered manner, such as SM4+AES round calculation unit 0 and SM4+AES round calculation unit 13. Figure 8 and Fig.13 As shown, including:

[0158] In step 501, the input selection module, the content of the reconfigurable S-box, the reconfigurable shift module, the reconfigurable column mixing module and the output selection module are configured according to the current encryption mode.

[0159] In step 502, the 128-bit plaintext data to be encrypted is input into SM4+AES round calculation unit 0, and the corresponding round key is input into SM4+AES round calculation units 0-13, and SM4 round calculation units 14-31.

[0160] In step 503, the round keys corresponding to other rounds are respectively input as shown in the attached Figure 8 The corresponding round computing unit is shown.

[0161] In step 504, if the configuration is AES-256 mode, the encryption result is output in the 14th round; if the configuration is AES-128 mode, the encryption result is output in the 10th round.

[0162] In step 505, if the configuration is SM4 mode, the encryption result is output in the last 32 rounds.

[0163] Embodiment 8:

[0164] The embodiment of the present invention is to illustrate the pipeline + serialized computing process with the structure of 14 SM4+AES round computing units under the corresponding encryption and decryption algorithm system in Example 5. In the embodiment of the present invention, the device compatible with the SM4 and AES encryption algorithms is referred to as the SM4+AES round computing unit, where different individuals are presented in a corresponding numbered manner, such as SM4+AES round computing unit 0 and SM4+AES round computing unit 13. At this time, it is assumed that SM4 encryption performs 4 serialized operations. Fig. 9 and Fig.14 As shown, including:

[0165] In step 601, the input selection module, the content of the reconfigurable S-box, the reconfigurable shift module, the reconfigurable column mixing module and the output selection module are configured according to the current encryption mode. Fig. 9 All SM4+AES round computing units in the process perform the initialization of step 601 above.

[0166] In step 602, if the current encryption mode is SM4 mode, the pulsation controller needs to be configured to output 8 consecutive beats every 32 clock cycles, which is the SM4 plaintext data window to be encrypted. If the current mode is AES mode, the pulsation controller is in a transparent transmission state. The output of the pulsation controller is the plaintext data to be encrypted.

[0167] In step 603, if the current mode is AES mode, the 128-bit plaintext data to be encrypted is input as shown in the attached Fig. 9 The SM4+AES round calculation unit 0 shown in the figure has a corresponding round key input as shown in the attached figure. Fig. 9 SM4+AES round calculation units 0-13 are shown.

[0168] In step 604, the round keys corresponding to the other rounds are respectively input as follows: Fig. 9 The corresponding SM4+AES round calculation units are shown.

[0169] In step 605, if the configuration is AES-256 mode, the encryption result is calculated and output in the 14th round (i.e. Fig. 9 The output of SM4+AES round calculation unit 13 is used as the encryption result); if configured as AES-128 mode, the encryption result is output in the 10th round (that is, Fig. 9 The output of SM4+AES round calculation unit 9 is used as the encryption result).

[0170] In step 606, if the current mode is SM4 mode, the 128-bit plaintext data to be encrypted and the round keys corresponding to the first 8 rounds are input as shown in the attached Fig. 9 SM4+AES round calculation units 0 to 7 are shown.

[0171] In step 607, the data output by SM4+AES round calculation unit 7 is iterated back to SM4+AES round calculation unit 0, and the keys corresponding to rounds 9 to 16 are input as shown in the attached figure. Fig. 9 SM4+AES round calculation units 0 to 7 are shown.

[0172] In step 608, the data output by SM4+AES round calculation unit 7 is iterated back to SM4+AES round calculation unit 0, and the keys corresponding to rounds 17 to 24 are input as shown in the attached figure. Fig. 9 SM4+AES round calculation units 0 to 7 are shown.

[0173] In step 609, the data output by SM4+AES round calculation unit 7 is iterated back to round calculation unit 0, and the key corresponding to rounds 25 to 32 is input as shown in the attached figure. Fig. 9 SM4+AES round calculation units 0 to 7 are shown.

[0174] In step 610, the calculation result of the SM4+AES round calculation unit 7 is output, and the output SM4 encryption result is output.

[0175] Embodiment 9:

[0176] Based on the round calculation unit described in Example 5, the present invention provides an encryption and decryption algorithm system, which adopts a pipeline calculation structure, such as Figure 8 As shown, it includes 32 round calculation units as described in Example 1, specifically including:

[0177] When used for AES encryption and decryption, each round computing unit is configured as the AES working mode, and the output of the 14th round computing unit is the output of AES encryption and decryption.

[0178] When used for SM4 encryption and decryption, each round computing unit is configured as the SM4 working mode, and the output of the 32nd round computing unit is the output of SM4 encryption and decryption.

[0179] The encryption and decryption algorithm system is compatible with both SM4 and AES encryption and decryption algorithms, while also ensuring the throughput of the algorithm.

[0180] Embodiment 10:

[0181] Based on the round calculation unit described in Example 5, the present invention provides an encryption and decryption algorithm system, which adopts a pipeline plus serialized calculation structure, such as Fig. 9 As shown, it includes 14 round calculation units as described in Example 1, specifically including:

[0182] When used for AES encryption and decryption, each round computing unit is configured as the AES working mode, and the output of the 14th round computing unit is the output of AES encryption and decryption.

[0183] When used for SM4 encryption and decryption, each round computing unit is configured as the SM4 working mode, and the input of the first round computing unit needs to be selected, and the output of the eighth round computing unit also needs to be selected. After 4 pollings, the output of the eighth round computing unit is used as the output of SM4 encryption and decryption.

[0184] The encryption and decryption system also includes a pulsation controller disposed at an input port of the system, specifically:

[0185] If the current mode is SM4 mode, 8 consecutive beats are output every 32 clock cycles, which is the SM4 plaintext data window to be encrypted; if the current mode is AES mode, the pulsation controller is in a transparent transmission state.

[0186] This embodiment avoids the waste of circuit resources by polling, and implements the SM4 encryption algorithm under the premise of ensuring the throughput of the AES encryption algorithm, with a higher throughput of encrypted data.

[0187] It is worth noting that the information interaction, execution process, etc. between the modules and units within the above-mentioned devices and systems are based on the same concept as the processing method embodiment of the present invention. The specific contents can be found in the description of the method embodiment of the present invention and will not be repeated here.

[0188] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0189] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A round calculation unit, characterized in that: It includes an input selection module, a reconfigurable S-box module, a reconfigurable shift module, a reconfigurable column mixing module and an output selection module, wherein the modules are cascade-coupled in sequence, wherein a round key processing module is connected across the input selection module and the output selection module, and the modules have two working modes: SM4 and AES; The reconfigurable S-box module includes a first S-box, a second S-box, a third S-box and a fourth S-box. Specifically, when working in the SM4 mode, the first S-box is configured as the S-box mode of the SM4 mode, and the second S-box, the third S-box and the fourth S-box are configured as a linear relationship; when working in the AES mode, the four S-box modules are all configured as the S-box mode of the AES mode; The reconfigurable shift module specifically includes: When working in SM4 mode, corresponding to the data output by the first S-box, three shifted displacement data are obtained according to the preset displacement strategy, and the displacement data is XOR-processed with the output of the first S-box as a group of outputs of the shift module, wherein the three groups of data obtained from the second S-box, the third S-box and the fourth S-box are respectively transparently transmitted in the shift module; When working in AES mode, after performing the corresponding AES shift operation, the shift operation result is output.

2. The round calculation unit according to claim 1, characterized in that The input selection module specifically includes: When working in SM4 mode, the result obtained by XORing the three groups of input X1, X2, X3 and the SM4 round key in the input selection module is output together with X1, X2 and X3; When working in AES mode, the output of the input selection module is the same as the input, which are X0, X1, X2 and X3.

3. The round calculation unit according to claim 2, characterized in that The input selection module includes a selector and an input XOR module, wherein the selector includes input port 1 and input port 2, and output port 1 and output port 2, the input port 1 of the input XOR module is connected to the output port 1 of the selector, the input port 2, input port 3, and input port 4 of the input XOR module are used for inputting data X1, X2, and X3 respectively, the output port 2 of the selector is connected to the round key processing module, and is transmitted to the output selection module by the second group of input ports of the round key processing module and the output selection module, specifically: When working in SM4 mode, the input port 1 of the selector is used to input X0, and the input port 2 of the selector is used for the SM4 round key; the output port 1 of the selector is used for the SM4 round key, and the output port 2 of the selector is used to output X0; When working in AES mode, the input port 1 of the selector is used to input X0, and the input port 2 of the selector is used to input the AES round key; wherein, the output port 1 of the selector and the output port 2 of the selector are respectively used to transparently transmit the data of the input port 1 of the selector and the input port 2 of the selector.

4. The round calculation unit according to claim 1, characterized in that The reconfigurable column mixing module specifically includes: When working in SM4 mode, data is transparently transmitted from the column mixing module; when working in AES mode, the column mixing module is effective.

5. The round calculation unit according to claim 1, characterized in that In order to meet the XOR round key operation of AES and the XOR X0 operation at the output of SM4, the output selection module has two groups of input ports and one group of output ports; the first group of input ports of the output selection module is used to obtain the 4 channel data after the input selection module, the S box module, the shift module and the column mixing module are sequentially cascaded, specifically: When working in SM4 mode, the second group of input ports of the output selection module inputs the data X0 obtained by the round key processing module from the input selection module, and performs an XOR operation on the input ports of the two output selection modules; when working in AES mode, the second group of input ports of the output selection module inputs the AES round key obtained by the round key processing module.

6. An encryption and decryption algorithm system, characterized in that: The method comprises 32 round computing units as described in any one of claims 1 to 5, specifically comprising: When used for AES encryption and decryption, each round computing unit is configured as the AES working mode, and the output of the 14th round computing unit is the output of AES encryption and decryption; When used for SM4 encryption and decryption, each round computing unit is configured as the SM4 working mode, and the output of the 32nd round computing unit is the output of SM4 encryption and decryption.

7. An encryption and decryption algorithm system, characterized in that: The invention comprises 14 round calculation units as described in any one of claims 1 to 5, specifically comprising: When used for AES encryption and decryption, each round computing unit is configured as the AES working mode, and the output of the 14th round computing unit is the output of AES encryption and decryption; When used for SM4 encryption and decryption, each round computing unit is configured as the SM4 working mode, and the input of the first round computing unit needs to be selected, and the output of the eighth round computing unit also needs to be selected. After 4 pollings, the output of the eighth round computing unit is used as the output of SM4 encryption and decryption.

8. The encryption and decryption algorithm system according to claim 7, characterized in that: It also includes a pulsation controller set at the input port of the system, specifically: If the current mode is SM4 mode, 8 consecutive beats are output every 32 clock cycles, which is the SM4 plaintext data window to be encrypted; if the current mode is AES mode, the pulsation controller is in a transparent transmission state.

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