Image sensing device

Abstract

The present disclosure relates to an image sensing device. The image sensing device may include a photoelectric conversion element, a floating diffusion region, and a transfer gate. The photoelectric conversion element may be formed in a lower region of a substrate. The floating diffusion region may be formed in an upper region of the substrate. The transfer gate may be formed in the upper region of the substrate adjacent to the floating diffusion region. The transfer gate may include a recessed electrode having a triangular cross-sectional shape.

Description

Technical Field

[0001] Embodiments of the disclosed technology relate to an image sensing device. Background Art

[0002] Image sensing devices are used in electronic devices to convert optical images into electrical signals. Recent developments in the computer and communications industries have led to an increased demand for higher-performance image sensing devices in various devices such as smartphones, digital cameras, camcorders, personal communication systems (PSCs), game consoles, security cameras, medical miniature cameras, robots, and infrared sensing devices.

[0003] CMOS image sensors are superior to other types of image sensors in terms of how they process image sensing signals. Furthermore, because CMOS manufacturing technology is used to manufacture CMOS image sensors, the CMOS image sensor and other signal processing circuits can be integrated into a single chip, enabling the production of miniaturized CMOS image sensors and low-power image sensors at lower costs. Summary of the Invention

[0004] The disclosed technology can be implemented in some exemplary embodiments to provide an image sensing device capable of improving charge transfer efficiency between a photoelectric conversion element and a floating diffusion area.

[0005] In an exemplary embodiment of the present disclosure, an image sensing device may include a photoelectric conversion element, a floating diffusion region, and a transfer gate. The photoelectric conversion element may be formed in a lower region of a substrate. The floating diffusion region may be formed in an upper region of the substrate. The transfer gate may be formed in the upper region of the substrate adjacent to the floating diffusion region. The transfer gate may include a recessed electrode having a triangular cross-sectional shape.

[0006] In an exemplary embodiment of the present disclosure, an image sensing device may include a photoelectric conversion element, a floating diffusion region, and a transfer gate. The photoelectric conversion element may be formed in a lower region of a substrate. The floating diffusion region may be formed in an upper region of the substrate. The transfer gate may include a recessed electrode and a plate-shaped electrode. The recessed electrode may be formed in the upper region of the substrate. The recessed electrode may have a first cross-sectional shape. The plate-shaped electrode may be formed on the substrate to be electrically connected to the recessed electrode. The plate-shaped electrode may have a second cross-sectional shape different from the first cross-sectional shape.

[0007] In an exemplary embodiment of the present disclosure, an image sensing device may include a photoelectric conversion element, a floating diffusion region, and a transfer gate. The photoelectric conversion element may be formed in a lower region of a substrate. The floating diffusion region may be formed in an upper region of the substrate. The transfer gate may include a first recessed electrode, a second recessed electrode, and a plate-shaped electrode. The first recessed electrode may be formed in the upper region of the substrate. The first recessed electrode may have a first cross-sectional shape. The second recessed electrode may be formed in the upper region of the substrate. The second recessed electrode may be spaced apart from the first recessed electrode. The second recessed electrode may have a second cross-sectional shape. A plate-shaped electrode may be formed on the substrate to electrically connect the first recessed electrode and the second recessed electrode. The plate-shaped electrode may have a third cross-sectional shape different from the first cross-sectional shape and the second cross-sectional shape.

[0008] In some embodiments of the disclosed technology, a transfer gate adjacent to a floating diffusion region may include a triangular or polygonal recessed electrode and a plate-shaped electrode having a cross-sectional shape different from that of the recessed electrode, thereby improving the charge transfer efficiency between the photoelectric conversion element and the floating diffusion region. Consequently, image lag may be eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of an image sensing device based on some embodiments of the disclosed technology is shown.

[0010] Figure 2 An example of a pixel array of an image sensing device based on some embodiments of the disclosed technology is shown.

[0011] Figure 3 Examples of pixel groups based on some embodiments of the disclosed technology are shown.

[0012] Figure 4 An example of a unit pixel of an image sensing device based on some embodiments of the disclosed technology is shown.

[0013] Figure 5A It is along Figure 4 A cross-sectional view taken along line AA' in FIG. Figure 5B It is along Figure 4 A cross-sectional view taken along line BB' in FIG. Figure 5C It is along Figure 4 A cross-sectional view taken along line CC' in FIG. Figure 5D It is along Figure 4 A cross-sectional view taken along line D-D' in FIG.

[0014] Figure 6A and Figure 6B It shows Figure 4 A plan view of a unit pixel PX in FIG.

[0015] Figure 7 is a plan view illustrating a unit pixel of an image sensing device according to some embodiments of the disclosed technology.

[0016] Figure 8A It is along Figure 7 A cross-sectional view taken along line AA' in FIG. Figure 8B It is along Figure 7 A cross-sectional view taken along line BB' in FIG. Figure 8C It is along Figure 7 A cross-sectional view taken along line CC' in FIG. Figure 8D It is along Figure 7 A cross-sectional view taken along line D-D' in FIG.

[0017] Figure 9A and Figure 9B It shows Figure 7 A plan view of a unit pixel PX in FIG. DETAILED DESCRIPTION

[0018] The features of the technology disclosed in this patent document are described by way of examples of image sensing devices with reference to the accompanying drawings. Although several embodiments of the disclosed technology will be discussed, the disclosed technology can be implemented in various ways beyond the details of the examples described herein.

[0019] The disclosed technology can be implemented in some embodiments to provide an image sensing device including a transfer transistor configured to improve charge transfer efficiency between a photoelectric conversion element and a floating diffusion region (FD) and prevent image lag.

[0020] In the exemplary embodiment discussed below, the first direction D1, the second direction D2, and the third direction D3 may include three directions perpendicular to each other. For example, in an XYZ coordinate system, the first direction D1 may be the X direction, the second direction D2 may be the Y direction, and the third direction D3 may be the Z direction.

[0021] Figure 1 An example of an image sensing device based on some embodiments of the disclosed technology is shown.

[0022] Reference Figure 1 , based on some implementations, an image sensing device 100 may include a pixel array 110, a correlated double sampler (CDS) 120, an analog-to-digital converter (ADC) 130, a buffer 140, a row driver 150, a timing generator 160, a control register 170, and a ramp signal generator 180. Pixel array 110 may include a plurality of image sensing pixels arranged in a matrix array. Figure 1The elements of image sensing device 100 shown are for illustration and not limitation. In other embodiments, the above elements may be combined with additional elements, or some of the above elements may be omitted.

[0023] The image sensing device 100 may include a lens (not shown). The lens may include an optical lens or a lens assembly used in conjunction with the image sensing device 100 to focus light corresponding to an image of an object, and the image processor 200 may control the lens. The image processor 200 may transmit an electrical signal corresponding to an image captured by the image sensing device 100 to an electronic device such as a display device.

[0024] The image processor 200 may include a camera controller 220, an image signal processor 210, and an interface device (e.g., a PC I / F, not shown). The camera controller 220 may be configured to control the control register 170. In some implementations, the camera controller 220 may use an integrated circuit (IC) such as an internal integrated circuit (IIC). 2 C) to control the control register 170 of the image sensing device 100. The image signal processor 210 may receive the image information as an output signal from the buffer 140. The image signal processor 210 may process the image information to improve the quality of an image corresponding to the image information for viewing on a display device.

[0025] The pixel array 110 may include a plurality of pixel groups 10 arranged in a matrix array. Each of the pixel groups 10 may include a plurality of unit pixels adjacent to each other. For example, each of the pixel groups 10 based on one embodiment of the disclosed technology may include, for example, four unit pixels arranged in a (2×2) matrix array. In another embodiment, each of the pixel groups 10 may have a (1×2) matrix array, a (2×3) matrix array, a (3×3) matrix array, or a (4×4) matrix array. Each of the unit pixels may convert an optical image into an electronic image signal. Each of the unit pixels may send an electronic image signal to the CDS 120. The pixel array 110 may include a plurality of photoelectric converter devices such as photodiodes or photodetectors to detect incident light or convert incident light into an electrical signal.

[0026] The CDS 120 may hold and sample electrical signals from pixels of the pixel array 110. For example, the CDS 120 may sample a reference voltage level and a voltage level of a received electronic image signal based on a clock signal provided from the timing generator 160. The CDS 120 may transmit an analog signal corresponding to a difference between the reference voltage level and the voltage level of the electronic image signal to the ADC 130.

[0027] The ADC 130 may convert the received analog signal into a digital signal and then transmit the digital signal to the buffer 140 .

[0028] The buffer 140 may hold or latch the received digital signal. The buffer 140 may sequentially output the latched digital signal to the image signal processor 210. The buffer 140 may include a memory configured to hold or latch the digital signal and a sense amplifier configured to amplify the digital signal.

[0029] Row driver 150 may activate pixels of pixel array 110 to detect or convert incident light based on signals provided by timing generator 160. For example, row driver 150 may generate selection signals or drive signals for selecting or activating one or more row lines.

[0030] The timing generator 160 may generate one or more timing signals for controlling the CDS 120 , the ADC 130 , the row driver 150 , and the ramp signal generator 180 .

[0031] The control register 170 may generate control signals for controlling the buffer 140, the timing generator 160, and the ramp signal generator 180. The buffer 140, the timing generator 160, and the ramp signal generator 180 may be controlled by the control signals from the control register 170. The control register 170 may be operated by the camera controller.

[0032] The ramp signal generator 180 may generate a ramp signal for processing the image signal output from the buffer 140 according to the control of the timing generator 160 .

[0033] Figure 2 shows an example of a pixel array of an image sensing device based on some embodiments of the disclosed technology, and Figure 3 Examples of pixel groups based on some embodiments of the disclosed technology are shown.

[0034] Reference Figure 2 and Figure 3 , the pixel array 110 may include pixel groups 10 sequentially arranged in a matrix array. Each of the pixel groups 10 may include a plurality of unit pixels. For example, each of the pixel groups 10 may include first to fourth unit pixels PX1 to PX4 arranged in a (2×2) matrix array.

[0035] Each of the first to fourth unit pixels PX1 to PX4 may include image sensor pixels that are physically, electrically, and / or optically isolated by an isolation structure ISO. That is, a pixel region including the first to fourth unit pixels PX1 to PX4 may be defined by the isolation structure ISO. In one implementation, the pixel regions may be isolated from one another by an isolation structure ISO formed in the substrate to a certain depth from the front or rear surface of the substrate. In another implementation, the pixel regions may be isolated from one another by an isolation structure ISO formed in the substrate from the front to the rear surface of the substrate.

[0036] Each of the first to fourth unit pixels PX1, PX2, PX3, and PX4 (pixel regions) may have a polygonal shape in a plan view. For example, each of the first to fourth unit pixels PX1, PX2, PX3, and PX4 may have a square shape. The isolation structure ISO for isolating the first to fourth unit pixels PX1, PX2, PX3, and PX4 from each other may be a grid type. The isolation structure ISO may include a trench isolation structure and a junction isolation structure, or a combination of a trench isolation structure and a junction isolation structure. The trench isolation structure may include a trench formed on a substrate and an insulating material layer formed in the trench. The junction isolation structure may include an impurity region.

[0037] Each of the first to fourth unit pixels PX1, PX2, PX3, and PX4 may include a photoelectric conversion element PD. The photoelectric conversion element PD may generate a photocurrent corresponding to the incident light. Examples of the photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination of two or more of the photodiode, phototransistor, photogate, and pinned photodiode (PPD). For example, the photoelectric conversion element PD may include a photodiode. The photodiode may include an N-type impurity region and a P-type impurity region vertically stacked in a substrate.

[0038] Each of the first to fourth unit pixels PX1, PX2, PX3, and PX4 may include a floating diffusion region FD and a tap region TAP. The floating diffusion region FD may be located at one corner of each pixel region, and the tap region may be located at another corner of each pixel region. The floating diffusion region FD and the tap region TAP may overlap with the photoelectric conversion element PD formed in each pixel region. The floating diffusion region FD and the tap region TAP may be aligned with each other in a first direction D1. The floating diffusion region FD and the tap region TAP may include an impurity region formed in a substrate. The floating diffusion region FD has a conductivity type opposite to that of the tap region TAP. For example, the floating diffusion region FD may be an N-type impurity region, and the tap region TAP may be a P-type impurity region.

[0039] In some implementations, such as Figure 2 As shown, the first unit pixel PX1 may be located in the upper left region of the pixel group 10. The first floating diffusion region FD1 of the first unit pixel PX1 may be located at the lower right corner of the first unit pixel PX1. The first tap region TAP1 of the first unit pixel PX1 may be located at the lower left corner of the first unit pixel PX1. The second unit pixel PX2 may be located in the upper right region of the pixel group 10. The second floating diffusion region FD2 of the second unit pixel PX2 may be located at the lower left corner of the second unit pixel PX2. The second tap region TAP2 of the second unit pixel PX2 may be located at the lower right corner of the second unit pixel PX2. The third unit pixel PX3 may be located in the lower left region of the pixel group 10. The third floating diffusion region FD3 of the third unit pixel PX3 may be located at the upper right corner of the third unit pixel PX3. The third tap region TAP3 of the third unit pixel PX3 may be located at the upper left corner of the third unit pixel PX3. The fourth unit pixel PX4 may be located in the lower right region of the pixel group 10.

[0040] The fourth floating diffusion area FD4 of the fourth unit pixel PX4 may be located at an upper left corner of the fourth unit pixel PX4 .

[0041] The fourth tap region TAP4 of the fourth unit pixel PX4 may be located at the upper right corner of the fourth unit pixel PX4. Therefore, the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 in the pixel group 10 may be formed adjacent to one another. Furthermore, the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be electrically connected to one another via conductive lines.

[0042] Each of the first to fourth unit pixels PX1, PX2, PX3, and PX4 may include a first pixel transistor PTR1 and a second pixel transistor PTR2. The first pixel transistor PTR1 and the second pixel transistor PTR2 may overlap the photoelectric conversion element PD. The first pixel transistor PTR1 may be spaced apart from the second pixel transistor PTR2. The first pixel transistor PTR1 may be located between the floating diffusion area FD and the tap area TAP in a first direction D1. The first pixel transistor PTR1 may include a transfer transistor Tx configured to transfer photogenerated charge carriers generated by the photoelectric conversion element PD to the floating diffusion area FD in response to a transfer signal. The second pixel transistor PTR2 may be formed adjacent to the first pixel transistor PTR1 in a second direction D2. The second pixel transistor PTR2 may include a reset transistor Rx, a drive transistor Dx, a select transistor Sx, and a conversion gain transistor DCGx. The reset transistor Rx may be configured to initialize the floating diffusion area FD in response to the reset signal. The drive transistor Dx may be configured to generate an amplified output signal Vout corresponding to the amount of photogenerated charge carriers stored in the floating diffusion region FD. The select transistor Sx may be configured to provide a current to the drive transistor Dx in response to a select signal. Figure 1 The conversion gain transistor DCGx may be configured to change the capacitance of the floating diffusion region FD in response to the conversion gain signal.

[0043] For example, the reset transistor Rx may be located at the first unit pixel PX1. The conversion gain transistor DCGx may be located at the second unit pixel PX2. The drive transistor Dx may be located at the third unit pixel PX3. The select transistor Sx may be located at the fourth unit pixel PX4. The floating diffusion region FD, the reset transistor Rx, the conversion gain transistor DCGx, the drive transistor Dx, and the select transistor Sx may be connected via Figure 3 The wires in the circuit are electrically connected to each other.

[0044] In one implementation, the conversion gain transistor DCGx may be electrically connected between the floating diffusion region FD and the reset transistor Rx. In another implementation, the floating diffusion region FD may be electrically connected between the reset transistor Rx and the conversion gain transistor DCGx.

[0045] For example, Figure 3As shown, the reset transistor Rx and the conversion gain transistor DCGx can be connected in series. The drain of the reset transistor Rx can be connected to the VDD terminal, and the source of the conversion gain transistor DCGx can be commonly connected to the first floating diffusion FD1 through the fourth floating diffusion FD4. The first transfer transistor Tx1 and the photoelectric conversion element PD, connected in series, are connected between the first floating diffusion FD1 and ground. The second transfer transistor Tx2 and the photoelectric conversion element PD, connected in series, are connected between the second floating diffusion FD2 and ground. The third transfer transistor Tx3 and the photoelectric conversion element PD, connected in series, are connected between the third floating diffusion FD3 and ground. The fourth transfer transistor Tx4 and the photoelectric conversion element PD, connected in series, are connected between the fourth floating diffusion FD4 and ground. The drain of the drive transistor Dx can be connected to the VDD terminal, and the gate of the drive transistor Dx can be connected to the connection node of the first floating diffusion FD1 through the fourth floating diffusion FD4 and the source of the conversion gain transistor DCGx. The select transistor Sx can be connected between the source of the drive transistor and the Vout terminal.

[0046] Figure 4 shows an example of a unit pixel of an image sensing device based on some embodiments of the disclosed technology, Figure 5A It is along Figure 4 A cross-sectional view taken along line AA' in FIG. Figure 5B It is along Figure 4 The cross-sectional view taken along line BB' in FIG. Figure 5C It is along Figure 4 The cross-sectional view taken along line CC' in FIG. Figure 5D It is along Figure 4 A cross-sectional view taken along line D-D' in FIG. Figure 6A and Figure 6B It shows Figure 4 A plan view of a unit pixel PX in FIG.

[0047] Reference Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D A unit pixel PX implemented based on some embodiments of the disclosed technology may include a substrate 300, a first isolation structure 306, a photoelectric conversion element PD, a well region 310, and a second isolation structure 308. The substrate 300 may have a front surface FS and a back surface BS. The first isolation structure 306 may be formed in the substrate 300 to define a pixel region. The photoelectric conversion element PD may be formed in a lower region of the substrate 300. The well region 310 may be formed in an upper region of the substrate 300. The second isolation structure 308 may be formed in the well region 310 to define a first active region 320 and a second active region 340.

[0048] The substrate 300 may include a bulk single crystal silicon wafer, a silicon-on-insulator (SOI) wafer, a compound semiconductor wafer including Si-Ge, a wafer including a silicon epitaxial layer, etc. For example, the substrate 300 may include a bulk single crystal silicon wafer doped with P-type impurities.

[0049] Although not shown in the drawings, a control circuit for controlling the unit pixel PX may be further formed on the front surface FS of the substrate 300. Figure 1 The control circuit may include a CDS 120, an ADC 130, a buffer 140, a row driver 150, a timing generator 160, a control register 170, and a ramp signal generator 180. The back surface BS of the substrate 300 may correspond to a surface configured to receive light incident on the photoelectric conversion element PD. In addition, a filter, a grid pattern, a microlens, or other structures may be formed on the back surface BS of the substrate 300.

[0050] The first isolation structure 306 can be configured to define a pixel area. In addition, the first isolation structure 306 can physically, electrically and / or optically isolate adjacent unit pixels PX from each other to prevent electrical crosstalk and / or optical crosstalk. The first isolation structure 306 can be configured to surround the pixel area. The first isolation structure 306 may include a trench isolation structure. The trench isolation structure may include a trench formed in the substrate 300 and an insulating layer formed in the trench. The insulating layer in the trench may include a single layer or a multilayer including stacked insulating layers with different properties. The insulating layer formed in the trench may include an insulating material with a certain refractive index (refractivity) to reduce or minimize optical crosstalk by preventing incident light from interfering with adjacent unit pixels PX. In addition, the insulating layer formed in the trench may include a dielectric material with a high dielectric constant having a fixed charge to prevent electrical crosstalk. In some implementations, the trench isolation structure may include a shallow trench isolation (STI) 302 and a deep trench isolation (DTI) 304. For example, first isolation structure 306 may include STI 302 contacting front surface FS of substrate 300 and DTI 304 contacting back surface of STI 302 and back surface BS of substrate 300. The width of STI 302 may be substantially equal to or greater than the width of DTI 304.

[0051] In one implementation, the first isolation structure 306 may include the STI 302 and the DTI 304. In another implementation, the first isolation structure 306 may include only the DTI 304. In one example, the first isolation structure 306 may contact the front surface FS and the back surface BS of the substrate 300 and penetrate the substrate 300. In another example, the first isolation structure 306 may contact the front surface FS of the substrate 300. The isolation structure 306 may be spaced apart from the back surface BS of the substrate 300.

[0052] The photoelectric conversion element PD in the lower region of the substrate 300 may generate a current corresponding to incident light. The photoelectric conversion element PD may include a photodiode. The photodiode may include an N-type impurity region and a P-type impurity region vertically stacked.

[0053] The well region 310 in the upper region of the substrate 300 can provide channels for the first pixel transistor PTR1 and the second pixel transistor PTR2, respectively. The well region 310 can have a rear surface that contacts the upper surface of the photoelectric conversion element PD. The well region 310 can overlap the photoelectric conversion element PD. The well region 310 may include an impurity region formed by implanting impurities into the substrate 300. For example, the well region 310 may include a P-type impurity region.

[0054] A second isolation structure 308 may be formed in the well region 310 to define a first active region 320 and a second active region 340. A first pixel transistor PTR1 may be formed in the first active region 320. A second pixel transistor PTR2 may be formed in the second active region 340. The second isolation structure 308 may extend in the first direction D1. Both ends of the second isolation structure 308 may contact the first isolation structure 306 in the first direction D1. The second isolation structure 308 may include a junction isolation structure. The junction isolation structure may include an impurity region having the same conductivity type as the well region 310. In one example, the junction isolation structure may include a P-type impurity region. The doping concentration of the junction isolation structure may be higher than the doping concentration of the well region 310.

[0055] In one implementation, the second isolation structure 308 may include a junction isolation structure. In another implementation, the second isolation structure 308 may include a trench isolation structure such as a shallow trench isolation (STI).

[0056] In addition, the unit pixel PX implemented based on some embodiments of the disclosed technology may include a first pixel transistor PTR1 and a tap region TAP formed in a first active region 320. In one example, the unit pixel PX may include a floating diffusion region FD and a tap region TAP formed in a well region 310, and a first gate 330 formed between the floating diffusion region FD and the tap region TAP. The floating diffusion region FD and the tap region TAP may be spaced apart from each other along a first direction D1. The first gate 330 may include a recessed gate. Although in 5A to 5D Although not shown in the figure, a gate insulating layer of the first gate 330 may be formed between the gate electrode and the substrate 300 .

[0057] The floating diffusion region FD may overlap one corner of the photoelectric conversion element PD. The tap region TAP may overlap another corner of the photoelectric conversion element PD. Each of the floating diffusion region FD and the tap region TAP may include an impurity region formed by implanting impurities into the substrate 300. In one example, the floating diffusion region FD may include an N-type impurity region. The tap region TAP may include a P-type impurity region. The tap region TAP may have the same conductivity type as the well region 310. The doping concentration of the tap region TAP may be higher than the doping concentration of the well region 310.

[0058] The first pixel transistor PTR1 may include Figure 3 The transfer transistor Tx in the first pixel transistor 330 is configured to transfer photogenerated charge carriers generated in the photoelectric conversion element PD to the floating diffusion area FD in response to a transfer signal as a gate signal. Therefore, the first gate 330 may include a transfer gate 330 configured to receive the transfer signal. The floating diffusion area may serve as a source of the first pixel transistor PTR1. The photoelectric conversion element PD may serve as a drain of the first pixel transistor PTR1.

[0059] The transfer gate 330 may include a recessed electrode 332 formed in the well region 310. The recessed electrode 332 may have a first cross-sectional shape that minimizes the path of photogenerated charge carriers (e.g., electrons traveling from the photoelectric conversion element PD to the floating diffusion area FD). The recessed electrode 332 may overlap the photoelectric conversion element PD. The recessed electrode 332 may have a bottom surface configured to face the upper surface of the photoelectric conversion element PD in the third direction D3. Therefore, the bottom surface of the recessed electrode 332 may be spaced apart from the upper surface of the photoelectric conversion element PD in the third direction D3. The transfer gate 330 may include a plate electrode 334. The plate electrode 334 may be formed on the substrate 300. The plate electrode 334 may be electrically connected to the recessed electrode 332. The plate electrode 334 may have a second cross-sectional shape that minimizes the path of photogenerated charge carriers (e.g., electrons traveling from the photoelectric conversion element PD to the floating diffusion area FD). The second cross-sectional shape may be different from the first cross-sectional shape. The first and second cross-sectional shapes may differ from each other to improve the transfer efficiency of photogenerated charge carriers traveling between the photoelectric conversion element PD and the floating diffusion area FD. In one embodiment of the disclosed technology, the first cross-sectional shape may be a triangle, and the second cross-sectional shape may be a polygonal shape including at least four corners. In one example, when the transfer gate 330 is formed between the tap area TAP and the floating diffusion area FD, the transfer efficiency of photogenerated charge carriers traveling from the tap area TAP may depend on the path the photogenerated charge carriers take to the floating diffusion area FD, which may vary depending on the cross-sectional shape of the recessed electrode 332. For example, when the cross-sectional shape of the recessed electrode 332 is square, photogenerated charge carriers travel from the tap area TAP to the floating diffusion area FD along the sides of the square-shaped recessed electrode 332. As a result, the photogenerated charge carriers need to travel a long distance, and the sides of the recessed electrode 332 facing the tap area TAP may act as a barrier to the flow of photogenerated charge carriers, reducing the transfer efficiency of the charge carriers. In contrast, in some embodiments of the disclosed technology, the side surfaces of the recessed electrode 332 facing the tap area TAP and the floating diffusion area FD, respectively, are not parallel to the sidewalls of the tap area TAP and the floating diffusion area FD. This prevents the side surfaces of the recessed electrode 332 from acting as barriers to the flow of photogenerated charge carriers. In one implementation, the recessed electrode 332 has a triangular cross-sectional shape to reduce the length of the path of photogenerated charge carriers flowing from the tap area TAP to the floating diffusion area FD. Furthermore, the triangular-shaped recessed electrode 332 lacks any side structures that act as barriers to the flow of photogenerated charge carriers, thereby improving charge carrier transfer efficiency and preventing image lag.

[0060] In one implementation, the first cross-sectional shape may be a triangular shape as described above. In another implementation, the first cross-sectional shape may be a Figure 6A In another embodiment, the first cross-sectional shape may be as follows: Figure 6B Trapezoidal shape shown.

[0061] In some implementations, the plate electrode 334 of the transfer gate 330 may have a polygonal cross-sectional shape including at least four corners to cover the recessed electrode 332. In some implementations, a portion of the transfer gate 330 may overlap a portion of the floating diffusion area FD to ensure a contact area between the transfer gate 330 and a conductive line for applying a transfer signal to the transfer gate 330 and to improve charge transfer efficiency.

[0062] The unit pixel PX may further include a second pixel transistor PTR2 formed in the second active region 340. In some implementations, the unit pixel PX may include a second gate 350 formed on the substrate 300, and a first junction region 352 and a second junction region 354 formed in the well region 310 on both sides of the second gate 350. The first junction region 352 and the second junction region 354 may serve as impurity regions of the second pixel transistor PTR2, such as the source and drain of the second pixel transistor PTR2, respectively. The first junction region 352 and the second junction region 354 may include N-type impurity regions.

[0063] Although 5A to 5D Although not shown, a gate insulating layer of the second gate 350 may be formed between the gate electrode and the substrate 300. In addition, the second gate 350 according to one embodiment may include a planar gate. In another embodiment, the second gate 350 may include a recessed gate, a saddle-fin gate, a fin gate, a buried gate, a vertical gate, or other gate structures.

[0064] The second pixel transistor PTR2 may include Figure 3 The reset transistor Rx shown is configured to initialize the floating diffusion area FD in response to the reset signal. Figure 3 The driving transistor Dx shown is configured to generate an amplified output signal corresponding to the amount of photogenerated charge carriers in the floating diffusion area FD. Figure 3 The output signal is transmitted to the Figure 1 The column line selection transistors Sx and Figure 3Any of the conversion gain transistors DCGx shown is configured to change the capacitance of the floating diffusion region FD in response to the conversion gain signal. For example, when the second pixel transistor PTR2 is a drive transistor Dx, the second gate 350 can be connected to the floating diffusion region FD. The first junction region 352 and the second junction region 354 can be connected to the power supply voltage node VDD and the select transistor Sx, respectively.

[0065] In some embodiments of the disclosed technology, a transfer gate 330 adjacent to the floating diffusion region FD in an image sensing device may include a recessed electrode 332 having a first cross-sectional shape (e.g., a polygonal shape including at least three corners) to improve the transfer efficiency of photogenerated charge carriers between the photoelectric conversion element PD and the floating diffusion region FD.

[0066] Figure 7 is a plan view showing a unit pixel of an image sensing device according to some embodiments of the disclosed technology, Figure 8A It is along Figure 7 A cross-sectional view taken along line AA' in FIG. Figure 8B It is along Figure 7 The cross-sectional view taken along line BB' in FIG. Figure 8C It is along Figure 7 The cross-sectional view taken along line CC' in FIG. Figure 8D It is along Figure 7 A cross-sectional view taken along line D-D' in FIG. Figure 9A and Figure 9B It shows Figure 7 A plan view of the unit pixel PX in FIG. Figure 7 and Figures 8A to 8D , elements having the same reference numerals as those described above may have the same or similar structures.

[0067] Reference Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D The unit pixel PX of the exemplary embodiment may include a substrate 300, a first isolation structure 306, a photoelectric conversion element PD, a well region 310, and a second isolation structure 308. The substrate 300 may have a front surface FS and a back surface BS. The first isolation structure 306 may be formed in the substrate 300 to define a pixel region. The photoelectric conversion element PD may be formed in a lower region of the substrate 300. The well region 310 may be formed in an upper region of the substrate 300. The second isolation structure 308 may be formed in the well region 310 to define a first active region 320 and a second active region 340.

[0068] The unit pixel PX according to some exemplary embodiments of the disclosed technology may include a first pixel transistor PTR1 and a tap region TAP formed in a first active region 320. In one example, the unit pixel PX may include a floating diffusion region FD and a tap region TAP formed in a well region 310, and a first gate 330 formed between the floating diffusion region FD and the tap region TAP. The floating diffusion region FD and the tap region TAP may be spaced apart from each other in a first direction D1. The first gate 330 may include a recessed gate. Although in Figures 8A to 8D Although not shown in the figure, a gate insulating layer of the first gate 330 may be formed between the gate electrode and the substrate 300 .

[0069] The first pixel transistor PTR1 may include a transfer transistor configured to transfer photogenerated charge carriers generated in the photoelectric conversion element PD to the floating diffusion area FD in response to a transfer signal. Therefore, the first gate 360 may include a transfer gate 360 configured to receive the transfer signal. The floating diffusion area may serve as the source of the first pixel transistor PTR1. The photoelectric conversion element PD may serve as the drain of the first pixel transistor PTR1.

[0070] The transfer gate 360 may include a first recessed electrode 362 and a second recessed electrode 364. The first recessed electrode 362 is formed in the well region 310. The first recessed electrode 362 may have a first cross-sectional shape. The second recessed electrode 364 may be spaced apart from the first recessed electrode 362. The second recessed electrode 364 may have a second cross-sectional shape. To effectively improve the transmission efficiency of photogenerated charge carriers moving from the tap region TAP, the first recessed electrode 362 and the second recessed electrode 364 may be spaced apart from each other in the second direction D2. The first recessed electrode 362 and the second recessed electrode 364 may overlap the photoelectric conversion element PD. Each of the first recessed electrode 362 and the second recessed electrode 364 may have a bottom surface configured to face the upper surface of the photoelectric conversion element PD in the third direction D3. Therefore, the rear surface of each of the first recessed electrode 362 and the second recessed electrode 364 may be spaced apart from the upper surface of the photoelectric conversion element PD. The first recessed electrode 362 and the second recessed electrode 364 are formed in the third direction D3. The transfer gate 360 may include a plate electrode 366. The plate electrode 366 may be formed on the substrate 300 to electrically connect the first recessed electrode 362 and the second recessed electrode 364. The plate electrode 366 may have a third cross-sectional shape that is different from the first cross-sectional shape and the second cross-sectional shape. The first cross-sectional shape, the second cross-sectional shape, and the third cross-sectional shape may be different from each other to improve the transmission efficiency of photogenerated charge carriers between the photoelectric conversion element PD and the floating diffusion region FD. For example, the first cross-sectional shape and the second cross-sectional shape may be polygonal shapes including at least four corners. In some implementations, each of the first cross-sectional shape and the second cross-sectional shape may include any one of a triangular shape, a rhombus shape, and a trapezoidal shape. However, the first cross-sectional shape and the second cross-sectional shape may be different from each other. For example, the first cross-sectional shape may be a triangular shape, and the second cross-sectional shape may be a rhombus shape.

[0071] In some exemplary embodiments of the disclosed technology, each of the first cross-sectional shape and the second cross-sectional shape may include any one of a triangular shape, a rhombus shape, and a trapezoidal shape, and the first cross-sectional shape and the second cross-sectional shape may be different from each other. In other embodiments of the disclosed technology, such as Figure 9A As shown, each of the first cross-sectional shape and the second cross-sectional shape may include any one of a triangular shape, a rhombus shape, and a trapezoidal shape, and the first cross-sectional shape may be substantially the same as the second cross-sectional shape. The area of the first cross-sectional shape may be substantially the same as the area of the second cross-sectional shape. In addition, the first cross-sectional shape may be symmetrical with the second cross-sectional shape. Alternatively, as Figure 9BAs shown, each of the first cross-sectional shape and the second cross-sectional shape may include any one of a triangle, a rhombus, and a trapezoid, and the first cross-sectional shape may be substantially the same as the second cross-sectional shape. The area of the first cross-sectional shape may be different from the area of the second cross-sectional shape. In addition, unlike the above example, the first cross-sectional shape is asymmetrical to the second cross-sectional shape.

[0072] The plate-shaped electrode 366 of the transfer gate 360, which has a polygonal cross-sectional shape including at least four corners, may cover the first recessed electrode 362 and the second recessed electrode 364. In some implementations, a portion of the transfer gate 360 may overlap a portion of the floating diffusion region FD to ensure a contact area between the transfer gate 360 and a conductive line for applying a transfer signal to the transfer gate 360 and to improve charge transfer efficiency.

[0073] The unit pixel PX may further include a second pixel transistor PTR2 formed in the second active region 340. In some implementations, the unit pixel PX may include a second gate 350 formed on the substrate 300, and a first junction region 352 and a second junction region 354 formed in the well region 310 on both sides of the second gate 350. The first junction region 352 and the second junction region 354 may serve as impurity regions of the second pixel transistor PTR2, such as the source and the drain of the second pixel transistor PTR2, respectively. The first junction region 352 and the second junction region 354 may include N-type impurity regions. Although in Figures 8A to 8D Although not shown in the figure, a gate insulating layer of the second gate 350 may be formed between the gate electrode and the substrate 300 .

[0074] In some embodiments of the disclosed technology, a transfer gate 360 adjacent to a floating diffusion region may include a first recessed electrode 362 having a first cross-sectional shape and a second recessed electrode 364 having a second cross-sectional shape. The first cross-sectional shape may be any one of a triangular shape, a rhombus shape, and a trapezoidal shape, and the second cross-sectional shape may be any one of a triangular shape, a rhombus shape, and a trapezoidal shape. Thus, the transfer efficiency of photogenerated charge carriers between the photoelectric conversion element PD and the floating diffusion region FD may be improved.

[0075] In addition, the first recess electrode 362 may be spaced apart from the second recess electrode 364 to further improve the transfer efficiency of photogenerated charge carriers between the photoelectric conversion element PD and the floating diffusion area FD.

[0076] Only limited examples of implementations or embodiments of the disclosed technology are described or illustrated. Based on the content disclosed and illustrated in this patent document, the disclosed implementations or embodiments may be modified and enhanced, and other implementations or embodiments are also possible.

[0077] CROSS-REFERENCE TO RELATED APPLICATIONS

[0078] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0029831, filed on March 8, 2021, which is hereby incorporated by reference herein in its entirety.

Claims

1. An image sensing device, comprising: a substrate comprising an upper region and a lower region; a photoelectric conversion element configured to convert light into electric charge and formed in the lower region of the substrate; a tap region formed in the upper region of the substrate; a floating diffusion region formed in the upper region of the substrate to receive the charge from the photoelectric conversion element; as well as a transfer gate coupled between the floating diffusion region and the photoelectric conversion element to transfer the charge from the photoelectric conversion element to the floating diffusion region, wherein the transmission gate is arranged between the tap region and the floating diffusion region, Wherein, the transmission gate comprises: a first recessed electrode formed in the upper region of the substrate and configured to have a first cross-sectional shape; a second recessed electrode spaced apart from the first recessed electrode in the upper region of the substrate and configured to have a second cross-sectional shape; and a plate-shaped electrode formed on the substrate and electrically connected to the first recessed electrode and the second recessed electrode, and configured to have a third cross-sectional shape different from the first cross-sectional shape and the second cross-sectional shape, wherein each of the first cross-sectional shape and the second cross-sectional shape is a triangle shape, a rhombus shape or a trapezoidal shape, and The first cross-sectional shape to the third cross-sectional shape are cut in a direction parallel to the substrate. wherein the tap region, the transfer gate, and the floating diffusion region are aligned with each other in a first direction, and the first recessed electrode is spaced apart from the second recessed electrode in a second direction perpendicular to the first direction, and Wherein, sides of each of the first cross-sectional shape and the second cross-sectional shape facing the tap region and the floating diffusion region respectively are not parallel to sidewalls of the tap region and the floating diffusion region.

2. The image sensing device according to claim 1, wherein The first cross-sectional shape is the same as the second cross-sectional shape.

3. The image sensing device according to claim 1, wherein The first cross-sectional shape is different from the second cross-sectional shape.

4. The image sensing device according to claim 1, wherein The third cross-sectional shape has a polygonal shape including at least four corners.

5. The image sensing device according to claim 1, wherein The floating diffusion region is configured to overlap with one corner of the photoelectric conversion element, and the tap region is configured to overlap with the other corner of the photoelectric conversion element facing the one corner.

6. The image sensing device according to claim 1, wherein The plate electrode is configured to cover the first recess electrode and the second recess electrode, and a portion of the plate electrode is configured to overlap a portion of the floating diffusion area.

7. The image sensing device according to claim 1, wherein: The first recess electrode and the second recess electrode are configured to overlap with the photoelectric conversion element, and have bottom surfaces spaced apart from an upper surface of the photoelectric conversion element.

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