Processor and system for automatic fusion of matrix multiplication and reduction operations

Abstract

Apparatuses, systems, and techniques for performing matrix multiplication with reduction fusion using a graphics processing unit. In at least one embodiment, one or more circuits multiply two or more sub-portions of one or more matrices and generate two or more vectors from the multiplication using two or more parallel operations.

Description

TECHNICAL FIELD

[0001] At least one embodiment is directed to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment is directed to operations performed on graphics processing units and operations including matrix multiplication and reductions encountered in training and using neural networks in accordance with various new techniques described herein. BACKGROUND

[0002] Artificial neural networks, such as deep neural networks having multiple layers of neurons, generally involve operations that use matrix multiplication operations. Matrix multiplication involves performing repetitive arithmetic operations (multiplication and addition) on the same matrix elements. For example, during multiplication of two N x N matrices, any given element in each of the two input matrices becomes part of the computation of N output elements in the result matrix. Thus, computing matrix multiplication on a single core central processing unit (CPU) involves a huge overhead in which the same matrix elements are loaded multiple times. Thus, the speed of loading becomes a “bottleneck” of processing when multiplying matrices, which prevents even a high-speed CPU from realizing its full computational potential. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 is an example computing device in which matrix multiplication fused with reductions can be performed using a multi-core graphics processing unit (GPU) in accordance with at least one embodiment;

[0004] Figure 2 A plurality of sub-portions (tiles) are shown that can be used to represent input and output matrices in a plurality of loops of a matrix multiplication fused with reductions (MMFR) operation performed by a multi-core GPU in accordance with at least one embodiment;

[0005] Figure 3A Basic elements of a matrix multiply-accumulate (MMA) operation are shown that use tile representations of input and output matrices and can be implemented in a MMFR operation performed by a multi-core GPU in accordance with at least one embodiment;

[0006] Figure 3B A first operation of the MMA in is depicted that shows the use of tile representations of input and output matrices and as can be implemented in a MMFR operation performed by a multi-core GPU in accordance with at least one embodiment; Figure 3A

[0007] A second operation of the MMA in is depicted; Figure 3C Figure 3A

[0008] Figure 3D A third operation of the MMA in is depicted that shows the use of tile representations of input and output matrices and as can be implemented in a MMFR operation performed by a multi-core GPU in accordance with at least one embodiment;​​ Figure 3A-3B An example of a matrix multiplication fused with a reduce operation illustrating the use of block representations in the input and output matrices, and as may be implemented in an MMFR operation performed by a multi-core GPU;

[0009] Figure 4A illustrates GPU thread ownership of individual matrix elements in input and output matrices during MMFR execution on a multi-core GPU according to one embodiment;

[0010] Figure 4B illustrates the reallocation of thread ownership of individual matrix elements of an output matrix during MMFR execution on a multi-core GPU according to one embodiment;

[0011] Figure 4C shows a reduction operation fused with a matrix multiplication during MMFR execution on a multi-core GPU according to one embodiment;

[0012] Figure 5 is a flow chart of an example method for performing matrix multiplication fused with reduction using a multi-core graphics processing unit (GPU) in accordance with at least one embodiment;

[0013] Figure 6 is the use according to at least one embodiment Figure 2 Flowchart of another example method 600 of performing matrix multiplication fused with reduction using a multi-core GPU for multiple blocks shown in FIG;

[0014] Figure 7A Inference and / or training logic according to at least one embodiment is shown;

[0015] Figure 7B Inference and / or training logic according to at least one embodiment is shown;

[0016] Figure 8 illustrates the training and deployment of a neural network according to at least one embodiment;

[0017] Figure 9 An example data center system is shown in accordance with at least one embodiment;

[0018] Figure 10A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 10B According to at least one embodiment, Figure 10A Examples of camera positions and fields of view for autonomous vehicles;

[0020] Figure 10C According to at least one embodiment Figure 10Aa block diagram of an example system architecture of an autonomous vehicle;

[0021] Figure 10D is a diagram illustrating a system for communication between one or more cloud-based servers and an autonomous vehicle in accordance with at least one embodiment; Figure 10A

[0022] Figure 11 is a block diagram illustrating a computer system in accordance with at least one embodiment;

[0023] Figure 12 is a block diagram illustrating a computer system in accordance with at least one embodiment;

[0024] Figure 13 illustrates a computer system in accordance with at least one embodiment;

[0025] Figure 14 illustrates a computer system in accordance with at least one embodiment;

[0026] Figure 15A illustrates a computer system in accordance with at least one embodiment;

[0027] Figure 15B illustrates a computer system in accordance with at least one embodiment;

[0028] Figure 15C illustrates a computer system in accordance with at least one embodiment;

[0029] Figure 15D illustrates a computer system in accordance with at least one embodiment;

[0030] Figure 15E and Figure 15F illustrates a shared programming model in accordance with at least one embodiment;

[0031] Figure 16 illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0032] Figures 17A-17B illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0033] Figures 18A-18B illustrates additional exemplary graphics processor logic in accordance with at least one embodiment;

[0034] Figure 19 illustrates a computer system in accordance with at least one embodiment;

[0035] Figure 20A illustrates a parallel processor in accordance with at least one embodiment; ​

[0036] Figure 20B shows a partition unit according to at least one embodiment;

[0037] Figure 20C illustrates a processing cluster according to at least one embodiment;

[0038] Figure 20D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0039] Figure 21 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0040] Figure 22 A graphics processor according to at least one embodiment is shown;

[0041] Figure 23 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 24 A deep learning application processor according to at least one embodiment is shown;

[0043] Figure 25 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0044] Figure 26 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0047] Figure 29 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0048] Figure 30 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figures 31A-31B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0050] Figure 32 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0051] Figure 33illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0052] Figure 34 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0053] Figure 35 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0054] Figure 36 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0055] Figure 37 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment; DETAILED DESCRIPTION

[0056] Matrix multiplication fused with reduction

[0057] Figure 1 is an example computing device 100 in accordance with at least one embodiment in which matrix multiplication fused with reduction may be performed using a multi-core graphics processing unit (GPU 110). The reduction operation performed after the matrix multiplication operation may include converting the output matrix into a vector by summing all elements of the output matrix in each column (row), selecting a minimum (maximum) element from each column (row), and so on. The matrix multiplication fused with reduction (MMFR) operation may be performed in conjunction with an application using a neural network (e.g., implemented by a neural network engine 120). In at least one embodiment, the MMFR operation may be performed by a combination of software instructions provided by a matrix multiplication and reduction module (MRM) 125 and hardware instructions implemented as part of an instruction set architecture (ISA) of the GPU 110. In at least one embodiment, the GPU 110 includes a plurality of cores 111, each core capable of executing multiple threads (not shown). In at least one embodiment, the cores 111 may include one or more Tensor Core Unit (TCU). Each core can run multiple threads 112 concurrently (e.g., in parallel). In at least one embodiment, threads 112 can access registers 113. Registers 113 can be thread-specific registers, and access rights to the registers are limited to the respective threads. In addition, all threads in the core can access shared registers 114. In at least one embodiment, each core 111 can include a scheduler 115 for distributing computing tasks and processes among different threads 112 in the core 111. The dispatch unit 116 can use the correct dedicated registers 113 and shared registers 114 to execute the scheduled tasks on the appropriate thread. The computing device 100 may include one or more input / output components 140 to facilitate information exchange with one or more users or developers.

[0058] In at least one embodiment, GPU 110 may have a cache 118 to which multiple cores 111 may share access. Furthermore, computing device 100 may include GPU memory 119, where GPU 110 may store intermediate and / or final results (outputs) of computations performed by GPU 110. After completing a particular task, GPU 110 (or CPU 130) may migrate the outputs to main memory 132. In at least one embodiment, CPU 130 may execute processes involving a large number of serial computational tasks (assigned by neural network engine 120), while GPU 110 may execute tasks involving parallel processing (such as matrix multiplication and reduction). In at least one embodiment, neural network engine 120 may determine which processes will be executed on GPU 110 and which processes will be executed on CPU 130. In other embodiments, CPU 110 may determine which processes will be executed on GPU 110 and which processes will be executed on CPU 130. In at least one embodiment, the MRM 125 may execute one or more kernels on the GPU 110 to perform matrix multiplication P=A×B+C, and / or matrix reduction Red[D], for example, one or more fused MMFR operations such as Red[A×B+C]. The MMFR operations may be performed using multiple loops (hierarchical iterations). Each loop may represent the input matrix (e.g., A and B) by multiple sub-parts of one or more matrices or reduced-size matrix blocks. For example, the outer loop may represent the input matrix by the largest block (e.g., grid-level block), while the innermost loop may represent the input matrix by the smallest block. Here, the outermost loop is referred to as the first loop, and the innermost loop is referred to as the last loop. There may be any total number of loops. In at least one embodiment, the last loop is implemented by hardware instructions executed by one or more threads 112 in one or more cores 111. The remaining loops may be implemented by software instructions of the MRM 125.

[0059] Figure 2 A plurality of tiles 200 are shown that may be used to represent input and output matrices in multiple cycles of an MMFR operation performed by a multi-core GPU, in accordance with at least one embodiment. Figure 2Five loops (and five different block sizes) are shown, but in other embodiments any other number of loops (greater than five or less than five) may be used. In the described embodiment, the input matrix is ​​represented in the first (outermost) loop by grid blocks (grid-level blocks) 210. In the second loop, the grid blocks 210 are represented as block blocks 220. In at least one embodiment, the block blocks 220 can be 128×128 blocks, for example, blocks with 128 elements in each row and each column. The block blocks 220 can be calculated using a block-level matrix multiply-accumulate (MMA) operation. In at least one embodiment, the block-level MMA operation determines the block blocks 220 by one or more 128×128×32 MMA operations, which is a shorthand way of expressing an operation involving the multiplication of a 128×32 matrix by a 32×128 matrix.

[0060] In at least one embodiment, in the next (third) level of loop, each block 220 may be represented as multiple warp blocks 230. In at least one embodiment, the warp blocks 230 may be 64×64 blocks. Each warp block 230 may be computed using warp-level multiplication operations (MMA). In at least one embodiment, the warp-level MMA operations determine each warp block via one or more 64×64×32 MMA operations, each of which involves multiplying a 64×32 matrix by a 32×64 matrix.

[0061] In at least one embodiment, in the fourth loop, each warp block 230 may be represented as multiple macro MMA blocks 240. In at least one embodiment, the macro MMA blocks 240 may be 16×16 blocks. The macro MMA blocks 240 may be computed using macro MMA operations. In at least one embodiment, the macro MMA operations determine the macro MMA blocks using one or more 16×16×8 matrix multiplications, including multiplications of a 16×8 matrix by an 8×16 matrix.

[0062] In at least one embodiment, in a fifth (and final) loop, each macro MMA tile 240 can be represented as four quad pairs 250, each quad pair (QP) computing an 8x8 tile in macro MMA tile 240 (which can be further decomposed into two 8x4 element tiles). In at least one embodiment, each QP can be computed using a hardware instruction of GPU microarchitecture, e.g., an 8x8x4 MMA operation. Hardware instruction can be implemented by 8 GPU threads, such that a complete macro MMA tile 240 is computed by 32 GPU threads. 8x8x4 MMA hardware instruction of macro architecture should be understood as exemplary, as in various possible embodiments, any other MMA hardware with a predetermined dimension m x n x p of software instruction can be used instead, as can be implemented in any hardware processing unit (GPU, CPU, etc.) or through any software logic.

[0063] As described in more detail below, in at least one embodiment, one or more fused reduction operations can be performed in each hierarchical loop. Row-wise reductions are indicated with arrows. (In certain embodiments, reduction for a fifth loop is not depicted and can not be performed.) Fourth loop reduction is indicated with solid arrows across top rows in macro MMA 240, third loop reduction is indicated with dashed arrows across top rows (including macro MMA tiles) in warp bundle tiles 230, second loop reduction is indicated with dotted-dashed arrows across top rows (including warp bundle tiles) in block tiles 220, and first loop reduction is indicated with open arrows across top rows (including block tiles) in grid tiles 210. Similar reductions can be performed on all other rows (or columns) or across only certain rows (or columns).

[0064] Advantages of using fused reduction to compute MMFR operations in multiple hierarchical loops include, without limitation, performing reduction operations (e.g., sum across rows or columns) while individual elements in product matrix A x B are still loaded in registers accessible by GPU threads that have performed matrix multiplication.

[0065] Matrix dimensions of tiles and operations used to compute individual tiles are for example purposes only. In at least one embodiment, dimensions of certain tiles can be different. In various embodiments, dimensions of all tiles can be different. In at least one embodiment, some or all tiles can be non-square (e.g., rectangular). Similarly, dimensions of matrices used as input to hardware instructions can also be different. In at least one embodiment, all hierarchical loops are performed using software instructions.

[0066] Figure 3AThe basic elements of a matrix multiply-accumulate operation 300 according to at least one embodiment are shown, which uses a block representation of the input and output matrices and can be implemented in an MMFR operation executed by a multi-core GPU. A naive implementation of the multiplication of two N×N matrices A and B (C=A×B) is as follows, according to the standard mathematical formula,

[0067]

[0068] In the output matrix N 2 The computation of each of the elements involves loading N elements from each of the input matrices (2N memory operations). The number of operations can be greatly reduced if a block representation of the input matrices is used. Figure 3A Shown is the decomposition of two 4×4 matrices A and B into 2×2 blocks (subparts) of their respective matrices A and B: upper left (UL), upper right (UR), lower left (DL), and lower right (DR). Figure 3A As shown in , the upper left block of the output matrix C can be calculated as

[0069] C UL =A UL ×B UL +A UR ×B LL .

[0070] Therefore, the upper left block C of the output matrix UL The computation of can be performed using two MMA operations on a 2×2 matrix, using non-overlapping sets of elements in the input matrix, and can be performed in parallel (followed by a serial operation that adds the results of the two operations).

[0071] Figure 3B Depicted is a diagram according to at least one embodiment Figure 3A The first operation 310 of the MMA 300 in FIG. 310 illustrates the use of block representations of input and output matrices as may be implemented in an MMFR operation performed by a multi-core GPU. The first operation 310 converts A UL and B UL The multiplication is performed as a standard 2×2 matrix multiplication and the four output values ​​are stored in C UL accumulator.

[0072] C UL =A UL ×B UL .

[0073] It clearly shows that the accumulator matrix C UL elements.

[0074] Figure 3C Depicts Figure 3Athe second operation 320 of the MMA 300 in FIG. 3. Operation 320 similarly multiplies A UR and B DL as the multiplication of a standard 2x2 matrix and adds the four output values into the accumulator block C UL .

[0075] C UL = C UL + A UR x B DL .

[0076] The elements in the product A UR x B DL are clearly shown. By adding the values of the matrix elements of this product to the elements of this accumulator block, the correct values of the elements in the upper left block of the output matrix C are obtained.

[0077] A similar MMFR operation can be performed using n x n blocks to represent N x N input and output matrices: i = nr + a, j = ns + m, k = nt + b, where the indices r, t, s (0 < r, t, s < N / n - 1) are the enumerated block numbers and the Greek indices a, b, m (0 < a, b, m < n - 1) are the enumerated elements within the block. Thus, a matrix element A nr+α，ns+μ may be represented as the element (a, m) in the block (r, s): e.g., A nr+α，ns+μ = (A rs ) αμ . The sum of matrix elements can be computed as the sum of the elements in the block and the sum of the blocks. Because the summation operations are commutative (can be performed in different orders),

[0078]

[0079] The output matrix can be obtained by (1) computing the matrix product of the input matrices with reduced dimension N / n x N / n, treating the blocks as "super-elements" of the input matrices, and (2) computing the n x n product of the respective super-elements according to the rules of matrix multiplication.

[0080] The multiplication of the matrix C = A x B with the reduction fusion of the product C can be performed in a similar manner. For example, the first row reduction operation, (or in symbolic form, R = Red[C]), can be determined by summing over both the block index r and the element index a (both together determine the index of a matrix element, i = nr + a) according to the identity of the last equation in the previous paragraph:

[0081]

[0082] Therefore, the reduction fused with matrix multiplication can be performed by: (1) performing the reduction on each block product (i.e., α-summation), (2) summing the block products to represent the complete output matrix (s-summation), and (3) performing output matrix-level reduction by summing the blocks for each row (r-summation).

[0083] Figure 3D Depicted is a method based on at least one embodiment of Figures 3A-3B Example matrix multiplication fused with a reduce operation 330 illustrating the use of block representations of input and output matrices as may be implemented in an MMFR operation performed on a multi-core GPU. Depicted is a reduce operation performed on the top two rows of the output matrix C. Shown is the product A UL ×B UL and A UR ×B DL (This determines the upper left block C of the output matrix UL ) and the product A UL ×B UR and A UR ×B DR (This determines the upper right block C of the output matrix UR ). Row reduction is equivalent to the sum of all elements in each row of the matrix (or the matrix block). The output of row reduction is a column vector of dimension N×1. To obtain the block C UL The row reduction of the column vector Red[A UL ×B UL and Red[A UR ×B DL ] are added together. To obtain block C UR The row reduction of the column vector Red[A UL ×B UR ] and Red[A UR ×B DR ] are added together. Finally, to obtain the row-wise reduction of the entire output matrix C, Figure 3D All four column vectors in are added together. From the direct summation, we can see that the two elements of the resulting 2×1 vector are the same as and The reduction of the bottom two rows of the output matrix C can also be performed in a similar way.

[0084] The same or similar operations can be performed on matrices of dimensions other than 4×4, including rectangular matrices M×N. Row-wise reduction operations can also be performed. Perform the same or similar operations. MMFR operations involving any number of loops (and correspondingly any number of intermediate blocking levels) can also be performed in a similar manner, performing a corresponding reduction operation at each blocking level after performing computations on the elements of that blocking.

[0085] Figures 4A-4C An implementation of matrix multiplication fused with reduction operations using a multi-core GPU is shown, in accordance with at least some embodiments. Figure 4A 4. GPU thread ownership 400 of individual matrix elements in input and output matrices during MMFR execution on a multi-core GPU according to one embodiment is shown. For ease of illustration, an embodiment of computing macro MMA tiles 240 is shown, but tiles of any other dimensions can be similarly computed. In at least one embodiment, the input matrices can be a 16×8 matrix (A) and an 8×16 matrix (B), while the output matrix can be a 16×16 macro MMA tile matrix (C). The computation can be performed in parallel by 32 GPU threads (e.g., thread 112). Each GPU thread can own a certain number of elements in each matrix. Thread ownership means that each GPU thread loads multiple elements of each input matrix into a (dedicated) register (e.g., register 113) of a specific thread and also stores the corresponding elements in shared memory (e.g., shared register 114) so ​​that the input matrix elements can be accessed by other threads. Figure 4A The ownership distribution of elements in input matrix A and input matrix B among 32 GPU threads is shown. Specifically, the first 4 elements of row 0 of input matrix A are owned by thread 0, while the last 4 elements of row 7 of input matrix A are owned by thread 15, and so on. Similarly, the first 4 elements of column 1 of input matrix B are owned by thread 1, while the last 4 elements of column 15 of input matrix B are owned by thread 31, and so on. In the embodiment shown, each thread owns 4 matrix elements of input matrix A and 4 matrix elements of input matrix B.

[0086] In at least one embodiment, Figure 4A The ownership allocation of the elements of the input matrix shown can be predicted based on the specific GPU architecture. For example, each GPU thread can access two registers 113 or two banks of shared registers 114 at a time per GPU core clock cycle. Therefore, if Figure 4A The allocation of ownership shown ensures that no thread must access the same bank twice per clock cycle. Figure 4A The ownership described in is exemplary, and many other allocation schemes may be used instead.

[0087] In at least one embodiment, it involves the execution of an MMFR operation and Figures 4A-4C The GPU threads shown in FIG4 may also own some elements of the output matrix C. In at least one embodiment shown, each thread owns 8 elements of the 16×16 output matrix C. For example, thread 4 may own the following elements of the output matrix C: C 40 、C 41 、C 44 、C 45 、C 60 、C 61 、C 64 、C 65 .

[0088] The threads involved in the MMFR operation can be grouped together to execute on the GPU cores. For example, Figure 4A The 32 threads shown in FIG and performing macro MMA 16×16×8 operations to compute a macro MMA block 240 (e.g., a 16×16 block of the output matrix C) can be divided into four quad pairs (QPs). For example, a first QP1 can include threads 0…3 and threads 16…19, a second QP2 can include threads 4…7 and threads 20…23, a third QP3 can include threads 8…11 and threads 24…27, and a fourth QP4 can include threads 12…15 and threads 28…31. Each QP can compute a quarter of the output block C. In at least one embodiment, the portion computed by each thread can include two 8×4 blocks of the output matrix C, as shown in FIG. Figure 4A As shown, the bottom pane. In at least one embodiment, the respective tiles may be computed by hardware MMA 8×8×4 instructions. The input to each hardware MMA 8×8×4 instruction may be the 8×4 region (composed of two 4×4 tiles) associated with the corresponding QP in input matrix A, and the 4×8 tiles associated with the same QP in input matrix B. For example, the arguments to the hardware MMA 8×8×4 instruction to be executed by QP1 may be the 8×4 region (composed of two 4×4 tiles) associated with threads 0…3 and 16…19 (and in Figure 4A The 8 half rows of the input matrix A (and the 8 half columns of the input matrix B) are identified by the label “QP1” in the figure, and the output instruction of the hardware MMA8×8×4 can be the 8×8 part of the output matrix C (composed of two 8×4 blocks), as shown in the figure.

[0089] In at least one embodiment, a GPU thread may have elements of the output matrix C such as Figure 4AAs shown, and the respective elements are provided (loaded) during upstream computation of a larger block, such as a warp block 230, a block block 220, a grid block 210, or any other block that can be programmed by the MRM 125 or any other software module responsible for block matrix multiplication. For example, a 64×64 warp block 230 can be computed using multiple (e.g., 16) macro MMA 16×16×8 operations that make up a larger 64×64×32 operation. In the next cycle, a 128×128 block block 220 can be computed using multiple (e.g., four) 64×64×32 operations that make up a larger 128×128×32 operation, and so on, until a maximum predetermined block size is reached. The maximum block size can vary depending on the embodiment and / or task being solved (which specifies the size of the matrix to be multiplied). In at least one embodiment, the grid block 210 can be the largest block size, for example, 256×256. In some embodiments, the grid tiles 220 may be larger in size, for example, 512×512 or 512×256 or any other size. If the size of the input matrix is ​​not a multiple of the grid tiles, the input matrix may be padded with zeros until the input matrix is ​​a multiple of the grid tiles. If the size of the input matrix is ​​smaller than the size of the grid tiles, the MRM 125 may use the block tiles as the largest size tiles, and so on.

[0090] In order to fuse the reduction operations with the computation of blocks of different (increasing) sizes, the MRM 125 can perform additional operations on each computation cycle (block level). QP-level, warp-level, and block-level reductions can be performed by the same (first) kernel. At the grid level, in at least one embodiment, the final reduction can involve synchronization of all blocks (e.g., threads in the grid) and can therefore be performed by a separate (second) kernel to achieve such synchronization at a global level. Specifically, the second kernel can reduce the results of the different block computations to obtain the final reduction result. For example, if the MMFR operation is of size M×N×K, the M×N output matrix can be reduced by reallocating the reduction dimensions across P blocks, and the fused kernel can store the block-level reduction results as block matrices of M×P or P×N shape, depending on whether the reduction is performed in row form or column form. The second grid-level reduction kernel can then perform the block-level reduction to an M×1 column vector or a 1×N row vector.

[0091] Figure 4B Illustrated is the reallocation 410 of thread ownership of individual matrix elements of an output matrix during MMFR execution on a multi-core GPU, according to one embodiment. Figure 4B The redistribution at the level of the macro MMA block 240 is depicted. Figure 4B The top matrix in is the same as Figure 4AIn at least one embodiment, to improve the processing efficiency of different matrix elements of the macro MMA block during the reduction operation, the MRM 125 can redistribute the ownership of the matrix elements among the threads of the thread warp to ensure that more (e.g., the maximum possible number) of consecutive elements are processed by the same thread. In at least one embodiment, as Figure 4B As shown in the lower pane of , reallocation can be performed 410. The numbers within the cells represent the threads that own the respective matrix elements after reallocation. In at least one embodiment, to perform the reallocation, the old threads copy their respective elements to a shared memory (e.g., shared register 114), and then load a contiguous block of elements from the shared memory into a register of a particular thread (e.g., register 113).

[0092] As shown, after reallocation, the upper left quadrant of the entire 8x8 tile can be associated with QP1; the remaining quadrants can be similarly reallocated to be associated with QP2, QP3, and QP4. Reallocation 410 can be used for row-wise reduction. After reallocation 410, all elements in the same row within each 8x8 quadrant are efficiently processed by the same thread. If a column-wise reduction is to be performed, in at least one embodiment, the reallocation is obtained from reallocation 410 by swapping all numbers on the main diagonal across the tile (representing the allocated threads) (so that the first

[0093] Figure 4C A reduction operation 420 is shown fused with a matrix multiplication during MMFR execution on a multi-core GPU, according to one embodiment. The reduction operation can be performed using eight hardware MMA 8×8×4 instructions (two hardware instructions for each QP). More specifically, for row-wise reduction, the MRM 125 can prepare two (identical) auxiliary 4×8 input matrices for each QP, where the first column is filled with ones and the rest of the matrix is ​​filled with zeros. Subsequently, each 8×8 quadrant can be multiplied by the corresponding auxiliary 4×8 to obtain a reduction accumulator consisting of four 8×8 sub-arrays, each owned by the corresponding QP. Therefore, each element of the first column of each sub-array (represented by a cell without zeros) is equal to the sum of the eight elements of the corresponding row of the corresponding sub-array.

[0094] In at least one embodiment, at the next warp block level, each warp block 230 may be represented by a number of macro MMA blocks 240. Figure 2 In the embodiment shown in , each warp block 230 consists of 16 macro MMA blocks 240 arranged in a 4×4 arrangement.) Partial reductions of warp blocks 230 can be performed by consecutive partial reductions (across each individual QP) of all macro MMA blocks 240 along the same row in the respective warp block 230. (In Figure 2In the embodiment shown in FIG. 3, each partial reduction corresponds to the sum of 4 macro-MMA tiles 240 arranged in a given thread warp tile 230 row. In performing such a partial reduction, the same partial accumulator can be used in a single row in the macro-MMA tile 240. In Figure 2 In the embodiment shown in FIG. 4, the accumulator matrix is 16x16. Each 8x8 partial accumulator matrix can be associated with an independent QP and can consist almost entirely of zeros except for the first column, as shown in FIG. 5. Figure 4C

[0095] In at least one embodiment, the partial reduction accumulator matrix can next be summed across the different quadruplets. In Figure 4C In the arrangement shown in FIG. 6, the QP1 partial accumulator can be summed with the QP2 partial accumulator, and the QP3 partial accumulator can be summed with the QP4 partial accumulator. In In a GPU architecture, thread warp level primitives such as_shfl_sync() can be used to communicate across different QPs to perform thread warp level reductions.

[0096] In at least one embodiment, at the next block tile level, each block tile 220 can be represented by several thread warp tiles 230. (In Figure 2 In the embodiment shown in FIG. 7, each block tile 220 is composed of 4 thread warp tiles 230 arranged in a 2x2 arrangement. In at least one embodiment, since different thread warp tiles can be executed by independent thread groups, the MRM 125 can first copy its thread warp level reduction results to shared memory (e.g., shared registers 114). A single thread warp from each row in the thread warp tiles 230 can then perform the loading and summing of the thread warp level reduction results. The results of the block level reduction can then be copied to a global memory buffer (e.g., cache 118, or shared registers 114).

[0097] In at least one embodiment, at the next grid tile level, the block level reduction results stored in the global memory buffer can be used as input for a grid level reduction. The grid level reduction can be performed by a second kernel that sums along the same row elements of the input buffer in turn. The computation can be parallelized by allocating rows across different blocks, thereby reducing multiple rows in parallel.

[0098] In the above embodiments, row-wise reductions were described for the sake of specificity. In at least one embodiment, the fusion of column-wise reductions for matrix multiplication can be performed in the same manner as for the auxiliary input matrix with zero along the row (e.g., the first row) instead of along the column. Such an auxiliary input matrix can be used to reduce the output of the matrix multiplication column by column. The remaining operations - e.g., thread warp level, block level, and grid level reductions - can be performed in a similar manner as the row-wise reductions described above.​

[0099] In the above-described embodiments, row-wise (or column-wise) reduction involves summing rows (or columns) of the output matrix. In at least one embodiment, other reduction operations can be fused with matrix multiplication, such as reduction operations that extract the minimum (maximum) value from a row (or column). In such embodiments, a single thread can perform the reduction on the tile owned by the thread, and thread-warp-level primitives (e.g., GPU primitives GPU primitives shfl_sync() can be used to perform reductions across threads in a thread warp. The remaining operations - e.g., thread-warp-level, block-level, and grid-level reductions - can be performed in a similar manner as the reductions described above.

[0100] Figure 5 is a flowchart of an example method 500 of performing matrix multiplication fused with reduction using a multi-core graphics processing unit (GPU), according to at least one embodiment. In at least one embodiment, method 500 is performed by one or more circuits (e.g., GPU cores) that can multiply two or more sub-portions (tiles) of one or more matrices and can produce two or more vectors from the multiplication using one or more parallel operations. MMFR operations performed using method 500 can be performed in the context of a neural network application and can compute various values, such as outputs produced by previous neural network layers that can be used as inputs to a next (e.g., hidden) neural network layer, or can represent a final output of an entire neural network. In at least one embodiment, Figure 6 Method 500 and method 600 in FIG. 6 can be performed by a processing unit of computing device 100. More specifically, method 500 and 600 can be performed by GPU 110, which includes one or more circuits and one or more memory devices, such as registers 113, shared registers 114, cache 118, GPU memory 119, and the like. In at least one embodiment, method 500 and method 600 can be performed by a plurality of processing threads (e.g., GPU threads), each thread performing one or more individual functions, routines, subroutines, or operations of the method. In at least one embodiment, processing threads implementing method 500 (and similarly method 600) can be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, processing threads implementing method 500 (and similarly method 600) can be performed asynchronously with respect to each other. The various operations of method 500 and 600 can be performed in a different order than shown in Figure 5 and Figure 6 In at least one embodiment, some operations of these methods can be performed concurrently with other operations. In at least one embodiment, Figure 5 and Figure 6The one or more operations illustrated in the middle can not always be performed.

[0101] In at least one embodiment, a processing unit executing method 500 can receive two or more input matrices: a first matrix (e.g., matrix A) and a second matrix (e.g., matrix B). At block 510, method 500 can include programming a plurality of hierarchical operations to be performed on the first and second matrices. For example, a processing unit can identify how many levels of blocking to deploy based on a size of the first and second matrices. Processing logic can further allocate processing tasks among one or more circuits (e.g., among various cores 111 of GPU 110) and further among various processing threads of the one or more circuits. Allocation of processing tasks can be performed to enable parallel execution in each hierarchical operation.

[0102] Blocks 510-540 can be performed multiple times. For example, some or each of blocks 510-540 can be performed for each hierarchical operation. At block 520, a processing unit can represent the first matrix (and / or the second matrix) via a first plurality (and / or a second plurality) of blocks (subparts) corresponding to a size of a level of the hierarchical operation. In at least one embodiment, the number of hierarchical operations and the size of the blocks can be the same as illustrated in the middle. In various other embodiments, the number of hierarchical operations can be as low as 2 or can be greater than 5. Likewise, the size of the blocks can also be arbitrary. In at least one embodiment, the blocks can have dimensions (height and width) that are powers of 2, e.g., 16, 32, 64, 128, etc., however in other embodiments, any other block size can be used. Figure 2

[0103] At block 530, a processing unit can perform a plurality of matrix multiplication operations, e.g., starting with a hierarchical operation corresponding to a smallest block size (lowest level of hierarchy). Each smallest block can be computed in parallel by various processing threads that load elements of the input matrices (corresponding to the respective blocks) and perform multiplication operations on the loaded elements. While computing the smallest size blocks, a processing unit executing method 500 can perform a next hierarchical operation corresponding to a next smallest block size, and so on, up to a highest level of hierarchy, until a full matrix multiplication of the first and second matrices is performed.

[0104] ​In at least one embodiment, at block 530, the processing unit executing method 500 may apply a reduction operation to the result of the matrix multiplication in two or more hierarchical operations. For example, after computing one block, the processing unit may perform a reduction operation (e.g., summing across rows and / or columns in each computed block, identifying the maximum / minimum element in each row and / or column across each computed block, etc.) before the next hierarchical operation begins execution. Thus, the output vector Red[A×B] may be computed using the block vectors representing the results of the reduction operation at the previous level of the hierarchical operation of the block.

[0105] Figure 6 is the use according to at least one embodiment Figure 2 Flowchart of another example method 600 for performing matrix multiplication fused with reduction using a multi-core GPU, as shown in FIG. In at least one embodiment, at block 610, a processing unit executing method 600 may receive a first matrix (e.g., matrix A) and a second matrix (e.g., matrix B). At block 615, method 600 may include representing the first matrix and the second matrix by a plurality of grid blocks (e.g., grid block 210). At block 620, method 600 may include representing each grid block (of the first matrix and the second matrix) by a plurality of block blocks (e.g., block block 220). At block 625, method 600 may include representing each block block (of the first matrix and the second matrix) by a plurality of warp blocks (e.g., warp block 230). At block 630, method 600 may include representing each warp block (of the first matrix and the second matrix) by a plurality of macro MMA blocks (e.g., macro MMA block 240).

[0106] At block 635, the processing unit executing method 600 may perform multiple matrix multiplication operations in parallel at the macro MMA block level. In at least one embodiment, such matrix multiplication may involve one or more levels of block operations. For example, Figure 2 As shown, the macro MMA block 240 can still be represented by smaller sub-regions corresponding to the four pairs 250. Once the macro MMA block of the product matrix A×B is calculated, the processing unit executing the method 600 can perform a macro MMA level reduction 640 at block 640. In at least one embodiment, the processing unit executing the method 600 can perform a redistribution of the elements of the individual calculations of the macro MMA block between processing threads at block 645, as described with respect to FIG. Figure 4B As described above, in order to promote more efficient reduction operations in block operations at higher hierarchical levels.

[0107] In at least one embodiment, processing unit executing method 600 can perform a thread bundle level blocked multiplication at a thread bundle level and then perform a reduction operation at block 650. In at least one embodiment, processing unit executing method 600 can perform a block level blocked multiplication at a block level and then perform a reduction operation at block 655. In at least one embodiment, processing unit executing method 600 can perform a grid level blocked multiplication at a grid level and then perform a reduction operation at block 665. In at least one embodiment, method 600 can output vector Red[AxB] at block 665.

[0108] Inference and training logic

[0109] Figure 7A Inference and / or training logic 715 is shown to include one or more components for performing the operations associated with inference and / or training operations in accordance with one or more embodiments. As shown, inference and / or training logic 715 includes forward weight storage 720 and output weight storage 725.

[0110] In at least one embodiment, inference and / or training logic 715 can include, without limitation, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters of neurons or layers of a neural network configured in aspects of one or more embodiments that are trained and / or used for inferencing. In at least one embodiment, training logic 715 can include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or order, where weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs) or simply circuits). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which that code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 can be included with other on-chip or off-chip data storage, including a processor’s Ll, L2, or L3 cache or system memory.

[0111] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 701 is internal or external to a processor, for example, or composed of DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage space on or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0112] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 705 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 705 stores weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0113] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 705 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0114] In at least one embodiment, code and / or data store 701 and code and / or data store 705 may be separate storage structures. In at least one embodiment, code and / or data store 701 and code and / or data store 705 may be the same storage structure. In at least one embodiment, code and / or data store 701 and code and / or data store 705 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data store 701 and code and / or data store 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0115] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 710 to generate activations stored in activation storage 720, wherein weight values ​​stored in code and / or data storage 705 and / or in code and / or data storage 701 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 705 or code and / or data storage 701 or other on-chip or off-chip storage.

[0116] In at least one embodiment, one or more ALUs 710 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 710 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, one or more ALUs 710 may be included within an execution unit of a processor or otherwise included in a group of ALUs accessible by the execution units of a processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0117] In at least one embodiment, activation storage 720 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 720 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, whether activation storage 720 is internal or external to the processor, for example, or comprises DRAM, SRAM, flash memory, or other storage types, can be selected based on the available on-chip or off-chip storage, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0118] In at least one embodiment, Figure 7A The inference and / or training logic 715 shown in FIG may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7A The illustrated inference and / or training logic 715 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0119] Figure 7B Inference and / or training logic 715 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 715 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B The inference and / or training logic 715 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7BThe inference and / or training logic 715 illustrated in FIG. 10 can be used in combination with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as field programmable gate arrays (FPGAs). In at least one embodiment, the inference and / or training logic 715 includes, without limitation, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 7B In at least one embodiment, each of code and / or data storage 701 and code and / or data storage 705 is associated with a dedicated computing resource, such as computing hardware 702 and computing hardware 706, respectively. In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that perform only mathematical functions (e.g., linear algebraic functions) on information stored in code and / or data storage 701 and code and / or data storage 705, respectively, the results of which are stored in activation storage 720.

[0120] In at least one embodiment, each of code and / or data storage 701 and 105 and corresponding computing hardware 702 and 706 correspond to different layers of a neural network, such that activations resulting from one “storage / computing pair 701 / 702” of code and / or data storage 701 and computing hardware 702 are provided as input to the next “storage / computing pair 705 / 706” of code and / or data storage 705 and computing hardware 706 in order to reflect the conceptual organization of a neural network. In at least one embodiment, each storage / computing pair 701 / 702 and 705 / 706 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computing pairs (not shown) can be included in inference and / or training logic 715 after or in parallel with storage computing pairs 701 / 702 and 705 / 706.

[0121] Neural network training and deployment

[0122] Figure 8Training and deployment of a deep neural network is shown in accordance with at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, training framework 804 is a PyTorch framework, while in other embodiments, training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 804 trains untrained neural network 806 and enables it to be trained using processing resources described herein to generate a trained neural network 808. In at least one embodiment, weights can be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0123] In at least one embodiment, untrained neural network 806 is trained using supervised learning, where training dataset 802 includes inputs paired with desired outputs for the inputs, or where training dataset 802 includes inputs with known outputs and the output of neural network 806 is manually layered. In at least one embodiment, untrained neural network 806 is trained in a supervised manner and inputs from training dataset 802 are processed and the resulting output is compared to a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 806. In at least one embodiment, training framework 804 adjusts weights that control untrained neural network 806. In at least one embodiment, training framework 804 includes tools to monitor how well untrained neural network 806 is converging to a model (e.g., trained neural network 808) that is suitable for generating correct answers (e.g., results 814) based on input data (e.g., new dataset 812). In at least one embodiment, training framework 804 repeatedly trains untrained neural network 806 while adjusting weights to improve the output of untrained neural network 806 using a loss function and adjustment algorithm (e.g., stochastic gradient descent). In at least one embodiment, training framework 804 trains untrained neural network 806 until untrained neural network 806 reaches a desired accuracy. In at least one embodiment, trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0124] In at least one embodiment, unsupervised learning is used to train untrained neural network 806, where untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 802 will include input data without any associated output data or “ground truth” data. In at least one embodiment, untrained neural network 806 can learn groupings within training dataset 802 and can determine how individual inputs relate to untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 808 that is capable of performing operations useful to reduce dimensionality of new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identification of data points in new dataset 812 that deviate from normal patterns of new dataset 812.

[0125] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mix of labeled and unlabeled data is included in training dataset 802. In at least one embodiment, training framework 804 can be used to perform incremental learning, for example, through a transfer of learning technique. In at least one embodiment, incremental learning enables trained neural network 808 to adapt to new dataset 812 without forgetting knowledge that was imprinted into trained neural network 808 during initial training.

[0126] Data Center

[0127] Figure 9 An example data center 900 that can use at least one embodiment is shown. In at least one embodiment, data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0128] In at least one embodiment, as Figure 9As shown, the data center infrastructure layer 910 can include a resource orchestrator 912, grouped computing resources 914, and node computing resources (“node C.R.s”) 916(1)-916(N), where “N” represents a positive integer (which can be a different integer “N” than the integer used in other figures). In at least one embodiment, the node C.R.s 916(1)-916(N) can include, but are not limited to, any number of central processing units (“CPUs” or “processors”), including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc., memory storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R.s 916(1)-916(N) can be a server having one or more of the above-described computing resources.

[0129] In at least one embodiment, the grouped computing resources 914 can include individual groups of node C.R.s housed within one or more racks (not shown), or housed within a number of racks (also not shown) within various geographic locations of a data center. In at least one embodiment, an individual group of node C.R.s within the grouped computing resources 914 can include a grouped computing, network, memory, or storage resource that can be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors can be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches, in any combination.

[0130] In at least one embodiment, the resource orchestrator 912 can configure or otherwise control the one or more node C.R.s 916(1)-916(N) and / or the grouped computing resources 914. In at least one embodiment, the resource orchestrator 912 can include a software design infrastructure (“SDI”) management entity for the data center 900. In at least one embodiment, the resource orchestrator 912 can include hardware, software, or some combination thereof.

[0131] In at least one embodiment, as Figure 9As shown, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework that supports software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or the application 942 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 928 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 922 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 900. In at least one embodiment, the configuration manager 924 may be capable of configuring different layers, such as the software layer 930 and the framework layer 920 including Spark and a distributed file system 928 for supporting large-scale data processing. In at least one embodiment, the resource manager 926 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 928 and the job scheduler 922. In at least one embodiment, the cluster or group computing resources may include group computing resources 914 on the data center infrastructure layer 910. In at least one embodiment, the resource manager 926 may coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0132] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least a portion of the node CRs 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0133] In at least one embodiment, one or more applications 942 included in application layer 940 can include one or more types of applications used by at least portions of node C.R.s 916(1)-916(N), grouped computing resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of applications can include, but are not limited to, any number and type of genomics applications, cognitive computing, applications, and machine learning applications including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0134] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource orchestrator 912 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modification actions can relieve data center operators of data center 900 from making possibly poor configuration decisions and can avoid underutilization and / or poorly performing portions of a data center.

[0135] In at least one embodiment, data center 900 can include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information in accordance with one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by computing weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 900. In at least one embodiment, using weight parameters computed by one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using resources described above with respect to data center 900.

[0136] In at least one embodiment, a data center can use CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using resources described above. Furthermore, one or more software and / or hardware resources described above can be configured as a service to allow users to train or perform information inference such as image recognition, speech recognition, or other artificial intelligence services.

[0137] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, inference and / or training logic 715 can be used in Figure 7A and / or Figure 7BDetails regarding inference and / or training logic 715 are provided. In at least one embodiment, inference and / or training logic 715 can be used in system Figure 9 for inferencing or predicting operations based, at least in part on weight parameters computed using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0138] Autonomous vehicle

[0139] Figure 10A An example of an autonomous vehicle 1000 is shown, in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1000 (alternatively referred to herein as “vehicle 1000”) can be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1000 can be a semi-truck tractor-trailer used for hauling cargo. In at least one embodiment, vehicle 1000 can be an airplane, a robotic vehicle, or another type of vehicle.

[0140] Autonomous vehicles can be described in terms of automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806 published on June 15, 2018, Standard No. J3016-201609 published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1000 can be capable of functioning according to one or more of Levels 1 through 5 of the automation scale. For example, in at least one embodiment, vehicle 1000 can be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment.

[0141] In at least one embodiment, vehicle 1000 can include, without limitation, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1000 can include, without limitation, a propulsion system 1050, such as a combustion engine, a hybrid electric device, a fully electric motor, and / or another propulsion system type. In at least one embodiment, propulsion system 1050 can be connected to a drivetrain of vehicle 1000, which can include, without limitation, a transmission to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 can be controlled in response to receiving signals from throttle / accelerator 1052.

[0142] In at least one embodiment, when propulsion system 1050 is operating (e.g., when vehicle 1000 is in motion), steering system 1054 (which can include, without limitation, a steering wheel) is used to steer vehicle 1000 (e.g., along a desired path or course). In at least one embodiment, steering system 1054 can receive signals from steering actuator 1056. In at least one embodiment, a steering wheel can be optional for full automation (Level 5) functionality. In at least one embodiment, brake sensor system 1046 can be used to operate vehicle brakes in response to signals received from brake actuator 1048 and / or brake sensors.

[0143] In at least one embodiment, controller 1036 can include, without limitation, one or more system on a chip (“SoC”) (e.g., one or more processors) that can be configured to perform one or more operations described herein. In at least one embodiment, controller 1036 can include, without limitation, one or more processors that can be configured to perform one or more operations described herein. Figure 10A) and / or a graphics processing unit ("GPU") provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, controller 1036 can send signals to operate vehicle brakes via brake actuator 1048, operate steering system 1054 via one or more steering actuators 1056, and operate propulsion system 1050 via one or more throttles / accelerators 1052. In at least one embodiment, one or more controllers 1036 can include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist the driver in driving vehicle 1000. In at least one embodiment, one or more controllers 1036 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0144] In at least one embodiment, the one or more controllers 1036 provide signals for controlling one or more components and / or systems of the vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1058 (e.g., one or more global positioning system sensors), one or more RADAR sensors 7060, one or more ultrasonic sensors 7062, one or more LIDAR sensors 7064, one or more inertial measurement unit (IMU) sensors 7066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 7068, one or more wide angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360 degree cameras), long range cameras (e.g., infrared cameras), and / or a plurality of other sensors. Figure 10A Not shown), mid-range camera ( Figure 10A), one or more speed sensors 1044 (e.g., for measuring the speed of the vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more brake sensors (e.g., as part of a brake sensor system 1046), and / or other sensor types are received.

[0145] In at least one embodiment, one or more controllers 1036 may receive input (e.g., represented by input data) from a dashboard 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1034, an audible annunciator, a speaker, and / or other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 10A ), location data (e.g., the location of the vehicle 1000, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1036, etc. For example, in at least one embodiment, the HMI display 1034 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0146] In at least one embodiment, the vehicle 1000 further includes a network interface 1024 that can communicate over one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, the network interface 1024 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1026 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN and SigFox) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0147] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided. In at least one embodiment, inference and / or training logic 715 can be used in system Figure 10A for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0148] Figure 10B An example of camera locations and fields of view of an autonomous vehicle 1000 of FIG. 1 is shown, in accordance with at least one embodiment. In at least one embodiment, the cameras and respective fields of view are one example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras can be included and / or cameras can be located at different locations on vehicle 1000. Figure 10A In at least one embodiment, camera types for cameras can include, but are not limited to, digital cameras that can be suitable for use with components and / or systems of vehicle 1000. In at least one embodiment, one or more cameras can operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, camera types can have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., in accordance with an embodiment. In at least one embodiment, cameras can be capable of using a rolling shutter, a global shutter, another type of shutter, or combinations thereof. In at least one embodiment, a color filter array can include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a clear pixel camera, such as a camera with an RCCC, RCCB, and / or RBGC color filter array, can be used in an effort to improve photosensitivity.

[0149] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

[0150]

[0151] ​In at least one embodiment, one or more cameras can be mounted in mounting assemblies, such as custom designed (three-dimensional (“3D”) printed) assemblies, in order to cut out stray light and reflections from within vehicle 1000 (e.g., reflections of instrument cluster in windshield mirror) that can interfere with camera’s image data capture capabilities. With regard to rearview mirror mounting assemblies, in at least one embodiment, rearview mirror assemblies can be 3D printed custom designed such that camera mounting plates match shape of rearview mirror. In at least one embodiment, one or more cameras can be integrated into rearview mirror. In at least one embodiment, for side view cameras, one or more cameras can also be integrated within four pillars at each corner of a cabin.

[0152] In at least one embodiment, cameras with a field of view that includes portions of environment in front of vehicle 1000 (e.g., front-facing cameras) can be used for surround view, as well as to help identify forward path and obstacles with the help of one or more controllers 1036 and / or control SoCs, thereby providing information that is critical to generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, front-facing cameras can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras can also be used for ADAS functions and systems, including but not limited to Lane Departure Warning (“LDW”), Adaptive Cruise Control (“ACC”), and / or other functions (such as traffic sign recognition).

[0153] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal-oxide semiconductor”) color imager. In at least one embodiment, a wide-view camera 1070 can be used to perceive objects (e.g., pedestrians, crossing or bicycles) entering from the periphery. Although only one wide-view camera 1070 is shown in FIG. 10B, in other embodiments, there can be any number (including zero) of wide-view cameras on vehicle 1000. In at least one embodiment, any number of long-range cameras 1098 (e.g., long-range stereo camera pairs) can be used for depth-based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, long-range cameras 1098 can also be used for object detection and classification, as well as basic object tracking. Figure 10B

[0154] ​In at least one embodiment, any number of stereo cameras 7068 can also be included in a forward-facing configuration. In at least one embodiment, one or more stereo cameras 7068 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and multi-core microprocessors with integrated controller area network (“CAN”) or Ethernet interfaces on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of an environment of vehicle 1000, including distance estimates for all points in an image. In at least one embodiment, one or more stereo cameras 7068 can include, without limitation, a compact stereo-vision sensor that can include, without limitation, two camera lenses (one each on left and right) and an image processing chip that can measure distance from vehicle 1000 to a target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 7068 can be used in addition to those described herein.

[0155] In at least one embodiment, cameras with a field of view that includes a portion of an environment to the sides of vehicle 1000 (e.g., side-view cameras) can be used for surround view, providing information for creating and updating an occupancy grid, as well as generating side collision warnings. For example, in at least one embodiment, surround cameras 1074 (e.g., four surround cameras as shown in Figure 10B In at least one embodiment, one or more surround cameras 1074 can include, without limitation, any number and combination of wide-view cameras, fisheye lenses, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye lens cameras can be located on front, back, and sides of vehicle 1000. In at least one embodiment, vehicle 1000 can use three surround cameras 1074 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., front-facing cameras) as a fourth surround view camera.

[0156] In at least one embodiment, cameras with a field of view that includes a portion of an environment to the rear of vehicle 1000 (e.g., rear-view cameras) can be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras can be used, including, without limitation, cameras that are also suitable as one or more forward-facing cameras (e.g., long-range cameras 1098 and / or one or more mid-range cameras 1076, one or more stereo cameras 7068, one or more infrared cameras 1072, etc.), as described herein.

[0157] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B , details regarding the reasoning and / or training logic 715 are provided herein. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in Figure 10B for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0158] Figure 10C According to at least one embodiment, Figure 10A A block diagram of an example system architecture for an autonomous vehicle 1000 is provided. In at least one embodiment, Figure 10C Each of one or more components, one or more features, and one or more systems of vehicle 1000 is shown as being connected via bus 1002. In at least one embodiment, bus 1002 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1000 that facilitates control of various features and functions of vehicle 1000, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1002 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0159] In at least one embodiment, FlexRay and / or Ethernet protocols can be used in addition to or instead of CAN. In at least one embodiment, there can be any number of buses 1002, which can include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses that use other protocols. In at least one embodiment, two or more buses can be used to perform different functions, and / or can be used for redundancy. For example, a first bus can be used for collision avoidance functions, and a second bus can be used for actuation control. In at least one embodiment, each bus of buses 1002 can communicate with any component of vehicle 1000, and two or more of buses 1002 can communicate with respective components. In at least one embodiment, each of any number of system on a chip (“SoC”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of one or more controllers 1036, and / or every computer within a vehicle can have access to same input data (e.g., input from sensors of vehicle 1000), and can be connected to a common bus, such as a CAN bus.

[0160] In at least one embodiment, vehicle 1000 can include one or more controllers 1036, such as those described herein with respect to Figure 10A In at least one embodiment, controllers 1036 can be used for a variety of functions. In at least one embodiment, controllers 1036 can be coupled to any of various other components and systems of vehicle 1000, and can be used to control vehicle 1000, artificial intelligence of vehicle 1000, infotainment of vehicle 1000, and / or other functions.

[0161] In at least one embodiment, vehicle 1000 can include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 can include, without limitation, central processing units (“one or more CPUs”) 1006, graphics processing units (“one or more GPUs”) 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data stores 1016, and / or other non- shown components and features. In at least one embodiment, one or more SoCs 1004 can be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 can be combined with a high definition (“HD”) map 1022 in a system (e.g., a system of vehicle 1000), which HD map 1022 can be obtained from one or more servers via a network interface 1024. In at least one embodiment, one or more SoCs 1004 can be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 can be combined with a high definition (“HD”) map 1022 in a system (e.g., a system of vehicle 1000), which HD map 1022 can be obtained from one or more servers via a network interface 1024. Figure 10C ) to obtain map refreshes and / or updates.

[0162] In at least one embodiment, one or more CPUs 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1006 may be active at any given time.

[0163] In at least one embodiment, one or more CPUs 1006 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1006 can further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a reduced power state entry sequence in software, where the work is offloaded to the microcode.

[0164] In at least one embodiment, one or more GPUs 1008 may include an integrated GPU (or referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1008 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use a computing application programming interface (API). In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0165] In at least one embodiment, one or more GPUs 1008 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1008 can be fabricated on Fin Field Effect Transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to increase performance while reducing programming.

[0166] In at least one embodiment, one or more GPU(s) 1008 can include high bandwidth memory (“HBM”) and / or 16 GB High Bandwidth Memory Second Generation (“HBM2”) memory subsystems to provide, in some examples, a peak memory bandwidth of about 900 GB / s. In at least one embodiment, in addition to, or alternatively to, HBM memory, synchronous graphics random access memory (“SGRAM”) can be used, such as graphics double data rate type five synchronous random-access memory (“GDDR5”).

[0167] In at least one embodiment, one or more GPU(s) 1008 can include unified memory technology. In at least one embodiment, address translation services (“ATS”) support can be used to allow one or more GPU(s) 1008 to directly access one or more CPU(s) 1006 page tables. In at least one embodiment, when a memory management unit (“MMU”) of a GPU of one or more GPU(s) 1008 experiences a miss, an address translation request can be sent to one or more CPU(s) 1006. In response, a CPU of one or more CPU(s) 1006 can look up a virtual-to-physical mapping for an address in its page tables and transmit a translation back to one or more GPU(s) 1008, in at least one embodiment. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for memory of both one or more CPU(s) 1006 and one or more GPU(s) 1008, reducing programming of one or more GPU(s) 1008 and porting of applications to one or more GPU(s) 1008.

[0168] In at least one embodiment, one or more GPU(s) 1008 can include any number of access counters that can track how frequently one or more GPU(s) 1008 is accessing memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to physical memory of a processor that most frequently accesses the page, improving efficiency of memory ranges shared between processors.

[0169] In at least one embodiment, one or more SoC(s) 1004 can include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more cache(s) 1012 can include a level three (“L3”) cache that can be available to and / or connected to one or more CPU(s) 1006 and one or more GPU(s) 1008. In at least one embodiment, one or more cache(s) 1012 can include a write-back cache that can track state of lines, for example, by using a cache coherence protocol (e.g., MESI, MSI, etc.). In at least one embodiment, although smaller cache sizes can be used, an L3 cache can include 4 MB of memory or more, according to embodiments.

[0170] In at least one embodiment, one or more SoC(s) 1004 can include one or more accelerator(s) 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoC(s) 1004 can include a hardware acceleration cluster that can include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) can enable hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, hardware acceleration cluster can be used to supplement and offload some tasks of one or more GPU(s) 1008 (e.g., freeing up more cycles of one or more GPU(s) 1008 to perform other tasks). In at least one embodiment, one or more accelerator(s) 1014 can be used for target workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to withstand the speedup test. In at least one embodiment, a CNN can include a region-based or region with convolutional neural network (“RCNN”) and a fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0171] In at least one embodiment, one or more accelerators 1014 (e.g., hardware acceleration clusters) can include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs can include, without limitation, one or more Tensor Processing Units (“TPUs”) that can be configured to provide an additional 100 trillion operations per second for deep learning applications and inferencing. In at least one embodiment, a TPU can be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs can be further optimized for a particular set of neural network types and floating point operations and inferencing. In at least one embodiment, design of one or more DLAs can provide higher performance per mm than a typical general purpose GPU, and often significantly outperform CPUs. In at least one embodiment, one or more TPUs can perform several functions including support for INT8, INT16, and FP16 data types for features and weights, single instance convolution functions, and post-processor functions, for example. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions including, for example and without limitation: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, as well as recognition and detection, using data from microphones; CNNs for facial recognition and vehicle owner identification using data from camera sensors; and / or CNNs for safety and / or safety related events.

[0172] In at least one embodiment, a DLA can perform any of functions of GPU(s) 1008, and by using an inferencing accelerator, for example, a designer can target one or more DLAs or GPU(s) 1008 for any function. For example, in at least one embodiment, a designer can concentrate processing and floating point operations for CNNs on one or more DLAs, and leave other functions to GPU(s) 1008 and / or accelerator(s) 1014.

[0173] In at least one embodiment, one or more accelerators 1014 can include a programmable vision accelerator (“PVA”), which can be alternatively referred to herein as a computer vision accelerator. In at least one embodiment, one or more PVAs can be designed and configured to accelerate computer vision algorithms used for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs can strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs can include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0174] In at least one embodiment, RISC cores can interact with image sensors (e.g., image sensors of any of cameras described herein), image signal processors, etc. In at least one embodiment, each RISC core can include any number of memories. In at least one embodiment, RISC cores can use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores can execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores can be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores can include instruction caches and / or tightly coupled RAM.

[0175] In at least one embodiment, DMA can enable components of a PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, DMA can support any number of features for providing optimizations to a PVA, including but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0176] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0177] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0178] In at least one embodiment, one or more accelerators 1014 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using the APB).

[0179] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0180] In at least one embodiment, one or more SoCs 1004 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0181] In at least one embodiment, one or more accelerators 1014 have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithm domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, the PVA, such as in the vehicle 1000, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0182] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0183] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0184] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 7066 associated with vehicle 1000 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 7064 or one or more RADAR sensors 7060), etc.

[0185] In at least one embodiment, one or more SoCs 1004 may include one or more data stores 1016 (e.g., memory). In at least one embodiment, one or more data stores 1016 may be on-chip memory of one or more SoCs 1004 that may store neural networks to be executed on one or more GPUs 1008 and / or DLAs. In at least one embodiment, one or more data stores 1016 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1016 may include an L2 or L3 cache.

[0186] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1004 thermal and temperature sensors, and / or manage one or more SoCs 1004 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1004 may use the ring oscillator to detect the temperature of one or more CPUs 1006, one or more GPUs 1008, and / or one or more accelerators 1014. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1004 into a lower power consumption state and / or place the vehicle 1000 into a driver's safe parking pattern (e.g., bringing the vehicle 1000 to a safe stop).

[0187] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors that can be used as an audio processing engine, which can be an audio subsystem that can provide hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0188] In at least one embodiment, one or more processors 1010 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0189] In at least one embodiment, one or more processors 1010 can further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, safety cluster engine can include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores can operate in lockstep mode and can function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1010 can further include a real-time camera engine that can include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 can further include a high dynamic range signal processor that can include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0190] In at least one embodiment, one or more processors 1010 can include a video image compositor that can be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce a final video to produce a final image for a player window. In at least one embodiment, video image compositor can perform lens distortion correction on one or more wide-view cameras 1070, one or more surround cameras 1074, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1004 that is configured to identify in-cabin events and respond accordingly.

[0191] In at least one embodiment, in-cabin systems can perform, without limitation, lip reading to activate cellular service and place a phone call, dictate an email, change a destination of a vehicle, activate or change infotainment systems and settings of a vehicle, or provide voice-activated web surfing. In at least one embodiment, certain functionality is available to a driver when a vehicle is operating in autonomous mode, otherwise it is disabled.

[0192] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0193] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, and does not require one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0194] In at least one embodiment, one or more of the SoCs 1004 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1004 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0195] In at least one embodiment, one or more of the SoCs 1004 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1004 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 7064, one or more RADAR sensors 7060, etc., which may be connected via an Ethernet channel), data from the bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1004 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to free one or more of the CPUs 1006 from routine data management tasks.

[0196] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data storage devices 1016, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0197] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0198] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1020) may include text and word recognition, thereby allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the symbols and pass this semantic understanding to a path planning module running on the CPU Complex.

[0199] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: Flashing lights indicate icy conditions" along with connected lights can be interpreted by multiple neural networks independently or collectively. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1008.

[0200] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1000. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0201] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphones 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use a CNN to classify ambient and urban sounds, as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify relative proximity of emergency vehicles (e.g., by using Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles for regions in which a vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, a CNN will seek to detect European sirens, while in North America, a CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used to execute emergency vehicle safety routines, slow vehicle down, pull vehicle to side of road, stop vehicle, and / or idle vehicle until emergency vehicle passes, with assistance of one or more ultrasonic sensors 7062.

[0202] In at least one embodiment, vehicle 1000 can include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs) that can be coupled to one or more SoCs 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1018 can include an X86 processor, such as one or more CPUs 1018 can be used to perform any of a variety of functions, such as including arbitrating inconsistent results between ADAS sensors and one or more SoCs 1004, and / or one or more supervisory controllers 1036 monitor status and health and / or an on-chip information system (“information SoC”) 1030.

[0203] In at least one embodiment, vehicle 1000 can include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs) that can be coupled to one or more SoCs 1004 via a high-speed interconnect (e.g., NVIDIA’s NVLINK channel). In at least one embodiment, one or more GPUs 1020 can provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and can be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1000.

[0204] In at least one embodiment, vehicle 1000 can further include network interface 1024, which can include, without limitation, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1024 can be used to enable wireless connectivity through Internet cloud services (e.g., with servers and / or other network equipment) with other vehicles and / or computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link can be established between vehicle 1000 and another vehicle and / or an indirect link can be established (e.g., through a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link can be used to provide a direct link. In at least one embodiment, a vehicle-to-vehicle communication link can provide vehicle 1000 with information about vehicles in a vicinity of vehicle 1000 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1000). In at least one embodiment, this aforementioned functionality can be part of a cooperative adaptive cruise control functionality of vehicle 1000.

[0205] In at least one embodiment, network interface 1024 can include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1036 to communicate over wireless networks. In at least one embodiment, network interface 1024 can include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion can be performed in any technically feasible way. For example, frequency conversion can be performed through well-known processes and / or using a superheterodyne process. In at least one embodiment, radio frequency front end functionality can be provided by a separate chip. In at least one embodiment, a network interface can include wireless functionality to communicate over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocol.

[0206] In at least one embodiment, vehicle 1000 can further include one or more data stores 1028, which can include, without limitation, off-chip (e.g., of SoC(s) 1004) storage. In at least one embodiment, one or more data stores 1028 can include, without limitation, one or more storage elements including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that can store at least one bit of data.

[0207] In at least one embodiment, vehicle 1000 can further include one or more GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 can be used including, for example and without limitation, a GPS using a universal serial bus (“USB”) connector with an Ethernet connection to a serial interface (e.g., RS-232) bridge.

[0208] In at least one embodiment, vehicle 1000 can further include one or more RADAR sensors 7060. In at least one embodiment, one or more RADAR sensors 7060 can be used by vehicle 1000 for long range vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, a RADAR functional safety level can be ASIL B. In at least one embodiment, one or more RADAR sensors 7060 can use CAN bus and / or bus 1002 (e.g., to transmit data generated by one or more RADAR sensors 1060) for control and access to object tracking data, in certain examples can access an Ethernet channel for access to raw data. In at least one embodiment, a wide variety of RADAR sensor types can be used. For example and without limitation, one or more of RADAR sensors 7060 can be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 7060 are pulse Doppler RADAR sensors.

[0209] In at least one embodiment, one or more RADAR sensors 7060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 7060 can help distinguish between static and moving objects and can be used by the ADAS system 1038 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 7060 included in the long-range RADAR system may include, but are not limited to, a monostatic multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1000 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas can extend the field of view, allowing for quick detection of vehicles 1000 entering or leaving the lane.

[0210] In at least one embodiment, as an example, the medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, the short-range RADAR system may include, but is not limited to, any number of RADAR sensors 7060 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1038 for blind spot detection and / or lane change assistance.

[0211] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 7062. In at least one embodiment, one or more ultrasonic sensors 7062, which may be positioned at the front, rear, and / or side of the vehicle 1000, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 7062 may be used, and different ultrasonic sensors 7062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 7062 may operate at an ASIL B functional safety level.

[0212] In at least one embodiment, the vehicle 1000 can include one or more LIDAR sensors 7064. In at least one embodiment, the one or more LIDAR sensors 7064 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 7064 can operate at functional safety level ASIL B. In at least one embodiment, the vehicle 1000 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 7064 that can use Ethernet channels (e.g., provide data to a Gigabit Ethernet switch).

[0213] In at least one embodiment, one or more LIDAR sensors 7064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 7064 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, the one or more LIDAR sensors 7064 may comprise small devices that can be embedded in the front, rear, sides, and / or corners of the vehicle 1000. In at least one embodiment, the one or more LIDAR sensors 7064 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 7064 may be configured for a horizontal field of view between 45 and 135 degrees.

[0214] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1000. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1000 to the object. In at least one embodiment, flash LIDAR can allow for the generation of a highly accurate and distortion-free image of the surrounding environment with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0215] In at least one embodiment, the vehicle 1000 may also include one or more IMU sensors 7066. In at least one embodiment, the one or more IMU sensors 7066 may be located at the center of the rear axle of the vehicle 1000. In at least one embodiment, the one or more IMU sensors 7066 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 7066 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 7066 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0216] In at least one embodiment, the one or more IMU sensors 7066 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude; in at least one embodiment, the one or more IMU sensors 7066 can enable the vehicle 1000 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 7066. In at least one embodiment, the one or more IMU sensors 7066 and the one or more GNSS sensors 1058 can be combined in a single integrated unit.

[0217] In at least one embodiment, the vehicle 1000 can include one or more microphones 1096 positioned within and / or around the vehicle 1000. In at least one embodiment, the one or more microphones 1096 can be used for emergency vehicle detection and identification, among other things.

[0218] In at least one embodiment, the vehicle 1000 may further include any number of camera types, including one or more stereo cameras 7068, one or more wide angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long range cameras 1098, one or more mid range cameras 1076, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1000. In at least one embodiment, the type of camera used depends on the vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the camera types and the camera types used. Figure 10A and Figure 10B Each camera can be described in more detail.

[0219] In at least one embodiment, vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, one or more vibration sensors 1042 may measure vibration of a component (e.g., an axle) of vehicle 1000. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0220] In at least one embodiment, the vehicle 1000 may include an ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1038 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0221] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 7060, one or more LIDAR sensors 7064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle in close proximity to the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1000 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0222] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via the network interface 1024 and / or one or more wireless antennas 1026. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately preceding (e.g., the vehicle immediately preceding and in the same lane as vehicle 1000), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1000, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0223] In at least one embodiment, an FCW system is designed to warn a driver of a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or one or more RADAR sensors 7060 coupled to a dedicated processor, a digital signal processor (“DSP”), an FPGA, and / or an ASIC that is electrically coupled to provide driver feedback such as a display, a speaker, and / or a vibrating component. In at least one embodiment, an FCW system can provide a warning, for example, in the form of a sound, a visual warning, a vibration, and / or a quick brake pulse.

[0224] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, an AEB system can use one or more forward-facing cameras and / or one or more RADAR sensors 7060 coupled to a dedicated processor, a DSP, an FPGA, and / or an ASIC. In at least one embodiment, when an AEB system detects a hazard, it typically first warns a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, the AEB system can automatically apply brakes in an attempt to prevent or at least mitigate the effects of a predicted collision. In at least one embodiment, an AEB system can include technologies such as dynamic brake support and / or crash imminent braking.

[0225] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to warn the driver when vehicle 1000 crosses lane markers. In at least one embodiment, an LDW system is not active when a driver indicates an intentional lane departure, such as by activating turn signals. In at least one embodiment, an LDW system can use a forward-facing camera coupled to a dedicated processor, a DSP, an FPGA, and / or an ASIC that is electrically coupled to provide driver feedback such as a display, a speaker, and / or a vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, if vehicle 1000 begins to deviate from a lane, an LKA system provides a steering input or braking to correct vehicle 1000.

[0226] In at least one embodiment, a BSW system detects and warns vehicle drivers of vehicles in a car’s blind spot. In at least one embodiment, a BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system can provide additional warnings when a driver uses turn signals. In at least one embodiment, a BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 7060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that are electrically coupled to driver feedback such as displays, speakers, and / or vibrating components.

[0227] In at least one embodiment, a RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside of a rear camera range while vehicle 1000 is backing up. In at least one embodiment, a RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, a RCTW system can use one or more rear-facing RADAR sensors 7060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that are electrically coupled to provide driver feedback such as displays, speakers, and / or vibrating components.

[0228] In at least one embodiment, conventional ADAS systems can be prone to false positives, which can annoy and distract drivers, but are typically not catastrophic because conventional ADAS systems warn the driver and allow that driver to decide whether a safety situation is truly present and take appropriate action. In at least one embodiment, in the event of a result conflict, vehicle 1000 itself decides whether to heed the results of a primary computer or a secondary computer (e.g., a first controller or a second controller of controller 1036). For example, in at least one embodiment, ADAS system 1038 can be a backup and / or secondary computer for providing perception information to a backup computer plausibility module. In at least one embodiment, a backup computer plausibility monitor can run redundant varieties of software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 1038 can be provided to a supervisory MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer conflict, then a supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0229] In at least one embodiment, a host computer can be configured to provide a confidence score to a supervisory MCU to indicate a host computer’s confidence in a selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the host computer’s instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in cases where a confidence score does not satisfy a threshold, and in cases where the host computer and secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between computers to determine an appropriate result.

[0230] In at least one embodiment, a supervisory MCU can be configured to run a neural network trained and configured to determine conditions under which a secondary computer provides false alarms based at least in part on output from a host computer and output from a secondary computer. In at least one embodiment, a neural network in a supervisory MCU can learn when to trust output of a secondary computer, and when not to. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, a neural network in a supervisory MCU can learn when the FCW system identifies metal objects that are not actually dangerous, such as drain grates or manhole covers that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, a neural network in a supervisory MCU can learn to override LDW when there is a bicyclist or pedestrian present and it is actually safest to lane depart. In at least one embodiment, a supervisory MCU can include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, a supervisory MCU can include and / or be included as a component of one or more SoCs 1004.

[0231] In at least one embodiment, ADAS system 1038 can include a secondary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the secondary computer can use classic computer vision rules (if-then), and presence of a neural network in a supervisory MCU can improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on a host computer, and non-identical software code running on a secondary computer provides consistent overall results, a supervisory MCU can be more confident that overall results are correct, and that the bug in software or hardware on the host computer will not cause a significant error.

[0232] In at least one embodiment, output of ADAS system 1038 can be input into a perception module of host computer and / or a dynamic driving task module of host computer. For example, in at least one embodiment, if ADAS system 1038 indicates a forward collision warning due to an object directly in front, perception block can use this information when identifying the object. In at least one embodiment, as described herein, a secondary computer can have its own neural network that is trained to reduce risk of false positives.

[0233] In at least one embodiment, vehicle 1000 can further include infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as a SoC, in at least one embodiment, infotainment system SoC 1030 can not be a SoC and can include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1030 can include, without limitation, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephony (e.g., hands free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear parking assistance, radio data system, vehicle related information such as fuel level, total covered distance, brake fluid level, oil level, doors open / close, air cleaner information, etc.) to vehicle 1000. For example, infotainment SoC 1030 can include a radio, disc player, navigation system, video player, USB and Bluetooth connectivity, car, in-car entertainment system, WiFi, steering wheel audio controls, hands-free voice controls, heads-up display (“HUD”), HMI display 1034, telematics equipment, control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1030 can be further used to provide information (e.g., visual and / or audible) to a user of vehicle 1000, such as information from ADAS system 1038, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0234] In at least one embodiment, the infotainment SoC 1030 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 can communicate with other devices, systems, and / or components of the vehicle 1000 via the bus 1002. In at least one embodiment, the infotainment SoC 1030 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1036 (e.g., the vehicle 1000's main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1030 can cause the vehicle 1000 to enter a driver-to-safety stop mode, as described herein.

[0235] In at least one embodiment, the vehicle 1000 may further include an instrument panel 1032 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1032 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1032 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1030 and the instrument panel 1032. In at least one embodiment, the instrument panel 1032 may be included as part of the infotainment SoC 1030, or vice versa.

[0236] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Provides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Figure 10C for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0237] Figure 10D In accordance with at least one embodiment, a cloud-based server and Figure 10A1080 . FIGURE 107 is a diagram of a system 1078 for communicating between autonomous vehicles 1000. In at least one embodiment, system 1078 may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but are not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). The GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 1088 developed by NVIDIA and / or PCIe connections 1086. In at least one embodiment, the GPUs 1084 are connected via NVLink and / or NVSwitch SoC, and the GPUs 1084 and PCIe switches 1082 are connected via a PCIe interconnect. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1078 may include, but is not limited to, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0238] In at least one embodiment, one or more servers 1078 may receive image data representing an image from a vehicle via one or more networks 1090 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1078 may transmit an updated neural network 1092 and / or map information 1094, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1090. In at least one embodiment, updates to the map information 1094 may include, but not limited to, updates to the HD map 1022, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1092 and / or map information 1094 may be generated by new training and / or experience derived from data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1078 and / or other servers).

[0239] In at least one embodiment, one or more servers 1078 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1090, and / or the machine learning model can be used by one or more servers 1078 to remotely monitor the vehicle.

[0240] In at least one embodiment, one or more servers 1078 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1078 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 can include the deep learning infrastructure of a data center using CPU power.

[0241] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1000, such as an image sequence and / or objects that the vehicle 1000 has located within that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1000, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1000 is malfunctioning, the one or more servers 1078 may send a signal to the vehicle 1000 to instruct the vehicle's 1000 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0242] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, hardware structure 715 is used to execute one or more embodiments. Figure 7A and / or Figure 7B Details regarding the hardware structure 715 are provided.

[0243] Computer system

[0244] Figure 11 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 1100 may include, but is not limited to, components such as processor 1102, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1100 may include a processor such as the Intel® processor 1102 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0245] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a DSP, a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0246] In at least one embodiment, the computer system 1100 may include, but is not limited to, a processor 1102, which may include, but is not limited to, one or more execution units 7108 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1100 is a single-processor desktop or server system, but in another embodiment, the computer system 1100 may be a multi-processor system. In at least one embodiment, the processor 1102 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110, which may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0247] In at least one embodiment, processor 1102 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1706 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0248] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating point operations, is also located in the processor 1102. In at least one embodiment, the processor 1102 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109 in the instruction set of a general-purpose processor, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1102. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0249] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another storage device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0250] In at least one embodiment, a system logic chip can be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1116, and the processor 1102 can communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 can provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 can initiate data signals between the processor 1102, the memory 1120, and other components in the computer system 1100, and bridge data signals between the processor bus 1110, the memory 1120, and the system I / O interface 1122. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to the memory 1120 via a high-bandwidth memory path 1118 , and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114 .

[0251] In at least one embodiment, the computer system 1100 may use the system I / O interface 1122 as a proprietary hub interface bus to couple the MCH 1116 to the I / O controller hub ("ICH") 1130. In at least one embodiment, the ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub ("Flash BIOS") 1128, a wireless transceiver 1126, a data store 1124, a legacy I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 (e.g., a USB port), and a network controller 1134. In at least one embodiment, the data store 1124 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0252] In at least one embodiment, Figure 11 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 11 An exemplary SoC may be shown. In at least one embodiment, Figure 11The devices illustrated in FIG. 12A can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using a compute express link (CXL) interconnect.

[0253] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 can be used in Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 can be used in Figure 11 a system to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0254] Figure 12 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210, in accordance with at least one embodiment. In at least one embodiment, electronic device 1200 can be, for example and without limitation, a laptop, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0255] In at least one embodiment, electronic device 1200 can include, without limitation, a processor 1210 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface, such as an Industry Standard 2 In at least one embodiment, electronic device 1200 can include, without limitation, a processor 1210 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface, such as an Industry Standard Figure 12 In at least one embodiment, a system is illustrated that includes interconnected hardware devices or “chips,” while in other embodiments, Figure 12 In at least one embodiment, an exemplary SoC can be illustrated. In at least one embodiment, Figure 12 The devices illustrated in FIG. 12A can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 one or more components of computer system 1200 are interconnected using a compute express link (CXL) interconnect.

[0256] In at least one embodiment, Figure 12It may include a display 1224, a touch screen 1225, a touchpad 1230, a near field communication unit ("NFC") 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset ("EC") 1235, a trusted platform module ("TPM") 1238, a BIOS / firmware / flash memory ("BIOS, FW Flash") 1222, a DSP 1260, a drive 1220 (e.g., a solid state disk ("SSD") or a hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 1250, a Bluetooth unit 1252, a wireless wide area network unit ("WWAN") 1256, a global positioning system (GPS) unit 1255, a camera ("USB 3.0 camera") 1254 (e.g., a USB 3.0 camera), and / or a low power double data rate ("LPDDR") memory unit ("LPDDR3") 1215 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0257] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described herein. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252 and the WWAN unit 1256 may be implemented as a next generation form factor (NGFF).

[0258] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Provides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Figure 12for use in performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0259] Figure 13 A computer system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0260] In at least one embodiment, computer system 1300 includes, but is not limited to, at least one central processing unit ("CPU") 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1304 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1322 provides an interface to other computing devices and networks for receiving data using computer system 1300 and transmitting data to other systems.

[0261] In at least one embodiment, computer system 1300 includes, but is not limited to, input device 1308, parallel processing system 1312, and display device 1306, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0262] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Provides details about the reasoning and / or training logic 715. In at least one embodiment, the reasoning and / or training logic 715 may be implemented in the system Figure 13 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0263] Figure 14 A computer system 1400, in accordance with at least one embodiment, is shown. In at least one embodiment, computer system 1400 includes, without limitation, a computer 1410 and a USB stick 1420.

[0264] In at least one embodiment, computer 1410 can include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1410 includes, without limitation, a server, a cloud instance, a laptop computer, and a desktop computer.

[0265] In at least one embodiment, USB stick 1420 includes, without limitation, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1430 can include, without limitation, any number and type of processing core (not shown). In at least one embodiment, processing unit 1430 includes an application specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1430 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1430 is a visual processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0266] In at least one embodiment, USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 can include any number and type of logic that enables processing unit 1430 to interface with a device (e.g., computer 1410) via USB interface 1440.

[0267] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided herein in conjunction with FIGS. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 can be used in system FIG. 1 by platform 100 in conjunction with other components described herein, for example, to implement techniques associated with one or more embodiments. Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided herein. In at least one embodiment, inference and / or training logic 715 can be used in system FIG. 1 by platform 100 in conjunction with other components described herein, for example, to implement techniques associated with one or more embodiments. Figure 14In use, inference or prediction operations are performed based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0268] Figure 15A An exemplary architecture is shown in which a plurality of GPUs 1510(1)- 1510(N) are communicatively coupled to a plurality of multi-core processors 1505(1)- 1505(M) over high-speed links 1540(1)-1540(N) (e.g., buses, point-to- point interconnects, etc.). In at least one embodiment, high-speed links 1540(1)-1540(N) support a communication throughput of 4GB / s, 30GB / s, 80GB / s or higher. In at least one embodiment, various interconnect protocols can be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, which can vary from figure to figure.

[0269] In addition, and in at least one embodiment, two or more GPUs 1510 are interconnected by high-speed links 1529(1)-1529(2), which can be implemented using similar or different protocols / links than those used for high-speed links 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 can be connected by an interconnection fabric 1528, which is an exemplary high-speed link using similar or different protocols / links than those used for high-speed links 1540(1)-1540(N). Exemplary Figure 15A All communication between various system components shown in FIG. 15.

[0270] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1501 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0271] As described herein, although the various multi-core processors 1505 and GPUs 1510 may be physically coupled to specific memories 1501, 1520, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1501(1)-1501(M) may each contain 64GB of system memory address space, and GPU memories 1520(1)-1520(N) may each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. Other values ​​of N and M are also possible.

[0272] Figure 15B Additional details are shown for the interconnection between the multi-core processor 1507 and the graphics acceleration module 1546 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to the processor 1507 via a high-speed link 1540 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1546 may be selectively integrated on a package or chip with the processor 1507.

[0273] In at least one embodiment, processor 1507 includes multiple cores 1560A-1560D, each core having a translation lookaside buffer ("TLB") 1567A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by each group of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to the system memory 1514, which may include Figure 15A Processor memory 1501(1)-1501(M) in.

[0274] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 via inter-core communication over a coherence bus 1564. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1564 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1564 to snoop cache accesses.

[0275] In at least one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in a cache coherence protocol as a peer of cores 1560A-1560D. In particular, in at least one embodiment, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0276] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may each include a separate GPU. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may selectively include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a common package, line card, or chip.

[0277] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1538 may store commands and data for efficient access by the graphics processing engines 1531(1)-1531(N). In at least one embodiment, a fetch unit 1544 may be used to keep data stored in the cache 1538 and graphics memory 1533(1)-1533(M) consistent with the core caches 1562A-1562D, 1556, and system memory 1514. As previously described, this task may be accomplished via proxy circuitry 1525 acting on behalf of cache 1538 and graphics memory 1533(1)-1533(M) (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0278] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and context management circuitry 1548 manages thread contexts. For example, context management circuitry 1548 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1548 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In at least one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0279] In at least one embodiment, the MMU 1539 translates virtual / effective addresses from the graphics processing engine 1531 into real / physical addresses in the system memory 1514. In at least one embodiment, the accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1546 can be dedicated to a single application executing on the processor 1507, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1531 (1)-1531 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0280] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system for the graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1531(1)-1531(N).

[0281] In at least one embodiment, because the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped into the real address space seen by host processor 1507, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1536 is to physically separate graphics processing engines 1531(1)-1531(N) so that they appear to the system as independent units.

[0282] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each graphics processing engine 1531(1)-1531(N), respectively, and N=M. In at least one embodiment, graphics memories 1533(1)-1533(M) store instructions and data that are processed by each graphics processing engine 1531(1)-1531(N). In at least one embodiment, graphics memories 1533(1)-1533(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0283] In at least one embodiment, to reduce data traffic on high-speed link 1540, biasing techniques may be used to ensure that the data stored in graphics memory 1533(1)-1533(M) is the data most frequently used by graphics processing engines 1531(1)-1531(N), and preferably is not used (at least not frequently) by cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1531(-1)-1531(N)) in caches 1562A-1562D, 1556, and system memory 1514.

[0284] Figure 15C Another exemplary embodiment is shown in which an accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly with the accelerator integrated circuit 1536 via interface 1537 and interface 1535 (which may also be any form of bus or interface protocol) over a high-speed link 1540. In at least one embodiment, the accelerator integrated circuit 1536 may perform operations related to the graphics processing engine 1531(1)-1531(N). Figure 15B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherency bus 1564 and caches 1562A-1562D, 1556. In at least one implementation, the accelerator integrated circuit instance supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0285] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1531(1)-1531(N), thereby providing virtualization within a VM / partition.

[0286] In at least one embodiment, graphics processing engines 1531(1)-1531(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1531(1)-1531(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0287] In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engines 1531(1)-1531(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1531(1)-1531(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0288] Figure 15DAn exemplary accelerator integrated slice 1590 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1536. In at least one embodiment, the application is an effective address space 1582 in system memory 1514, which stores a process element 1583. In at least one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on the processor 1507. In at least one embodiment, the process element 1583 contains the process state of the corresponding application 1580. In one embodiment, the work descriptor (WD) 1584 contained in the process element 1583 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0289] In at least one embodiment, the graphics acceleration module 1546 and / or the individual graphics processing engines 1531(1)-1531(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1584 to the graphics acceleration module 1546 to start a job in a virtualized environment.

[0290] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when a graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0291] In operation, in at least one embodiment, a WD fetch unit 1591 in the accelerator integrated slice 1590 fetches a next WD 1584, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in registers 1545 and used by the MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of the MMU 1539 includes segment / page roaming circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. In at least one embodiment, the interrupt management circuitry 1547 may process interrupt events 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, effective addresses 1593 generated by the graphics processing engines 1531(1)-1531(N) are translated into real addresses by the MMU 1539.

[0292] In at least one embodiment, registers 1545 are replicated for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546, and the registers 1545 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1590. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0293]

[0294]

[0295] Example registers that may be initialized by the operating system are shown in Table 2.

[0296]

[0297] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1531(1)-1531(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0298] Figure 15EAdditional details are shown for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1598 in which a list of process elements 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 is accessible via a hypervisor 1596 that virtualizes a graphics acceleration module engine for an operating system 1595.

[0299] In at least one embodiment, a shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in a system to use a graphics acceleration module 1546. In at least one embodiment, there are two programming models in which a graphics acceleration module 1546 is shared by multiple processes and partitions, namely, time-sliced sharing and graphics-directed sharing.

[0300] In at least one embodiment, in this model, a system hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, for a graphics acceleration module 1546 to support virtualization by a system hypervisor 1596, the graphics acceleration module 1546 can adhere to certain requirements, such as (1) an application’s job request must be autonomous (i.e., no state needs to be kept between jobs), or the graphics acceleration module 1546 must provide a context save and restore mechanism, (2) the graphics acceleration module 1546 guarantees that an application’s job request completes within a specified amount of time, including any translation faults, or the graphics acceleration module 1546 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1546 processes must be ensured when operating in a directed sharing programming model.

[0301] In at least one embodiment, an application 1580 needs to use a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP) for an operating system 1595 system call. In at least one embodiment, the graphics acceleration module type describes a target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for a graphics acceleration module 1546 and can take the form of a graphics acceleration module 1546 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes work to be done by a graphics acceleration module 1546.

[0302] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may selectively apply the current AMR value before placing the AMR into the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of an area in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0303] Upon receiving the system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 calls the hypervisor 1596 using the information shown in Table 3.

[0304]

[0305]

[0306] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1596 verifies that operating system 1595 has registered and been granted permission to use graphics acceleration module 1546. Then, in at least one embodiment, hypervisor 1596 places process element 1583 into a linked list of process elements of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0307]

[0308] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1590 registers 1545 .

[0309] like Figure 15FAs shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1501(1)-1501(N) and GPU memory 1520(1)-1520(N). In this implementation, operations executed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access processor memory 1501(1)-1501(M), and vice versa, thereby reducing programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion is allocated to second processor memory 1501(N), a third portion is allocated to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1501 and GPU memory 1520, thereby allowing any processor or GPU to access that memory using a virtual address that maps to any physical memory.

[0310] In at least one embodiment, bias / coherency management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherency between the caches of one or more host processors (e.g., 1505) and GPU 1510 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 15F Multiple instances of bias / coherence management circuits 1594A- 1594E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1505 and / or within an accelerator integrated circuit 1536 .

[0311] One embodiment allows GPU memory 1520 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1520 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1505 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1510. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0312] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits of memory per GPU-attached page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU memories 1520, with or without a bias cache in GPU 1510 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0313] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1520 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1510 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1505 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1505 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1510. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0314] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1505 bias to GPU bias, but not for the reverse migration.

[0315] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1505 and GPU 1510, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1505, and vice versa.

[0316] One or more hardware structures 715 are used to implement one or more embodiments. Figure 7A and / or Figure 7B Details regarding one or more hardware structures 715 are provided.

[0317] Figure 16An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0318] Figure 16 16 is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic that includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I 2 2S / I 2 2C controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0319] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used within integrated circuit 1600 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0320] Figures 17A-17B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0321] Figures 17A-17B is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system on a chip integrated circuit according to at least one embodiment is shown, which can be fabricated using one or more IP cores. Figure 17B Another exemplary graphics processor 1740 of a system on a chip integrated circuit according to at least one embodiment is shown, which can be fabricated using one or more IP cores. In at least one embodiment, Figure 17A The graphics processor 1710 of FIG. 17A is a low power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 of FIG. 17B is a higher performance graphics processor core.

[0322] In at least one embodiment, each graphics processor 1710, 1740 can be a variant of the graphics processor 1610 of FIG. 16. Figure 16 In at least one embodiment, the graphics processor 1710 of FIG. 17A is a variant of the graphics processor 1610 of FIG. 16.

[0323] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processor(s) 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D, through 1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 can execute different shader programs via separate logical

[0324] In at least one embodiment, graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide a mapping of virtual to physical addresses for graphics processor 1710, including for vertex processor 1705 and / or fragment processors 1715A-1715N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may synchronize with other MMUs within the system, including with other MMUs. Figure 16 One or more MMUs associated with one or more application processors 1605, graphics processor 1015, and / or video processor 1620 enable each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable graphics processor 1710 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0325] In at least one embodiment, graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F through 1755N-1 and 1755N), such as Figure 17B As shown, it provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1755A-1755N and a tiling unit 1758 to accelerate tile-based rendering operations, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0326] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BProvides details about the inference and / or training logic 715. In at least one embodiment, the inference and / or training logic 715 may be implemented in an integrated circuit. Figure 17A and / or Figure 17B for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0327] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 18A Shows that can be included in Figure 16 Graphics core 1800 within graphics processor 1610, and in at least one embodiment, may be such as Figure 17B Unified shader cores 1755A-1755N are shown. Figure 18B A highly parallel general purpose graphics processing unit ("GPGPU") 1830 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0328] In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820, which are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1807A-1801N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1800. In at least one embodiment, slices 1807A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler 1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1807A-1801N may include a set of additional function units (AFUs 1812A-1812N), floating point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address calculation units (ACUs 1813A-1813N), double precision floating point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N).

[0329] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1815A-1815N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1817-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0330] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding inference and / or training logic 715. In at least one embodiment, inference and / or training logic 715 may be used in graphics core 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0331] Figure 18BA general-purpose processing unit (GPGPU) 1830 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1830 can be directly linked to other instances of GPGPU 1830 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1830 includes a host interface 1832 to enable connection to a host processor. In at least one embodiment, host interface 1832 is a PCI Express interface. In at least one embodiment, host interface 1832 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 to assign execution threads associated with those commands to a group of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 may serve as a higher level of cache for cache memory within compute clusters 1836A-1836H.

[0332] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0333] In at least one embodiment, computing clusters 1836A-1836H each include a set of graphics cores, e.g. Figure 18A The graphics core 1800 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0334] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to function as a compute cluster. In at least one embodiment, the communications used by compute clusters 1836A-1836H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to a GPU link 1840, enabling direct connections to other instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 reside in separate data processing systems and communicate via a network device accessible through host interface 1832. In at least one embodiment, GPU link 1840 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1832 .

[0335] In at least one embodiment, GPGPU 1830 can be configured to train neural networks. In at least one embodiment, GPGPU 1830 can be used within an inference platform. In at least one embodiment, where GPGPU 1830 is used for inference, GPGPU 1830 can include fewer compute clusters 1836A-1836H than when GPGPU 1830 is used for training a neural network. In at least one embodiment, the memory technology associated with memory 1844A-1844B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0336] Reasoning and / or training logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BDetails regarding the inference and / or training logic 715 are provided. In at least one embodiment, inference and / or training logic 715 can be used in GPGPU 1830 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0337] Figure 19 A block diagram of a computer system 1900 is shown, in accordance with at least one embodiment. In at least one embodiment, computer system 1900 includes a processing subsystem 1901, with one or more processor(s) 1902, and a system memory 1904, communicating via an interconnection path 1905, which can include a memory hub 1905. In at least one embodiment, the memory hub 1905 can be a separate component, or it can be integrated into one or more of the processor(s) 1902. In at least one embodiment, memory hub 1905 couples with processor(s) 1902 through communication links 1906. In at least one embodiment, processor(s) 1902 can include one or more of processing cores, which can be implemented, for example, as processors 1820, 1830, 1840, 1850, and / or 1860, in FIG. 18, and / or as one or more of the processing cores within processors 1820, 1830, 1840, 1850, and / or 1860.

[0338] In at least one embodiment, processing subsystem 1901 includes one or more parallel processor(s) 1912, which can communicate with processor(s) 1902, over a communication link 1913, such as bus, or other communication link. In at least one embodiment, communication link 1913 can be implemented with, without limitation, a Peripheral Component Interconnect Express (PCI-E) bus, or a proprietary implementation of a communication link. In at least one embodiment, one or more parallel processor(s) 1912 form a graphics processing subsystem, which can output pixel data to one or more display device(s) 1910A via I / O hub 1907. In at least one embodiment, one or more parallel processor(s) 1912 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 1910B.

[0339] In at least one embodiment, system storage 1914 can connect to I / O hub 1907 to provide storage mechanisms for computing system 1900. In at least one embodiment, I / O switches 1916 can be used to provide an interface mechanism to enable connections between I / O hub 1907 and other components, such as network adapter 1918 and / or wireless network adapter 1919 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 1920. In at least one embodiment, network adapter 1918 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0340] In at least one embodiment, computing system 1900 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which can also be connected to I / O hub 1907. In at least one embodiment, interconnection of the various components of computing system 1900 can be implemented using any suitable protocols, including PCI-based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocols. Figure 19 In at least one embodiment, communication paths between various components of computing system 1900 can be implemented using any suitable protocols, including protocols

[0341] In at least one embodiment, parallel processor 1912 includes circuitry such as, for example, video circuitry, constituting a graphics processing unit (GPU). In at least one embodiment, parallel processor 1912 includes circuitry optimized for general use such as, for example, one or more integrated circuit devices that each include a general purpose microprocessor and a level two cache. In at least one embodiment, components of computing system 1900 can be integrated with one or more other system elements onto a single integrated circuit. For example, in at least one embodiment, parallel processor 1912, memory hub 1905, processor 1902, and I / O hub 1907 can be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1900 can be integrated into a single package to form a system in a package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 1900 can be integrated into a multichip module (MCM), which can be interconnected with other multichip modules to form a modular computing system.

[0342] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Inferences can be made using one or more of the components of the system 700, such as one or more of the processors 702, the accelerator 704, and the like. Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided. In at least one embodiment, inference and / or training logic 715 can be used in systems 1900 to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. Figure 19 Details regarding inference and / or training logic 715 are provided. In at least one embodiment, inference and / or training logic 715 can be used in systems 1900 to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0343] Processor

[0344] Figure 20A A parallel processor 2000, according to at least one embodiment, is shown. In at least one embodiment, various components of parallel processor 2000 can be implemented using one or more integrated circuits, which collectively form programmable processing sub-system 1914 of system 1900. In at least one embodiment, parallel processor 2000 is a variant of the Figure 19 Variants of one or more parallel processors 1912 are shown.

[0345] In at least one embodiment, parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 can be directly connected to other devices. In at least one embodiment, I / O unit 2004 connects with other devices via use of a hub or switch interface, such as memory hub 2105. In at least one embodiment, connections between memory hub 2005 and I / O unit 2004 form a communication link 2013. In at least one embodiment, I / O unit 2004 connects with a host interface 2006 and a memory crossbar switch 2016, where host interface 2006 receives commands directed to processing operations and memory crossbar switch 2016 receives commands directed to memory operations.

[0346] In at least one embodiment, when host interface 2006 receives command buffers via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to distribute commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in a valid state before distributing tasks to processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2012. In at least one embodiment, host software can identify workloads for scheduling on processing array 2012 through one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing array 2012 by scheduler 2010 logic within a microcontroller that includes scheduler 2010 .

[0347] In at least one embodiment, processing cluster array 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B, through cluster 2014N), where "N" represents a positive integer (which may be a different integer than the integer "N" used in other figures). In at least one embodiment, each cluster 2014A-2014N of processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2010 may use various scheduling and / or work distribution algorithms to distribute work to clusters 2014A-2014N of processing cluster array 2012, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 2010 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0348] In at least one embodiment, processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2012 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2012 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0349] In at least one embodiment, processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2002 may transfer data from system memory via I / O units 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0350] In at least one embodiment, when parallel processing unit 2002 is used to perform graphics processing, scheduler 2010 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2014A-2014N of processing cluster array 2012. In at least one embodiment, portions of processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2014A-2014N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2014A-2014N for further processing.

[0351] In at least one embodiment, the processing cluster array 2012 can receive processing tasks to be executed via the scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2010 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2008. In at least one embodiment, the front end 2008 can be configured to ensure that the processing cluster array 2012 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0352] In at least one embodiment, each of the one or more instances of parallel processing unit 2002 can be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 can be accessed via memory crossbar 2016, which can receive memory requests from processing cluster array 2012 and I / O unit 2004. In at least one embodiment, memory crossbar 2016 can access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 can include multiple partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N), each of which can be coupled to a portion of parallel processor memory 2022 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory cells, such that the first partition unit 2020A has a corresponding first memory cell 2024A, the second partition unit 2020B has a corresponding memory cell 2024B, and the Nth partition unit 2020N has a corresponding Nth memory cell 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory cells.

[0353] In at least one embodiment, memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2022. In at least one embodiment, local instances of parallel processor memory 2022 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0354] In at least one embodiment, any of the clusters 2014A-2014N in the processing cluster array 2012 can process data to be written to any memory unit 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to transmit the output of each cluster 2014A-2014N to any partition unit 2020A-2020N or another cluster 2014A-2014N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 218 via the memory crossbar 2016 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 2016 has connections to memory interface 2018 for communicating with I / O unit 2004, and connections to local instances of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory that is not local to parallel processing unit 2002. In at least one embodiment, memory crossbar 2016 can use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0355] In at least one embodiment, multiple instances of parallel processing unit 2002 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2002 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0356] Figure 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is Figure 20A 2020N。In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025 and an ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 communicates with memory units in the parallel processor memory (such as Figure 20A interacts with one of the memory units 2024A-2024N (e.g., within parallel processor memory 2022).

[0357] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2026 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0358] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 2016 rather than through the pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Figure 19 1910), routed by processor 1302 for further processing, or by Figure 20A One of the processing entities within parallel processor 2000 is routed for further processing.

[0359] Figure 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 20A In at least one embodiment, processing cluster 2014 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0360] In at least one embodiment, the operation of the processing cluster 2014 can be controlled by a pipeline manager 2032 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 Figure 20AThe scheduler 2010 receives instructions, and manages execution of those instructions by the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures can be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 can be included within a processing cluster 2014. In at least one embodiment, a graphics multiprocessor 2034 can process data, and a data crossbar 2040 can be used to distribute the processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, a pipeline manager 2032 can facilitate distribution by, for example, specifying destinations of processed data.

[0361] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 can include an identical set of functional execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shift operations, and the like. In at least one embodiment, same functional- unit hardware can be leveraged to perform a number of different operations and any combination of hardware

[0362] In at least one embodiment, instructions transmitted to the processing cluster 2014 form a thread for execution. In at least one embodiment, a set of threads executing across a group of parallel processing engines forms a warp. In at least one embodiment, a thread group is scheduled to execute on a graphics multiprocessor 2034. In at least one embodiment, each thread within a thread group allocates one or more registers to be shared among the thread group. In at least one embodiment, a thread group is assigned a number of thread slots, and each thread is assigned at least one thread slot. In at least one embodiment, a thread can be assigned including more than one thread slot to enable parallel execution on a multithreaded execution resource. In at least one embodiment, a thread group is executed on a graphics multiprocessor 2034 up to, but not including, a context switch. In at least one embodiment, thread execution is preemptible by control software.

[0363] In at least one embodiment, graphics multiprocessor 2034 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2034 can abandon the internal cache and use cache memory within processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 can also access partition units (e.g., Figure 20A L2 cache within partition units 2020A-2020N) of the graphics multiprocessor 2002 is shared across all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034, which can share common instructions and data, which can be stored in L1 cache 2048.

[0364] In at least one embodiment, each processing cluster 2014 may include a memory management unit ("MMU") 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside in Figure 20A 2018. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034 or the L1 cache 2048 or the processing cluster 2014. In at least one embodiment, the physical address is processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0365] In at least one embodiment, processing cluster 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 for performing texture mapping operations in accordance with texture coordinate values. In at least one embodiment, texture data is read from an internal texture Ll cache (not shown) or from an L2 cache (not shown) as needed. In at least one embodiment, texture data is also fetched from a graphics processor memory, such as a shared memory 2070, an L2 cache, or a system memory, as needed. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to a data crossbar 2040 in processing cluster 2014. In at least one embodiment, data crossbar 2040 performs a write operation for the task results to shared memory 2070 via a memory crossbar 2016. In at least one embodiment, data crossbar 2040 performs read for task data from shared memory 2070 via memory crossbar 2016. In at least one embodiment, data crossbar 2040 also performs a read operation for task data from a shared memory 2070 via memory crossbar 2016 and performs a write operation for a task result to shared memory 2070 via memory crossbar 2016. In at least one embodiment, data crossbar 2040 is configured to perform the read and write operations as specific instructions of a vertex or geometry processing pipeline. Figure 20A In at least one embodiment, pre-ROP 2042 is configured to receive data from graphics multiprocessor 2034, direct the data to a ROP unit that can be located within a same processor as pre-ROP 2042 or an application specific integrated circuit (ASIC) coupled to a processing cluster 2014, organize the pixel color data, and perform address translation operations. In at least one embodiment, pre-ROP 2042 is also configured to include, for example, a data compression unit and a cache memory.

[0366] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7L and / or 7M. Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7L and / or 7M. In at least one embodiment, inference and / or training logic 715 can be used in graphics processing cluster 2014 to perform inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0367] Figure 20D A graphics multiprocessor 2034 according to at least one embodiment is shown. In at least one embodiment, graphics multiprocessor 2034 is coupled to a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, graphics multiprocessor 2034 has a graphics processing pipeline that includes, in at least one embodiment, without limitation, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit(s) (GPGPU) core(s) 2062, and one or more load / store units 2066. In at least one embodiment, GPGPU core(s) 2062 and load / store units 2066 are coupled by a memory and cache interconnect 2068 with cache memory 2072 and shared memory 2070.

[0368] In at least one embodiment, the instruction cache 2052 receives a stream of instructions to be executed from the pipeline manager 2032. In at least one embodiment, the instructions are cached in the instruction cache 2052 and dispatched for execution by the instruction unit 2054. In one embodiment, the instruction unit 2054 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2062. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2056 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2066.

[0369] In at least one embodiment, register file 2058 provides a set of registers for the functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2062, load / store unit 2066) connected to graphics multiprocessor 2034. In at least one embodiment, register file 2058 is divided between each functional unit such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is divided between the different warps being executed by graphics multiprocessor 2034.

[0370] In at least one embodiment, the GPGPU cores 2062 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions for the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function or special-function logic.

[0371] In at least one embodiment, GPGPU cores 2062 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU cores 2062 can physically execute SIMD 4, SIMD 8, and SIMD 16 instructions and logically execute a SIMD 1, SIMD 2, and SIMD 32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated by a shader compiler during compilation of code written by a programmer. In at least one embodiment, a programmer writing code for the programmable processing unit 2000 can write SIMD code in a high level programming language, which is then compiled into multiple instruction packets that can include one or more SIMD instructions and / or one or more SIMD control instructions. In at least one embodiment, a single

[0372] In at least one embodiment, memory and cache interconnect 2068 is an interconnect network that connects each functional unit of graphics multiprocessor 2034 to register file 2058 and shared memory 2070. In at least one embodiment, memory and cache interconnect 2068 is a crossbar interconnect that allows load / store units 2066 to effect load and store operations between shared memory 2070 and register file 2058. In at least one embodiment, register file 2058 can operate at the same frequency as GPGPU cores 2062, so that there is very little latency in transferring data between GPGPU cores 2062 and register file 2058. In at least one embodiment, shared memory 2070 can be used to enable communication between threads executing on functional units within graphics multiprocessor 2034. In at least one embodiment, cache memory 2072 can be used to cache data stored in shared memory 2070, for example, to allow data to be accessed more quickly. In at least one embodiment, shared memory 2070 can also be used to store program metadata, for example, to store information about programs that are executed on graphics multiprocessor 2034. In at least one embodiment, in addition to automatically cached data stored in cache memory 2072, threads executing on GPGPU cores 2062 can store data in shared memory in a programmed manner.

[0373] In at least one embodiment, parallel processor(s) or GPGPUs as described herein are communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed

[0374] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7i-7m. Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7i-7m. In at least one embodiment, inference and / or training logic 715 can be used in graphics processing unit 2034 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0375] Figure 21A multi-GPU computing system 2100 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 2100 can include a processor 2102 coupled to a plurality of general purpose graphics processing units (GPGPUs) 2706A-D via a host interface switch 2104. In at least one embodiment, host interface switch 2104 is a PCI Express switch device that couples processor 2102 to a PCI Express bus over which processor 2102 can communicate with GPGPUs 2706A-D. In at least one embodiment, GPGPUs 2706A-D can be interconnected via a set of high-speed P2P GPU-to-GPU links 2116. In at least one embodiment, GPU-to-GPU links 2116 connect to each of GPGPUs 2706A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2116 enable direct communication between each GPGPU 2706A-D without having to communicate through host interface bus 2104 to which processor 2102 is connected. In at least one embodiment, where GPU-to-GPU traffic is directed to P2P GPU links 2116, host interface bus 2104 remains available for system memory access or communication with other instances of multi-GPU computing system 2100, e.g., via one or more network devices. While in at least one embodiment GPGPUs 2706A-D are connected to processor 2102 via host interface switch 2104, in at least one embodiment processor 2102 includes direct support for P2P GPU links 2116 and can be directly connected to GPGPUs 2706A-D.

[0376] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 can be used in multi-GPU computing system 1500 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein. Figure 7A Figure 7B Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 can be used in multi-GPU computing system 1500 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0377] Figure 22 ​is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, graphics processor 2200 includes ring interconnect 2202, front-end pipeline 2204, media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2200 is one of a number of processors integrated within a multi-core processing system.

[0378] In at least one embodiment, graphics processor 2200 receives batches of commands via ring interconnect 2202. In at least one embodiment, incoming commands are interpreted by a command streamer 2203 in pipeline front-end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, command streamer 2203 supplies commands to geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, command streamer 2203 supplies commands to a video front end 2234, which couples with a media engine 2237. In at least one embodiment, media engine 2237 includes a Video Quality Engine (VQE) 2230 for video and image post-processing, and a multi-format encode / decode (MFX) 2233 engine to provide hardware-accelerated

[0379] In at least one embodiment, graphics processor 2200 includes a scalable thread execution resource having (featureing) graphics cores 2280A-2280N (which can be modular and sometimes referred to as core slices), each including a plurality of sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2200 can have any number of graphics cores 2280A. In at least one embodiment, graphics processor 2200 includes graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, graphics processor 2200 is a low power processor with a single sub-core (e.g., 2250A). In at least one embodiment, graphics processor 2200 includes multiple graphics cores 2280A-2280N each including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each sub-core in first sub-cores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each sub-core in second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[0380] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided herein in conjunction with FIGS. 7A and / or 7B. In examples in which inference and / or training logic 715 are used for Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided herein. In at least one embodiment, inference and / or training logic 715 can be used in graphics processor 2200 to perform inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0381] Figure 23is a block diagram illustrating micro-architecture for a processor 2300 that can include logic circuits to execute instructions, in accordance with at least one embodiment. In at least one embodiment, processor 2300 can execute instructions including x86 instructions, ARM instructions, specialized instructions for application specific integrated circuits (ASICs), and the like. In at least one embodiment, processor 2300 can include registers to store packed data, such as 64-bit wide MMX® registers enabled by Intel Corporation of Santa Clara, California in microprocessors employing MMX technology, Streaming SIMD (Single Instruction, Multiple Data) extensions (“SSE”), SSE2, SSE3, SSE4, AVX, or higher (generically referred to as “SSEx”) technology, and the like. In at least one embodiment, processor 2300 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference. TM In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher (generically referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2300 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0382] In at least one embodiment, processor 2300 includes an in-order front-end (“front-end”) 2301 to fetch instructions to be executed and to prepare instructions for execution by other pipelines. In at least one embodiment, front-end 2301 can include several units. In at least one embodiment, instruction prefetcher 2326 fetches instructions from memory and provides pre-fetched instructions to instruction decoder 2328 which in turn decodes or interprets instructions. In at least one embodiment, instruction decoder 2328 decodes a received instruction as one or more operations on

[0383] In at least one embodiment, some instructions can be converted into a single micro- operation, while others can require several micro-operations to complete. In at least one embodiment, if more than four micro-instructions are needed to complete a single instruction, then instruction decoder 2328 can access microcode ROM 2332 to perform the instruction. In at least one embodiment, instructions can be decoded into a small number of micro-instructions to handle at instruction decoder 2328. In at least one embodiment, if multiple micro-instructions are needed to complete an operation, then an instruction can be stored in microcode ROM 2332. In at least one embodiment, a trace cache 2330 references an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading a microcode sequence from microcode ROM 2332 to complete one or more instructions, in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 2332 completes sequencing of micro-operations for an instruction, a front end 2301 of a machine can resume fetching micro-operations from trace cache 2330.

[0384] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2303 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. In at least one embodiment, the OOO engine 2303 includes, but is not limited to, an allocator / register renamer 2340, a memory microinstruction queue 2342, an integer / floating-point microinstruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2304, and a simple floating-point scheduler ("simple FP scheduler") 2306. In at least one embodiment, the fast scheduler 2302, the slow / general purpose floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to as "microinstruction schedulers 2302, 2304, 2306." In at least one embodiment, the allocator / register renamer 2340 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2340 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2340 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2342 for memory operations and an integer / floating-point microinstruction queue 2344 for non-memory operations, preceding the memory scheduler 2346 and the microinstruction schedulers 2302, 2304, 2306. In at least one embodiment, the microinstruction schedulers 2302, 2304, 2306 determine when a microinstruction is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2302 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2304 and the simple floating-point scheduler 2306 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2302, 2304, 2306 arbitrate on dispatch ports to schedule microinstructions for execution.

[0385] In at least one embodiment, execution block 2311 includes, without limitation, integer register file / bypass network 2308, floating point register file / bypass network (“FP register file / bypass network”) 2310, address generation units (“AGUs”) 2312 and 2314, fast arithmetic logic units (“fast ALUs”) 2316 and 2318, slow arithmetic logic unit (“slow ALU”) 2320, floating point ALU (“FP”) 2322, and floating point move unit (“FP move”) 2324. In at least one embodiment, integer register file / bypass network 2308 and floating point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310.” In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating point ALU 2322, and floating point move unit 2324 are also referred to herein as “execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324.” In at least one embodiment, execution block 2311 can include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

[0386] In at least one embodiment, register networks 2308, 2310 can be arranged between micro-instruction schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating point register file / bypass network 2310 performs floating point operations. In at least one embodiment, each of register networks 2308, 2310 can include, without limitation, a bypass network that can bypass or forward a just-completed result that has not yet been written into a register file to a new dependee. In at least one embodiment, register networks 2308, 2310 can communicate data with each other. In at least one embodiment, integer register file / bypass network 2308 can include, without limitation, two separate register files, one for low order 32 bits data, a second for high order 32 bits data. In at least one embodiment, floating point register file / bypass network 2310 can include, without limitation, 128 bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0387] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 can execute instructions. In at least one embodiment, register files 2308, 2310 store integer and floating point data operand values that microinstructions need to operate on. In at least one embodiment, processor 2300 can include, without limitation, any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 can execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 2322 can include, without limitation, a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. In at least one embodiment, instructions for dealing with floating point values can be handled with floating point hardware. In at least one embodiment, ALU operations can be passed to fast ALUs 2316, 2318. In at least one embodiment, fast ALUs 2316, 2318 can execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 2320 as slow ALU 2320 can include, without limitation, integer execution hardware for long latency type operations such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be executed by AGUs 2312, 2314. In at least one embodiment, fast ALUs 2316, fast ALUs 2318, and slow ALU 2320 can execute integer operations on 64 bit data operands. In at least one embodiment, fast ALUs 2316, fast ALUs 2318, and slow ALU 2320 can be implemented to support a range of operand data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 can be implemented to support a range of operations on operands of various widths including 128 bits wide packed data operands which can be operated on in conjunction with SIMD and multimedia instructions.

[0388] In at least one embodiment, micro-instruction schedulers 2302, 2304, 2306 schedule dependent operations prior to completion of parent load execution. In at least one embodiment, because micro-instructions can be speculatively scheduled and executed in processor 2300, processor 2300 can also include logic to handle memory misses. In at least one embodiment, if a data load in a data cache misses, there can be a dependent operation running in a pipeline that causes a scheduler to temporarily have incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations can need to be replayed and independent operations can be allowed to complete. In at least one embodiment, a scheduler and replay mechanism of at least one embodiment of a processor can also be designed to capture instruction sequences for text string compare operations.

[0389] In at least one embodiment, a “register” can refer to an on-board processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used from outside of a processor (from a programmer’s perspective). In at least one embodiment, a register can not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein can be implemented by circuitry within a processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packing data.

[0390] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7L and / or 7M. In at least one embodiment, inference and / or training logic 715 can be used in Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7L and / or 7M. In at least one embodiment, portions or all of inference and / or training logic 715 can be incorporated into execution block 2311 and other memory or registers shown or not shown. For example, in at least one embodiment, training and / or inferencing techniques described herein can use one or more ALUs shown in execution block 2311. Further, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of execution block 2311 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0391] Figure 24A deep learning application processor 2400 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2400 uses instructions that, if executed by the deep learning application processor 2400, cause the deep learning application processor 2400 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2400 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2400 performs matrix multiplication operations or "hardwires" them into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2400 includes, but is not limited to, processing clusters 2410(1)-2410(12), inter-chip links (“ICLs”) 2420(1)-2420(12), inter-chip controllers (“ICCs”) 2430(1)-2430(2), second generation high bandwidth memory (“HBM2”) 2440(1)-2440(4), memory controllers (“MemCtrlr”) 2442(1)-2442(4), high bandwidth memory physical layer (“HBM PHY”) 2444(1)-2444(4), a management controller central processing unit (“management controller CPU”) 2450, serial peripheral interface, inter-integrated circuit, and general purpose input / output blocks (“SPI, I2C, GPIO”) 2460, peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2470, and sixteen lane peripheral component interconnect express ports (“PCI Express x 16”)2480.

[0392] In at least one embodiment, the processing cluster 2410 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2400 can include any number and type of processing clusters. In at least one embodiment, the inter-chip link 2420 is bidirectional. In at least one embodiment, the inter-chip link 2420 and the inter-chip controller 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2400 can include any number (including zero) and type of ICL 2420 and ICC 2430.

[0393] In at least one embodiment, HBM2 2440 provides a total of 32 GB of memory. In at least one embodiment, HBM2 2440(i) is associated with both a memory controller 2442(i) and an HBM PHY 2444(i), where “i” is any integer. In at least one embodiment, any number of HBM2s 2440 can provide any type and total amount of high bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2442 and HBM PHYs 2444. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2460, and DMA 2470 and / or PCIe 2480 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0394] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7i and / or 7j. Figure 7A and / or Figure 7B Details regarding inference and / or training logic 715 are provided below in conjunction with FIGS. 7i and / or 7j. In at least one embodiment, deep learning application processor is used to train machine learning models (e.g., neural networks) to predict or infer information provided to deep learning application processor 2400. In at least one embodiment, deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by deep learning application processor 2400. In at least one embodiment, processor 2400 can be used to perform one or more neural network use cases described herein.

[0395] Figure 25is a block diagram of a neuromorphic processor 2500, in accordance with at least one embodiment. In at least one embodiment, neuromorphic processor 2500 can receive one or more inputs from a source external to neuromorphic processor 2500. In at least one embodiment, these inputs can be transmitted to one or more neurons 2502 within neuromorphic processor 2500. In at least one embodiment, neurons 2502 and components thereof can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2500 can include, without limitation, thousands or millions of instances of neurons 2502, although any suitable number of neurons 2502 can be used. In at least one embodiment, each instance of neurons 2502 can include neuron input 2504 and neuron output 2506. In at least one embodiment, neurons 2502 can generate outputs that can be transmitted to inputs of other instances of neurons 2502. In at least one embodiment, neuron input 2504 and neuron output 2506 can be interconnected via synapses 2508.

[0396] In at least one embodiment, the neurons 2502 and synapses 2508 can be interconnected so that the neuromorphic processor 2500 operates to process or analyze information received by the neuromorphic processor 2500. In at least one embodiment, the neuron 2502 can send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2504 exceeds a threshold. In at least one embodiment, the neuron 2502 can sum or integrate the signal received at the neuron input 2504. For example, in at least one embodiment, the neuron 2502 can be implemented as a leaky integrate-and-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2502 can generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-and-trigger neuron can sum the signal received at the neuron input 2504 into a membrane potential and can apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may trigger if multiple input signals are received at neuron input 2504 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2502 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2502 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2506 when the result of applying the transfer function to neuron input 2504 exceeds a threshold. In at least one embodiment, once neuron 2502 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2502 may resume normal operation after a suitable period of time (or recovery period).

[0397] In at least one embodiment, neurons 2502 can be interconnected via synapses 2508. In at least one embodiment, synapses 2508 can be operable to transmit a signal from an output of a first neuron 2502 to an input of a second neuron 2502. In at least one embodiment, a neuron 2502 can transmit information across more than one instance of synapse 2508. In at least one embodiment, one or more instances of a neuron output 2506 can be connected to an instance of a neuron input 2504 in the same neuron 2502 via an instance of synapse 2508. In at least one embodiment, an instance of a neuron 2502 that generates an output to be transmitted across an instance of synapse 2508 can be referred to as a "presynaptic neuron" relative to that instance of synapse 2508. In at least one embodiment, an instance of a neuron 2502 that receives an input transmitted across an instance of synapse 2508 can be referred to as a "postsynaptic neuron" relative to an instance of synapse 2508. In at least one embodiment, with respect to the various instances of synapses 2508, because an instance of neuron 2502 can receive input from one or more instances of synapses 2508 and can also transmit output through one or more instances of synapses 2508, a single instance of neuron 2502 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0398] In at least one embodiment, neurons 2502 may be organized into one or more layers. In at least one embodiment, each instance of a neuron 2502 may have a neuron output 2506 that may fan out to one or more neuron inputs 2504 via one or more synapses 2508. In at least one embodiment, the neuron output 2506 of a neuron 2502 in a first layer 2510 may be connected to the neuron input 2504 of a neuron 2502 in a second layer 2512. In at least one embodiment, layers 2510 may be referred to as "feed-forward layers." In at least one embodiment, each instance of a neuron 2502 in an instance of the first layer 2510 may fan out to each instance of a neuron 2502 in the second layer 2512. In at least one embodiment, the first layer 2510 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 2502 in each instance of the second layer 2512 may fan out to fewer than all instances of a neuron 2502 in the third layer 2514. In at least one embodiment, the second layer 2512 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2502 in the second layer 2512 can fan out to neurons 2502 in multiple other layers, including neurons 2502 in the second layer 2512. In at least one embodiment, the second layer 2512 can be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2500 can include, but is not limited to, any suitable combination of recurrent layers and feedforward layers, including, but not limited to, sparsely connected feedforward layers and fully connected feedforward layers.

[0399] In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, a reconfigurable interconnect fabric or a dedicated hardwired interconnect to connect synapses 2508 to neurons 2502. In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2502 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2508 may be connected to neurons 2502 using an interconnect fabric such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0400] Figure 26A processing system is shown in accordance with at least one embodiment. In at least one embodiment, system 2600 includes one or more processor(s) 2602 and one or more graphics processor(s) 2608, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having many processor(s) 2602 or processor core(s) 2607. In at least one embodiment, system 2600 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0401] In at least one embodiment, system 2600 can include or be incorporated within a server-based gaming platform, including a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2600 is a mobile phone, a smart phone, a tablet device, or a mobile internet device. In at least one embodiment, processing system 2600 can also include or be coupled with a wearable device, such as a smart watch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2600 is a television or set top box device having one or more processor(s) 2602, as well as a graphical interface generated by one or more graphics processor(s) 2608.

[0402] In at least one embodiment, one or more processor(s) 2602 each include one or more processor cores 2607 to process instructions which, when executed, implement the operations for system and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction sequence 2609. In at least one embodiment, instruction sequence 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). In at least one embodiment, processor cores 2607 can each process different instruction sequences 2609 which can include instructions to facilitate emulation of other instruction sequences. In at least one embodiment, processor cores 2607 can each also include other processing devices, such as digital signal processors (DSPs).

[0403] In at least one embodiment, the processor 2602 includes a cache memory 2604. In at least one embodiment, the processor 2602 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2602. In at least one embodiment, the processor 2602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared among the processor cores 2607 using known cache coherence techniques. In at least one embodiment, the processor 2602 further includes a register file 2606. The processor can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 2606 can include general purpose registers or other registers.

[0404] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transmit communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2610 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a platform controller hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between memory devices and other components of the processing system 2600, while the platform controller hub (PCH) 2630 provides connections to input / output (I / O) devices via a local I / O bus.

[0405] In at least one embodiment, memory device 2620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or a phase change memory device, among others. In at least one embodiment, memory device 2620 can be a system memory of processing system 2600, to store data 2622 and instructions 2621 for use when one or more processors 2602 executes an application or process. In at least one embodiment, memory controller 2616 also couples with an optional external graphics processor 2612, which can communicate with one or more graphics processors 2608 in processors 2602 to perform graphics and media operations.

[0406] In at least one embodiment, platform controller hub 2630 enables peripherals coupled to bridge 2622 to interact with a processor coupled to memory controller hub 2616. In at least one embodiment, platform controller hub 2630 can mediate communication between a processor coupled to memory controller hub 2616 and devices coupled to bridge 2622 via an I / O bus (e.g., a PCI bus). In at least one embodiment, platform controller hub 2630 can provide a plurality of different I / O buses for coupling to devices. In at least one embodiment, platform controller hub 2630 can enable devices to be connected to memory controller hub 2616 via an I / O bus (e.g., an internal bus such as PCI using a PCI-to-PCI bridge 2623). In at least one embodiment, platform controller hub 2630 can also enable a display controller 2650 (e.g., a graphics processing unit (GPU)) to be connected to a display device (e.g., a flat panel display) via an internal bus such as a microchannel bus.

[0407] In at least one embodiment, memory controller 2616 and instances of platform controller hub 2630 can be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, platform controller hub 2630 and / or memory controller 2616 can be external to one or more processor(s) 2602. For example, in at least one embodiment, system 2600 can include an external memory controller 2616 and platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that is in communication with a processor(s) 2602.

[0408] Inference and / or training logic 715 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are described in more detail below. Figure 7A and / or Figure 7BDetails regarding the inference and / or training logic 715 are provided. In at least one embodiment, some or all of inference and / or training logic 715 can be incorporated with system 2600. For example, in at least one embodiment, the training and / or inference techniques described herein can use one or more ALUs embodied in a 3D pipeline. Moreover, in at least one embodiment, the inference and / or training operations described herein can be done using logic other than that shown. In at least one embodiment, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not) that configure ALUs of graphics processor 2600 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. Figure 10A or Figure 10B

[0409] Figure 27 is a block diagram of a processor 2700 having one or more processor cores 2702A-2702N, an integrated memory controller 2714, and an integrated graphics processor 2708, according to at least one embodiment. In at least one embodiment, processor 2700 can include additional cores, up to and including the additional core 2702N represented by the dashed line. In at least one embodiment, each processor core 2702A-2702N includes one or more internal cache units 2704A-2704N. In at least one embodiment, each processor core can also access one or more shared cache units 2706.

[0410] In at least one embodiment, internal cache units 2704A-2704N and shared cache unit 2706 represent a cache memory hierarchy within processor 2700. In at least one embodiment, cache memory units 2704A-2704N can include at least one level of instruction and data caches per processor core and one or more shared level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache, where the highest level of cache prior to main memory is classified as an LLC. In at least one embodiment, cache coherence logic maintains coherence between various cache units 2706 and 2704A-2704N.

[0411] ​In at least one embodiment, processor 2700 can also include a set of one or more bus controller units 2716 and a system agent core 2710. In at least one embodiment, one or more bus controller units 2716 manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, system agent core 2710 provides management functionality for various processor components. In at least one embodiment, system agent core 2710 includes one or more integrated memory controllers 2714 to manage access to various external memory devices (not shown).

[0412] In at least one embodiment, one or more processor cores 2702A-2702N include support to

[0413] In at least one embodiment, processor 2700 also includes graphics processor 2708, which can be configured to perform a graphics processing operations. In at least one embodiment, graphics processor 2708 couples with shared cache unit 2706, and system agent core 2710, which includes one or more integrated memory controllers 2714. In at least one embodiment, system agent core 2710 also includes a display controller 2711 for driving one or more coupled displays to present graphics processor output. In at least one embodiment, display controller 2711 can also be a separate module coupled with graphics processor 2708 via at least one interconnect, or can be integrated within graphics processor 2708.

[0414] In at least one embodiment, ring based interconnect unit 2712 is used to couple the internal components of processor 2700. In at least one embodiment, an alternative interconnect unit can be used, such as a point-to-point interconnect, a switched interconnect, or other technology. In at least one embodiment, graphics processor 2708 couples with ring interconnect 2712 via I / O link 2713.

[0415] In at least one embodiment, I / O link 2713 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2718 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2702A-2702N and the graphics processor 2708 uses the embedded memory module 2718 as a shared last-level cache.

[0416] In at least one embodiment, the processor cores 2702A-2702N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2702A-2702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2702A-2702N execute a common instruction set, while one or more other processor cores 2702A-2702N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2...

Claims

1. A processor, comprising: One or more circuits to multiply two or more sub-portions of one or more matrices and generate two or more vectors from the multiplication using two or more parallel operations, the two or more parallel operations comprising a plurality of hierarchical operations to: performing a reduction of a matrix multiplication MM of a first matrix of the one or more matrices and a second matrix of the one or more matrices, and wherein the one or more circuits are further configured to: At each hierarchical operation, representing the first matrix via a first plurality of sub-portions, the first plurality of sub-portions having a size corresponding to an order of the respective hierarchical operation; as well as At the respective hierarchical operations, a reduction operation is applied to the result of the MM by multiplying the result of the MM by an auxiliary matrix, each element of the first column of the auxiliary matrix having a value of 1.

2. The processor of claim 1 , wherein the one or more circuits are further configured to: At the respective hierarchical operations, the reduction operation is applied to a result of the MM involving one of the first plurality of sub-portions to generate a corresponding vector of the two or more vectors.

3. The processor of claim 2, wherein the one or more circuits are further configured to represent the second matrix via a plurality of second sub-portions.

4. The processor of claim 3, wherein in the respective hierarchical operations, the number of matrix elements in each of the first plurality of subdivisions is equal to the number of matrix elements in each of the second plurality of subdivisions.

5. The processor of claim 2, wherein the one or more circuits are configured to use one or more instances of a hardware instruction for MM including a matrix of predetermined dimensions to perform a hierarchical operation at a lowest hierarchical level.

6. The processor of claim 5, wherein the one or more circuits are configured to execute the hardware instructions using a plurality of threads, each thread being associated with: a plurality of input matrix elements into each of the matrices input into the hardware instruction; and A plurality of output matrix elements in the matrix output by the hardware instruction.

7. The processor of claim 6, wherein the one or more circuits are to reallocate at least some of the plurality of output matrix elements to different threads before applying the reduction operation.

8. The processor of claim 6, wherein the one or more circuits are configured to store the plurality of input matrix elements and the plurality of output matrix elements associated with each thread in registers accessible by the corresponding thread.

9. The processor of claim 2, wherein the auxiliary matrix comprises at least one of a row of zero elements or a column of zero elements.

10. The processor of claim 2, wherein the one or more circuits are configured to perform a highest-level hierarchy operation using a core that is distinct from one or more cores configured to perform other hierarchy operations.

11. A system comprising: One or more circuits to multiply two or more sub-portions of one or more matrices and generate two or more vectors from the multiplication using two or more parallel operations, the two or more parallel operations comprising a plurality of hierarchical operations to: performing a reduction of a matrix multiplication MM of a first matrix of the one or more matrices and a second matrix of the one or more matrices, and wherein the one or more circuits are further configured to: At each hierarchical operation, representing the first matrix via a first plurality of sub-portions, the first plurality of sub-portions having a size corresponding to an order of the respective hierarchical operation; as well as applying a reduction operation to a result of the MM at the respective hierarchical operation by multiplying the result of the MM by an auxiliary matrix, wherein each element of the first column of the auxiliary matrix has a value of 1; as well as One or more memories for storing the two or more vectors.

12. The system of claim 11, wherein the one or more circuits are further configured to: At each hierarchical operation, the reduction operation is applied to a result of the MM involving one of the first plurality of sub-portions to generate a corresponding vector of the two or more vectors.

13. The system of claim 12, wherein the one or more circuits are further configured to represent the second matrix via a plurality of second sub-portions.

14. The system of claim 13, wherein in the respective hierarchical operations, the number of matrix elements in each of the first plurality of subdivisions is equal to the number of matrix elements in each of the second plurality of subdivisions.

15. The system of claim 12, wherein the one or more circuits are configured to use one or more instances of a hardware instruction of MM including a matrix of predetermined dimensions to perform a hierarchical operation at a lowest hierarchical level.

16. The system of claim 15, wherein the one or more circuits are configured to execute the hardware instructions using a plurality of threads, each thread being associated with: a plurality of input matrix elements into each of the matrices input into the hardware instruction; and A plurality of output matrix elements in the matrix output by the hardware instruction.

17. The system of claim 16, wherein the one or more circuits are to reallocate at least some of the plurality of output matrix elements to different threads before applying the reduction operation.

18. The system of claim 16, wherein the one or more circuits are configured to store the plurality of input matrix elements and the plurality of output matrix elements associated with each thread in registers accessible by the corresponding thread.

19. The system of claim 12, wherein the auxiliary matrix comprises at least one of a row of zero elements or a column of zero elements.

20. The system of claim 12, wherein the one or more circuits are configured to perform a highest-level hierarchical operation using a core that is distinct from one or more cores configured to perform other hierarchical operations.

21. A method comprising: multiplying two or more subsections of one or more matrices using one or more circuits; as well as Generating two or more vectors from the multiplication using two or more parallel operations, the two or more parallel operations comprising a plurality of hierarchical operations for: performing a reduction of a matrix multiplication MM of a first matrix of the one or more matrices and a second matrix of the one or more matrices, each hierarchical operation comprising: representing the first matrix via a first plurality of sub-portions, the first plurality of sub-portions having a size corresponding to an order of a respective hierarchical operation; as well as A reduction operation is applied to the result of the MM by multiplying the result of the MM by an auxiliary matrix, wherein each element of the first column of the auxiliary matrix has a value of 1.

22. The method of claim 21, wherein each layering operation further comprises: The reduction operation is applied to a result of the MM involving one of the first plurality of sub-portions to generate a vector of the two or more vectors.

23. The method of claim 22, wherein each layering operation further comprises: The second matrix is ​​represented via a plurality of second sub-portions.

24. The method of claim 23, wherein in each hierarchical operation, the number of matrix elements in each of the first plurality of subdivisions is equal to the number of matrix elements in each of the second plurality of subdivisions.

25. The method of claim 22, wherein the lowest level of hierarchical operation is performed using one or more instances of a hardware instruction for MM including a matrix of predetermined dimensions.

26. The method of claim 25, wherein the hardware instructions are executed by a plurality of threads in a graphics processing unit, each thread being associated with: a plurality of input matrix elements into each of the matrices input into the hardware instruction; and A plurality of output matrix elements in the matrix output by the hardware instruction.

27. The method of claim 26, wherein at least some of the plurality of output matrix elements are reallocated to different threads prior to applying the reduction operation.

28. The method of claim 26, wherein the plurality of input matrix elements and the plurality of output matrix elements associated with each thread are stored in registers accessible by the corresponding thread.

29. The method of claim 22, wherein the auxiliary matrix comprises at least one of a row of zero elements or a column of zero elements.

30. The method of claim 22, wherein the highest-level hierarchical operation is performed by a kernel that is different from one or more kernels that perform other hierarchical operations.

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