Method of reading / writing data, memory, storage device and terminal

Abstract

A method for reading / writing data, a memory, a storage device and a terminal, the memory comprising S memory blocks, N global bit lines and a signal amplification circuit, each of the S memory blocks being connected with the N global bit lines, the N global bit lines being connected with the signal amplification circuit, the signal amplification circuit being used for amplifying electrical signals in the N global bit lines; each of the memory blocks comprising N columns of memory cells, N local bit lines and N bit line switches, wherein: in each of the memory blocks, the i-th column of memory cells is connected with the i-th local bit line; the i-th local bit line is connected with the i-th global bit line through the i-th bit line switch of the N bit line switches. By fine-grained storage array, the i-th local bit line of the S memory blocks can share a global bit line, the local bit line is shortened, the parasitic capacitance caused by the local bit line is reduced, and the memory delay is reduced.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a method for reading / writing data, a memory, a storage device, and a terminal. Background Technology

[0002] With the development of computer technology, the bottleneck to improving the operating speed of computer systems lies in memory, and most of the memory latency comes from row cycle time (tRC) latency. The relatively bulky size of a single memory array (typically 512 rows * 1024 columns of memory cells) is one of the main reasons for high tRC latency. In large-cell memory arrays, each transistor turn-on on a word line and each long-distance data transfer on a bit line causes memory latency.

[0003] Reducing memory latency is a pressing technical problem that needs to be solved to improve computer performance. Summary of the Invention

[0004] This invention provides a method for reading / writing data, a memory, a storage device, and a terminal, which can solve the technical problem of high latency in current computer systems.

[0005] In a first aspect, embodiments of this application provide a memory, including S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks is connected to the N global bit lines, and the N global bit lines are connected to the signal amplification circuit. The signal amplification circuit amplifies the electrical signals in the N global bit lines, where S and N are positive integers, and S ≥ 2. Each memory block includes N columns of memory cells, N local bit lines, and N bit line switches, wherein:

[0006] In each storage block, the i-th column of the N columns of storage cells is connected to the i-th local bit line among the N local bit lines; the i-th local bit line is connected to the i-th global bit line among the N global bit lines through the i-th bit line switch among the N bit line switches, where N is a positive integer and i is a positive integer not greater than N.

[0007] In the aforementioned memory, the i-th local bit line in each memory block is connected to the same global bit line, i.e., the i-th global bit line, through a bit line switch. Therefore, by controlling the on / off state of the i-th bit line switch in each memory block, the on / off state of the i-th local bit line and the i-th global bit line in each memory block can be controlled. This allows the i-th local bit lines of S memory blocks to share a single global bit line, and the S memory blocks to share a single signal amplification circuit and bit line driving circuit. This reduces the number of signal amplification circuits and bit line driving circuits in the memory, lowering the memory manufacturing cost. Furthermore, finer-grained memory array design can shorten local bit lines, reduce parasitic capacitance caused by local bit lines, and decrease read / write operation latency.

[0008] In one possible implementation, the signal amplification circuit includes N differential amplifiers, wherein the i-th differential signal amplifier among the N differential amplifiers is used to amplify the electrical signal on the i-th global bit line.

[0009] The aforementioned memory can simultaneously read data from storage cells located in different columns, thereby improving the speed of memory read operations.

[0010] In one possible implementation, the signal amplification circuit includes P multiplexers and P differential amplifiers; the input of the k-th multiplexer of the P multiplexers is connected to at least two of the N global bit lines, and the output of the k-th multiplexer of the P multiplexers is connected to the k-th differential amplifier of the P differential amplifiers. The k-th multiplexer of the P multiplexers is used to select one of the electrical signals transmitted by the at least two global bit lines for output, where P is a positive integer not greater than N, and k is a positive integer not greater than P.

[0011] The memory using the above-mentioned signal amplification circuit allows data in multiple memory cells indirectly connected to different multiplexers to be read simultaneously, balancing speed and cost.

[0012] In one possible implementation, each memory block further includes N first control lines that are respectively connected to the control terminals of the N bit line switches. The N first control lines are all connected to a first control circuit, which is used to control the conduction of the N bit line switches.

[0013] In one possible implementation, the memory further includes a bit line driving circuit connected to the N global bit lines for inputting electrical signals into the N global bit lines.

[0014] In one possible implementation, the storage cells in each storage block are arranged in M ​​rows * N columns of storage cells, and each storage block also includes M word lines. The j-th row of storage cells in the M rows * N columns is connected to the j-th word line in the M word lines, where M is a positive integer and j is a positive integer not greater than M.

[0015] Optionally, the memory further includes a word line driving circuit connected to the word lines in the S memory blocks, the word line driving circuit being used to control the potential of the word lines.

[0016] In one possible implementation, each memory block is divided into T sub-blocks, arranged in S rows and T columns, with each column forming a memory domain. The memory comprises T memory domains and W global word lines, where T and W are positive integers and T ≥ 2. Each of the T memory domains comprises W rows of memory cells, W local word lines, and W word line switches, wherein:

[0017] In each storage domain, the vth row of the W rows of storage cells is connected to the vth local word line among the W local word lines; the vth local word line is connected to the vth local word line among the W global word lines through the vth word line switch among the W bit line switches, where W is a positive integer and v is a positive integer not greater than W.

[0018] The aforementioned memory, through fine-grained memory, not only shortens local bit lines but also local word lines, further reducing memory operation latency and improving memory performance.

[0019] Optionally, each storage domain further includes W second control lines that are respectively connected to the W word line switches. The W second control lines are all connected to a second control circuit, which is used to control the conduction of the W word line switches.

[0020] Optionally, the memory further includes a word line driving circuit, which is connected to the global word lines in the T memory domains and is used to control the potential of the global word lines.

[0021] Secondly, embodiments of this application also provide a storage device, including: any of the memory and storage controller described in the first aspect above, wherein the memory is coupled to the storage controller.

[0022] For details on the specific implementation of the memory, please refer to the relevant description in the first aspect above, which will not be repeated here.

[0023] Thirdly, embodiments of this application also provide a terminal, including: a processor and any of the memory described in the first aspect above, wherein the memory is coupled to the processor.

[0024] For details on the specific implementation of the memory, please refer to the relevant description in the first aspect above, which will not be repeated here.

[0025] Fourthly, embodiments of this application also provide a method for reading data, applied to a memory, the memory including S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks is connected to the N global bit lines, and the N global bit lines are connected to the signal amplification circuit. The signal amplification circuit is used to amplify the electrical signals in the N global bit lines, where S and N are positive integers, and S ≥ 2. Each memory block includes N columns of memory cells, N local bit lines, and N bit line switches. In each memory block, the i-th column of the N columns of memory cells is connected to the i-th local bit line among the N local bit lines, and the i-th local bit line is connected to the i-th global bit line among the N global bit lines through the i-th bit line switch among the N bit line switches, where N is a positive integer and i is a positive integer not greater than N. The method includes:

[0026] Select a target storage cell in the target storage block, wherein the target storage cell is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N;

[0027] Turn on the y-th bit line switch in the target memory block so that the electrical signal in the target memory cell is transmitted to the y-th global bit line among the N global bit lines through the y-th local bit line;

[0028] The electrical signal in the y-th global bit line is amplified by the signal amplification circuit.

[0029] In one possible implementation, the signal amplification circuit includes N differential amplifiers, wherein the i-th differential signal amplifier among the N differential amplifiers is connected to the i-th global bit line, and the amplification of the electrical signal in the y-th global bit line by the signal amplification circuit specifically includes:

[0030] The electrical signal in the y-th global bit line is amplified by a target differential amplifier, wherein the target differential amplifier is the differential amplifier connected to the y-th global bit line among the N differential amplifiers.

[0031] In one possible implementation, the signal amplification circuit includes P multiplexers and P differential amplifiers; the input of the k-th multiplexer of the P multiplexers is connected to at least two of the N global bit lines, and the output of the k-th multiplexer of the P multiplexers is connected to the k-th differential amplifier of the P differential amplifiers. The k-th multiplexer of the P multiplexers is used to select one global bit line signal from the electrical signals transmitted by the at least two global bit lines for output, where P is a positive integer not greater than N, and k is a positive integer not greater than P. Amplifying the electrical signal in the y-th global bit line through the signal amplification circuit specifically includes:

[0032] The electrical signal in the y-th global bit line is input to the target differential amplifier connected to the target multiplexer by connecting the target multiplexer to the target multiplexer;

[0033] The electrical signal in the y-th global bit line is amplified by the target differential amplifier.

[0034] In one possible implementation, each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, wherein turning on the y-th bit line switch in the target memory block includes:

[0035] A control signal is input to the first control line connected to the y-th bit line switch to turn on the y-th bit line switch.

[0036] In one possible implementation, the storage cells in each storage block are arranged in M ​​rows * N columns. Each storage block also includes M word lines. The j-th row of the M rows * N columns of storage cells is connected to the j-th word line of the M word lines, where M is a positive integer and j is a positive integer not greater than M. The target storage cell is connected to the x1-th word line of the target storage block, where x1 is a positive integer not greater than M.

[0037] Selecting the target storage unit in the target storage block includes:

[0038] Input a control signal to select the target memory cell into the x1th word line.

[0039] In one possible implementation, each memory block is divided into T sub-blocks, and the sub-blocks in the memory are arranged in S rows and T columns, with each column forming a memory domain. The memory includes T memory domains and W global word lines, where T and W are positive integers and T ≥ 2. Each memory domain includes W rows of memory cells, W local word lines, and W word line switches. The v-th row of memory cells is connected to the v-th local word line among the W local word lines. The v-th local word line is connected to the v-th local word line among the W global word lines via the v-th word line switch among the W bit line switches, where W is a positive integer and v is a positive integer not greater than W. The target memory cell is connected to the x2-th local word line in the target memory domain, where x2 is a positive integer not greater than W. The target memory cell in the selected target memory block includes:

[0040] Turn on the x2th word line switch in the target memory domain to turn on the x2th local word line and the x2th global word line in the W global word line;

[0041] A control signal for selecting the target memory cell is input to the x2th global word line of the W global word lines.

[0042] Optionally, the storage domain further includes W second control lines respectively connected to the W word line switches, wherein turning on the x2th word line switch in the target storage domain includes:

[0043] A control signal is input to the second control line connected to the x2th word line switch to turn on the x2nd word line switch.

[0044] Fifthly, embodiments of this application also provide a method for writing data, applied to a memory, the memory including S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks is connected to the N global bit lines, and the N global bit lines are connected to the signal amplification circuit. The signal amplification circuit is used to amplify the electrical signals in the N global bit lines, where S and N are positive integers, and S ≥ 2. Each memory block includes N columns of memory cells, N local bit lines, and N bit line switches. In each memory block, the i-th column of memory cells is connected to the i-th local bit line among the N local bit lines, and the i-th local bit line is connected to the i-th global bit line among the N global bit lines through the i-th bit line switch among the N bit line switches. N is a positive integer, and i is a positive integer not greater than N. The method includes:

[0045] Select a target storage cell in the target storage block, wherein the target storage cell is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N;

[0046] Turn on the y-th bit line switch in the target memory block to turn on the y-th local bit line and the y-th global bit line among the N global bit lines;

[0047] The target electrical signal is input to the y-th global bit line so that the target electrical signal is stored in the target memory cell.

[0048] In one possible implementation, each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, wherein turning on the y-th bit line switch in the target memory block includes:

[0049] A control signal is input to the first control line connected to the y-th bit line switch to turn on the y-th bit line switch.

[0050] In one possible implementation, the storage cells in each storage block are arranged in M ​​rows * N columns. Each storage block also includes M word lines. The j-th row of storage cells in the M rows * N columns is connected to the j-th word line of the M word lines, where M is a positive integer and j is a positive integer not greater than M. The target storage cell is connected to the x1-th word line in the target storage block, where x1 is a positive integer not greater than M. The target storage cell in the selected target storage block includes:

[0051] Input a control signal to select the target memory cell into the x1th word line.

[0052] In one possible implementation, each memory block is divided into T sub-blocks, and the sub-blocks in the memory are arranged in S rows and T columns, with each column forming a memory domain. The memory includes T memory domains and W global word lines, where T and W are positive integers and T ≥ 2. Each memory domain includes W rows of memory cells, W local word lines, and W word line switches. The v-th row of memory cells is connected to the v-th local word line among the W local word lines. The v-th local word line is connected to the v-th local word line among the W global word lines via the v-th word line switch among the W bit line switches, where W is a positive integer and v is a positive integer not greater than W. The target memory cell is connected to the x2-th word line in the target memory domain, where x2 is a positive integer not greater than W. Selecting the target memory cell in the target memory block includes:

[0053] Turn on the x2th word line switch in the target memory domain to turn on the x2th local word line and the x2th global word line in the W global word line;

[0054] A control signal for selecting the target memory cell is input to the x2th global word line of the W global word lines.

[0055] Optionally, the storage domain further includes W second control lines respectively connected to the W word line switches, wherein turning on the x2th word line switch in the target storage domain includes:

[0056] A control signal is input to the second control line connected to the x2th word line switch to enable the x2th word line switch to turn on.

[0057] In a sixth aspect, embodiments of this application also provide a storage controller applied to any of the memory described in the first aspect, including a method for implementing any of the data reading methods described in the fourth aspect.

[0058] In a seventh aspect, embodiments of this application also provide a storage controller applied to any of the memory described in the first aspect, including a method for implementing any of the data reading methods described in the fifth aspect.

[0059] Eighthly, embodiments of this application also provide a chip, including any of the memory types described in the first aspect. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0061] Figure 1 This is a circuit diagram of a memory provided by existing technology;

[0062] Figure 2 This is a circuit diagram of a memory provided in an embodiment of this application;

[0063] Figure 3 This is a circuit diagram of a storage unit provided in an embodiment of this application;

[0064] Figure 4 This is a circuit diagram of another memory provided in an embodiment of this application;

[0065] Figure 5 This is a schematic diagram illustrating the working principle of a storage unit provided in an embodiment of this application;

[0066] Figure 6 This is a circuit diagram of yet another memory provided in an embodiment of this application;

[0067] Figure 7 This is a schematic diagram illustrating the working principle of a storage unit provided in an embodiment of this application;

[0068] Figure 8 This is a circuit diagram of a signal method circuit provided in an embodiment of this application;

[0069] Figure 9 This is a circuit diagram of another signal method circuit provided in an embodiment of this application;

[0070] Figure 10 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0071] Figure 11A This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0072] Figure 11B This is a schematic diagram of the structure of another computing device provided in an embodiment of this application;

[0073] Figure 12 This is a flowchart illustrating a method for reading data provided in an embodiment of this application;

[0074] Figure 13 This is a flowchart illustrating a method for writing data provided in an embodiment of this application;

[0075] Figure 14 This is a schematic diagram of the structure of a storage controller provided in an embodiment of this application;

[0076] Figure 15 This is a schematic diagram of another storage controller provided in an embodiment of this application. Detailed Implementation

[0077] The memory shown in the embodiments of this application can be random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), high bandwidth memory (HBM), read only memory (ROM), and can also be cache, flash memory, hard disk drive (HDD), solid state disk (SSD), etc.

[0078] To reduce memory latency, a method of fine-grained architecture for unit memory arrays can be adopted. For example... Figure 1 The diagram shown is a schematic diagram of a memory structure provided in an embodiment of this application. In this memory, the original memory array is divided into multiple smaller memory arrays, and logic circuits, such as bit line sense amplifiers (BLSA) or differential amplifiers (SA), are configured for each smaller memory array. Because the memory array is made more granular, the bit lines are shortened, thereby reducing the parasitic capacitance caused by the bit lines and reducing the memory latency.

[0079] However, while finer granularity reduces the capacity of each unit of memory array, it requires more area to configure logic circuits, resulting in a reduction in storage capacity for the same chip area and a significant increase in cost per unit (bit).

[0080] To reduce memory latency and lower memory cost, this application provides a memory that refines the memory array, shortens the length of bit lines within a unit memory array, reduces parasitic capacitance, and connects the bit lines (also called local bit lines) within each unit memory array to the global bit line via switches. This allows the bit lines within each unit memory array to share the global bit line, signal amplification circuit, bit line driving circuit, etc., thereby reducing circuit driving time and memory cost.

[0081] First, let's introduce the key terms used in this application.

[0082] (1) Unit storage array

[0083] A unit storage array is a storage array composed of storage cells, in which each row of storage cells is connected to a word line and each column of storage cells is connected to a bit line.

[0084] (2) Storage domain, storage block

[0085] In this application, a storage block or storage domain can be a unit storage array or multiple unit storage arrays arranged along the bit line or word line direction.

[0086] (3) Local bitline (LBL), global bitline (GBL), bitline switch

[0087] Bit lines are classified into local bit lines and global bit lines based on their location. Bit lines that are located only in a single unit memory array or connected only to memory cells in the same unit memory array are called local bit lines; bit lines that are located in multiple unit memory arrays or connected to memory cells in multiple unit memory arrays are called global bit lines.

[0088] It should be understood that in this application, the global bit lines are not directly connected to memory cells, but are connected to the local bit lines through a switch, which is referred to as the bit line switch in this application. That is, the bit line switch is a switch used to connect the local bit lines and the global word lines.

[0089] (4) Local wordline (LWL), global wordline (GWL), wordline switch

[0090] Word lines are classified into local word lines and global word lines based on their location. A word line that is only located within a single memory array or only connected to memory cells within the same memory array is called a local word line; a word line that is located in multiple memory arrays or connected to memory cells in multiple memory arrays is called a global word line.

[0091] It should be understood that in this application, the global word line is not directly connected to the memory cell, but is connected to the local word line through a switch. This switch is referred to as the word line switch in this application. That is, the word line switch is used to connect the local word line and the global word line.

[0092] The memory provided in this application is described below with reference to the accompanying drawings.

[0093] like Figure 2 The diagram shown is a circuit schematic of a memory according to an embodiment of this application. The memory may include S memory blocks, N global bit lines, a signal amplification circuit, a bit line driving circuit, and a word line driving circuit. Specifically: each of the S memory blocks is connected to N global bit lines; the N global bit lines are connected to the signal amplification circuit and the bit line driving circuit; the signal amplification circuit amplifies the electrical signals in the N global bit lines, where S and N are positive integers, and S ≥ 2. The bit line driving circuit selects the global bit line corresponding to a memory cell during a write operation to input an electrical signal to that global bit line; the word line driving circuit inputs an electrical signal to the word line corresponding to a memory cell during an operation (read or write operation).

[0094] It should be noted that, although Figure 2 The diagram shows bit line drive circuits, word line drive circuits, etc., but signal amplification circuits, bit line drive circuits, and word line drive circuits are not essential circuits for this application memory.

[0095] In some embodiments, the memory may further include a bit line driving circuit connected to the aforementioned N global bit lines for inputting electrical signals into the N global bit lines. It should be understood that the bit line driving circuit functions during memory write operations.

[0096] For example, when data needs to be written to a certain memory cell, the bit line driving circuit inputs the electrical signal corresponding to the data to be written into the global bit line electrically connected to the memory cell. The memory cell has two states, "0" and "1". For example, when the memory cell needs to be set to the "1" state, the bit line driving circuit inputs a high potential into the global bit line connected to it. Conversely, when the memory cell needs to be set to the "0" state, the bit line driving circuit inputs a low potential into the global bit line connected to it.

[0097] Each of the S memory blocks comprises N columns of memory cells, N local bit lines, and N bit line switches. Within each memory block, the i-th column of memory cells is connected to the i-th local bit line among the N local bit lines; the i-th local bit line is connected to the i-th global bit line among the N global bit lines via the i-th bit line switch among the N bit line switches, where N is a positive integer and i is a positive integer not greater than N. The value of i can be 1, 2, ..., N.

[0098] like Figure 2 The memory shown has S memory blocks, denoted as memory block (1), memory block (2), ..., memory block (S). N global bit lines are denoted as GBL(1), GBL(2), ..., GBL(N), where GBL(i) represents the i-th global bit line among the N global bit lines. Within each memory block, N local bit lines are denoted as LBL(1), LBL(2), ..., LBL(N), and N bit line switches are denoted as bit line switch 1, bit line switch 2, ..., bit line switch N, where LBL(i) represents the i-th local bit line in a memory block, and bit line switch i represents the i-th bit line switch in a memory block. It should be understood that although the N local bit lines and N bit line switches in each memory block use the same representation, LBL(i) in any two different memory blocks are actually two different local bit lines; similarly, bit line switch i in any two different memory blocks are actually two different bit line switches.

[0099] In one embodiment of this application, each memory block is a memory cell array comprising N columns of memory cells. S memory blocks are arranged along the bit line direction to form a memory block array, which also comprises N columns of memory cells. In this case, the memory cell located in the i-th column of each memory block remains in the i-th column of the memory block array composed of the S memory blocks. For a memory block, each memory cell in the i-th column is connected to the i-th local bit line, and the i-th local bit line is connected to the i-th global bit line through the i-th bit line switch.

[0100] As can be seen, the i-th local bit line in each memory block is connected to the same global bit line, i.e., the i-th global bit line, through a bit line switch. Therefore, by controlling the on / off state of the i-th bit line switch in each memory block, the on / off state of the i-th local bit line and the i-th global bit line in each memory block can be controlled. This allows the i-th local bit lines of S memory blocks to share a single global bit line, and the S memory blocks to share a single signal amplification circuit and bit line driving circuit. This reduces the number of signal amplification circuits and bit line driving circuits in the memory, lowering the memory manufacturing cost. Furthermore, finer-grained memory array design can shorten local bit lines, reduce parasitic capacitance caused by local bit lines, and decrease read / write operation latency.

[0101] In some embodiments, the memory cell can be a 1T1C (1 Transistor-1 Capacitor) memory cell, that is, it consists of one transistor and one capacitor, such as... Figure 3 The diagram shown is a circuit schematic of a storage unit provided in an embodiment of this application. Figure 3 Transistor T within the dashed box c Together with capacitor C, they form a storage cell, which is connected to a transistor T. c The capacitor C is controlled to charge / discharge. For example, for a memory cell, transistor T... c The gate of the transistor is connected to the word line, and the source and drain of the transistor are connected to the local bit line and capacitor C, respectively. Here, we take transistor T as an example. c Taking a field-effect transistor as an example, it should be understood that transistor T... c Other types of transistors, such as bipolar junction transistors, can also be used; this is not a limitation here. It should also be understood that the memory cell can be a memory cell with other structures, such as SRAM, where the memory cell includes transistors and latches; this is not a limitation here.

[0102] In some embodiments, a bit line switch may include a switch formed by at least one transistor that has on and off functions. For example, a bit line switch is a transistor.

[0103] It should be understood that the transistors in the memory cell or the transistors in the bit line switch can include bipolar transistors, field-effect transistors, etc. Figure 4 The diagram shown is a circuit schematic of another memory provided in an embodiment of this application. Figure 4 Using a bit line switch as a transistor T b Let's take a storage unit of 1T1C as an example to illustrate.

[0104] In some embodiments, such as Figure 2 or Figure 4 The memory shown may further include N first control lines, each connected to the control terminals of N bit line switches, and all N first control lines are connected to a first control circuit. Figure 2 or Figure 4 (Not shown in the diagram), the first control circuit is used to control the on and off of each bit line switch in the S memory blocks. In each memory block, N first control lines are represented as SC1(1), SC1(2), ..., SC1(N), where SC1(i) ​​represents the i-th first control line in a memory block. It should be understood that although the N first control lines in each memory block are represented in the same way, SC1(i) ​​in any two different memory blocks in the S memory blocks are actually two different first control lines.

[0105] For example, when a read / write operation is required on a specific memory cell within a memory block, the memory cell needs to be turned on via a bit line switch connected to a local bit line. In this case, the first control circuit can apply a high potential to the first control line connected to the bit line switch to keep the bit line switch on. Conversely, if no read / write operation is required, the memory cell that does not require read / write operation is turned off via the bit line switch connected to the local bit line. In this case, the first control circuit can apply a low potential to the first control line connected to the bit line switch to keep the bit line switch off. It should be understood that the above explanation uses an N-type MOS transistor as an example for the bit line switch.

[0106] In this embodiment of the application, a storage block may include multiple storage cells arranged in an array. Each storage block includes N columns of storage cells, but the number of rows of storage cells in each storage block may be the same or different. For example, as Figure 2 or Figure 4 As shown, the storage cells in each storage block are arranged in M ​​rows * N columns. For each storage block, there are also M word lines. The j-th row of storage cells in the M rows * N columns is connected to the j-th word line in the M word lines, where M is a positive integer and j is a positive integer not greater than M.

[0107] like Figure 5The diagram shown illustrates the working principle of a storage unit according to an embodiment of this application. When performing read or write operations on the storage unit, it is necessary to select the word line WL and the local bit line LBL connected to the storage unit. Furthermore, selecting the local bit line LBL requires selecting the global bit line GBL and the SC1 connected to the local bit line LBL.

[0108] Among them, transistor T b and transistor T c Taking N-type MOS transistors as an example, gating WL means inputting a high potential into WL to activate transistor T. c When the circuit is turned on, capacitor C can charge / discharge; strobing the LBL means that a high potential is input into the SCI connected to the LBL to enable transistor T. b The LBL is turned on, and the GBL connected to the LBL is turned on, and the output or input electrical signal of the GBL is selected to perform read or write operations respectively.

[0109] It should be noted that, Figure 2 or Figure 4 The memory shown is illustrated using the example where the total number of rows of storage cells in each storage block is the same, i.e., the total number of rows is M. In another embodiment of this application, the total number of rows of storage cells in different storage blocks can be different. For example, storage block 1 is an array of storage cells consisting of M1 rows * N columns, and storage block 2 is an array of storage cells consisting of M2 rows * N columns. M1 is not equal to M2, and this will not be exemplified here. M1 and M2 are both positive integers.

[0110] In some embodiments, the memory further includes a word line driving circuit that connects to all word lines in S memory blocks. The word line driving circuit controls the potential of the word lines it connects to, thereby controlling the on / off state of the transistors located on each word line. For example, the transistors in the memory cells of the word line driving circuit are N-type MOS transistors. When a row of memory cells needs to be selected, the word line driving circuit applies a high potential to the word lines connected to that row of memory cells; conversely, when the row of memory cells does not need to be selected, the word line driving circuit applies a low potential to the word lines connected to that row of memory cells.

[0111] In some embodiments, such as Figure 6 The diagram shown is a circuit diagram of another type of memory provided in this application embodiment. In this memory, each of the S memory blocks is divided into T memory sub-blocks. The memory sub-blocks are arranged in S rows and T columns, and each column of memory sub-blocks forms a memory domain. Therefore, the memory can include T memory domains. The memory also includes W global word lines, where T and W are positive integers, and T ≥ 2. Each of the T memory domains includes W rows of memory cells, W local word lines, and W word line switches, wherein:

[0112] In each storage domain, the vth storage cell in the W rows of storage cells is connected to the vth local word line in the W local word lines; the vth local word line is connected to the vth local word line in the W global word lines through the vth word line switch in the W bit line switches, where W is a positive integer and v is a positive integer not greater than W.

[0113] like Figure 7 The diagram illustrates the working principle of another storage unit provided in this application embodiment. When performing read or write operations on this storage unit, it is necessary to select the word line LWL and the local bit line LBL connected to the storage unit. Further, selecting the local bit line LBL requires selecting the global bit line GBL and the SC1 connected to the local bit line LBL. Selecting the local word line LWL requires selecting the global word line GWL and the SC2 connected to the local word line LWL.

[0114] Among them, transistor T b Transistor T c Transistor T r Taking N-type MOS transistors as an example, gate LWL means that a high potential is input into SC2 connected to LWL to activate transistor T. r When the LWL is turned on, the GWL connected to the LWL is turned on, and a high potential is input to the GWL, causing the transistor T to conduct. c When the circuit is turned on, capacitor C can charge / discharge; strobing the LBL means inputting a high potential into the SCI connected to the LBL to enable transistor T. b The LBL is turned on, and the GBL connected to the LBL is turned on, and the output or input electrical signal of the GBL is selected to perform read or write operations respectively.

[0115] It should be understood that the number of columns of storage cells in different storage domains can be the same or different; this is not limited here. For example... Figure 6 As shown, storage domain (1) includes n1 columns of storage units, and memory (T) includes N-n2 columns of storage units, where n1 is a positive integer greater than 1 and n2 is a positive integer less than N. Optionally, N is a multiple of T, and each storage domain includes the same number of columns of storage units, i.e., N / T columns. It should also be understood that the total number of rows of storage units in each storage block can be the same or different, which is not limited here. For example, as Figure 5 The memory shown has a storage block (1) consisting of an array of storage units in rows v1 and columns N, and a storage block (S) consisting of an array of storage units in rows v2 and columns N. v1 is a positive integer greater than 1, and v2 is a positive integer less than W. Here, we take the memory consisting of storage units in rows W and columns N as an example to illustrate the concept, where W is a positive integer greater than 1.

[0116] like Figure 6The memory shown has T memory domains, denoted as memory domain 1, memory domain 2, ..., memory domain T. W global word lines are denoted as GWL(1), GWL(2), ..., GWL(W), where GWL(v) represents the v-th global word line among the W global word lines. In each memory domain, W local word lines are denoted as LWL(1), LWL(2), ..., LWL(W), and W word line switches are denoted as word line switch 1, word line switch 2, ..., word line switch W, where LWL(v) represents the v-th local word line in a memory domain, and word line switch v represents the v-th word line switch in a memory domain. It should be understood that although the W local word lines and W word line switches in each memory domain use the same representation, LWL(v) in any two different memory domains are actually two different local word lines; similarly, word line switches v in any two different memory domains are actually two different word line switches.

[0117] In some embodiments, each memory block is a memory cell array comprising N columns of memory cells. S memory blocks are arranged along the bit line direction to form a memory block array, which also comprises N columns of memory cells. In this case, each memory block is divided into T memory sub-blocks, each of which is a smaller memory cell matrix than the memory block, and the number of columns of memory cells in the t-th sub-block of each memory block is the same. All memory sub-blocks in the memory are arranged into S rows * T columns. Here, the region formed by one column of memory sub-blocks is called a memory domain, and the memory comprises T memory domains. A memory cell located in row v in each memory domain is still located in row v in the memory array composed of T memory domains. For a memory domain, each memory cell in row v is connected to the v-th local word line, and the v-th local word line is connected to the v-th global word line through the v-th word line switch.

[0118] As can be seen, the v-th local word line in each memory domain is connected to the same global word line, i.e., the v-th global word line, through a word line switch. Therefore, by controlling the on / off state of the v-th word line switch in each memory domain, the on / off state of the v-th local word line and the v-th global word line in each memory domain can be controlled. This allows the v-th local word lines of T memory domains to share a single global word line, and the T memory domains to share a single word line driver circuit. This reduces the number of word line driver circuits in the memory and lowers the manufacturing cost. Furthermore, finer-grained memory array design can shorten local word lines, reduce parasitic capacitance caused by local word lines, and decrease read / write operation latency.

[0119] Optionally, such as Figure 6The memory shown may further include W second control lines, each connected to W word line switches, and each of the W second control lines is connected to a second control circuit. Figure 6 (Not shown in the diagram), the second control circuit is used to control the on and off of each word line switch in the T memory domains.

[0120] In each storage domain, W second control lines are represented as SC2(1), SC2(2), ..., SC2(W), where SC2(v) represents the v-th second control line in a storage domain. It should be understood that although the W second control lines in each storage domain use the same representation, SC2(v) in any two different storage domains in the T storage domains are actually two different second control lines.

[0121] In some embodiments, the memory further includes a word line driving circuit connected to the global word lines in the T memory domains. This word line driving circuit controls the potential of all global word lines in the T memory domains. It should be understood that the word line driving circuit controls the potential of T local word lines connected to the global word lines by controlling the potential of the global word lines. Furthermore, by turning on one or more word line switches among the T word line switches connected to the global word lines, the memory cells on the local word lines connected to the one or more word line switches are selected.

[0122] For example, when a read / write operation is required on a memory cell, the word line switch connected to that memory cell via a local word line needs to be turned on. At this time, the second control circuit can apply a high potential to the second control line connected to the word line switch to turn the word line switch on. Simultaneously, the word line drive circuit applies a high potential to the global word line connected to the memory cell. This turns both the global word line and the local word line connected to the memory cell on, and the high potential is applied to the control terminal of the transistor in that memory cell to select it. Conversely, if a read / write operation is not required, the word line switch connected to the local word line for that memory cell is turned off. In this case, the second control circuit can apply a low potential to the second control line connected to the word line switch to turn the word line switch off. It should be understood that the above explanation uses an N-type MOS transistor as an example for the word line switch.

[0123] It should be understood that the signal amplification circuit operates when a read operation is performed on a memory cell. For example... Figure 8 and Figure 9 The diagram shown is a schematic diagram of two differential amplifier circuits provided in the embodiments of this application.

[0124] like Figure 8The circuit shown includes a differential amplifier circuit, which may include N differential amplifiers, each corresponding to one of the N global bit lines. The i-th differential signal amplifier among the N differential amplifiers is used to amplify the electrical signal on the i-th global bit line.

[0125] In practical applications, one input terminal of the i-th differential signal is connected to the i-th global bit line, and the electrical signal on the i-th global bit line is input. The other input terminal is connected to the reference signal. The output of the i-th differential signal amplifier is the signal after removing the reference signal from the electrical signal on the i-th global bit line. Then, the data corresponding to the output signal is identified.

[0126] The above memory combination Figure 8 The differential amplifier circuit shown can enable data in memory cells located in different columns to be read simultaneously, thereby improving the speed of memory read operations.

[0127] In some embodiments, the signal amplification circuit may include P multiplexers and P differential amplifiers. Each multiplexer and differential amplifier corresponds one-to-one. The input of the k-th multiplexer is connected to at least two of the N global bit lines. The output of the k-th multiplexer is connected to the k-th differential amplifier. The k-th multiplexer is used to select one global bit line from the electrical signals transmitted via the global bit lines connected to it for output, where P is a positive integer not greater than N, and k is a positive integer not greater than P.

[0128] The memory using the above-mentioned signal amplification circuit allows data in multiple memory cells indirectly connected to different multiplexers to be read simultaneously, balancing speed and cost.

[0129] like Figure 9 The diagram shows another differential amplifier circuit where P=1. In this case, all global bit lines share a single differential amplifier. A single memory read operation can only read data from one memory cell.

[0130] It should be understood that the aforementioned memory may also include decoders and other functional units used to implement reading and writing data in the memory, which are not limited here.

[0131] like Figure 10 The illustration shows a storage device 100 provided in an embodiment of this application. The storage device 100 may include a memory 101 and a storage controller 102, with the storage controller 102 coupled to the memory 101. The memory may be as described above. Figure 2 , Figure 4 or Figure 6 Any of the aforementioned memory types.

[0132] In some embodiments, the storage device 100 may be memory, and the storage controller is a memory controller, used to receive a request sent by the processor for a target storage unit, and then respond to the request through the target storage unit in the storage device. The request includes read requests and write requests.

[0133] In some embodiments, the storage device may be other memory, such as cache memory, DRAM, etc., which are not limited here.

[0134] like Figure 11A The illustration shows a computing device 110A provided in an embodiment of this application. This computing device 110A may include a processor 111 and a memory 112, wherein the processor 111 and the memory 112 are coupled, for example, connected via a bus 113; the memory 112 may be as described above. Figure 2 , Figure 4 or Figure 6 Any of the aforementioned memory types.

[0135] like Figure 11B The illustration shows another computing device provided in an embodiment of this application. This computing device 110B may include a processor 114, a memory controller 115, and a memory 116. The processor 114 and memory controller 115 are coupled, and the memory controller 115 and memory 116 are coupled. The memory 116 may be as described above. Figure 2 , Figure 4 or Figure 6 Any of the aforementioned memory types.

[0136] Computing devices can be terminals, such as mobile phones, tablets, laptops, personal computers, smart TVs, set-top boxes, smartwatches, smart bracelets, virtual reality (VR) devices, augmented reality (AR) devices, smart speakers, etc. Computing devices can also be routers, servers, cloud servers, cloud computing devices, etc., which include storage and have data processing capabilities.

[0137] In combination with the above Figure 2 , Figure 4 or Figure 6 The memory, the storage device described in 10 above, and the memory described above... Figure 11A , Figure 11B The aforementioned computing device, below describes a method for reading data according to an embodiment of this application. This method is executed by a storage controller or a storage device including a storage controller, or a computing device, and may include, but is not limited to, the following steps:

[0138] S12: Select the target storage cell in the target storage block. The target storage cell is connected to the y-th local bit line in the target storage block, where y is a positive integer not greater than N.

[0139] Optionally, gating the target memory cell directs the transistors in the target memory cell to activate, such as... Figure 3 Transistor T in the memory cell c A high-potential signal is input into the word line connected to the target memory cell so that the electrical signal stored in the target memory cell can be transmitted to the local bit line, or the electrical signal in the local bit line can be transmitted to the target memory cell.

[0140] In one implementation of this application, the storage controller receives a read request from the processor. The read request requests to read data from a target storage cell within a target storage block. The read request carries address information indicating the location of the target storage cell. Upon receiving the read request, the storage controller can determine the row and column addresses of the target storage cell in the memory based on the address information. The column address indicates the identifier of the column containing the target storage cell, and the row address indicates the identifier of the row containing the target storage cell.

[0141] It should be understood that a local bit line and a word line in a memory block can determine the location of a memory cell. The column address of the target memory cell can include the identifier of the local bit line to which the target memory cell is connected. Similarly, the row address of the target memory cell can include the identifier of the word line or local word line to which the target memory cell is connected.

[0142] For example, in memory as Figure 2 In the case of a memory as shown in Figure 4, the target memory cell is connected to the x1-th word line and the y-th local bit line in the target memory block, where x1≤W, y≤N, W is the total number of rows of memory cells in the memory block, and N is the total number of columns of memory addresses in the memory block.

[0143] For example, in memory such as Figure 6 When the memory is shown, the target memory cell is connected to the x2th local word line in the target memory domain, and the target memory cell is connected to the yth local bit line in the target memory block, where x2≤W, y≤N, W is the total number of rows of memory cells in the memory block, and N is the total number of columns of memory addresses in the memory block.

[0144] Optionally, the memory controller can obtain the row address and column address of the target memory cell determined by the address information through a decoder, and then determine the local bit line, word line, or local word line connected to the target memory cell. The following sections will address these parameters respectively. Figure 2 , Figure 6 The memory shown, and Figure 6 The memory shown illustrates two methods for implementing gating of the target memory:

[0145] First implementation method:

[0146] In memory as such Figure 2 , Figure 4 When the memory is shown, the memory controller can input a control signal to the x1th word line in the target memory block to select the target memory cell through the word line drive circuit.

[0147] For example, if the transistor in the memory cell is an N-type MOS transistor, when it is necessary to select a certain row of memory cells, the word line driving circuit applies a high potential to the x1 word line connected to the target memory cell. At this time, all memory cells in the x1 row of the target memory block are selected, and the target memory cell is also selected.

[0148] The second implementation method:

[0149] In memory as such Figure 6 When the memory is shown, the memory controller can turn on the x2th word line switch in the target memory domain to turn on the x2th local word line in the target memory domain and the x2th global word line in the W global word lines. Then, the word line driving circuit inputs a control signal for selecting the target memory cell to the x2th global word line in the W global word lines.

[0150] One implementation of the memory controller turning on the x2nd word line switch in the target memory domain is as follows: the memory controller inputs a control signal to the second control line SC2(x2) connected to the x2nd word line switch to turn on the x2nd word line switch. If the word line switch is an N-type MOS transistor, the control signal can be a high potential.

[0151] It should be understood that the storage controller can also first input a control signal to the x2nd global word line out of the W global word lines and then turn on the x2nd word line switch.

[0152] If the transistor in the memory cell is an N-type MOS transistor, the control signal can be a high potential. When the word line drive circuit applies a high potential to the x2th global word line, since the x2th word line switch in the target memory domain is turned on, the high potential on the x2th global word line is applied to all memory cells in the x2th row of the target memory domain through the x2th local word line in the target memory domain. All memory cells in the x2th row of the target memory domain are selected, and the target memory cell is also selected.

[0153] S14: Turn on the y-th bit line switch in the target memory block so that the electrical signal in the target memory cell is transmitted to the y-th global bit line among the N global bit lines through the y-th local bit line.

[0154] It is understandable that after the y-th bit line switch in the target memory block is turned on, the y-th local bit line in the target memory is transmitted to the N global bit lines and turned on with the y-th global bit line.

[0155] One implementation of the memory controller turning on the y-th bit line switch in the target memory block is as follows: the memory controller inputs a control signal to the first control line SC1(y) connected to the y-th bit line switch in the target memory block to turn on the y-th bit line switch. If the bit line switch is an N-type MOS transistor, the control signal can be a high potential.

[0156] S16: Amplify the electrical signal in the y-th global bit line through a signal amplification circuit.

[0157] For a signal amplification circuit including N differential amplifiers (such as...) Figure 8 As shown in the figure, one implementation of S16 can be: the storage controller amplifies the electrical signal in the y-th global bit line through the target differential amplifier, wherein the target differential amplifier is the differential amplifier connected to the y-th global bit line among N differential amplifiers.

[0158] For a signal amplification circuit including P differential amplifiers and P multiplexers (such as...) Figure 9 As shown, one implementation of S16 is as follows: the storage controller inputs the electrical signal in the y-th global bit line to the target differential amplifier connected to the target multiplexer via the target multiplexer connected to the y-th global bit line; the target multiplexer is the multiplexer connected to the y-th global bit line among P multiplexers, used to transmit only the electrical signal in the y-th global bit line to the differential amplifier (here called the target differential amplifier) ​​connected to the target multiplexer, and then amplifies the electrical signal in the y-th global bit line through the target differential amplifier.

[0159] Furthermore, the storage controller can read the data corresponding to the electrical signal and send the read data to the processor.

[0160] It should be understood that the purpose of amplifying the electrical signal in the y-th global bit line is to remove the reference signal from the electrical signal, so that the amplified signal is closer to the signal stored in the target memory cell in the target memory block, so as to accurately identify the data in the target memory cell.

[0161] In combination with the above Figure 2 , Figure 4 or Figure 6 The memory, the storage device described in 10 above, and the memory described above... Figure 11A , Figure 11BThe aforementioned computing device, below describes a method for writing data according to an embodiment of this application. This method is executed by a storage controller or a storage device including a storage controller, or a computing device, and may include, but is not limited to, the following steps:

[0162] S22: Select the target memory cell in the target memory block. The target memory cell is connected to the y-th local bit line in the target memory block, where y is a positive integer not greater than N.

[0163] In one implementation of this application, the storage controller receives a write request from the processor. The write request requests the writing of target data into a target storage cell within a target storage block. The write request carries address information indicating the location of the target storage block. Upon receiving the write request, the storage controller can determine the row and column addresses of the target storage cell in the memory based on the address information. The column address indicates the identifier of the column containing the target storage cell, and the row address indicates the identifier of the row containing the target storage cell.

[0164] The implementation method for determining the row and column addresses of the target storage unit in the target storage block based on the address information carried by the write and read requests is the same, as detailed above. Figure 12 The relevant descriptions in the data reading method embodiments shown are not repeated here.

[0165] It should be understood that a local bit line and a word line in a memory block can determine the location of a memory cell, and the column address of the target memory cell can include the identifier of the local bit line to which the target memory cell is connected. Similarly, the row address of the target memory cell can include the identifier of the word line or local word line to which the target memory cell is connected.

[0166] For example, in memory as Figure 2 or Figure 4 When the memory is shown, the target memory cell is connected to the x1-th word line and the y-th local bit line in the target memory block, where x1≤W, y≤N, W is the total number of rows of memory cells in the memory block, and N is the total number of columns of memory addresses in the memory block.

[0167] For example, in memory such as Figure 6 When the memory is shown, the target memory cell is connected to the x2th local word line in the target memory domain, and the target memory cell is connected to the yth local bit line in the target memory block, where x2≤W, y≤N, W is the total number of rows of memory cells in the memory block, and N is the total number of columns of memory addresses in the memory block.

[0168] It should be understood that, although in Figure 12 The method embodiment for reading data shown and in Figure 13In the illustrated methods for writing data, the terms y, x1, x2, target storage block, target storage unit, and target storage domain are used. It should be understood that in the two methods described above, the positive integer actually referred to by y, the positive integer actually referred to by x1, the positive integer actually referred to by x2, the storage block actually referred to by the target storage block, the storage unit actually referred to by the target storage unit, and the storage domain actually referred to by the target storage domain can all be different.

[0169] For details on the implementation of gating the target memory unit, please refer to the above. Figure 12 The specific implementation of selecting the target storage unit in the illustrated data reading method embodiment will not be described in detail here.

[0170] S24: Turn on the y-th bit line switch in the target memory block to turn on the y-th local bit line and the y-th global bit line among the N global bit lines.

[0171] For a detailed implementation of S24, please refer to the above. Figure 12 The relevant descriptions in step S14 of the method embodiment shown will not be repeated here.

[0172] S26: Input the electrical signal corresponding to the target data to the y-th global bit line so that the electrical signal is stored in the target memory unit.

[0173] For example, if a storage unit only includes two states, "0" and "1", then data "1" corresponds to a high potential and data "1" corresponds to a low potential.

[0174] It should be understood that when the target memory cell is selected, the electrical signal corresponding to the target data can be input to the y-th global bit line through the bit line driving circuit. Since the y-th bit line switch of the target memory block is turned on, the electrical signal can be transmitted to the target memory cell through the y-th local bit line of the target memory block. The electrical signal can be stored in the capacitor in the target memory cell.

[0175] like Figure 14 The image shown is a storage controller provided in an embodiment of this application; this storage controller can be applied to the above-mentioned... Figure 2 , Figure 4 or Figure 6 The memory shown, the storage device described in 10 above, and the memory described above Figure 11A , Figure 11B The computing device, the storage controller 1400, may include the following functional units:

[0176] The gating module 1401 is used to gating a target storage cell in a target storage block, wherein the target storage cell is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N;

[0177] The conduction module 1402 is used to conduct the y-th bit line switch in the target memory block so that the electrical signal in the target memory cell is transmitted to the y-th global bit line among the N global bit lines through the y-th local bit line;

[0178] Amplification module 1403 is used to amplify the electrical signal in the y-th global bit line through the signal amplification circuit.

[0179] In one alternative implementation, corresponding to the above... Figure 8 The memory of the signal amplification circuit shown, the amplification module 1403 is specifically used to: amplify the electrical signal in the y-th global bit line through the target differential amplifier, wherein the target differential amplifier is the differential amplifier connected to the y-th global bit line among the N differential amplifiers.

[0180] In one alternative implementation, the memory corresponding to the above-mentioned P multiplexers and P differential amplifiers (as described above) Figure 9 The signal amplification circuit shown in the diagram has a memory. The amplification module 1403 is specifically used to: input the electrical signal in the y-th global bit line to the target differential amplifier connected to the target multiplexer through the target multiplexer; and amplify the electrical signal in the y-th global bit line through the target differential amplifier.

[0181] In an optional implementation, each storage block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and the conduction module 1402 is specifically used to: input a control signal to the first control line connected to the y-th bit line switch to enable the y-th bit line switch to conduct.

[0182] In one alternative implementation, corresponding to Figure 2 or Figure 4 The memory shown has a target memory cell connected to the x1th word line in the target memory block, where x1 is a positive integer not greater than M. The gating module 1401 is specifically used to input a control signal for gating the target memory cell into the x1th word line.

[0183] In one alternative implementation, corresponding to Figure 6 The memory shown has a target memory cell connected to the x2th local word line in the target memory domain, where x2 is a positive integer not greater than W. The gating module 1401 is specifically used to: turn on the x2th word line switch in the target memory domain to turn on the x2th local word line and the x2th global word line in the W global word lines; and input a control signal for gating the target memory cell to the x2th global word line in the W global word lines.

[0184] Optionally, the storage domain further includes W second control lines respectively connected to the W word line switches, and the conduction module 1402 is specifically used to: input a control signal to the second control line connected to the x2th word line switch to enable the x2th word line switch to conduct.

[0185] It should be noted that the specific implementation of each module in the aforementioned storage control 1400 can be found in the above... Figure 2 , Figure 4 and Figure 6 The memory shown, and Figure 12 The relevant descriptions in the method embodiments shown will not be repeated here.

[0186] like Figure 15 The image shown is another storage controller provided in an embodiment of this application; this storage controller can be applied to the above-mentioned... Figure 2 , Figure 4 or Figure 6 The memory shown, the storage device described in 10 above, and the memory described above Figure 11A , Figure 11B The computing device, the storage controller 1500, may include the following functional units:

[0187] The gating module 1501 is used to gating the target storage cell in the target storage block, wherein the target storage cell is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N;

[0188] The conduction module 1502 is used to conduct the y-th bit line switch in the target memory block, so as to conduct the y-th local bit line and the y-th global bit line among the N global bit lines;

[0189] The writing module 1503 is used to input the electrical signal corresponding to the target data into the y-th global bit line so that the electrical signal is stored in the target storage unit.

[0190] In an optional implementation, each memory block further includes N first control lines that are respectively connected to the control terminals of the N bit line switches. The conduction module 1502 is specifically used to: input a control signal to the first control line connected to the y-th bit line switch to enable the y-th bit line switch to conduct.

[0191] In one alternative implementation, corresponding to Figure 2 or Figure 4 The memory shown has a target memory cell connected to the x1th word line in the target memory block, where x1 is a positive integer not greater than M. The gating module 1501 is specifically used to input a control signal for gating the target memory cell into the x1th word line.

[0192] In one alternative implementation, corresponding to Figure 6 The memory shown has the target memory cell connected to the x2th word line in the target memory domain, where x2 is a positive integer not greater than W. The gating module 1501 is specifically used to: turn on the x2th word line switch in the target memory domain to turn on the global word line corresponding to the row address and the local word line corresponding to the row address; and input a gating signal for gating the target memory cell to the x2th global word line among the W global word lines.

[0193] Optionally, the storage domain further includes W second control lines respectively connected to the W word line switches, and the conduction module 1502 is specifically used to include: inputting a control signal to the second control line connected to the x2th word line switch to enable the x2th word line switch to conduct.

[0194] It should be noted that the specific implementation of each module in the aforementioned storage control 1500 can be found in the above description. Figure 2 , Figure 4 and Figure 6 The memory shown, and the above Figure 13 The relevant descriptions in the method embodiments shown will not be repeated here.

[0195] The above-mentioned transistors are all N-type MOS transistors, as an example. It should be understood that different types of transistors control their conduction and cutoff in different ways, and the specific implementation is existing technology, which will not be elaborated here. In addition, the "control terminal of the transistor" mentioned in this application can be the gate of a field-effect transistor, the base of a bipolar junction transistor, etc., which are used to control the conduction of the source and drain of the field-effect transistor, and the conduction of the collector and emitter, respectively.

[0196] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0197] Those skilled in the art will appreciate that the functionality described in conjunction with the various illustrative logic blocks, modules, and algorithmic steps disclosed herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality described by the various illustrative logic blocks, modules, and steps can be stored or transmitted as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium may comprise a computer-readable storage medium, which corresponds to a tangible medium, such as a data storage medium, or a communication medium that includes any medium facilitating the transfer of a computer program from one place to another (e.g., according to a communication protocol). In this way, the computer-readable medium may substantially correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium, such as a signal or carrier wave. The data storage medium may be any available medium accessible by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this application. A computer program product may comprise a computer-readable medium.

[0198] Instructions can be executed by one or more processors, such as digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein can refer to any of the foregoing structures or any other structures suitable for implementing the techniques described herein. Furthermore, in some aspects, the functionality described in the various illustrative logic blocks, modules, and steps described herein can be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into combined codecs. Moreover, the techniques can be fully implemented within one or more circuit or logic elements.

[0199] The technology of this application can be implemented in a wide variety of devices or apparatuses, including wireless handheld devices, integrated circuits (ICs), or a set of ICs (e.g., chipsets). The various components, modules, or units described in this application are intended to emphasize functional aspects of the apparatus for performing the disclosed technology, but do not necessarily need to be implemented by different hardware units. In fact, as described above, the various units can be combined with suitable software and / or firmware within a codec hardware unit, or provided via interoperable hardware units (containing one or more processors as described above).

[0200] The terminology used in the above embodiments is for the purpose of describing specific embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one” and “one or more” refer to one, two, or more than two. The term “and / or” is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0201] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0202] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, It includes S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks is connected to the N global bit lines, and the N global bit lines are connected to the signal amplification circuit. The signal amplification circuit is used to amplify the electrical signals in the N global bit lines. S and N are positive integers, and S ≥ 2. Each memory block includes N columns of memory cells, N local bit lines, and N bit line switches, wherein: In each storage block, the i-th column of the N columns of storage cells is connected to the i-th local bit line among the N local bit lines; the i-th local bit line is connected to the i-th global bit line among the N global bit lines through the i-th bit line switch among the N bit line switches, where N is a positive integer and i is a positive integer not greater than N; Each storage block is divided into T storage sub-blocks. The storage sub-blocks in the memory are arranged in S rows and T columns, with each column forming a storage domain. The memory includes T storage domains and W global word lines, where T and W are positive integers and T ≥ 2. Each of the T storage domains includes W rows of storage cells, W local word lines, and W word line switches, where: In each storage domain, the vth row of the W rows of storage cells is connected to the vth local word line among the W local word lines; the vth local word line is connected to the vth local word line among the W global word lines through the vth word line switch among the W bit line switches, where W is a positive integer and v is a positive integer not greater than W.

2. The memory as claimed in claim 1, characterized in that, The signal amplification circuit includes N differential amplifiers, and the i-th differential signal amplifier among the N differential amplifiers is used to amplify the electrical signal on the i-th global bit line.

3. The memory as claimed in claim 1, characterized in that, The signal amplification circuit includes P multiplexers and P differential amplifiers; the input terminal of the kth multiplexer of the P multiplexers is connected to at least two of the N global bit lines, and the output terminal of the kth multiplexer of the P multiplexers is connected to the kth differential amplifier of the P differential amplifiers. The kth multiplexer of the P multiplexers is used to select one of the electrical signals transmitted by the at least two global bit lines for output, where P is a positive integer not greater than N, and k is a positive integer not greater than P.

4. The memory according to any one of claims 1-3, characterized in that, Each storage block further includes N first control lines that are respectively connected to the control terminals of the N bit line switches. The N first control lines are all connected to a first control circuit, which is used to control the conduction of the N bit line switches.

5. The memory according to any one of claims 1-3, characterized in that, The memory also includes a bit line driving circuit, which is connected to the N global bit lines and is used to input electrical signals into the N global bit lines.

6. The memory according to any one of claims 1-3, characterized in that, The storage cells in each storage block are arranged in M ​​rows. N columns of storage units, each storage block further includes M word lines, the M rows The j-th row of the N-column storage cells is connected to the j-th word line of the M word lines, where M is a positive integer and j is a positive integer not greater than M.

7. The memory as claimed in claim 6, characterized in that, The memory also includes a word line driving circuit, which is connected to the word lines in the S memory blocks and is used to control the potential of the word lines.

8. The memory as claimed in claim 1, characterized in that, Each storage domain further includes W second control lines that are respectively connected to the W word line switches. The W second control lines are all connected to a second control circuit, which is used to control the conduction of the W word line switches.

9. The memory as claimed in claim 1 or 8, characterized in that, The memory also includes a word line driving circuit, which is connected to the global word lines in the T memory domains and is used to control the potential of the global word lines.

10. A storage device, characterized in that, include: The memory and memory controller as described in any one of claims 1-9, wherein the memory is coupled to the memory controller.

11. A terminal, characterized in that, include: The processor and the memory as described in any one of claims 1-9, wherein the memory is coupled to the processor.

12. A method for reading data, characterized in that, This invention relates to a memory system comprising S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks is connected to the N global bit lines, and the N global bit lines are connected to the signal amplification circuit. The signal amplification circuit amplifies the electrical signals in the N global bit lines. S and N are positive integers, and S ≥ 2. Each memory block comprises N columns of memory cells, N local bit lines, and N bit line switches. Within each memory block, the i-th column of the N columns of memory cells is connected to the i-th local bit line among the N local bit lines. The i-th local bit line is connected to the i-th global bit line among the N global bit lines via the i-th bit line switch among the N bit line switches. N is a positive integer. The number i is a positive integer not greater than N; each storage block is divided into T storage sub-blocks, and the storage sub-blocks in the memory are arranged in S rows and T columns, with each column of storage sub-blocks forming a storage domain. The memory includes T storage domains and W global word lines, where T and W are positive integers and T ≥ 2; each storage domain includes W rows of storage cells, W local word lines, and W word line switches; wherein, the v-th row of storage cells in the W rows is connected to the v-th local word line in the W local word lines; the v-th local word line is connected to the v-th local word line in the W global word lines through the v-th word line switch in the W bit line switches, where W is a positive integer and v is a positive integer not greater than W. The method includes: Select a target storage cell in the target storage block, wherein the target storage cell is connected to the y-th local bit line in the target storage block, where y is a positive integer not greater than N, and the target storage cell is connected to the x2-th local word line in the target storage domain, where x2 is a positive integer not greater than W. Turn on the y-th bit line switch in the target memory block so that the electrical signal in the target memory cell is transmitted to the y-th global bit line among the N global bit lines through the y-th local bit line; The electrical signal in the y-th global bit line is amplified by the signal amplification circuit. The selection of the target memory cell in the target memory block includes: turning on the x2nd word line switch in the target memory domain to turn on the x2nd local word line and the x2nd global word line among the W global word lines; and inputting a control signal for selecting the target memory cell to the x2nd global word line among the W global word lines.

13. The method as described in claim 12, characterized in that, The signal amplification circuit includes N differential amplifiers. The i-th differential signal amplifier among the N differential amplifiers is connected to the i-th global bit line. Amplifying the electrical signal in the y-th global bit line through the signal amplification circuit specifically includes: The electrical signal in the y-th global bit line is amplified by a target differential amplifier, wherein the target differential amplifier is the differential amplifier connected to the y-th global bit line among the N differential amplifiers.

14. The method as described in claim 12, characterized in that, The signal amplification circuit includes P multiplexers and P differential amplifiers. The input of the k-th multiplexer is connected to at least two of the N global bit lines, and the output of the k-th multiplexer is connected to the k-th differential amplifier. The k-th multiplexer is used to select one global bit line signal from the at least two global bit lines for output. P is a positive integer not greater than N, and k is a positive integer not greater than P. Amplifying the electrical signal in the y-th global bit line through the signal amplification circuit specifically includes: The electrical signal in the y-th global bit line is input to the target differential amplifier connected to the target multiplexer by connecting the target multiplexer to the target multiplexer; The electrical signal in the y-th global bit line is amplified by the target differential amplifier.

15. The method according to any one of claims 12-14, characterized in that, Each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and turning on the y-th bit line switch in the target memory block includes: A control signal is input to the first control line connected to the y-th bit line switch to turn on the y-th bit line switch.

16. The method according to any one of claims 12-14, characterized in that, The storage cells in each storage block are arranged in M ​​rows. N columns of storage units, each storage block further includes M word lines, the M rows The j-th row of N column storage cells is connected to the j-th word line of the M word lines, where M is a positive integer and j is a positive integer not greater than M. The target storage cell is connected to the x1-th word line of the target storage block, where x1 is a positive integer not greater than M. Selecting the target storage cell in the target storage block includes: Input a control signal to select the target memory cell into the x1th word line.

17. The method as described in claim 12, characterized in that, The storage domain further includes W second control lines respectively connected to the W word line switches, and turning on the x2th word line switch in the target storage domain includes: A control signal is input to the second control line connected to the x2th word line switch to turn on the x2nd word line switch.

18. A method for writing data, characterized in that, This invention relates to a memory system comprising S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks is connected to the N global bit lines, and the N global bit lines are connected to the signal amplification circuit. The signal amplification circuit amplifies the electrical signals in the N global bit lines. S and N are positive integers, and S ≥ 2. Each memory block comprises N columns of memory cells, N local bit lines, and N bit line switches. Within each memory block, the i-th column of the N columns of memory cells is connected to the i-th local bit line among the N local bit lines. The i-th local bit line is connected to the i-th global bit line among the N global bit lines via the i-th bit line switch among the N bit line switches. N is a positive integer. The number, i, is a positive integer not greater than N; each storage block is divided into T storage sub-blocks, and the storage sub-blocks in the memory are arranged in S rows and T columns, with each column of storage sub-blocks forming a storage domain. The memory includes T storage domains and W global word lines, where T and W are positive integers and T ≥ 2; each storage domain includes W rows of storage cells, W local word lines, and W word line switches; wherein, the v-th row of storage cells in the W rows is connected to the v-th local word line in the W local word lines; the v-th local word line is connected to the v-th local word line in the W global word lines through the v-th word line switch in the W bit line switches, where W is a positive integer and v is a positive integer not greater than W; the method includes: Select a target storage cell in the target storage block, wherein the target storage cell is connected to the y-th local bit line in the target storage block, where y is a positive integer not greater than N, and the target storage cell is connected to the x2-th word line in the target storage domain, where x2 is a positive integer not greater than W; Turn on the y-th bit line switch in the target memory block to turn on the y-th local bit line and the y-th global bit line among the N global bit lines; The target electrical signal is input to the y-th global bit line so that the target electrical signal is stored in the target memory cell; The selection of the target memory cell in the target memory block includes: turning on the x2nd word line switch in the target memory domain to turn on the x2nd local word line and the x2nd global word line among the W global word lines; and inputting a control signal for selecting the target memory cell to the x2nd global word line among the W global word lines.

19. The method as described in claim 18, characterized in that, Each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and turning on the y-th bit line switch in the target memory block includes: A control signal is input to the first control line connected to the y-th bit line switch to turn on the y-th bit line switch.

20. The method as claimed in any one of claims 18 or 19, characterized in that, The storage cells in each storage block are arranged in M ​​rows. N columns of storage units, each storage block further includes M word lines, the M rows The j-th row of N column storage cells is connected to the j-th word line of the M word lines, where M is a positive integer and j is a positive integer not greater than M. The target storage cell is connected to the x1-th word line of the target storage block, where x1 is a positive integer not greater than M. The target storage cells in the selected target storage block include: Input a control signal to select the target memory cell into the x1th word line.

21. The method as described in claim 20, characterized in that, The storage domain further includes W second control lines respectively connected to the W word line switches, and turning on the x2th word line switch in the target storage domain includes: A control signal is input to the second control line connected to the x2th word line switch to enable the x2th word line switch to turn on.

Images