Integrated circuit (IC) package using a thermally conductive package substrate with die area separation and related manufacturing methods

Abstract

An integrated circuit (IC) package and related manufacturing methods using a thermally conductive semiconductor package substrate with die area separation are disclosed. The package substrate includes die separation, wherein the metal contacts in one or more dielectric layers of the package substrate below the (multiple) IC die (e.g., in the core die area) are thicker than other metal contacts in the dielectric layer (e.g., in the peripheral die area). This facilitates higher thermal dissipation of the (multiple) IC die through the thicker metal contacts in the package substrate. Crosstalk shielding of the package substrate may not be sacrificed because the thinner metal contacts of the package substrate carrying high-speed signaling may have a smaller thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layers in the package substrate may also include dielectric materials with different thermal conductivities to further promote thermal dissipation and / or desired electrical or mechanical properties.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 969,706, filed on February 4, 2020, entitled “INTEGRATED CIRCUIT (IC) PACKAGE SEMPLOYING A THERMAL CONDUCTIVE PACKAGE SUBSTRATE WITH DIE REGION SPLIT, AND RELATED FABRICATION METHODS,” the contents of which are incorporated herein by reference in their entirety.

[0003] This application also claims priority to U.S. Patent Application No. 16 / 921,152, filed on July 6, 2020, entitled “INTEGRATED CIRCUIT (IC) PACKAGE SEMPLOYING A THERMAL CONDUCTIVE PACKAGE SUBSTRATE WITH DIE REGION SPLIT, AND RELATED FABRICATION METHODS,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] The field of the present disclosure relates to a package substrate included in a chip package to provide electrical connections between integrated circuit (IC) chip(s) and a circuit board, and more particularly to heat dissipation of the IC chip(s) through the package substrate. Background Art

[0005] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as "semiconductor packages" or "chip packages." IC packages include one or more semiconductor die as (multiple) ICs, which are mounted on a package substrate and electrically coupled to the package substrate to provide physical support and electrical interfaces to the (multiple) semiconductor die. The package substrate may be, for example, an embedded trace substrate (ETS), including embedded electrical traces in one or more dielectric layers and vertical interconnects that couple the electrical traces together to provide an electrical interface between (multiple) semiconductor die. (Multiple) semiconductor die are mounted to and electrically connected to interconnects exposed in the top layer of the package substrate to electrically couple the (multiple) semiconductor die to the electrical traces of the package substrate. (Multiple) IC semiconductor die and the package substrate are encapsulated in a packaging material (such as a molding compound) to form an IC package. The IC package may also include external solder balls that are electrically coupled to interconnects exposed in the bottom layer of the package substrate to electrically couple the solder balls to electrical traces in the package substrate. The solder balls provide an external electrical interface to the semiconductor die(s) in the IC package. The solder balls are electrically coupled to metal contacts on a printed circuit board (PCB) when the IC package is mounted to the PCB to provide an electrical interface between electrical traces in the PCB to the IC chip through a package substrate in the IC package.

[0006] Advances in the electrical performance of silicon ICs have led to ever-shrinking IC die. However, as the area of ​​the IC die becomes smaller, power consumption increases, thereby increasing the power density on the die. The increased power density on the die directly translates into an increase in the heat generated by the die. As the semiconductor junction temperature rises, carrier mobility decreases, which reduces the performance of the transistors and other electrical components of the IC. For example, the continued increase in temperature in the IC die that increases the semiconductor junction temperature may lead to a significant reduction in the life of the IC. In addition, from the perspective of consumer use, for certain types of electronic devices, increased IC die temperature may be problematic. For example, handheld consumer devices such as mobile phones, laptop computers, tablet computers, e-readers, smart phones, etc. cannot exceed a specific temperature along the surface that the user may touch in order to protect the user from burns.

[0007] Therefore, heat dissipation in ICs has become a very important consideration to prevent the IC die from operating at high temperatures that could affect IC performance and reliability. Heat sinks can be used to dissipate heat, but heat sinks may not be practical in small form factor IC packages due to size constraints. Figure 1A cross-sectional schematic diagram of a flip chip IC package 100 ("IC package 100") that does not include a heat sink is shown. IC package 100 includes a semiconductor die 102 ("IC die 102") having a front surface 104 (i.e., an active surface) that is coupled to a package substrate 106 via a die attach and / or underfill adhesive 108. An epoxy and / or resin molding compound 110 may also be used to stabilize and protect the IC die 102. Solder bumps 112 are formed on a bottom surface 114 of the package substrate 106 to provide an electrical interface to the IC die 102 when the IC package 100 is mounted to a printed circuit board (PCB). The IC die 102 may have on-chip thermal sensors and control logic that help control the power consumption and thus the heat 116 generated by the IC package 100 by using dynamic thermal management techniques. However, these dynamic thermal management techniques may limit the operating frequency of IC die 102 to keep IC die 102 cool, thereby sacrificing the performance of IC package 100. Thermal management techniques may also affect the life of IC package 100 because changes in temperature may cause IC die 102 to expand and contract and introduce thermal stresses in IC die 102.

[0008] Therefore, there is a need for an improved passive thermal management system, method, and apparatus that adequately dissipates heat generated by an IC in an IC package without adversely affecting the performance of the IC. Summary of the invention

[0009] Aspects disclosed herein include integrated circuit (IC) packages that employ a thermally conductive semiconductor package substrate with die area separation. Related chip packages and methods of manufacturing semiconductor package substrates with die area separation are also disclosed. An IC package is provided that includes one or more semiconductor dies (also referred to as "IC dies") mounted on a package substrate. Die interconnects (e.g., core solder bumps) on the bottom surface of the (multiple) semiconductor dies are electrically coupled to substrate interconnects exposed on the top surface of the package substrate to electrically couple the IC in the IC die to electrical traces in the package substrate. For example, the package substrate includes one or more dielectric layers that include one or more wiring layers of electrical traces that can be electrically coupled to electrical traces in adjacent dielectric layers through vertical interconnects (such as vertical vias). The electrical traces are coupled to substrate interconnects exposed on the bottom surface of the package substrate, which are electrically coupled to electrical connectors (e.g., solder balls) that are exposed from packaging material encapsulating the IC die(s) and the package substrate as part of the IC package and provide an external electrical interface to the IC die(s) when mounted to a printed circuit board (PCB).

[0010] The electrical traces in the packaging substrate of the IC package not only provide an electrical interface to the (multiple) IC die, but can also be used to dissipate the heat generated by the (multiple) IC die when powered on and in operation. The (multiple) IC die includes a core die area in which a core integrated circuit ("core circuit") is formed. As an example, the core circuit may include hard circuit macros, such as a computer processing unit (CPU), a graphics processor unit (GPU), a memory, a modem, and / or a core power distribution rail. As an example, the (multiple) IC die also includes a peripheral die area outside the core die area in a non-core or peripheral area, and the non-core or peripheral area includes peripheral circuits, such as input / output (I / O) circuits and electrical wiring traces to provide an interface to the core circuit. The core circuit generally generates more heat than the peripheral circuit. In this regard, in order to facilitate improved heat dissipation of the core circuit of the (multiple) IC die, in the exemplary aspects disclosed herein, at least one dielectric layer of the packaging substrate includes a die area separated between its metal contacts for electrical traces. One or more metal contacts of electrical traces in a dielectric layer below the (multiple) IC die in the height direction (i.e., Z-axis direction) are thicker in the height direction than other metal contacts of electrical traces in the same dielectric layer. In this way, as an example, the IC package can have more effective thermal (i.e., heat) dissipation of heat generated from the (multiple) IC die through the thicker metal contacts of the electrical traces of the (multiple) dielectric layers of the package substrate. For example, this can compensate for reduced heat dissipation that might otherwise occur if the IC package and its package substrate are reduced in height, and thus reduce the volume of the metal contacts of the electrical traces in the package substrate to facilitate the reduction in the height of the IC package.

[0011] As a non-limiting example, one or more metal contacts of electrical traces in a dielectric layer below a core die region of (multiple) IC dies may be fabricated to be taller in height direction than metal contacts of electrical traces in the same dielectric layer below a peripheral die region of (multiple) IC dies. In this way, as an example, the IC package may have more effective thermal (i.e., heat) dissipation of heat generated from core circuits in (multiple) IC dies through thicker metal contacts of electrical traces in the core die region of (multiple) dielectric layers of the package substrate. As an example, by providing die-core separation in the package substrate, metal contacts of electrical traces in the peripheral die region of the dielectric layer in the package substrate may still be sized to have a smaller thickness than in the core die region of the dielectric layer to facilitate crosstalk shielding. Thus, heat dissipation of (multiple) IC dies through the core die region of the package substrate may not be sacrificed to still facilitate crosstalk shielding in the peripheral die region of the package substrate.

[0012] To further facilitate heat dissipation of the (multiple) IC die in the IC package, the dielectric layer of the thicker metal contacts containing electrical traces in the package substrate can also include a dielectric material having a higher thermal conductivity (e.g., in units of Watts per meter (m) Kelvin (K) (W / mK)) than the dielectric material disposed adjacent to and / or around the shorter metal contacts in the dielectric layer. For example, the dielectric layer in the package substrate (containing thicker metal contacts for electrical traces in the core die region than in the peripheral die region thereof) can also include a dielectric material having a higher thermal conductivity in its core die region than the thermal conductivity of the dielectric material in its peripheral die region. The dielectric material having a higher thermal conductivity helps to improve heat transfer compared to a dielectric material having a lower thermal conductivity. As an example, the dielectric material in the peripheral die region of the dielectric layer can be a different dielectric material than the dielectric material in the core die region of the dielectric layer and is selected based on desired electrical properties (such as signaling speed) and / or mechanical properties (such as less sensitivity to thermal stress). In this regard, in an exemplary aspect, an integrated circuit (IC) package is provided. The IC package includes a substrate arranged in a horizontal plane, the substrate including a first dielectric material having a first thermal conductivity, a second dielectric material having a second thermal conductivity lower than the first thermal conductivity, and a wiring layer. The wiring layer includes one or more first metal contacts arranged adjacent to the first dielectric material, each of the one or more first metal contacts having a first height in a height direction orthogonal to the horizontal plane. The wiring layer also includes one or more second metal contacts arranged adjacent to the second dielectric material, each of the one or more second metal contacts having a second height in a height direction, the second height being less than the first height.

[0013] On the other hand, a method for manufacturing a packaging substrate for an integrated circuit (IC) package is provided. The method includes: forming a substrate disposed in a horizontal plane. The method also includes forming a dielectric layer, including: forming a first dielectric material having a first thermal conductivity; forming a second dielectric material having a second thermal conductivity lower than the first thermal conductivity; and forming a wiring layer. The method of forming the wiring layer also includes: forming one or more first metal contacts adjacent to the first dielectric material, each of the one or more first metal contacts having a first height in a height direction orthogonal to the horizontal plane; and forming one or more second metal contacts adjacent to the second dielectric material, each of the one or more second metal contacts having a second height in a height direction, the second height being less than the first height. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a side view of an exemplary flip chip integrated circuit (IC) package including an encapsulated semiconductor die mounted on and electrically coupled to a package substrate;

[0015] Figure 2A illustrates a top view of an exemplary IC die;

[0016] Figure 2B The diagram contains Figure 2A a cross-sectional side view of an exemplary IC package with an IC die mounted on and electrically coupled to a package substrate that dissipates heat generated by the IC die;

[0017] Figure 3A illustrates a side view of an exemplary IC package, the IC package including a package substrate that facilitates heat dissipation from an IC die by including a dielectric layer, the dielectric layer including a die region separation, the die region separation having one or more metal contacts with electrical traces underlying a core die region of the IC die(s), the one or more metal contacts being thicker in height than metal contacts of the electrical traces in the dielectric layer underlying a peripheral die region of the IC die(s), and wherein the core die region of the dielectric layer also includes a dielectric material having a higher thermal conductivity than the dielectric material in the peripheral die region;

[0018] Figure 3B yes Figure 3A A more detailed side view of a package substrate in an IC package;

[0019] Figure 4 is another exemplary two-layer (2L) package substrate that facilitates heat dissipation from an IC die by including a dielectric layer that includes a die region separation having one or more metal contacts of electrical traces beneath a core die region of the IC die(s), the one or more metal contacts being thicker in a height direction than metal contacts of electrical traces beneath a peripheral die region of the IC die(s) in the dielectric layer, and wherein the core die region of the dielectric layer further includes a dielectric material having a higher thermal conductivity than the dielectric material in the peripheral die region;

[0020] Figure 5 is a diagram illustrating the manufacture of a package substrate (including FIG. 3A to FIG. 3B and Figure 4 A flowchart of an exemplary process for a packaging substrate in FIG.

[0021] 6A to 6T The diagram shows Figure 5 The exemplary process of manufacturing the exemplary manufacturing stage of the package substrate including the separation of the die area;

[0022] Figure 7is a block diagram of an exemplary processor-based system that may be provided in one or more IC dies that may be provided in a corresponding IC package including a package substrate (including die area separation) including, but not limited to FIG. 3A to FIG. 3B and Figure 4 A packaging substrate in; and

[0023] Figure 8 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component formed of one or more IC dies that may be provided in a corresponding IC package including a package substrate (including die area separation), the package substrate including but not limited to FIG. 3A to FIG. 3B and Figure 4 The packaging substrate in. DETAILED DESCRIPTION

[0024] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Aspects disclosed herein include integrated circuit (IC) packages that employ a thermally conductive semiconductor package substrate with die area separation. Related chip packages and methods of manufacturing semiconductor package substrates with die area separation are also disclosed. An IC package is provided that includes one or more semiconductor dies (also referred to as "IC dies") mounted on a package substrate. Die interconnects (e.g., core solder bumps) on the bottom surface of the (multiple) semiconductor die are electrically coupled to substrate interconnects exposed on the top surface of the package substrate to electrically couple the IC in the IC die to electrical traces in the package substrate. The package substrate includes one or more dielectric layers that include wiring layers for electrical traces that can be electrically coupled to electrical traces in adjacent dielectric layers through vertical interconnects (such as vertical interconnect paths (vias)). The electrical traces are coupled to substrate interconnects exposed on the bottom surface of the package substrate, which are electrically coupled to electrical connectors (e.g., solder balls) exposed from packaging material that encapsulates the IC die (s) and the package substrate as part of the IC package and provide an external electrical interface to the IC die (s) when mounted to a printed circuit board (PCB).

[0026] The electrical traces in the packaging substrate of the IC package not only provide an electrical interface to the (multiple) IC die, but can also be used to dissipate the heat generated by the (multiple) IC die when powered on and in operation. The (multiple) IC die includes a core die area in which a core integrated circuit ("core circuit") is formed. The core circuit may include hard circuit macros, such as a computer processing unit (CPU), a graphics processor unit (GPU), a memory, a modem, and / or a core power distribution rail, as an example. The (multiple) IC die also includes a peripheral die area outside the core die area in a non-core or peripheral area, which includes peripheral circuits, such as input / output (I / O) circuits and electrical wiring traces, as an example, to provide an interface to the core circuit. The core circuit generally generates more heat than the peripheral circuit. In this regard, in order to facilitate improved heat dissipation of the core circuit of the (multiple) IC die, in the exemplary aspects disclosed herein, at least one dielectric layer of the packaging substrate includes a die area separated between the metal contacts of its electrical traces. One or more metal contacts of electrical traces in a dielectric layer below the (multiple) IC die in the height direction (i.e., Z-axis direction) are thicker in the height direction than other metal contacts of electrical traces in the same dielectric layer. In this way, as an example, the IC package can have more effective thermal (i.e., heat) dissipation of heat generated from the (multiple) IC die through the thicker metal contacts of the electrical traces of the (multiple) dielectric layers of the package substrate. For example, this can compensate for reduced heat dissipation that might otherwise occur if the IC package and its package substrate are reduced in height, and thus reduce the volume of the metal contacts of the electrical traces in the package substrate to facilitate the reduction in the height of the IC package.

[0027] As a non-limiting example, one or more metal contacts of electrical traces in a dielectric layer below a core die region of (multiple) IC dies may be fabricated to be taller in height direction than metal contacts of electrical traces in the same dielectric layer below a peripheral die region of (multiple) IC dies. In this way, as an example, the IC package may have more effective thermal (i.e., heat) dissipation of heat generated from core circuits in (multiple) IC dies through thicker metal contacts of electrical traces in the core die region of (multiple) dielectric layers of the package substrate. As an example, by providing die-core separation in the package substrate, metal contacts of electrical traces in the peripheral die region of the dielectric layer in the package substrate may still be sized to have a smaller thickness than in the core die region of the dielectric layer to facilitate crosstalk shielding. Thus, heat dissipation of (multiple) IC dies through the core die region of the package substrate may not be sacrificed to still facilitate crosstalk shielding in the peripheral die region of the package substrate.

[0028] To further facilitate heat dissipation of the (multiple) IC die in the IC package, the dielectric layer of the thicker metal contacts containing electrical traces in the package substrate can also include a dielectric material having a higher thermal conductivity (e.g., in units of Watts per meter (m) Kelvin (K) (W / mK)) than the dielectric material disposed adjacent to and / or around the shorter metal contacts in the dielectric layer. For example, the dielectric layer in the package substrate (containing thicker metal contacts for electrical traces in the core die region than in the peripheral die region thereof) can also include a dielectric material having a higher thermal conductivity in its core die region than the thermal conductivity of the dielectric material in its peripheral die region. The dielectric material having a higher thermal conductivity helps to improve heat transfer compared to a dielectric material having a lower thermal conductivity. As an example, the dielectric material in the peripheral die region of the dielectric layer can be a different dielectric material than the dielectric material in the core die region of the dielectric layer and is selected based on desired electrical properties (such as signaling speed) and / or mechanical properties (such as less sensitivity to thermal stress).

[0029] In from Figure 3A Before discussing examples of IC packages using thermally conductive semiconductor package substrates with die area separation (eg, core die area separation), reference is first made to Figure 2A and Figure 2B Discuss IC packaging without die area separation.

[0030] Figure 2A The diagram shows Figure 2B 2 is a top view (in the XY plane) of an exemplary IC die 200 included in an IC package 202 that does not employ a thermally conductive semiconductor package substrate with die area separation. Figure 2A As shown, IC die 200 is a semiconductor die that includes a core die area 204 that includes a core IC 206 ("core circuit 206") formed in IC die 200. As non-limiting examples, core circuit 206 may include circuits that perform core operations of IC die 200, such as a computer processing unit (CPU), a graphics processor unit (GPU), memory, and / or a modem. Figure 2A As shown, the IC die 200 also includes a peripheral die area 208 outside the core die area 204. The peripheral die area 208 of the IC die 200 includes peripheral circuits 210 (e.g., input / output (I / O) circuits), and the peripheral circuits 210 include electrical wiring traces 212 ("electrical traces 212") to provide an interface to the core circuit 206. When power is supplied to the IC die 200 and the core circuit 206 and the peripheral circuit 210 are operating, the core circuit 206 and the peripheral circuit 210 generate heat. The heat generated by the core circuit 206 and the peripheral circuit 210 is generated by Figure 2BThe IC package 202 is shown to dissipate. Thermal dissipation of heat generated by the IC die 200 is important because the temperature may limit the operating frequency of the IC die 200. Large variations in temperature around the IC die 200 also cause the IC die 102 to expand and contract, which may introduce thermal stresses in the IC die 102 and thereby reduce the life of the IC die 200.

[0031] The IC package 202 may provide thermal dissipation of heat generated by the IC die 102 through the package substrate 214 of the IC die 200 . Figure 2B Pictured Figure 2A A side view of the IC die 200 of the IC package 202 along the AA' section line. For example, Figure 2B The IC package 202 in is a flip chip IC package that does not include a heat sink. The IC die 200 has a front surface 216 (i.e., an active surface) coupled to a package substrate 214 via a die attach and / or underfill adhesive. Epoxy and / or molding compound 218 may also be used to stabilize and protect the IC die 200. Solder balls 220 are formed on a bottom surface 222 of the package substrate 214 to provide an electrical interface to the IC die 200 when the IC package 202 is mounted to a printed circuit board (PCB). The package substrate 214 may be an embedded trace substrate (ETS) including one or more dielectric layers 226, the dielectric layer 226 including embedded electrical traces 224 (e.g., copper metal traces) to provide electrical signal routing between the solder balls 220 and the die interconnects 228. Metal contacts (e.g., copper contacts) are formed in the package substrate 214 in contact with the electrical traces 224 to provide contact pads for coupling to die interconnects 228, solder balls 220, and / or vertical interconnects that provide interconnections between different dielectric layers 226 in the package substrate 214. Thus, heat generated by the IC die 200 is more easily dissipated as indicated by arrows 230 through conduction paths from the die interconnects 228 and electrical traces 224 to the solder balls 220 than through the mold compound 218, for example.

[0032] Advances in the electrical performance of silicon integrated circuits (ICs) may result in shrinking in height (as shown in the Z-axis direction). Figure 2A and Figure 2B However, as the area of ​​the IC die 200 becomes smaller, the power consumption increases, and thus the power density on the IC die 200 increases. The increased power density on the IC die 200 directly translates into an increase in the heat generated by the IC die 200. In addition, it may also be desirable or necessary to reduce Figure 2B The height H1 of the IC package 202 in the height direction as shown in the Z-axis direction is reduced Figure 2BOne way to reduce the height H1 of the IC package 202 in the package substrate 214 is to reduce the height H2 of the package substrate 214. This can have the effect of reducing the height or thickness of the dielectric layer(s) 226 and the metal contacts connected to the electrical traces 224 in the package substrate 214. Reducing the height or thickness of the electrical traces 224 and / or the metal contacts connected to the electrical traces 224 reduces the volume of metal material in the dielectric layer(s) 226, thereby resulting in lower thermal dissipation of heat generated by the IC die 200. For example, reducing the thickness of the electrical traces 224 and / or the metal contacts connected to the electrical traces in the package substrate 214 (resulting in a smaller volume of metal in the dielectric layer(s) 226) can reduce crosstalk between high-speed signals carried on the electrical traces 224 from the peripheral circuits 210 in the IC die 200, and thus provide a crosstalk shielding technique. However, this comes at the expense of lower heat dissipation that may not be desirable or feasible for the IC die 200 and the IC package 202.

[0033] Figure 3A Illustrated is a side view of an exemplary IC package 302 that includes an IC die 300 and a package substrate 314 that facilitates higher thermal dissipation of the IC die 300 . Figure 3B Illustration of the combination Figure 3A Discussed Figure 3A FIG. 3 is a more detailed side view of the package substrate 314 of the IC package 302 in FIG. As discussed in more detail below, Figure 3A and Figure 3BThe package substrate 314 in includes a first dielectric layer 326(1) including a die region separation having one or more first metal contacts 324C(1) to electrical traces beneath a first die region 304 of the IC die 300. The first metal contacts 324C(1) to electrical traces beneath the first die region 304 of the IC die 300 and in the first die region 305(1) of the dielectric layer 326(1) have a height H3 (shown in the Z-axis direction) that is greater than a height H4 of the second metal contacts 324P(1) to electrical traces in the dielectric layer 326(1) beneath the second die region 308 of the IC die 300 in the second die region 305(2) of the dielectric layer 326(1). Thus, in this example, the first metal contact 324C(1) and the second metal contact 324P(1) in the dielectric layer 326(1) are not uniform in height, so that their respective volumes are not uniform. In this way, the volume of the first metal contact 324C(1) in the first die region 305(1) of the dielectric layer 326(1) is greater than the volume of the second metal contact 324P(1) in the second die region 305(2) of the dielectric layer 326(1) to facilitate higher thermal dissipation of the first die region 304 of the IC die 300 through the first die region 305(1) of the package substrate 314.

[0034] As an example, the height H4 of the second metal contact 324P(1) in the second die region 305(2) of the dielectric layer 326(1) of the package substrate 314 can be selected to reduce crosstalk between high-speed signals from the IC die 300 that are carried on electrical traces in the second die region 305(2) of the dielectric layer 326(1) as a crosstalk shielding technique. For example, the height H4 of the second metal contact 324P(1) in the second die region 305(2) can be ten (10) micrometers (μm), while the height H3 of the first metal contact 324C(1) in the first die region 305(1) can be 1.5 to 3.0 times the height H4, in which case the height H4 would be 15-30 μm. However, the reduced height H4 of the second metal contact 324P(1) in the second die region 305(2) may come at the expense of lower heat dissipation in the second die region 305(2) through the dielectric layer 326(1), but this may be without detriment or consequence if the second die region 308 of the IC die 300 does not generate heat that cannot be adequately dissipated in the second die region 305(2) through the dielectric layer 326(1).

[0035] In addition, Figure 3A and Figure 3BIn the example of the IC package 302 in FIG. 1 , the dielectric layer 326(1) may further include at least two different dielectric materials 330C(1), 330P(1) disposed adjacent to and / or around the respective first metal contact 324C(1) and second metal contact 324P(1), each having a different thermal conductivity. This facilitates further higher heat dissipation of the first die region 304 of the IC die 300 through the first die region 305(1) of the dielectric layer 326(1) of the package substrate 314. The first dielectric material 330C(1) disposed in the first die region 305(1) of the dielectric layer 326(1) is selected to have a higher thermal conductivity than the second dielectric material 330P(1) disposed in the second die region 305(2) of the dielectric layer 326(1). In this manner, the first dielectric material 330C(1) disposed in the first die region 305(1) of the dielectric layer 326(1) facilitates higher heat dissipation when, for example, the IC die 300 generates more heat in its first die region 304 above the first die region 305(1) of the dielectric layer 326(1). The second dielectric material 330P(1) disposed in the second die region 305(2) of the dielectric layer 326(1) can be selected to provide desired electrical and / or mechanical properties in the second die region 305(2) of the dielectric layer 326(1). For example, the second dielectric material 330P(1) having a lower thermal conductivity can provide more insulation for electrical traces in the second die region 305(2) of the dielectric layer 326(1) to reduce crosstalk. The second dielectric material 330P(1) having a lower thermal conductivity may also be less brittle and thus make the dielectric layer 326(1) as a whole less susceptible to cracking that could otherwise cause shorting of electrical traces in the second die region 305(2) of the dielectric layer 326(1).

[0036] refer to Figure 3A , IC package 302 includes a package substrate 314 arranged in a horizontal plane, which in this example is an XY axis plane. As an example, package substrate 314 can be made of a ceramic material in a stacked first dielectric layer 326 (1) and a second dielectric layer 326 (2). Package substrate 314 includes a bottom surface 322 and a Figure 3B The top surface 332 is positioned above the bottom surface 322 in the orientation shown. Note that "top" and "bottom" as used herein are relative terms and are not meant to limit or imply a strict orientation, i.e., an element referenced as "top" must always be oriented above an element referenced as "bottom" and vice versa. The package substrate 314 includes a top interconnect layer 334(1) that includes a plurality of interconnect layers 334(2) and a plurality of interconnect layers 334(3) disposed on the top surface 334(1) of the package substrate 314. Figure 3BThe first substrate interconnects 336C and the second substrate interconnects 336P are formed in the exposed patterns 338C, 338P of the top surface 332 as shown. The first substrate interconnects 336C and the second substrate interconnects 336P in the top interconnect layer 334(1) allow the package substrate 314 to be electrically coupled to the Figure 3A 328C and the second die interconnect 328P are shown in FIG. Alternatively, the first substrate interconnect 336C and the second substrate interconnect 336P may be the first metal contact 324C(1) and the second metal contact 324P(1) respectively. As a non-limiting example, the top interconnect layer 334(1) may be a solder layer, wherein the first substrate interconnect 336C and the second substrate interconnect 336P are solder bumps.

[0037] exist Figure 3B In the example shown, the package substrate 314 includes two dielectric layers 326(1), 326(2). The dielectric layer 326(1) includes a wiring layer 340(1), which includes a first metal contact 324C(1) and a second metal contact 324P(1) in the corresponding first die region 305(1) and the second die region 305(2) as described above, and each has a corresponding height H3 and H4 in the height direction (Z axis) orthogonal to the plane of the package substrate 314. The first metal contact 324C(1) and the second metal contact 324P(1) are in contact with the electrical traces routed in the wiring layer 340(1). The first metal contact 324C(1) and the second metal contact 324P(1) are electrically coupled to the corresponding first die interconnect 328C and the second die interconnect 328P to provide a connection from the first die interconnect 328C and the second die interconnect 328P to ... Figure 3A The conductive paths of the first die interconnect 328C and the second die interconnect 328P of the IC die 300 through the package substrate 314.

[0038] Continue to refer Figure 3B, the package substrate 314 in this example also includes a second dielectric layer 326(2). The second dielectric layer 326(2) includes a second wiring layer 340(2), which includes a third metal contact 324C(2) and a fourth metal contact 324P(2) also in the corresponding first die region 305(1) and the second die region 305(2), and each has a corresponding height H7 in the height direction (Z-axis) orthogonal to the plane of the package substrate 314. The third metal contact 324C(2) and the fourth metal contact 324P(2) contact the electrical traces routed in the second wiring layer 340(2). As an example, the third metal contact 324C(2) and the fourth metal contact 324P(2) are electrically coupled to the corresponding first metal contact 324C(1) and the second metal contact 324P(1) through vertical interconnects 342C(1), 342P(1) such as vertical interconnect vias (vias) or conductive pillars to provide a connection from the coupled to Figure 3A 305(1) and the second die region 305(2) are provided to form a conductive path from the first die interconnect 328C and the second die interconnect 328P of the IC die 300 to the third metal contact 324C(2) and the fourth metal contact 324P(2). For example, the vertical interconnects 342C(1), 342P(1) have a height H5 in this example, and the height H5 can be 35μm to 45μm. The package substrate 314 in this example also includes a third dielectric layer 326(3), which includes a third wiring layer 340(3), which includes a fifth metal contact 324C(3) and a sixth metal contact 324P(3) also in the corresponding first die region 305(1) and the second die region 305(2), and each has a corresponding height H8 in the height direction (Z-axis) orthogonal to the plane of the package substrate 314. The fifth metal contact 324C(3) and the sixth metal contact 324P(3) are in contact with electrical traces routed in the dielectric layer 326(3). The fifth metal contact 324C(3) and the sixth metal contact 324P(3) are electrically coupled to the corresponding third metal contact 324C(2) and the fourth metal contact 324P(2) through vertical interconnects 342C(2), 342P(2) having a height H7 to provide a connection from the coupled to Figure 3A The package substrate 314 further includes a bottom interconnect layer 334(2) including a first die interconnect 328C and a second die interconnect 328P of the IC die 300 to a fifth metal contact 324C(3) and a sixth metal contact 324P(3) having a height H8. Figure 3BThe third substrate interconnect 344C and the fourth substrate interconnect 344P are formed in the pattern 346C, 346P exposed on the bottom surface 322. The third substrate interconnect 344C and the fourth substrate interconnect 344P in the bottom interconnect layer 334(2) allow the package substrate 314 to be electrically coupled to the contact on the PCB to provide a connection between the PCB contact and the substrate. Figure 3A The conductive paths shown between the die interconnects 328C, 328P of the IC die 300. As a non-limiting example, the bottom interconnect layer 334(2) may be a solder layer, wherein the third substrate interconnect 344C and the fourth substrate interconnect 344P are solder bumps.

[0039] As described above, the height H3 of the first metal contact 324C(1) in the first dielectric layer 326(1) is higher than the height H4 of the second metal contact 324P(1) to provide greater heat dissipation of heat generated by the IC die 300 in the first die region 304 through the first die region 305(1) of the first dielectric layer 326(1). For example, as an example, the height H3 of the first metal contact 324C(1) can be between 15 μm and 30 μm, and as an example, the height H4 of the second metal contact 324P(1) can be between 5 μm and 10 μm. As a non-limiting example, the ratio of the height H3 of the first metal contact 324C(1) to the height H4 of the second metal contact 324P(1) can be at least 1.5 μm, and can be between 1.5 μm and 3.0 μm. In this example, the height H6 of the third metal contact 324C(2) and the fourth metal contact 324P(2) in the first die region 305(1) and the second die region 305(2) in the second dielectric layer 326(2) may be the same as the height H4 of the second metal contact 324P(1) in the second die region 305(2) of the first dielectric layer 326(1). Figure 3A and Figure 3B Although not shown in the example, the third metal contact 324C(2) in the second dielectric layer 326(2) may also be fabricated to be taller in height than the first metal contact 324C(1) to similarly increase heat dissipation through the second dielectric layer 326(2). Similarly, in this example, the height H8 of the fifth metal contact 324C(3) and the sixth metal contact 324P(3) in the first die region 305(1) and the second die region 305(2) in the third dielectric layer 326(3) may be the same as the height H4 of the second metal contact 324P(1) in the second die region 305(2) of the first dielectric layer 326(1). However, despite the Figure 3A and Figure 3BNot shown in the example, the fifth metal contact 324C(3) in the third dielectric layer 326(3) may also be fabricated to be taller in height than the first metal contact 324C(1) to similarly increase heat dissipation through the second dielectric layer 326(2).

[0040] To further facilitate heat dissipation of the first die region 305(1) through the dielectric layer 326(1) of the package substrate 314, as an example, the thermal conductivity of the first dielectric material 330C(1) can be at least 0.6 Watts per meter (m) Kelvin (K) (W / mK) and between 0.6 W / mK and 0.9 W / mK. As an example, the thermal conductivity of the second dielectric material 330P(1) can be 0.3 W / mK to 0.5 W / mK. As an example, the thermal conductivity of the first dielectric material 330C(1) can be at least 0.1 W / mK greater than the thermal conductivity of the second dielectric material 330P(1). As an example, the ratio of the thermal conductivity of the first dielectric material 330C(1) to the thermal conductivity of the second dielectric material 330P(1) can be at least 1.2. As an example, the dielectric constant of the first dielectric material 330C(1) (related to its permittivity) can be between 3.7 and 3.9, and the dielectric constant of the second dielectric material 330P(1) can be between 3.7 and 3.9. As an example, if the second dielectric material 330P(1) is selected to provide additional electrical and / or mechanical benefits, the dielectric constant of the second dielectric material 330P(1) can be between 3.3 and 4.2. The second dielectric layer 326(2) can include a single type of dielectric material having one of a given uniform thermal conductivity. Figure 3A In the example of FIG. 1 , the first die region 304 of the IC die 300 of the package substrate 314 can be considered as a core die region 304, which includes a core circuit 306, which is similar to the above-mentioned Figure 2A and Figure 2B The second die area 308 of the IC die 300 may be a peripheral die area 305(2) that includes a peripheral circuit 310 similar to the core circuit 206 in the IC die 200 described above. Figure 2A and Figure 2B314. The first die region 305(1) of the dielectric layer 326(1) of the package substrate 314 is similar to the peripheral circuit 210 in the IC die 200 in the package substrate 314. In this way, the first die region 305(1) of the dielectric layer 326(1) of the package substrate 314 is the core die region 304, and the second die region 305(2) of the dielectric layer 326(1) of the package substrate 314 is the peripheral die region 305(2). Therefore, the first metal contact 324C(1) in the wiring layer 340(1) of the dielectric layer 326(1) is the substrate core metal contact 324C(1) in the core die region 305(1) of the dielectric layer 326(1) of the package substrate 314. The second metal contact 324P(1) in the wiring layer 340(1) of the dielectric layer 326(1) is the substrate peripheral metal contact 324P(1) in the peripheral die region 305(2) of the dielectric layer 326(1) of the package substrate 314. The first metal contact 324C(1) and the second metal contact 324P(1) are configured to be electrically coupled to the first die interconnect 328C and the second die interconnect 328P (as the core die interconnect 328C and the peripheral die interconnect 328P) of the IC die 300. The first metal contact 324C(1) and the second metal contact 324P(1) are electrically coupled to the core die interconnect 328C and the peripheral die interconnect 328P through the first substrate interconnect 336C and the second substrate interconnect 336P (as the substrate core interconnect 336C and the substrate peripheral interconnect 336P).

[0041] In this manner, the volume of the substrate core metal contact 324C(1) in the core die region 305(1) of the dielectric layer 326(1) is greater than the volume of the substrate peripheral metal contact 324P(1) in the peripheral die region 305(2) of the dielectric layer 326(1) to facilitate higher thermal dissipation of the core die region 304 of the IC die 300 through the core die region 305(1) of the package substrate 314. In one example, the substrate core metal contact 324C(1) is disposed adjacent to the first dielectric material 330C(1), and the substrate peripheral metal contact 324P(1) is disposed adjacent to the second dielectric material 330P(1). As another example, the first dielectric material 330C(1) may be adjacent to and surround the substrate core metal contact 324C(1), and the second dielectric material 330P(1) may be adjacent to and surround the substrate peripheral metal contact 324P(1). As described above, the first dielectric material 330C(1) having a higher thermal conductivity facilitates higher thermal dissipation of the core die region 304 of the IC die 300 through the core die region 305(1) of the first dielectric layer 326(1) of the package substrate 314. The second dielectric material 330P(1) disposed in the peripheral die region 305(2) of the dielectric layer 326(1) can be selected to provide desired electrical and / or mechanical properties in the peripheral die region 305(2) of the dielectric layer 326(1), as described above.

[0042] Similarly, the third metal contact 324C(2) in the second dielectric layer 326(2) can be considered to be a substrate core metal contact 324C(2) in the core die region 305(1) of the dielectric layer 326(1) of the package substrate 314. The fourth metal contact 324P(2) in the second dielectric layer 326(2) can be considered to be a substrate peripheral metal contact 324P(2) in the peripheral die region 305(2) of the first dielectric layer 326(1) of the package substrate 314. The third dielectric layer 326(3) is disposed below the second dielectric layer 326(2) and includes a fifth metal contact 324C(3) and a sixth metal contact 324P(3) to provide conductivity between the electrical traces in the second dielectric layer 326(2) and the external interconnect 320 (in the form of solder balls in this example).

[0043] It should be noted that in this example, the first dielectric layer 326(1) includes the first wiring layer 340(1). The second dielectric layer 326(2) includes the second wiring layer 340(2). The third dielectric layer 326(3) includes the third wiring layer 340(3). The first dielectric material 330C(1) in the first dielectric layer 326(1) is disposed adjacent to and around the substrate core metal contact 324C(1) in the first wiring layer 340(1), and therefore, the first dielectric material 330C(1) can be considered to be also included in the first wiring layer 340(1). The second dielectric material 330P(1) in the first dielectric layer 326(1) is disposed adjacent to and around the substrate core metal contact 324C(1) in the first wiring layer 340(1), and therefore, the second dielectric material 330P(1) can be considered to be also included in the first wiring layer 340(1). The dielectric materials in the second dielectric layer 326 ( 2 ) and the third dielectric layer 326 ( 3 ) may also be considered to be included in their respective second wiring layer 340 ( 2 ) and third wiring layer 340 ( 3 ).

[0044] Figure 4 The diagram shows only Figure 3A and Figure 3B Another example of a package substrate 414 having two (2) dielectric layers in the package substrate 314 is shown. Figure 4 The package substrate 414 in the embodiment may be used for IC packaging, such as Figure 3A The IC package 302 in FIG. Figure 4 , the package substrate 414 includes the first dielectric layer 326 (1) and the third dielectric layer 326 (3), and does not include the intermediate second dielectric layer 326 (2) in the package substrate 314. In this regard, Figure 4 The package substrate 414 in FIG. 4 does not include the third metal contact 324C(2) and the fourth metal contact 324P(2) and their associated electrical traces. The first metal contact 324C(1) and the second metal contact 324P(1) in the first dielectric layer 326(1) are directly coupled to the fifth metal contact 324C(3) and the sixth metal contact 324P(3) in the third dielectric layer 326(3) through vertical interconnects 342C(1), 342P(1). Figure 4 The package substrate 414 and Figure 3A and Figure 3B Other common components between the package substrates 314 in FIG. 1 are shown using common element numbers and will not be re-described.

[0045] Figure 5 is a diagram illustrating the manufacture of a package substrate (including FIG. 3A to FIG. 3B and Figure 4 Flowchart of an exemplary process for packaging substrates 314 and 414 in FIG. FIG. 3A to FIG. 3Band Figure 4 The packaging substrate 314, 414 in the exemplary process is referenced. The process includes forming a packaging substrate 314, 414 ( Figure 5 502 in FIG. 50). The package substrate 314, 414 includes a top surface 332 and a bottom surface 322. The process also includes forming an interconnect layer 334(1) ( Figure 5 The process of forming the top interconnect layer 334(1) includes forming one or more substrate interconnects 336C, 336P ( Figure 5 For example, the process of forming the top interconnect layer 334(1) includes forming one or more first substrate interconnects 336C exposed through the top surface 332 of the substrate 314, 414. Figure 5 For another example, the process of forming the top interconnect layer 334(1) further includes forming one or more second substrate interconnects 336P exposed through the top surface 332 of the substrate 314, 414. Figure 5 The process also includes forming a first dielectric layer 326(1) ( Figure 5 510 in FIG.

[0046] The process of forming the dielectric layer 326(1) includes forming a first dielectric material 330C(1) having a first thermal conductivity ( Figure 5 The process of forming dielectric layer 326(1) includes forming a second dielectric material 330P(1) having a second thermal conductivity ( Figure 5 The process of forming dielectric layer 326(1) further includes forming wiring layer 340(1) ( Figure 5 As an example, forming wiring layer 340(1) includes forming one or more first metal contacts 324C(1) disposed adjacent to first dielectric material 330C(1), wherein each of the one or more first metal contacts 324C(1) has a first height H3 in a height direction orthogonal to a horizontal plane (XY), and wherein at least one of the one or more first metal contacts 324C(1) is electrically coupled to at least one of the one or more first substrate interconnects 336C(1). Figure 5The process of forming the dielectric layer 326(1) further includes forming one or more second metal contacts 324P(1) disposed adjacent to the second dielectric material 330C(1), wherein the one or more second metal contacts 324P(1) each have a second height H4 in a height direction, the second height H4 being less than the first height H3, and wherein at least one of the one or more second metal contacts 324P(1) is electrically coupled to at least one of the one or more second substrate peripheral interconnects 336P(1). Figure 5 520 in FIG.

[0047] 6A to 6T The diagram shows Figure 5 The exemplary process in the embodiment of the present invention is to manufacture an exemplary manufacturing stage of a package substrate including die area separation. Fig. 6A As shown in the exemplary manufacturing stage 600 (A) in FIG. 1 , the exemplary partial process begins by applying a copper seed layer 602 to a carrier 604 (eg, a copper carrier). Figure 6B As shown in the exemplary manufacturing stage 600 (B) in FIG. 1 , the process continues by applying a photoresist layer 606 on the copper seed layer 602. Figure 6C As shown in the exemplary manufacturing stage 600 (C) in FIG. 1 , a photolithography process is applied to form a wiring layer pattern 608 in the photoresist layer 606. The wiring layer pattern 608 includes a first opening 609 (1) at a first height to form a metal contact 624C (1) at a first height H3, and includes a second opening 609 (2) at a second height to form a metal contact 624P (1) at a second height H4. Fig.6D As shown in the exemplary manufacturing stage 600 (D) in FIG. 1 , a copper plating process is applied to form a first wiring layer 640 (1) in the wiring layer pattern 608 to form a first metal contact 624C (1) and a second metal contact 624P (1). A metal material 613 (e.g., copper) is disposed in the first opening 609 (1) and the second opening 609 (2) to form the metal contacts 624C (1), 624P (1). It should be noted that the first metal contact 624C (1) is taller than the second metal contact 624P (1) in the Z-axis or height direction. As shown in FIG. Fig. 6E As shown in exemplary manufacturing stage 600(E) in FIG. 6 , photoresist layer 606 is stripped to expose wiring layer 640(1) including first contact layer 612 to provide substrate interconnect 636C.

[0048] like Fig. 6F As shown in the exemplary manufacturing stage 600 (F) in FIG. 1 , the process continues by applying a non-conductive paste layer 614 on the first contact layer 612 for attaching an IC die (eg, Figure 3A IC bare chip 300 in FIG. Figure 6G As shown in the exemplary manufacturing stage 600 (G) in FIG. 1 , the process continues by coupling a bridge 616 to the first contact layer 612 on the non-conductive paste layer 614 for bonding the die to the substrate interconnect 636C on the first contact layer 612. The bridge 616 can be silicon or organic and have a fine pattern design for die-to-die connection. The bridge 616 can have sub-micron design capabilities (silicon) or have a minimum 2 μm fine pattern design capability (organic). Figure 6H As shown in the exemplary manufacturing stage 600 (H) in FIG. 1 , the process continues with applying a first stack 618 and a second stack 620. Fig.6I As shown in the exemplary manufacturing stage 600 (I) in FIG. 1 , the first stack 618 and the second stack 620 form a first dielectric layer 626 ( 1 ).

[0049] like Figure 6J As shown in the exemplary manufacturing stage 600 (J) in FIG. 1 , the process continues by etching a first vertical interconnect pattern 625 to either side of the bridge 616 and extending through the first dielectric layer 626 ( 1 ) to the first wiring layer 640 ( 1 ). Figure 6K As shown in the exemplary manufacturing stage 600 (K) in FIG. 1 , the process continues by applying copper in the first vertical interconnect pattern 625 to form a first plurality of vertical interconnects 642C ( 1 ), 642P ( 1 ) in addition to the second wiring layer 628 on the first dielectric layer 626 ( 1 ). Figure 6L As shown in the exemplary manufacturing stage 600 (L) in FIG. 1 , a second dielectric layer 626 ( 2 ) is formed on the first dielectric layer 626 ( 1 ), and a selective etching process is applied to form a second vertical interconnect pattern 632 . Figure 6M As shown in the exemplary manufacturing stage 600 (M) in FIG. 1 , the process continues by applying copper in the second vertical interconnect pattern 632 to form a second plurality of vertical interconnects 642C (2), 642P (2) in addition to the third wiring layer 640 (3) on the second dielectric layer 626 (2). Figure 6N As shown in the exemplary manufacturing stage 600 (N) in FIG. 1 , a third dielectric layer 626 ( 3 ) is applied on the second dielectric layer 626 ( 2 ), and patterns 646C, 646P are etched through the third dielectric layer 626 ( 3 ) to the wiring layer 640 ( 3 ). Fig.6O , the package 634 formed at this stage of manufacturing is reoriented, but it should be understood that this is for illustration purposes only and that the package 634 may remain in the original orientation for the remainder of the manufacturing process. Fig.6O In the process, the copper carrier 604 and the copper seed layer 602 are removed.

[0050] like Figure 6PAs shown in the exemplary manufacturing stage 600 (P) in FIG. 1 , the process continues by applying a fourth dielectric layer 626 (4) on the first dielectric layer 626 (1) and etching the fourth dielectric layer 626 (4) to form a contact pattern 638P and an empty center region 650 on the second die contact layer 644 (2). Figure 6Q , the process continues by forming a bottom interconnect layer 635(2) on the first die contact layer 644(1), and forming a portion of the first wiring layer 640(1) in the central region 650, followed by forming the first die contact layer 644(1). The process continues by coupling a first IC die 652 to the portion of the first die contact layer 644(1), and coupling a second die 654 to another portion of the first die contact layer 644(1) proximate to and horizontally spaced apart from the first IC die 652, followed by applying a first underfill layer 656.

[0051] like Figure 6R As shown in the exemplary manufacturing stage 600(R) in FIG. 1 , the process continues by attaching a first package 658 having a third semiconductor die 659 (which may be a memory, a semiconductor die, or an integrated logic chip) and coupled to the first wiring layer 640(1) using a second plurality of electrical (e.g., solder) joints 660 formed in a second joint pattern 638P that electrically couples the first package 658 to the first wiring layer 640(1). Figure 6S As shown in the exemplary manufacturing stage 600 (S) in FIG. 1 , the process continues by applying a second underfill layer 662 between the package 658 and the fourth dielectric layer 626 (4). Figure 6T As shown in exemplary manufacturing stage 600(T) in FIG. 8 , the process ends with forming a first plurality of external interconnects 620 in the form of solder balls in patterns 646C, 646P that electrically couple the third wiring layer 640(3) to the external interconnects 620.

[0052] It should be understood that although the above description mentions silicon bridges, copper plating, and lead solder materials, alternative materials may be used in place of these materials. Alternative materials may include the above alloys or materials that exhibit similar properties as described above. It should also be noted that the terms "top" and "bottom" as used herein are relative terms and are not meant to limit or imply a strict orientation, i.e., an element referenced "top" must always be oriented above an element referenced "bottom", and vice versa.

[0053] Including packaging substrate (including but not limited to FIG. 3A to FIG. 3B and Figure 4An IC package having a package substrate in a dielectric layer can be provided in or integrated into any processor-based device, the package substrate comprising a die area separation, the die area separation having one or more metal contacts of electrical traces beneath (multiple) IC dies, the one or more metal contacts being thicker in height direction than other metal contacts of the electrical traces in the dielectric layer, and wherein the dielectric layer further comprises a first dielectric material having a higher thermal conductivity than a second dielectric material. Without limitation, examples include a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a tablet computer, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disk (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor helicopter.

[0054] in this regard, Figure 7 An example of a processor-based system 700 is shown, which includes an IC package 702 (including but not limited to FIG. 3A to FIG. 3B and Figure 4, wherein the IC package 702 includes a die region separation according to any aspect disclosed herein, the die region separation having one or more metal contacts of electrical traces under the (multiple) IC die, the one or more metal contacts being thicker in height direction than other metal contacts of electrical traces in the dielectric layer, and wherein the dielectric layer further comprises a first dielectric material having a higher thermal conductivity than a second dielectric material. In this example, the processor-based system 700 can be formed as an IC 704 and a system on chip (SoC) 706 in the IC package 702. The processor-based system 700 includes a CPU 708, which includes one or more processors 710, which can also be referred to as CPU cores or processor cores. The CPU 708 can have a cache memory 712 coupled to the CPU 708 for quickly accessing temporarily stored data. The CPU 708 is coupled to a system bus 714, and can couple master devices and slave devices included in the processor-based system 700 to each other. As is known, CPU 708 communicates with these other devices by exchanging address, control, and data information on system bus 714. For example, CPU 708 may transmit a bus transaction request to memory controller 716, which is an example of a slave device. Figure 7 714 , but multiple system buses 714 may be provided, each of which constitutes a different structure.

[0055] Other master devices and slave devices may be connected to the system bus 714. Figure 7 As illustrated, as an example, these devices may include a memory system 720 including a memory controller 716 and (multiple) memory arrays 718, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728. Each of the memory system 720, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728 may be provided in the same or different IC packages 702. The (multiple) input devices 722 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (multiple) output devices 724 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The (multiple) network interface device 726 may be any device configured to allow data to be exchanged with a network 730. The network 730 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTHTM Network and Internet. The network interface device(s) 726 may be configured to support any type of communication protocol desired.

[0056] The CPU 708 may also be configured to access the display controller(s) 728 via the system bus 714 to control information sent to the display(s) 732. The display controller(s) 728 sends information to the display(s) 732 for display via the video processor(s) 734, which processes the information to be displayed into a format suitable for the display(s) 732. The display controller(s) 728 and the video processor(s) 734 may be included as ICs in the same or different IC packages 702, and are, by way of example, included in the same or different IC packages 702 that contain the CPU 708. The display(s) 732 may include any type of display, including, but not limited to, cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, light emitting diode (LED) displays, and the like.

[0057] Figure 8 An exemplary wireless communication device 800 is illustrated that includes a radio frequency (RF) component formed of one or more ICs 802, any of which may be included in an IC package 803 (including but not limited to an IC package 804). FIG. 3A to FIG. 3B and Figure 4 In a packaging substrate in the IC package 803, the IC package 803 includes a die area separation according to any aspect disclosed herein, the die area separation having one or more metal contacts of electrical traces under (multiple) IC dies, the one or more metal contacts being thicker in a height direction than other metal contacts of the electrical traces in the dielectric layer, and wherein the dielectric layer also includes a first dielectric material having a higher thermal conductivity than a second dielectric material.

[0058] As an example, the wireless communication device 800 may include or be provided in any of the above-referenced devices. Figure 8 As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include a memory for storing data and program codes. The transceiver 804 includes a transmitter 808 and a receiver 810 that support two-way communication. In general, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0059] The transmitter 808 or the receiver 810 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for the receiver 810. In a direct conversion architecture, a signal is frequency converted between RF and baseband in one stage. The superheterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800 in FIG. 8 , the transmitter 808 and the receiver 810 are implemented using a direct conversion architecture.

[0060] In the transmit path, the data processor 806 processes data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) for converting digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0061] Within the transmitter 808, low pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from the low pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An up-converter 818 up-converts the I and Q baseband signals using I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 822 through mixers 820(1), 820(2) to provide an up-converted signal 824. A filter 826 filters the up-converted signal 824 to remove undesired signals caused by the frequency up-conversion and noise in the receive frequency band. A power amplifier (PA) 828 amplifies the up-converted signal 824 from the filter 826 to obtain a desired output power level and provide a transmitted RF signal. The transmitted RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832 .

[0062] In the receive path, antenna 832 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate with a specific receive (RX) to TX ((RX)-to-TX) duplexer frequency spacing so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Down-conversion mixers 838 (1), 838 (2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to the data processor 806. In this example, the data processor 806 includes ADCs 846(1), 846(2) for converting the analog input signals into digital signals for further processing by the data processor 806.

[0063] exist Figure 8 In the wireless communication device 800 of FIG. 8 , a TX LO signal generator 822 generates I and Q TX LO signals used for frequency up-conversion, while an RX LO signal generator 840 generates I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal having a specific fundamental frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, an RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0064] It will be further understood by those skilled in the art that various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein can be adopted in any circuit, hardware component, integrated circuit (IC) or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been generally described above according to their functionality. How to implement this functionality depends on specific applications, design choices and / or design constraints imposed on the entire system. The technician can implement the described functionality in a varying manner for each specific application, but the implementation decision should not be interpreted as causing a departure from the scope of the present disclosure.

[0065] The various illustrative logical blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0066] The aspects disclosed herein may be embodied in hardware or in instructions stored in hardware and may be present in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and can write information to the storage medium. Alternatively, the storage medium may be a component of the processor. The processor and storage medium may be present in an ASIC. The ASIC may be present in a remote station. Alternatively, the processor and storage medium may be present in a remote station, a base station, or a server as discrete components.

[0067] It should also be noted that the operation steps described in any exemplary aspects of this article are described to provide examples and discussions. The described operations can be performed in many different orders other than the illustrated order. In addition, the operations described in a single operation step can actually be performed in many different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It should be understood that the operation steps illustrated in the flow chart can be modified as many different modifications that will be readily apparent to those skilled in the art. Those skilled in the art will also understand that any one of a variety of different techniques and skills can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be cited in the above entire specification can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0068] The previous description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit package, comprising: A substrate is disposed in a horizontal plane, the substrate comprising: a first dielectric material having a first thermal conductivity; a second dielectric material having a second thermal conductivity, the second thermal conductivity being lower than the first thermal conductivity; and Wiring layer, including: one or more first metal contact pads disposed adjacent to the first dielectric material, the one or more first metal contact pads each having a first height in a height direction orthogonal to the horizontal plane; and One or more second metal contact pads are arranged adjacent to the second dielectric material, each of the one or more second metal contact pads has a second height in the height direction, and the second height is less than the first height, The first dielectric material has a first dielectric material maximum height in the height direction, the second dielectric material has a second dielectric material maximum height in the height direction, and the first dielectric material maximum height is greater than the second dielectric material maximum height.

2. The IC package of claim 1 , wherein the substrate further comprises an interconnect layer, the interconnect layer comprising one or more substrate interconnects; At least one of the one or more first metal contact pads is electrically coupled to at least one first substrate interconnect of the one or more substrate interconnects; and At least one of the one or more second metal contact pads is electrically coupled to at least one second substrate interconnect among the one or more substrate interconnects.

3. The IC package of claim 1 , wherein the substrate comprises: Core die area, including: The first dielectric material has the first thermal conductivity; and The one or more first metal contact pads in the wiring layer include one or more substrate core metal contacts in the wiring layer and disposed adjacent to the first dielectric material, the one or more substrate core metal contacts each having the first height in the height direction; and A peripheral die region is arranged outside the core die region and adjacent to the core die region, the peripheral die region comprising: The second dielectric material has the second thermal conductivity, the second thermal conductivity being lower than the first thermal conductivity; and The one or more second metal contact pads include one or more substrate peripheral metal contacts in the wiring layer and are arranged adjacent to the second dielectric material, and the one or more substrate peripheral metal contacts each have the second height in the height direction, and the second height is smaller than the first height.

4. The IC package of claim 3, wherein the substrate further comprises: a second wiring layer disposed adjacent to the wiring layer; A second core die region is arranged to be aligned with the core die region in the height direction, the second core die region comprising: a third dielectric material having a third thermal conductivity; and one or more second substrate core metal contacts in the second wiring layer and disposed adjacent to the third dielectric material, the one or more second substrate core metal contacts each having a third height in the height direction; and A second peripheral die region is arranged to be aligned with the peripheral die region in the height direction, the second peripheral die region comprising: a fourth dielectric material having a fourth thermal conductivity; and One or more second substrate peripheral metal contacts are in the second wiring layer and are disposed adjacent to the fourth dielectric material, the one or more second substrate peripheral metal contacts each having a fourth height in the height direction.

5. The IC package of claim 3, further comprising: IC bare die, including: The core die area includes: one or more core circuits; and one or more core die interconnects electrically coupled to the one or more core circuits and at least one of the one or more substrate core metal contacts; and The peripheral die area is arranged outside the core die area and adjacent to the core die area, and the peripheral die area includes: one or more peripheral circuits; and One or more peripheral die interconnects are electrically coupled to the one or more peripheral circuits and at least one of the one or more substrate peripheral metal contacts. 6 . The IC package of claim 1 , wherein the first height is between 15 micrometers (μm) and 30 μm, and the second height is between 5 μm and 10 μm. 7 . The IC package of claim 1 , wherein a ratio of the first height to the second height is at least 1.

5.

8. The IC package of claim 1, wherein the first thermal conductivity is at least 0.6 Watts per meter (m) Kelvin (K) (W / mK).

9. The IC package of claim 1, wherein the first thermal conductivity is at least 0.1 W / mK greater than the second thermal conductivity.

10. The IC package of claim 1, wherein the first thermal conductivity is between 0.6 W / mK and 0.9 W / mK, and the second thermal conductivity is between 0.3 W / mK and 0.5 W / mK.

11. The IC package of claim 1, wherein a ratio of the first thermal conductivity to the second thermal conductivity is at least 1.

2.

12. The IC package of claim 1, wherein the substrate further comprises: a third dielectric material having a third thermal conductivity; a fourth dielectric material having a fourth thermal conductivity; as well as The second wiring layer includes: One or more third metal contacts are disposed adjacent to the third dielectric material, the one or more third metal contacts each having a third height in the height direction; as well as One or more fourth metal contacts are disposed adjacent to the fourth dielectric material, and each of the one or more fourth metal contacts has a fourth height in the height direction. 13 . The IC package of claim 12 , wherein the third height and the fourth height are the same height.

14. The IC package of claim 12, wherein the third height and the fourth height are different heights.

15. The IC package of claim 12, wherein the third height is equal to the first height, and the fourth height is equal to the second height.

16. The IC package of claim 12, wherein the third dielectric material and the fourth dielectric material are the same dielectric material, and wherein the third thermal conductivity is equal to the fourth thermal conductivity.

17. The IC package of claim 12, wherein the third thermal conductivity is greater than the fourth thermal conductivity.

18. The IC package of claim 1, wherein the substrate further comprises: one or more first vertical interconnects, each contacting a first metal contact pad among the one or more first metal contact pads; as well as One or more second vertical interconnects each contact a second metal contact pad among the one or more second metal contact pads.

19. The IC package of claim 2, wherein: The substrate comprises a top surface and a bottom surface; The one or more substrate interconnects in the interconnect layer include: one or more first substrate interconnects exposed through the top surface of the substrate; and one or more second substrate interconnects exposed through the top surface of the substrate; The at least one first metal contact pad of the one or more first metal contact pads is electrically coupled to at least one first substrate interconnect of the one or more first substrate interconnects; and The at least one second metal contact pad of the one or more second metal contact pads is electrically coupled to at least one second substrate interconnect of the one or more second substrate interconnects.

20. The IC package of claim 2, wherein the substrate further comprises a bottom interconnect layer, the bottom interconnect layer comprising: one or more third substrate interconnects, at least one of the one or more third substrate interconnects being electrically coupled to at least one of the one or more first metal contact pads; as well as One or more fourth substrate interconnects, at least one of the one or more fourth substrate interconnects being electrically coupled to at least one of the one or more second metal contact pads.

21. The IC package of claim 1, further comprising: IC bare die, including: one or more circuits; and one or more die interconnects; At least one of the one or more die interconnects is electrically coupled to at least one of the one or more circuits and at least one metal contact pad among the one or more first metal contact pads and the one or more second metal contact pads.

22. The IC package of claim 1 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disk (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor helicopter.

23. A method of manufacturing a packaging substrate for an integrated circuit (IC) package, comprising forming a substrate disposed in a horizontal plane, forming the substrate comprising: forming a dielectric layer, comprising: forming a first dielectric material having a first thermal conductivity; forming a second dielectric material having a second thermal conductivity, the second thermal conductivity being lower than the first thermal conductivity; and Forming a wiring layer, including: forming one or more first metal contact pads adjacent to the first dielectric material, the one or more first metal contact pads each having a first height in a height direction orthogonal to the horizontal plane; and forming one or more second metal contact pads adjacent to the second dielectric material, the one or more second metal contact pads each having a second height in the height direction, the second height being less than the first height, The first dielectric material has a first dielectric material maximum height in the height direction, the second dielectric material has a second dielectric material maximum height in the height direction, and the first dielectric material maximum height is greater than the second dielectric material maximum height.

24. The method according to claim 23, wherein forming the substrate further comprises forming an interconnect layer, and forming the interconnect layer comprises: forming one or more substrate interconnects, the one or more substrate interconnects comprising one or more substrate core interconnects and one or more substrate peripheral interconnects; as well as Forming the interconnect layer further comprises: electrically coupling at least one of the one or more first metal contact pads to at least one of the one or more substrate interconnects; as well as At least one of the one or more second metal contact pads is electrically coupled to at least one second substrate interconnect of the one or more substrate interconnects.

25. The method of claim 23, wherein: Forming the first dielectric material further includes: forming the first dielectric material in a core die region; Forming the second dielectric material further includes: forming the second dielectric material in a peripheral die region, the peripheral die region being disposed outside of and adjacent to the core die region; Forming the one or more first metal contact pads includes: forming one or more substrate core metal contacts adjacent to the first dielectric material, the one or more substrate core metal contacts each having the first height in the height direction orthogonal to the horizontal plane; and Forming the one or more second metal contact pads includes forming one or more substrate peripheral metal contacts adjacent to the second dielectric material, the one or more substrate peripheral metal contacts each having the second height in the height direction, the second height being less than the first height.

26. The method of claim 25, further comprising forming an IC die, forming the IC die comprising: forming one or more core circuits in the core die area; forming one or more core die interconnects in the core die region, the one or more core die interconnects being electrically coupled to the one or more core circuits and to at least one of the one or more substrate core metal contacts; forming one or more peripheral circuits in the peripheral die region, the peripheral die region being disposed outside of and adjacent to the core die region; as well as One or more peripheral die interconnects are formed in the peripheral die region, the one or more peripheral die interconnects being electrically coupled to the one or more peripheral circuits and at least one of the one or more substrate peripheral metal contacts.

27. The method according to claim 23, wherein forming the wiring layer further comprises: forming a wiring layer pattern in the wiring layer, the wiring layer pattern comprising one or more first openings at the first height and one or more second openings at the second height; disposing a metal material in the one or more first openings to form the one or more first metal contact pads at the first height; as well as A metal material is disposed in the one or more second openings to form the one or more second metal contact pads at the second height.

28. The method according to claim 23, wherein forming the wiring layer further comprises: forming one or more first vertical interconnects, each of the one or more first vertical interconnects contacting a first metal contact pad among the one or more first metal contact pads; as well as One or more second vertical interconnects are formed, each of the one or more second vertical interconnects being in contact with a second metal contact pad among the one or more second metal contact pads.

29. The method of claim 23, further comprising forming an IC die, forming the IC die comprising: forming one or more circuits; forming one or more die interconnects electrically coupled to the one or more circuits and at least one of the one or more first metal contact pads; as well as One or more die interconnects are formed that are electrically coupled to the one or more circuits and at least one of the one or more second metal contact pads.

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