An online monitoring circuit and method for open-circuit faults at the chip level of a multi-chip IGBT module

Abstract

The present invention discloses an on-line monitoring circuit and method for chip-level open-circuit faults of a multi-chip IGBT module, including a VCC circuit and an HSP conversion circuit; the VCC circuit includes a clamping NMOS, a bidirectional voltage regulator diode, a filter capacitor, an auxiliary voltage source, a protection resistor R1 and a protection resistor R2, wherein the protection resistor R2 is connected in parallel with the drain-source of the clamping NMOS, the source of the clamping NMOS is connected in series with the bidirectional voltage regulator diode, the bidirectional voltage regulator diode is connected in series with the protection resistor R1, the drain of the NMOS and the other end of the protection resistor R1 are connected in parallel with the device under test, and the filter capacitor and the auxiliary voltage source are connected in parallel and then connected to the gate of the NMOS and the other end of the protection resistor R1; the HSP conversion circuit includes a buffer, a comparator, a proportional differentiator and a sample and hold circuit, wherein the output end of the buffer is respectively connected to the proportional differentiator and the comparator, the output end of the proportional differentiator is connected to the input end of the sample and hold circuit, the comparator is connected to the trigger signal end of the sample and hold circuit, and the output end of the sample and hold circuit is connected to an external analog-to-digital converter.

Description

Technical Field

[0001] The present invention belongs to the field of industrial control computer and system manufacturing, and particularly relates to an online monitoring circuit and method for open-circuit faults at the chip level of a multi-chip IGBT module. Background Art

[0002] At present, power electronic systems play an important role in a wide range of industrial applications such as transportation, renewable energy systems, and industrial automation. As the core, power devices play a key role in the robustness and reliability of power electronic systems. However, in field applications, due to the influence of periodic electrical, thermal, and mechanical stress changes, the performance of power devices will gradually degrade, such as bond wire fatigue, aluminum electrode remodeling, and solder voids. When the degradation of the power module accumulates to a certain extent, it may cause catastrophic damage to the entire power electronic system. According to two industrial surveys on the causes of power electronic system failures, power devices account for 21% and 34% of the total failure distribution respectively, indicating that power devices are one of the weakest components in terms of reliability in the system. Therefore, it is necessary to perform online monitoring on power modules in critical applications to identify abnormal and degradation signals in advance and prevent unexpected catastrophic failures.

[0003] For high-power modules with multi-chip parallel connection, due to large temperature fluctuations and mismatches in the coefficient of thermal expansion (CTE) between materials, bond wire fatigue is one of the main degradation failure modes. When a single bond wire falls off due to fatigue failure, the other bond wires on the chip will bear a higher current density and generate more Joule heat, thus accelerating the open-circuit fault rate of the entire chip. As the number of open-circuit chips increases, the current-carrying capacity of the power module continuously decreases, and the junction temperature gradually rises until catastrophic thermal failure occurs. Since the detachment of a single bond wire is very insensitive in multi-chip power modules, chip-level open-circuit diagnosis can achieve a good compromise between monitoring difficulty and effect. For multi-chip IGBT modules, an open-circuit fault in a certain chip will not immediately cause catastrophic failure of the entire power module. Therefore, chip-level open-circuit diagnosis can be regarded as a precursor to the health monitoring of multi-chip power modules to some extent.

[0004] In recent years, great progress has been made in the online monitoring and diagnosis technology of power modules. Scholars at home and abroad have proposed a series of static and dynamic characteristic parameters to monitor the junction temperature and degradation of devices in real time. However, there are three main drawbacks that limit their application in practical engineering, which are specifically as follows:

[0005] (1) Safety: Some parameters are not conducive to device safety itself, such as voltage overshoot and crosstalk effect during turn-off. The former is considered a thermosensitive electrical parameter (TSEP) unrelated to bond wire degradation, but it may cause device overvoltage breakdown failure. The latter is used to diagnose open-circuit faults of IGBT chips, but it may cause mis-conduction of the device during the turn-on process of complementary devices. From the perspective of device application, certain measures need to be taken to reduce these two effects, such as active gate drive, adjacent decoupling technology, etc., which runs counter to the intention of online monitoring to improve parameter sensitivity.

[0006] (2) Operating condition sensitivity: Some parameters are closely related to operating conditions, thus greatly increasing the monitoring cost, such as the collector-emitter saturation voltage V CEsat . As a characteristic parameter of bond wire fatigue, V CEsat is closely related to the current and junction temperature of the device. Therefore, its monitoring accuracy depends on the measurement of dynamic current and junction temperature, and the slight changes caused by bond wire fatigue may be interfered by the operating conditions. The high sensitivity to operating conditions limits its diagnostic accuracy in practical engineering.

[0007] (3) Monitoring difficulty: Some parameters are difficult to extract under high-frequency operating conditions unless the operating state of the power device is changed, such as the turn-on delay time t don and the turn-off delay time t doff . During the process of extracting these variables, the gate resistance R G needs to be set large enough to achieve high sensitivity, such as 300Ω and 2000Ω. Due to excessive switching losses, it cannot be directly applied to high-frequency converters. Therefore, special gate drivers must be designed to switch to a larger resistance for parameter extraction within several PWM cycles, which greatly increases the complexity of the monitoring system. Although these characteristic parameters have good monitoring and diagnostic effects, they are difficult to apply in power electronic converters with high reliability requirements because they change the normal operating state of the device. Summary of the Invention

[0008] The purpose of the present invention is to provide an online monitoring circuit and method for chip-level open-circuit faults of a multi-chip IGBT module to solve the problems existing in the prior art. The present invention can provide accurate monitoring of the health status of the IGBT module in practical engineering, and thus provide strong support for the safe operation of power electronic devices, significantly improving the operation reliability of power electronic systems.

[0009] To achieve the above object, the present invention adopts the following technical solutions:

[0010] An on-line monitoring circuit for chip-level open-circuit faults of a multi-chip IGBT module, including a VCC circuit and an HSP conversion circuit. The output end of the VCC circuit is connected to the input end of the HSP conversion circuit, and the output end of the HSP conversion circuit is connected to a host computer through an analog-to-digital converter;

[0011] The VCC circuit includes a clamping NMOS, a bidirectional voltage regulator diode, a filter capacitor, an auxiliary voltage source, a protection resistor R1, and a protection resistor R2. Among them, the protection resistor R2 is connected in parallel with the drain-source of the clamping NMOS. The source of the clamping NMOS is connected in series with the bidirectional voltage regulator diode. The bidirectional voltage regulator diode is connected in series with the protection resistor R1. The drain of the NMOS and the other end of the protection resistor R1 are connected in parallel with the device under test. The filter capacitor and the auxiliary voltage source are connected in parallel and then connected to the gate of the NMOS and the other end of the protection resistor R1;

[0012] The HSP conversion circuit includes a buffer, a comparator, a proportional differentiator, and a sample and hold circuit. Among them, the output end of the buffer is respectively connected to the proportional differentiator and the comparator. The output end of the proportional differentiator is connected to the input end of the sample and hold circuit. The comparator is connected to the trigger signal end of the sample and hold circuit. The output end of the sample and hold circuit is connected to an external analog-to-digital converter;

[0013] The output end of the VCC circuit is the source of the clamping NMOS, which is connected to the input end of the buffer in the HSP conversion circuit.

[0014] An on-line monitoring method for chip-level open-circuit faults of a multi-chip IGBT module, including:

[0015] When the device under test is in the off state, the VCC circuit is used to isolate the high voltage to prevent the influence of the higher bus voltage on the HSP conversion circuit;

[0016] The HSP conversion circuit is used to convert the collector-emitter voltage V CE of the device under test into a voltage change rate dV CE / dt;

[0017] The voltage change rate dV CE / dt is output through the sample and hold circuit and transmitted to the host computer through an analog-to-digital converter as a characteristic parameter of the chip-level open-circuit fault.

[0018] Further, when the device under test is in the off state, the rising process of the collector-emitter voltage V CE of the device under test is divided into the following three stages:

[0019] In the first stage, the gate-emitter voltage V GE drops to the Miller plateau voltage V GP ;

[0020] In the second stage, the gate-emitter voltage V GE is maintained at the Miller plateau voltage V GP ;

[0021] In the third stage, the collector-emitter voltage V CE rises to the knee voltage V KNEE .

[0022] Furthermore, in the first stage, the gate-emitter voltage V GE drops to the Miller plateau voltage V GP , satisfying the following equation:

[0023] V CE ≤V GP -V TH

[0024] where V TH is the threshold voltage of a single IGBT chip in the device under test. According to the equivalent circuit, the gate-emitter voltage V GE is expressed as:

[0025]

[0026] where τ ies =(C GE +C OXD )(nR G +R gin ), V GG_ON and V GG_OFF are the turn-on and turn-off voltages of the gate drive, C GE is the gate-emitter capacitance, C OXD is the overlap oxide capacitance, n is the number of parallel IGBT chips in the device under test, R G is the external gate resistance of the entire IGBT device under test, R gin is the internal gate resistance of a single IGBT chip. The relationship between the collector-emitter voltage V CE and the gate-emitter voltage V GE is approximately expressed as:

[0027]

[0028] where I L is the load current, K T is a constant related to the structure of the device under test. Correspondingly, dV CE / dt is expressed as:

[0029]

[0030] Furthermore, in the second stage, the gate-emitter voltage V GEMaintained to the Miller platform voltage V GP , at this stage, dV CE / dt is expressed as:

[0031]

[0032] where g m is the transconductance of a single IGBT chip in the device under test;

[0033] Therefore

[0034]

[0035] where τ OXD = C OXD (nR G + R gin ).

[0036] Furthermore, in the third stage, the collector-emitter voltage V CE rises to the knee voltage V KNEE , at this stage:

[0037]

[0038]

[0039] where A g is the gate overlap area of a single IGBT chip in the device under test, N B is the base doping concentration, q is the unit electron charge, ε si is the dielectric constant of silicon, at this stage the closed-form expression of dV CE / dt is as follows:

[0040]

[0041] where τ GC = C GC (nR G + R gin ), C O is the charge extraction capacitance, that is

[0042]

[0043] where v sat is the carrier saturation velocity, p0 is the excess carrier density in the on state of the anode PN junction.

[0044] Furthermore, when the device under test is in the off state, the VCC circuit is used to isolate the high voltage to prevent the influence of the higher bus voltage on the HSP conversion circuit, specifically:

[0045] When the device under test is in the off state, its collector-emitter voltage V CE bus voltage V DC , the voltage V between the source of the NMOS and the emitter of the device under test SE is clamped to the Zener voltage V of the bi-directional Zener diode D Z , and the protection resistor R2 is determined by the following formula: Z

[0046]

[0047] where I DSS is the drain-source leakage current of the clamping NMOS. Therefore, the gate-source voltage V of the clamping NMOS G*S is clamped to:

[0048] V G*S_OFF = V O - V SE = V O - V Z

[0049] where V O is the external voltage source, C O is the filter capacitor. When the device under test is turned on, V SE decreases with the collector-emitter voltage V of the device under test CE , resulting in an increase in the gate-source voltage V of the NMOS. When the clamping NMOS turns to the linear operating region, it starts to be in a low-impedance state, and at this time, the following is satisfied: G*S

[0050]

[0051] where is the threshold voltage of the clamping NMOS. Since V DS = V CE - V SE , the above formula is rearranged as:

[0052]

[0053] The above inequality determines the accurate measurement range of V CE , and at this time, the following is satisfied:

[0054] V M = V SE = V CE - V DS ≈ V CE

[0055] V G*S_ON = V O - V M ≈ V O ​​

[0056] Among them, V M is the voltage output from the VCC circuit to the HSP conversion circuit.

[0057] Furthermore, the HSP conversion circuit is used to convert the collector-emitter voltage V of the device under test CE into a voltage change rate dV CE / dt and then maintain it in the second stage of turn-off. Specifically:

[0058] The output of the buffer is equal to the output V of the VCC circuit M , and the proportional differentiator converts the voltage into a voltage slope, and its output is:

[0059]

[0060] Among them, K D is the ratio of the proportional differentiator. When the output V of the VCC circuit M is less than the reference voltage V REF , the output of the comparator is high level, and the sample and hold circuit can track the signal of V K in real time. Once the output V of the VCC circuit M is greater than V REF , the comparator immediately becomes low level, making the sample and hold circuit enter the hold mode. Therefore, at this time, V K can be maintained at a stable value until the next switching cycle. In order to ensure that V K is maintained in the second stage, V REF should satisfy:

[0061] V GP - V TH ≤ V REF +(t AD + t PD ) × H SP ≤ V KNEE

[0062] Among them, t AD is the effective aperture delay of the sample and hold circuit, and t PD is the propagation delay of the comparator. Transforming the above formula into:

[0063]

[0064] The above inequality is regarded as the selection criterion of V REF . Finally, the output of the sample and hold circuit is transmitted to the host computer through the analog-to-digital converter as the characteristic parameter of the chip-level open-circuit fault.

[0065] Compared with the prior art, the present invention has the following beneficial technical effects:

[0066] The present invention can accurately monitor the health status of IGBT modules in actual engineering, thereby providing strong support for the safe operation of power electronic devices. Compared with the existing monitoring methods (as shown in Table 1), the advantages of the proposed method are specifically manifested as follows:

[0067] (1) In terms of safety, the monitoring methods based on crosstalk effect and V GE turn-on duration have certain potential risks. The open-circuit fault of the former monitoring circuit will introduce an excessive on-state gate resistance RM, thereby increasing the risk of overheating of the monitored high-frequency inverter. And V GE turn-on duration is based on an additional constant-current source driver. Once the switching sequence of the drive circuit is slightly incorrect, it will cause abnormal operation of the inverter. Therefore, both of the above situations will introduce potential risk factors to the gate of the power module and increase the uncertainty of inverter operation. For the proposed HSP monitoring method, its monitoring circuit is not connected to the gate, so it will not affect the normal operation of the device and the inverter. In addition, the failure of the monitoring circuit will not cause the failure of the monitored inverter.

[0068] (2) In terms of sensitivity to operating conditions, the main considerations are I L , T j and V DC . The monitoring method based on V GE overshoot is closely related to the above three, and the method based on V CEsat is susceptible to the influence of I L and T j . In addition, for the crosstalk effect, although the influence of the junction temperature can be ignored, the influence of the change of I L needs to be considered. And for the method based on V GE duration and V GE(pre-th) , the influence of the bus voltage V DC should be carefully considered. Compared with the above methods, the proposed HSP monitoring method has very low sensitivity to I L , T j and V DC . The influence of the operating conditions can be basically ignored in the monitoring of chip-level open-circuit faults. Therefore, it is more suitable for fault diagnosis under complex and changing operating conditions.

[0069] (3) In terms of extraction difficulty, the monitoring methods based on crosstalk effect and V GE duration rely on specially designed drive circuits and are difficult to apply to existing commercial inverters. For the methods based on V GE overshoot and V GE(pre-th)The method needs to consider the bandwidth of the chip and the speed of data acquisition, which poses a challenge to accurately obtaining dynamic signals. For the proposed HSP, its time-independent characteristic improves the extraction accuracy, and the sample-and-hold circuit ensures that the ADC has enough time to convert the analog signal. In addition, due to its compact design, the on-line monitoring circuit can be either plug-and-play in existing inverters or integrated into the newly designed gate drive circuit.

[0070] Table 1 Comparison of Chip-Level Open-Circuit Fault Diagnosis Methods

[0071]

[0072] ★★★—Good ★★—Average ★—Poor Description of the Drawings

[0073] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the drawings, where:

[0074] Figure 1 is the turn-off process of the IGBT device;

[0075] Figure 2 are the equivalent circuits and space charge region (SCR) distributions at different stages during the turn-off process of the IGBT device: (a) Stage I, (b) Stage II, (c) Stage III;

[0076] Figure 3 is the coupling relationship between the voltage change rate and the operating conditions at different stages;

[0077] Figure 4(a) is the schematic diagram of the on-line monitoring circuit, and Figure 4(b) is the theoretical waveform of the on-line monitoring circuit;

[0078] Figure 5 is the HSP monitoring circuit board;

[0079] Figure 6 are the test waveforms of the monitoring circuit board in the double-pulse experiment: (a) Healthy state, (b) Single-chip open-circuit state;

[0080] Figure 7 are the test waveforms of the monitoring circuit board in the inverter prototype: (a) Healthy state, (b) Single-chip open-circuit state;

[0081] Figure 8 are the digital quantities of the HSP in different states extracted by the host computer. Detailed Implementation Modes

[0082] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0083] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "include" and "comprise" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0084] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0085] It should be further understood that the term " / and" used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0086] The online monitoring method for the chip-level open-circuit fault of the multi-chip IGBT module of the present invention is introduced in detail as follows:

[0087] I. Online monitoring principle

[0088] The characteristic parameter of the chip-level open-circuit fault proposed by the method of the present invention is the voltage change rate dV CE / dt during a certain process in the turn-off transient. Taking the trench-gate field-stop (FS) IGBT as an example, its turn-off transient is as Figure 1 shown. The rising process of the collector-emitter voltage V CE can be divided into the following three stages.

[0089] In the first stage, the gate-emitter voltage V GE drops to the Miller plateau voltage V GP . In this stage, the MOS channel is in the linear operating region, and the collector-emitter voltage V CE only rises slightly. Therefore, the equivalent circuit at P1 and the distribution of the space charge region (SCR) can be expressed as Figure 2 (a). This stage continues until the MOS channel enters the saturation operation, approximately satisfying the following formula

[0090] V CE ≤VGP -V TH (1)

[0091] where V TH is the threshold voltage of the IGBT chip. According to the equivalent circuit, V GE can be expressed as

[0092]

[0093] where τ ies =(C GE +C OXD )(nR G +R gin ), V GG_ON and V GG_OFF are the turn-on and turn-off voltages of the gate drive, C GE is the gate-emitter capacitance, C OXD is the overlap oxide capacitance, n is the number of parallel IGBT chips, R G is the external gate resistance of the IGBT module, and R gin is the internal gate resistance of a single IGBT chip. In the linear operation of the MOS channel, the relationship between V CE and V GE can be approximately expressed as

[0094]

[0095] where I L is the load current and K T is a constant related to the device structure. Accordingly, dV CE / dt can be expressed as

[0096]

[0097] In the second stage, V GE is maintained until V GP . The Miller capacitance C GC is charged through the gate. The equivalent circuit and SCR distribution (SCR) at P2 are shown in Figure 2 (b). Before P2, due to the forward bias of V GC , the SCR does not extend below the gate region, so C GC is equal to C OXD . After P2, V GC starts to be negatively biased, causing the SCR below the gate region to start expanding. In this stage, dV CE / dt can be expressed as

[0098]

[0099] where V GPcan be approximately expressed as

[0100]

[0101] where g m is the transconductance of a single IGBT chip. Therefore, Equation (5) can be rearranged as

[0102]

[0103] where τ OXD = C OXD (nR G + R gin ).

[0104] In the third stage, after V CE rises to the inflection point voltage V KNEE , the gate region is completely covered by the SCR, as shown in Figure 2 (c). Therefore, due to the influence of the depletion capacitance C dep , C GC suddenly drops and can be expressed as

[0105]

[0106]

[0107] where A g is the gate overlap area of a single IGBT chip. N B is the base (drift region) doping concentration, q is the unit electron charge, and ε si is the dielectric constant of silicon. Therefore, V CE rises sharply, and at this time dV CE / dt is limited by the rate of SCR expansion. The closed-form expression of dV CE / dt in this stage is as follows:

[0108]

[0109] where τ GC = C GC (nR G + R gin ), and C O is the charge extraction capacitance, that is

[0110]

[0111] where v sat is the carrier saturation velocity. p0 is the excess carrier density in the conducting state of the anode pn junction, which is related to the junction temperature T j and I Lis related. According to formulas (4), (7), and (10), the coupling relationships between dV / dt at different stages and each parameter are summarized as CE shown. Among these three stages, the most obvious difference is that dV / dt in the second stage is a variable independent of time and is only related to T Figure 3 , I CE , V j , n, and R L . This characteristic makes dV / dt in the second stage more suitable than other stages as a characteristic parameter for on-line monitoring during the high-speed switching process, so that the errors introduced by aperture delay and the jitter of the sample and hold amplifier (SHA) can be almost eliminated. Therefore, in this method, dV / dt in the second stage is regarded as a health-sensitive parameter, denoted as HSP. GG_OFF G CE CE

[0112] II. On-line Monitoring Circuit Design

[0113] The on-line extraction circuit of HSP designed by this method is shown in Fig. 4(a) and mainly consists of a voltage clamping circuit (VCC) and an HSP conversion circuit.

[0114] The purpose of the VCC circuit is to isolate high voltage and prevent the influence of a relatively high bus voltage on the HSP conversion circuit. It mainly consists of a clamping NMOS, a bidirectional voltage regulator diode, a filter capacitor, an auxiliary power supply, and a protection resistor. When the device under test is in the off state, its V CE is approximately equal to the bus voltage V DC . At this time, the voltage V SE in Fig. 4 is clamped to the Zener voltage V Z of D Z . R2 can be determined by the following formula:

[0115]

[0116] where I DSS is the drain-source leakage current of the NMOS. Therefore, the gate-source voltage V G*S of the NMOS is clamped to

[0117] V G*S_OFF = V O - V SE = V O - V Z (13)

[0118] where V O is an external voltage source and C O is a filter capacitor. To enable the NMOS to safely block high voltage, V G*S ​​​​Should be maintained at an appropriate value during turn-off. When the device under test is turned on, V SE decreases with V CE , resulting in an increase in V G*S . After transitioning to the linear operating region, the NMOS starts to be in a low-impedance state, where

[0119]

[0120] where is the threshold voltage of the NMOS. Since V DS = V CE - V SE , the inequality (14) can be rearranged as

[0121]

[0122] The above inequality determines the accurate measurement range of V CE , where

[0123] V M = V SE = V CE - V DS ≈ V CE (16)

[0124] V G*S_ON = V O - V M ≈ V O (17)

[0125] where V M is the voltage output from VCC to the subsequent circuit. In addition, R1 is used to help reduce voltage spikes and oscillations during the switching transients of the device under test and is usually set to 10 Ω.

[0126] The purpose of the HSP conversion circuit is to convert V CE into the voltage change rate dV CE / dt and hold it during the second stage of turn-off. It mainly consists of a buffer, a comparator, a proportional differentiator, and a sample and hold (SHA). The theoretical output waveforms of the above parts are shown in Fig. 4(b). The buffer is mainly used to isolate the pre-stage VCC circuit and the post-stage HSP conversion circuit and eliminate their mutual influence. The output of the buffer is approximately equal to the output of VCC, i.e., V M . The proportional differentiator converts the voltage into a voltage slope, and its output is

[0127]

[0128] where K D is the ratio of the differentiator. In addition, the role of the comparator is to connect to the buffer to provide a trigger signal for the sample and hold. When VM Less than V REF When it is less than V, the output of the comparator S is high level, and the sample and hold circuit can track the signal of V in real time. K Once V M is greater than V REF , S immediately becomes low level, making the sample and hold circuit enter the hold mode. Therefore, at this time, V K can be maintained at a stable value until the next switching cycle. To ensure that V K can be maintained in the second stage, V REF should satisfy

[0129] V GP - V TH ≤V REF +(t AD + t PD ) × H SP ≤V KNEE (19)

[0130] where t AD is the effective aperture delay of the sample and hold circuit, and t PD is the propagation delay of the comparator. The above delays will affect the hold time of V K , thereby affecting the value of the extracted HSP. After a certain scaling, the inequality (19) can be transformed into

[0131]

[0132] The above inequality can be regarded as the selection criterion of V REF . Finally, the output of the sample and hold circuit can be transmitted to the host computer through the analog-to-digital converter (ADC) as the characteristic parameter of the chip-level open-circuit failure.

[0133] Taking the IGBT module of Infineon FF150R12ME3G as an example, the specific implementation steps of the method of the present invention are described.

[0134] Step 1: Design the VCC circuit. Select the clamping NMOS and component parameters in the VCC circuit according to the formulas (12)-(17) and the parameters of the device under test, as shown in Table 2. The measurement ranges of V G*S and V CE are 0-13V and 0-10V respectively, ensuring the measurement safety.

[0135] Table 2 Parameter design and measurement range of the VCC circuit

[0136]

[0137]

[0138] Step 2: Design the HSP conversion circuit. Determine the specific parameters of the circuit according to Formulas (18)-(20), as shown in Table 3.

[0139] Table 3 Parameters and Design Basis of the HSP Conversion Circuit

[0140]

[0141] Step 3: Design the PCB circuit board for on-line monitoring, as Figure 5 shown. The total area of the PCB board is 5 cm * 4.7 cm. In the double-pulse test, the measured waveform of the designed PCB is as Figure 6 shown, which is basically the same as the theoretical waveform in Fig. 4(b), indicating that the designed circuit board can achieve the predetermined function.

[0142] Step 4: Design the acquisition program of the ADC. Convert the analog quantity at the output end of the PCB into a digital quantity and transfer it to the upper computer in each switching cycle.

[0143] Step 5: Connect the on-line monitoring board in parallel with the device under test, and extract the HSP in real time under the inverter working condition. Finally, the measurement result of the oscilloscope is as Figure 7 shown. When the direction of I L is negative, the current flows into the device under test, and the output at this time is the monitored HSP. The results show that in the application of high-frequency inverters, the proposed monitoring circuit can accurately extract the HSP. In addition, the HSP digital quantities of power modules in different health states extracted are as Figure 8 shown. Although the changes of T j and I L in the inverter are large, as long as a single chip has an open circuit, the HSP will have an obvious mutation, and the fault signal can be immediately transmitted to the upper computer for fault determination.

[0144] The above content is only to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. An on-line monitoring circuit for open-circuit faults at the chip level of a multi-chip IGBT module, characterized in that, It includes a VCC circuit and an HSP conversion circuit. The output terminal of the VCC circuit is connected to the input terminal of the HSP conversion circuit, and the output terminal of the HSP conversion circuit is connected to a host computer through an analog-to-digital converter; The VCC circuit includes a clamping NMOS, a bidirectional voltage regulator diode, a filter capacitor, an auxiliary voltage source, a protection resistor R1, and a protection resistor R2. Among them, the protection resistor R2 is connected in parallel with the drain-source of the clamping NMOS. The source of the clamping NMOS is connected in series with the bidirectional voltage regulator diode. The bidirectional voltage regulator diode is connected in series with the protection resistor R1. The drain of the NMOS and the other end of the protection resistor R1 are connected in parallel with the device under test. The filter capacitor and the auxiliary voltage source are connected in parallel and then connected to the gate of the NMOS and the other end of the protection resistor R1; The HSP conversion circuit includes a buffer, a comparator, a proportional differentiator, and a sample and hold circuit. Among them, the output terminal of the buffer is respectively connected to the proportional differentiator and the comparator. The output terminal of the proportional differentiator is connected to the input terminal of the sample and hold circuit. The comparator is connected to the trigger signal terminal of the sample and hold circuit. The output terminal of the sample and hold circuit is connected to an external analog-to-digital converter; The output terminal of the VCC circuit is the source of the clamping NMOS, which is connected to the input terminal of the buffer in the HSP conversion circuit.

2. An online monitoring method for chip-level open-circuit faults of a multi-chip IGBT module, which uses the online monitoring circuit described in claim 1, is characterized in that, It includes: When the device under test is in the off state, the VCC circuit is used to isolate the high voltage to prevent the influence of the higher bus voltage on the HSP conversion circuit; Use the HSP conversion circuit to convert the collector-emitter voltage V of the device under test CE into the voltage change rate dV CE / dt; The voltage change rate dV CE / dt is output through the sample-and-hold circuit and transmitted to the host computer through the analog-to-digital converter to be used as a characteristic parameter for open-circuit faults at the chip level.

3. An online monitoring method for chip-level open-circuit faults of a multi-chip IGBT module according to claim 2, characterized in that, When the device under test is in the off state, the collector-emitter voltage V CE of the device under test during the rising process is divided into the following three stages: In the first stage, the gate-emitter voltage V GE drops to the Miller plateau voltage V GP ; In the second stage, the gate-emitter voltage V GE is maintained to the Miller plateau voltage V GP ; In the third stage, the collector-emitter voltage V CE rises to the knee voltage V KNEE .

4. The on-line monitoring method for chip-level open-circuit faults of a multi-chip IGBT module according to claim 3, characterized in that, In the first stage, the gate-emitter voltage V GE drops to the Miller plateau voltage V GP , satisfying the following equation: V GE ≤ V GP -V TH Where V TH is the threshold voltage of a single IGBT chip in the device under test. According to the equivalent circuit, the gate-emitter voltage V GE is expressed as: where τ ies =(C GE +C OXD )(nR G +R gin ), V GG_ON and V GG_OFF are the turn-on and turn-off voltages of the gate drive, C GE is the gate-emitter capacitance, C OXD is the overlap oxide capacitance, n is the number of parallel IGBT chips in the device under test, R G is the external gate resistance of the overall IGBT device under test, R gin is the internal gate resistance of a single IGBT chip, and the relationship between the collector-emitter voltage V CE and the gate-emitter voltage V GE is approximately expressed as: where I L is the load current, K T is a constant related to the structure of the device under test. Correspondingly, dV CE / dt is expressed as:

5. The on-line monitoring method for the chip-level open-circuit fault of a multi-chip IGBT module according to claim 4, characterized in that, In the second stage, the gate-emitter voltage V GE is maintained to the Miller plateau voltage V GP , and in this stage, dV CE / dt is expressed as: Among them, g m is the transconductance of a single IGBT chip in the device under test; Therefore where τ OXD = C OXD (nR G + R gin ).

6. The online monitoring method for chip-level open-circuit faults of a multi-chip IGBT module according to claim 5, characterized in that, In the third stage, the collector-emitter voltage V CE rises to the knee voltage V KNEE , and in this stage: Among them, A g is the gate overlap area of a single IGBT chip in the device under test, N B is the base doping concentration, q is the unit electron charge, ε si is the dielectric constant of silicon, and the closed-form expression of dV CE / dt in this stage is as follows: where τ GC = C GC (nR G + R gin ), C O is the charge extraction capacitance, i.e., where v sat is the carrier saturation velocity, and p0 is the excess carrier density in the conducting state of the anode PN junction.

7. An online monitoring method for chip-level open-circuit faults of a multi-chip IGBT module according to claim 6, characterized in that, When the device under test is in the off state, the VCC circuit is used to isolate the high voltage to prevent the influence of the higher bus voltage on the HSP conversion circuit, specifically: When the device under test is in the off state, its collector-emitter voltage V CE bus voltage V DC , the voltage V SE between the NMOS source and the emitter of the device under test is clamped to the zener voltage V Z of the two-way zener diode D Z , and the protection resistor R2 is determined by the following formula: where I DSS is the drain-source leakage current of the clamping NMOS. Therefore, the gate-source voltage V G * S of the clamping NMOS is clamped to: V G*S_OFF = V O - V SE = V O - V Z where V O is an external voltage source. When the device under test is turned on, V SE decreases with the collector - emitter voltage V CE of the device under test, resulting in an increase in the gate - source voltage V G*S of the NMOS. After the clamping NMOS turns to the linear operating region, it starts to be in a low - impedance state, and at this time, it satisfies: Among them is the threshold voltage of the clamping NMOS. Since V DS = V CE - V SE , the above formula is rearranged as: The above inequality determines the exact measurement range of V CE at this time, the following conditions are satisfied: V M = V SE = V CE -V DS ≈V CE V G*S_ON = V O -V M ≈V O Among which V M is the voltage output from the VCC circuit to the HSP conversion circuit.

8. The on-line monitoring method for chip-level open-circuit faults of a multi-chip IGBT module according to claim 6, characterized in that The collector-emitter voltage V of the device under test is converted into a voltage change rate dV CE / dt by the HSP conversion circuit and then maintained in the second stage of turn-off, specifically as follows: CE ​ The output of the buffer is equal to the output V of the VCC circuit M , and the proportional differentiator converts the voltage into a voltage slope, and its output is: where K D is the ratio of the proportional differentiator. When the output V of the VCC circuit M is less than the reference voltage V REF , the output of the comparator is high level, and the sample and hold circuit can track the signal of V K in real time. Once the output V of the VCC circuit M is greater than V REF , the comparator immediately becomes low level, making the sample and hold circuit enter the hold mode. Therefore, at this time, V K can be maintained at a stable value until the next switching cycle. To ensure that V K is maintained in the second stage, V REF should satisfy: V GP -V TH ≤V REF +(t AD +t PD )×H SP ≤V KNEE where t AD is the effective aperture delay of the sample and hold circuit, and t PD is the propagation delay of the comparator. The above equation can be transformed into: The above inequality is regarded as the selection criterion for V REF Finally, the output of the sample-and-hold circuit is transmitted to the host computer through the analog-to-digital converter and used as the characteristic parameter of the open-circuit fault at the chip level.

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