On-board Receiver for High-Dynamic Projectile Carriers

Abstract

The present application discloses an on-board receiver for a high-dynamic projectile carrier, which is characterized in that it includes: a first receiving antenna arranged at a first position of the high-dynamic projectile carrier; electrically connected to the first receiving antenna are: a first radio frequency unit, a first analog-to-digital signal sampling unit, a first pseudo-code generator, a first correlator, and a first frequency discriminator; a second receiving antenna arranged at a second position of the high-dynamic projectile carrier that is centrosymmetric with the first position; the internal structure of the second receiving antenna is basically the same as that of the first receiving antenna; a code loop electrically connected to a DLL discriminator; an FLL discriminator electrically connected to the first frequency discriminator and a second frequency discriminator; a frequency-locking loop electrically connected to the FLL discriminator. In this way, the continuity of the signal is ensured and the influence of rotation is eliminated when the receiver rotates, making the signal received by the receiver more stable.

Description

Technical Field

[0001] This application relates to the technical field of navigation signal acquisition, and particularly to an on-board receiver for a high-dynamic projectile carrier. Background Art

[0002] In the global navigation satellite system, the reception of satellite signals is an important research direction. At present, in order to ensure the coverage of received signals, many signal receivers use dual antennas to ensure stable signal reception.

[0003] In the prior art, data reception problems are usually processed by directly combining radio frequencies. After passing through a low-noise amplifier, a combiner is used to directly combine the signals and then send them to a radio frequency processing unit for processing. Such a signal reception method is simple and direct, and the signals are basically continuous.

[0004] However, in the process of implementing the prior art, the inventors found that:

[0005] The baseband of the receiver after combining cannot achieve accurate phase tracking, cannot achieve high-precision post-processing, and at the same time, the signal will cause a 3dB loss. There will be some blind spots within the entire rotation range, resulting in too long a signal interruption time and signal loss lock at low speeds. In the case of low rotation speeds, due to the slow rotation, using a single antenna causes too long an invisible time of the signal, so non-continuous reception causes certain difficulties.

[0006] Therefore, in order to compensate for signal visibility and offset the influence of rotation on the received signal, the embodiments of this application provide a related technical solution for an on-board receiver for a high-dynamic projectile carrier to solve the problem of stable signal reception under high-speed rotation conditions. Summary of the Invention

[0007] The embodiments of this application provide a related technical solution for an on-board receiver for a high-dynamic projectile carrier to solve the technical problem of unstable signal reception of existing signal receiving devices under high-speed rotation conditions.

[0008] An on-board receiver for a high-dynamic projectile carrier provided by this application includes:

[0009] A first receiving antenna arranged at a first position of the high-dynamic projectile carrier;

[0010] A first radio frequency unit electrically connected to the first receiving antenna;

[0011] A first analog-to-digital signal sampling unit electrically connected to the first radio frequency unit;

[0012] A first pseudo-code generator electrically connected to the first analog-to-digital signal sampling unit;

[0013] The first correlator electrically connected to the first analog-to-digital signal sampling unit;

[0014] The first frequency discriminator electrically connected to the first correlator;

[0015] The second receiving antenna arranged at the second position that is centrosymmetric with the first position center on the high-dynamic projectile carrier;

[0016] The second radio frequency unit electrically connected to the second receiving antenna;

[0017] The second analog-to-digital signal sampling unit electrically connected to the second radio frequency unit;

[0018] The second pseudo-code generator electrically connected to the second analog-to-digital signal sampling unit;

[0019] The second correlator electrically connected to the second analog-to-digital signal sampling unit;

[0020] The second frequency discriminator electrically connected to the second correlator;

[0021] The DLL discriminator connected to the first pseudo-code generator and the second pseudo-code generator;

[0022] The code loop electrically connected to the DLL discriminator;

[0023] The FLL discriminator electrically connected to the first frequency discriminator and the second frequency discriminator;

[0024] The frequency-locked loop electrically connected to the FLL discriminator.

[0025] Furthermore, the first receiving antenna and the second receiving antenna are respectively attached to the surface of the high-dynamic projectile carrier.

[0026] Furthermore, the on-projectile receiver further includes a first signal strength detection module electrically connected to the first frequency discriminator and a second signal strength detection module electrically connected to the second frequency discriminator, so as to determine the synthesis strategy of the FLL discriminator according to the signal strength.

[0027] Furthermore, the on-projectile receiver further includes:

[0028] The first down-converter directly electrically connected to the first analog-to-digital signal sampling unit;

[0029] The first early minus late correlator connected to both the first down-converter and the first pseudo-code generator.

[0030] Furthermore, the on-projectile receiver includes a first pseudo-code processing channel configured according to the following structure:

[0031] The first down-converter is electrically connected to the input port of the first early minus late correlator;

[0032] The first pseudo-code generator is electrically connected to the input port of the first early-minus-late correlator;

[0033] The output port of the first early-minus-late correlator is connected to the DLL discriminator;

[0034] The DLL discriminator is electrically connected to the code loop.

[0035] Furthermore, the on-board receiver further includes:

[0036] A second down-converter directly electrically connected to the second analog-to-digital signal sampling unit;

[0037] A second early-minus-late correlator connected to both the second down-converter and the second pseudo-code generator.

[0038] Furthermore, the on-board receiver includes a second pseudo-code processing channel configured as follows:

[0039] The second down-converter is electrically connected to the input port of the second early-minus-late correlator;

[0040] The second pseudo-code generator is electrically connected to the input port of the second early-minus-late correlator;

[0041] The output port of the second early-minus-late correlator is connected to the DLL discriminator;

[0042] The DLL discriminator is electrically connected to the code loop.

[0043] Furthermore, the on-board receiver further includes a first down-converter directly electrically connected to the first analog-to-digital signal sampling unit;

[0044] The on-board receiver further includes a first frequency processing channel configured as follows:

[0045] The first down-converter is electrically connected to the first correlator;

[0046] The first correlator is electrically connected to the first frequency discriminator;

[0047] The first frequency discriminator is electrically connected to the FLL discriminator;

[0048] The FLL discriminator is electrically connected to the frequency-locked loop.

[0049] Furthermore, the on-board receiver further includes a second down-converter directly electrically connected to the second analog-to-digital signal sampling unit;

[0050] The on-board receiver further includes a second frequency processing channel configured as follows:

[0051] The second down-converter is electrically connected to the second correlator;

[0052] The second correlator is electrically connected to the second frequency discriminator;

[0053] The second frequency discriminator is electrically connected to the FLL discriminator;

[0054] The FLL discriminator is electrically connected to the frequency-locked loop.

[0055] Further, the FLL discriminator is configured to:

[0056] When the signal intensities of the first frequency processing channel and the second frequency processing channel are greater than a predetermined threshold, the FLL discriminator outputs the average Doppler.

[0057] The technical solution provided by the embodiment of the present application has at least the following beneficial effects:

[0058] Through the design scheme of dual-antenna synthesis, the antennas are surface-mounted at symmetric positions to receive satellite signals, enabling the on-board receiver of the projectile to adapt to low-rotation applications, so as to solve the problem of signal reception with excessive centripetal acceleration during rotation and ensure the stability of signal reception. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments and descriptions thereof of the present application are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0060] Figure 1 is the internal electrical connection structure diagram of the on-board receiver provided by the embodiment of the present application;

[0061] Figure 2 is the receiver block diagram of the dual-antenna system provided by the embodiment of the present application;

[0062] Figure 3 is the design principle block diagram of the high-precision ballistic measurement verification receiver provided by the embodiment of the present application;

[0063] Figure 4 is the hardware block diagram of the on-board positioning and attitude measurement integrated receiver provided by the embodiment of the present application;

[0064] Figure 5 is the closed-loop control system block diagram provided by the embodiment of the present application;

[0065] Figure 6 is the physical implementation structure diagram of the adaptive bandwidth frequency-locked loop provided by the embodiment of the present application.

[0066] 100 On-board receiver for high-dynamic projectile carrier

[0067] 11 First receiving antenna

[0068] 111 First RF unit

[0069] 112 First analog-to-digital signal sampling unit

[0070] 113 First pseudo-code generator

[0071] 114 First correlator

[0072] 115 First frequency discriminator

[0073] 116 First signal strength detection module

[0074] 117 First down-converter

[0075] 118 First early minus late correlator

[0076] 12 Second receiving antenna

[0077] 121 Second RF unit

[0078] 122 Second analog-to-digital signal sampling unit

[0079] 123 Second pseudo-code generator

[0080] 124 Second correlator

[0081] 125 Second frequency discriminator

[0082] 126 Second signal strength detection module

[0083] 127 Second down-converter

[0084] 128 Second early minus late correlator

[0085] 13 DLL discriminator

[0086] 14 Code loop

[0087] 15 FLL discriminator

[0088] 16 Frequency-locked loop Detailed implementation manners

[0089] To make the objectives, technical solutions and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments of this application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0090] After the on-board satellite navigation receiving system is powered on and starts up, it completes equipment initialization and self-check status confirmation. After the on-board receiver is fired out of the barrel, it quickly completes receiver acquisition and tracking positioning, and simultaneously saves pseudo-range and carrier observation data. The functions such as acquisition and tracking positioning of the receiver are mainly realized by the satellite system. The satellite system sends positioning signals to the on-board receiver of the projectile carrier, and the on-board receiver receives satellite signals through an antenna installed on its carrier. However, due to the high-speed movement and rotation of the projectile, it will affect the on-board receiver antenna's reception of satellite signals. Therefore, in the global navigation satellite system, the reception of satellite signals is an important research direction. Currently, in order to ensure the coverage of received signals, many signal receiving ends use dual antennas to ensure stable signal reception. Usually, the receiver uses radio frequency direct combining to process data reception problems. After the signal sent by the satellite passes through the low-noise amplifier, it is combined by a combiner and directly sent to the radio frequency unit of the receiver for subsequent processing. Although this method can ensure the basic continuity of the signal, there are defects: the baseband of the combined receiver cannot achieve accurate phase tracking, high-precision post-processing cannot be achieved, and at the same time, the signal will cause a 3dB loss, and there will be some blind spots within the entire rotation range, resulting in too long signal interruption time and signal loss lock at low speeds. The relevant value combination is for combination after entering the baseband processing. In the case of low rotation speed, due to the slow rotation, using a single antenna causes too long signal invisible time, which causes certain difficulties for continuous signal reception.

[0091] In order to solve the problem of signal reception with excessive centripetal acceleration in the case of rotation and ensure the continuity and stability of the signal, this application adopts a scheme of combining dual antennas.

[0092] Specifically, please refer to Figure 1 and Figure 2 This application provides an on-board receiver 100 for a high-dynamic projectile carrier, including:

[0093] A first receiving antenna 11 arranged at the first position of the high-dynamic projectile carrier;

[0094] A first radio frequency unit 111 electrically connected to the first receiving antenna 11;

[0095] A first analog-to-digital signal sampling unit 112 electrically connected to the first radio frequency unit 111;

[0096] A first pseudo-code generator 113 electrically connected to the first analog-to-digital signal sampling unit 112;

[0097] A first correlator 114 electrically connected to the first analog-to-digital signal sampling unit 112;

[0098] A first frequency discriminator 115 electrically connected to the first correlator 114;

[0099] A second receiving antenna 12 disposed at a second position that is centrosymmetric with the high-dynamic projectile carrier and the center of the first position;

[0100] A second radio frequency unit 121 electrically connected to the second receiving antenna 12;

[0101] A second analog-to-digital signal sampling unit 122 electrically connected to the second radio frequency unit 121;

[0102] A second pseudo-code generator 123 electrically connected to the second analog-to-digital signal sampling unit 122;

[0103] A second correlator 124 electrically connected to the second analog-to-digital signal sampling unit 122;

[0104] A second frequency discriminator 125 electrically connected to the second correlator 124;

[0105] A DLL discriminator 13 connected to the first pseudo-code generator 113 and the second pseudo-code generator 123;

[0106] A code loop 14 electrically connected to the DLL discriminator 13;

[0107] [[ID=2B]]An FLL discriminator 15 electrically connected to the first frequency discriminator 115 and the second frequency discriminator 125;

[0108] A frequency-locked loop 16 electrically connected to the FLL discriminator 15.

[0109] It can be understood that the on-projectile receiver mainly receives satellite signals through the antenna, and the antenna continues to transmit the signals. Moreover, the projectile is in a high-speed moving state. Therefore, there is a certain electrical connection between the antenna of the receiver and the internal structure of the receiver to achieve the transmission of signals to the navigation device on the projectile carrier within a short time and improve the accuracy of the projectile to capture the target.

[0110] Specifically, the internal structure of the dual-antenna receiver provided in the embodiments of the present application is basically the same as that of a conventional receiver. The first receiving antenna 11 and the second receiving antenna 12 are symmetrically arranged on the surface of the projectile carrier with the projectile carrier as the center, that is, the first receiving antenna 11 is disposed at the first position of the projectile carrier, and the second receiving antenna 12 is disposed at the second position of the projectile carrier. When the satellite sends a signal to the projectile, the first receiving antenna 11 and the second receiving antenna 12 will simultaneously receive the signal sent by the satellite. The first receiving antenna 11 transmits the received signal to the first radio frequency unit 111 electrically connected thereto. Similarly, the second receiving antenna 12 will simultaneously transmit the received signal to the second radio frequency unit 121 connected thereto. In this way, when the on-projectile receiver receives the signal sent by the satellite, it can realize the signal processing under the rotation of the projectile through the dual-antenna processing channel.

[0111] It is understandable that the function of the Radio Remote Unit (RRU) is to convert the baseband optical signal into a radio frequency signal at the remote end. In this embodiment, that is, the satellite signals received by the first receiving antenna 11 and the second receiving antenna 12 are converted into an electric wave with a certain transmission frequency, namely a radio frequency signal, by the first radio frequency unit 111 and the second radio frequency unit 121.

[0112] Furthermore, after the first radio frequency unit 111 converts the satellite signal into a radio frequency signal, it will continue to send this radio frequency signal to the first analog-to-digital signal sampling unit 112 electrically connected to the first radio frequency unit 111. Similarly, after the second radio frequency unit 121 converts the satellite signal into a radio frequency signal, it will continue to send this radio frequency signal to the second analog-to-digital signal sampling unit 122 electrically connected to the second radio frequency unit 121. In this embodiment, an analog-to-digital converter, i.e., an A / D converter, is used as the analog-to-digital signal sampling unit to collect the radio frequency signals sent by the radio frequency unit.

[0113] It is understandable that an analog-to-digital converter generally refers to an electronic component that converts an analog signal into a digital signal. In the embodiment provided in this application, the analog-to-digital converter will convert the radio frequency signal sent by the radio frequency unit into a digital signal and continue to send it.

[0114] Furthermore, in the embodiment provided in this application, the first pseudo-code generator 113 and the first correlator 114 are electrically connected to the first analog-to-digital signal sampling unit 112 respectively to receive the digital signals sent by the first analog-to-digital signal sampling unit 112. Similarly, the second pseudo-code generator 123 and the second correlator 124 are electrically connected to the second analog-to-digital signal sampling unit 122 respectively to receive the digital signals sent by the second analog-to-digital signal sampling unit 122.

[0115] It is understandable that since the modern war pattern has developed towards the form of information warfare. In modern warfare, if the communication method of one's own side is cracked, it will be subject to signal interference from the enemy at any time. In this embodiment, if the satellite signal received by the projectile is cracked, the enemy will enter a defensive posture at the fastest speed and even send interference signals to the projectile, making it impossible for the projectile to accurately capture the target. Therefore, a pseudo-code generator is also provided in the internal structure of the on-board receiver in this embodiment. The pseudo-code generator has some statistical characteristics similar to random signals. This kind of signal has certain regularity, randomness, autocorrelation and cross-correlation, and is easy to generate and replicate. It is a common and important pseudo-random sequence in secure communication. In short, in this embodiment, the main function of the pseudo-code generator is to hide the real signal sent by the satellite to the projectile and generate a camouflage signal to deceive the enemy.

[0116] Specifically, when the first pseudo-code generator 113 receives the issued digital signal, it encrypts the digital signal using a pseudo-random sequence, so that the encrypted signal has the characteristics of pseudo-noise while carrying the original information, in order to achieve the purpose of hiding information during signal transmission. Similarly, the second pseudo-code generator 123 also encrypts the received digital signal in the same way.

[0117] Further, the digital signals encrypted by the first pseudo-code generator 113 and the second pseudo-code generator 123 are sent to the DLL discriminator 13 which is electrically connected to both the first pseudo-code generator 113 and the second pseudo-code generator 123 at the same time. The DLL discriminator 13 decrypts the encrypted data using the same sequence as that used by the first pseudo-code generator 113 and the second pseudo-code generator 123 to restore the original signal. In this way, by applying the pseudo-code generator and the DLL discriminator 13, the confidentiality and anti-interception ability of communication will be greatly improved.

[0118] Further, the DLL discriminator 13 is electrically connected to the code loop 14.

[0119] It can be understood that the code loop, whose full name is the code loop tracking loop, its main function is to keep the phase of the replicated C / A code consistent with that of the received C / A code, so as to obtain the code phase and its pseudo-range measurement value of the received signal. The code tracking loop is used to ensure accurate alignment with the position of the input signal C / A code. Usually, a delay locked loop (DLL), also known as a code early-late tracking loop, is used. In this loop, the pseudo-code generator generates three signals: early, prompt, and late, which are each 0.5 C / A code elements apart, and are respectively correlated with the input signal after removing the carrier. By observing these three correlation values, the forward and backward movement of the local C / A code is judged. In order to reduce the requirement of the tracking loop for the alignment degree of the local carrier phase, the code loop is usually designed in the form of two orthogonal I and Q channels.

[0120] Further, while the first analog-to-digital signal sampling unit 112 and the second analog-to-digital signal sampling unit 122 issue the digital signal to the first pseudo-code generator 113 and the second pseudo-code generator 123, they also issue the digital signal to the first correlator 114 and the second correlator 124 respectively.

[0121] It can be understood that the correlation receiver, simply referred to as the correlator, is a tool that extracts useful signals from interference and noise by using the correlation characteristics of signals. The satellite transmits a spread-spectrum BPSK signal, and the receiving end can only restore the baseband signal after despreading and demodulation, and to complete these tasks, the correlator is required. The correlator performs correlation processing on the local reproduced carrier frequency and C / A code with the input digital intermediate frequency, removes the carrier frequency and C / A code signals, and obtains various measurement data and status data for calculating the pseudo-range and navigation message.

[0122] Specifically, in the embodiments of the present application, the first analog-to-digital signal sampling unit 112 and the second analog-to-digital signal sampling unit 122 send the initial digital signals without any processing to the first correlator 114 and the second correlator 124, in order to facilitate the subsequent on-board receiver to collect more accurate data information. The first correlator 114 and the second correlator 124 extract the initial signals from interference and noise, and perform despreading and demodulation to restore the received signals into the original baseband signals, so that the on-board receiver can accurately locate after identification.

[0123] Furthermore, the baseband signals despread and demodulated by the first correlator 114 and the second correlator 124 are continuously sent to the first frequency discriminator 115 electrically connected to the first correlator 114 and the second frequency discriminator 125 electrically connected to the second correlator 124, which are used to discriminate the frequency difference between the signals input by their respective antennas and the local carrier. And the discrimination results are simultaneously sent to the FLL discriminator 15 electrically connected to the first frequency discriminator 115 and the second frequency discriminator 125. The FLL discriminator 15 sends the final processing results to the automatic frequency fine-tuning circuit with dynamic operation, that is, the frequency-locked loop.

[0124] It can be understood that the code loop and the carrier loop in a conventional GNSS receiver are two necessary loops for tracking satellite navigation signals. The stable tracking of satellite navigation signals is achieved through the pseudo-code tracking loop and the carrier tracking loop. These two loops are interdependent and restrictive. One is for the synchronization of the pseudo-code, and the other is for the synchronization of the carrier frequency and the carrier phase. The loop bandwidth of the GNSS receiver is related to the signal-to-noise ratio of the GNSS signal, the dynamic performance of the carrier, and the hardware performance. Therefore, when designing the loop, the various parameters of the loop are very important.

[0125] Specifically, the code loop of the on-board receiver in this embodiment belongs to the tracking loop with relatively low accuracy among the two loops, and its tracking error is about meter level when converted to distance. The accuracy of the frequency-locked loop is much higher than that of the code loop, and its tracking accuracy is about millimeter level when converted to distance. Therefore, its tracking threshold is greater than that of the pseudo-code tracking loop. Generally, in a receiver, the frequency-locked loop is used to assist the tracking of the code loop, so as to achieve the purpose of eliminating dynamic stress. Therefore, in the design of high-dynamic signal tracking, the focus is on the carrier loop, and the various errors of the frequency-locked loop are taken as the key points of analysis. The main sources of tracking errors of the frequency-locked loop mainly include phase jitter error and dynamic stress error. The main sources of phase jitter error mainly include thermal noise, oscillator noise caused by vibration, and Allan deviation. Since these three error sources are not correlated with each other, the phase jitter error is the square root of the sum of the squares of these uncorrelated error sources. For a GNSS receiver, the tracking threshold of the frequency-locked loop is set as: the 3σ tracking error does not exceed 1 / 4 of the range of the phase discriminator. Therefore, in the case of data modulation, the empirical threshold for the frequency-locked loop to lock is:

[0126]

[0127] Wherein, σ PLL is the PLL tracking error, σ T is the thermal noise, σ v is the oscillator jitter, θ A is the oscillator jitter caused by the Allan deviation, θ e is the dynamic stress error. The above are the error terms that affect the frequency-locked loop.

[0128] Under high-dynamic conditions and a certain carrier-to-noise ratio, in order to better maintain the signal tracking and locking ability of the frequency-locked loop, an inertial navigation assistance method can be adopted to cancel the carrier dynamic information and narrow the loop tracking bandwidth.

[0129] It should be noted that adopting an adaptive bandwidth loop design is a necessary means, but the auxiliary accuracy, time synchronization characteristics, and the impact on the dynamic response of the entire loop all need to be analyzed in depth. The difficulty of the adaptive loop design lies in how to adaptively adjust the receiver loop parameters according to the dynamic stress. Under dynamic conditions, in order to track the satellite signal, the receiver loop must be designed wide enough, and in order to ensure the signal tracking accuracy, the loop bandwidth of the receiver must be narrow enough. The loop bandwidth required by the dynamic performance and the loop bandwidth required by the noise are mutually restrictive. For the tracking loop noise, the narrower the bandwidth, the higher the tracking accuracy. Therefore, the embodiments of the present application can effectively solve this problem by assisting the tracking loop of the satellite navigation receiver. The code loop adopts a second-order code loop assisted by the carrier, and the carrier loop adopts an adaptive third-order frequency-locked loop architecture, which fully considers the various influences of the loop adapting to dynamic characteristic changes.

[0130] The frequency expression of the loop under dynamic conditions is as follows:

[0131]

[0132] Wherein, f0 is the intermediate frequency; Δf is the Doppler frequency shift, with the unit of Hz; df / dt is the Doppler velocity variable, with the unit of Hz / s; d 2 f / dt 2 is the Doppler acceleration variable, with the unit of Hz / s 2 . The Doppler frequency shift is obtained from the velocity information provided by the inertial navigation, the Doppler frequency shift velocity is obtained from the acceleration information, and the Doppler frequency shift acceleration is treated as a noise term. Among them, the Δf term is related to the velocity error, and the df / dt term is related to the acceleration error.

[0133] When the adaptive loop filter design calculates the Doppler using the corrected position and speed to assist the receiver loop, the receiver loop can be described as a closed-loop control system block diagram. Please refer to Figure 5 。

[0134] Among them, φ r (s) is the reference input signal, is the external phase noise, is the phase error output by the phase detector, is the loop filter of the frequency-locked loop, is the equivalent frequency error after filtering the phase error of the phase detector, and is the output signal of the voltage-controlled oscillator. It can be seen from the above figure that the loop output phase can be expressed as:

[0135] φ PLL (s) = H1(s)φ r (s) + H2(s)w φ (s) + H3(s)δf ext (s)

[0136]

[0137]

[0138]

[0139] The loop tracking error caused by the external frequency estimation deviation can be expressed as:

[0140] δf PLL (s) = -H2(s)δf ext (s)

[0141] According to the above two equations, when the bandwidth a INS is relatively large, the phase output signal and the reference input signal are linearly related. According to the above equation, the loop tracking error is only related to the external frequency assistance deviation, that is, only the speed deviation estimated by the navigation filter and the clock frequency deviation affect the loop tracking performance.

[0142] Please refer to Figure 6 , the embodiment of the present application provides a physical implementation structure of an adaptive bandwidth frequency-locked loop. The entire work process is as follows: After the satellite signal is down-converted and sampled, the signal completes carrier stripping, and is multiplied by the in-phase and quadrature carrier signals generated locally. The parameters of the amplitude signal are continuously adjusted according to the estimated Doppler frequency deviation and the carrier phase of the loop filter, so as to achieve tracking of the input signal. Among them, the estimated Doppler frequency is mainly used to cancel the influence of the carrier dynamic performance, and the carrier phase error of the loop filter is mainly used to track the noise error caused by thermal noise and clock error.

[0143] Through the above analysis, the high-precision measurement of the on-board receiver mainly depends on the data quality of the on-board receiver. The on-board differential positioning technology is pseudo-range differential, without the need to fix the integer ambiguity, thus greatly improving the positioning reliability. The carrier data is used to smooth the pseudo-range to reduce noise.

[0144] Furthermore, the first receiving antenna 11 and the second receiving antenna 12 are respectively attached to the surface of the high-dynamic projectile carrier.

[0145] Specifically, the receiving antenna adopted in the embodiment provided by the present application is a microstrip antenna, which can be patch-mounted on the projectile body, and the two are installed with a 180-degree difference to form a complementarity of the signal reception interval.

[0146] It can be understood that the rise of microwave integration technology and new manufacturing processes has promoted the development of microstrip antennas. The structure of a microstrip antenna generally consists of a dielectric substrate, a radiator, and a ground plane. The thickness of the dielectric substrate is much smaller than the wavelength. The metal thin layer at the bottom of the substrate is connected to the ground plane, and a metal thin layer with a specific shape is fabricated on the front surface through a photolithography process as the radiator. Compared with traditional antennas, microstrip antennas not only have the advantages of small size, light weight, low profile, easy conformal shaping, but also are easy to integrate, low cost, suitable for mass production, and also have the advantages of diverse electrical performance.

[0147] Specifically, there are many types of microstrip antennas. The microstrip patch antenna is adopted in the embodiment of the present application. This antenna is composed of a dielectric substrate, a radiation patch, and a ground plane, and is a common form of microstrip antenna. The shape of the radiation patch unit is diverse. Whether it is a regular rectangle, polygon, or an irregular ellipse, ring, or sector, etc., can be used as the radiation element. The maximum radiation direction of this type of microstrip antenna is generally in the broadside direction, that is, perpendicular to the substrate. In this embodiment, two identical microstrip patch antennas, namely the first receiving antenna 11 and the second receiving antenna 12, are attached to the same circumference on the surface of the high-dynamic projectile carrier, and the installation directions of the first receiving antenna 11 and the second receiving antenna 12 are opposite, that is, the two are installed with a 180-degree difference, which not only forms a complementarity of the signal reception interval, but also can cancel the equal and opposite Doppler effects generated by the rotation of the two.

[0148] Furthermore, the on-board receiver further includes a first signal intensity detection module 116 electrically connected to the first frequency discriminator 115 and a second signal intensity detection module 126 electrically connected to the second frequency discriminator 125, so as to determine the synthesis strategy of the FLL discriminator 15 according to the signal intensity.

[0149] Specifically, the on - missile receiver with a dual - antenna synthesis structure in this embodiment is the first signal strength detection module 116 and the second signal strength detection module 126 set for the two groups of processing channels corresponding to the first receiving antenna 11 and the second receiving antenna 12. The functions of these two groups of signal strength detection modules are as follows: Before the first frequency discriminator 115 and the second frequency discriminator 125 send the discrimination results of the frequency differences between the signals input by their respective antennas and the local carrier to the FLL discriminator, the local pseudo - code and carrier of the dual - antenna processing channels are updated through the discrimination results of the two, so as to determine the synthesis strategy of the two - path frequency discriminators, that is, the FLL discriminator, according to the signal strength.

[0150] It can be understood that since the two antennas are pasted on the missile body, the Doppler effects caused by their rotation are equal in magnitude and opposite in direction. Therefore, the average method can be used to eliminate the Doppler effect. When the signal strengths of both paths are greater than the predetermined threshold, the frequency discrimination values corresponding to the two antennas can be used to update the local pseudo - code and carrier of the dual - antenna processing channels. Such processing can cancel the Doppler effect caused by rotation. When only the signal strength of one path is greater than the predetermined threshold, the frequency update value corresponding to this path of antenna is used for updating. In this case, the rotational Doppler will enter the tracking loop, and only the low - pass effect of the channel loop filter can be used to mitigate it.

[0151] Furthermore, the on - missile receiver further includes:

[0152] The first down - converter 117 directly and electrically connected to the first analog - to - digital signal sampling unit 112;

[0153] The first early - minus - late correlator 118 connected to both the first down - converter 117 and the first pseudo - code generator 113 at the same time.

[0154] Furthermore, the on - missile receiver includes a first pseudo - code processing channel, configured according to the following structure:

[0155] The first down - converter 117 is electrically connected to the input port of the first early - minus - late correlator 118;

[0156] The first pseudo - code generator 113 is electrically connected to the input port of the first early - minus - late correlator 118;

[0157] The output port of the first early - minus - late correlator 118 is connected to the DLL discriminator;

[0158] The DLL discriminator 13 is electrically connected to the code loop 14.

[0159] It can be understood that in a receiver, if the intermediate frequency signal obtained after mixing is lower than the original signal, such a mixing method is called down-conversion. The purpose of down-conversion is to reduce the carrier frequency of the signal or directly remove the carrier frequency to obtain the baseband signal. In a communication system, in order to facilitate signal transmission and achieve channel multiplexing, the frequency of the transmitted signal is very high. Therefore, the frequency conversion of the signal is an important content in the research of communication systems. The down-conversion is performed in the on-board receiver of the embodiment of the present application. The method of down-conversion is to multiply the received signal by the local oscillator signal generated by the local oscillator, and then obtain the frequency-converted signal through a low-pass filter.

[0160] Specifically, the purpose of using the first down-converter 117 in the embodiment of the present application is that before the first analog-to-digital signal sampling unit 112 sends down the satellite signal collected by the first radio frequency unit 111, the first down-converter 117 reduces the carrier frequency of this signal or directly removes it to obtain the baseband signal of this signal, so that the data obtained by the subsequent analysis of this signal by the remaining modules is more accurate, thereby improving the accuracy of the projectile to capture the target.

[0161] Furthermore, the first down-converter 117 simultaneously sends the processed signal and the signal encrypted by the first pseudo-code generator 113 to the first early minus late correlator 118 connected to the first down-converter 117 and the first pseudo-code generator 113.

[0162] It can be understood that a code loop is adopted in the on-board receiver provided in this embodiment. In the code tracking loop, that is, the code loop, there are: an early correlator, a late correlator, and an immediate correlator on the quadrature channel. There are also such 3 correlators on the in-phase channel. The sent signal is first divided into two paths, which are respectively multiplied by two locally generated orthogonal carriers to form the input signals of the quadrature channel and the in-phase channel, and then correlated with the local early code, late code, and immediate code respectively. Then the results are sent to the code loop discriminator for processing.

[0163] In this embodiment, the input port of the first early minus late correlator 118 is connected to the first down-converter 117 and the first pseudo-code generator 113. When the first early minus late correlator 118 receives the information sent down by the first down-converter 117 and the first pseudo-code generator 113, it processes the information in the way of early code minus late code, and continues to send the output result to the DLL discriminator 13 electrically connected to its output port. Finally, the data is further processed by the DLL discriminator 13 and sent down to the code loop 14.

[0164] Furthermore, the on-board receiver further includes:

[0165] A second down-converter 127 directly electrically connected to the second analog-to-digital signal sampling unit 122;

[0166] The second early minus late correlator 128 is also connected to the second downconverter 127 and the second pseudocode generator 123 simultaneously.

[0167] Furthermore, the on-board receiver includes a second pseudocode processing channel, which is configured in the following structure:

[0168] The second downconverter 127 is electrically connected to the input port of the second early minus late correlator 128;

[0169] The second pseudocode generator 123 is electrically connected to the input port of the second early minus late correlator 128;

[0170] The output port of the second early minus late correlator 128 is connected to the DLL discriminator 13;

[0171] The DLL discriminator is electrically connected to the code loop.

[0172] Similarly, specifically, the purpose of using the second downconverter 127 in the embodiment of the present application is that, before the second analog-to-digital signal sampling unit 122 sends down the satellite signal collected by the second radio frequency unit 121, the second downconverter 127 reduces the carrier frequency of this signal or directly removes it to obtain the baseband signal of this signal, so that the data obtained by the remaining modules in the subsequent analysis of this signal is more accurate, thereby improving the accuracy of the projectile to capture the target.

[0173] Furthermore, the second downconverter 127 sends down the processed signal and the signal encrypted by the second pseudocode generator 123 simultaneously to the second early minus late correlator 128 connected to the second downconverter 127 and the second pseudocode generator 123.

[0174] In this embodiment, the input port of the second early minus late correlator 128 is connected to the second downconverter 127 and the second pseudocode generator 123. When the second early minus late correlator 128 receives the information sent down by the second downconverter 127 and the second pseudocode generator 123, it processes the information in the way of subtracting the late code from the early code, and continues to send the output result to the DLL discriminator 13 electrically connected to its output port. Finally, the DLL discriminator 13 further processes the data and sends it down to the code loop 14.

[0175] Furthermore, the on-board receiver also includes a first downconverter 117 directly electrically connected to the first analog-to-digital signal sampling unit 112;

[0176] The on-board receiver also includes a first frequency processing channel, which is configured in the following structure:

[0177] The first downconverter 117 is electrically connected to the first correlator 114;

[0178] The first correlator 114 is electrically connected to the first frequency discriminator 115;

[0179] The first frequency discriminator 115 is electrically connected to the FLL discriminator 15;

[0180] The FLL discriminator 15 is electrically connected to the frequency-locked loop 16.

[0181] Furthermore, the on-board receiver further includes a second down-converter 127 directly electrically connected to the second analog-to-digital signal sampling unit 112;

[0182] The on-board receiver further includes a second frequency processing channel configured as follows:

[0183] The second down-converter 127 is electrically connected to the second correlator 124;

[0184] The second correlator 124 is electrically connected to the second frequency discriminator 125;

[0185] The second frequency discriminator 125 is electrically connected to the FLL discriminator 15;

[0186] The FLL discriminator 15 is electrically connected to the frequency-locked loop 16.

[0187] Furthermore, the FLL discriminator 15 is configured to:

[0188] When the signal intensities of the first frequency processing channel and the second frequency processing channel are greater than a predetermined threshold, the FLL discriminator 15 outputs the average Doppler.

[0189] Specifically, in the embodiment provided in the present application, the modules with electrical connections in the internal structure of the on-board receiver form the first frequency processing channel and the second frequency processing channel. In each frequency processing channel, when the radio frequency unit transmits radio frequency information to the analog-to-digital signal sampling unit, the information will be divided into two paths and enter the first frequency processing channel and the second frequency processing channel respectively. In the first frequency processing channel, the radio frequency information is received by the first analog-to-digital signal sampling unit 112. The first analog-to-digital signal sampling unit 112 converts the radio frequency signal into a digital signal and sends it down to the first down-converter 117. The first down-converter 117 reduces the carrier frequency of the received digital signal or directly removes it to obtain the baseband signal of this signal, and continues to send the baseband signal down to the first correlator 114. The first correlator 114 will further extract the received initial baseband signal from interference and noise, perform despreading and demodulation, restore the initial baseband signal to the original baseband signal, and continue to send it down to the first frequency discriminator 115. The first frequency discriminator 115 will discriminate the frequency difference between the received baseband signal and the local carrier, and send the discrimination result down to the FLL discriminator 15.

[0190] Similarly, in the second frequency processing channel, the radio frequency information is received by the second analog-to-digital signal sampling unit 122. The second analog-to-digital signal sampling unit 122 converts the radio frequency signal into a digital signal and sends it to the second down-converter 127. The second down-converter 127 reduces the carrier frequency of the received digital signal or directly removes it to obtain the baseband signal of this signal, and continues to send the baseband signal to the second correlator 124. The second correlator 124 further extracts the received initial baseband signal from interference and noise, performs despreading and demodulation, restores the initial baseband signal to the original baseband signal, and continues to send it to the second frequency discriminator 125. The second frequency discriminator 125 discriminates the frequency difference between the signal and the local carrier according to the received baseband signal, and sends the discrimination result to the FLL discriminator 15.

[0191] When the FLL discriminator 15 receives the discrimination results of the first frequency discriminator 115 and the second frequency discriminator 125, combined with the automatic frequency fine-tuning circuit with dynamic operation, that is, the frequency-locked loop 16, it judges how many signal strengths are greater than the predetermined threshold. When the signal strengths of both paths are greater than the predetermined threshold, the frequency discrimination values corresponding to the two antennas can be used to update the local pseudo-code and carrier of the dual-antenna processing channel. Such processing can cancel the Doppler effect caused by rotation. When only the signal strength of one path is greater than the predetermined threshold, the frequency update value corresponding to the antenna of this path is used for updating. In this case, the rotational Doppler will enter the tracking loop, and only the low-pass effect of the channel loop filter can be used to reduce it.

[0192] Furthermore, an on-board receiver embodiment provided by the present application for a high-dynamic projectile carrier is applied to an on-board satellite navigation receiving system. Please refer to the design principle block diagram Figure 3 of the high-precision ballistic measurement verification receiver.

[0193] It can be understood that after the on-board satellite navigation receiving system is powered on and started, it completes device initialization and self-check status confirmation. After the on-board receiver is fired out of the barrel, it quickly completes receiver acquisition and tracking positioning, and simultaneously saves pseudo-range and carrier observation data. The on-board device imports the stored ballistic observables and the observation data collected by the reference station device into the post-data processing and analysis software for differential positioning calculation, which is used as the on-board reference to evaluate the ballistic measurement accuracy of the on-board satellite navigation device. The post-data processing and analysis software gives the final analysis and evaluation results, including parameters such as the error magnitude and the error characteristics of each segment, which are used to improve the positioning and control strategy of the on-board navigation receiver.

[0194] Specifically, the design principle block diagram of the high-precision ballistic measurement verification receiver includes: a battery module, an on-board GNSS antenna, and a high-precision ballistic measurement receiver. The high-precision ballistic measurement receiver specifically includes a combiner and frequency converter module and a GNSS verification receiver board. The GNSS verification receiver board specifically includes a signal correlation processing module, a loop filtering processing module, a vector joint processing module, a loop control module, a satellite navigation information processing module, and a roll tracking loop processing module. GNSS stands for Global Navigation Satellite System. The on-board GNSS antenna is used to receive signals and transmit the received signals to the combiner and frequency converter module. After preliminary processing, the combiner and frequency converter module transmits the signals to the GNSS verification receiver board for processing. The battery module serves as the power supply for the high-precision ballistic measurement receiver.

[0195] Furthermore, the high-precision ballistic measurement verification receiver here can also be understood as an on-board satellite positioning and attitude measurement integrated receiver. For its hardware design structure block diagram, please refer to Figure 4 .

[0196] Specifically, when designing the high-precision ballistic measurement receiver in a high-dynamic environment, the receiver is designed to be small-sized, low-power, and capable of receiving Beidou satellite signals. From a structural perspective, the entire ballistic measurement system consists of the original on-board Beidou navigation terminal, the high-precision ballistic measurement verification receiver, the on-board verification data storage module, the antenna, and the on-board power supply, etc. When specifically designing the high-precision ballistic measurement verification receiver, the RF receiver can use the MAX2769 chip, and the baseband part uses the DSP+FPGA architecture to complete the baseband signal processing. The power consumption of the high-precision ballistic measurement verification receiver is about 2W. The RF part using the MAX2769 chip includes 2 low-noise amplifiers LNA-B3 that can cover the B3 frequency point, down-conversion, crystal oscillator, clock drive, etc. The FPGA in the baseband part can use the EP3C80 chip, and the DSP can use the TMS320C6748 chip. The high-precision ballistic measurement verification receiver in a high-dynamic environment is divided into two parts: RF and baseband. The RF part mainly completes the following tasks: filtering, amplifying, mixing, and sampling the satellite signals, and outputting 4-bit digital intermediate frequency for the baseband part to perform signal and information processing; receiving the BPSK signal provided by the baseband part, mixing and amplifying it to the antenna. The DSP and FPGA in the baseband part cooperate to complete the acquisition, tracking, etc. of the intermediate frequency signal.

[0197] It should be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising the said element.

[0198] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. An on-board receiver for a high-dynamic projectile carrier, characterized in that Comprising: A first receiving antenna disposed at a first position of a high-dynamic projectile carrier; A first radio frequency unit electrically connected to the first receiving antenna; A first analog-to-digital signal sampling unit electrically connected to the first radio frequency unit; A first pseudo-code generator electrically connected to the first analog-to-digital signal sampling unit; A first correlator electrically connected to the first analog-to-digital signal sampling unit; A first frequency discriminator electrically connected to the first correlator; A second receiving antenna disposed at a second position that is centrosymmetric with the first position of the high-dynamic projectile carrier; A second radio frequency unit electrically connected to the second receiving antenna; A second analog-to-digital signal sampling unit electrically connected to the second radio frequency unit; A second pseudo-code generator electrically connected to the second analog-to-digital signal sampling unit; A second correlator electrically connected to the second analog-to-digital signal sampling unit; A second frequency discriminator electrically connected to the second correlator; A DLL discriminator connected to the first pseudo-code generator and the second pseudo-code generator; A code loop electrically connected to the DLL discriminator; An FLL discriminator electrically connected to the first frequency discriminator and the second frequency discriminator; A frequency-locked loop electrically connected to the FLL discriminator; The on-board receiver further includes a first signal strength detection module electrically connected to the first frequency discriminator and a second signal strength detection module electrically connected to the second frequency discriminator, so as to determine the synthesis strategy of the FLL discriminator according to the signal strength; The on-board receiver further includes a first down-converter directly electrically connected to the first analog-to-digital signal sampling unit; The on-board receiver further includes a first frequency processing channel configured according to the following structure: The first down-converter is electrically connected to the first correlator; The first correlator is electrically connected to the first frequency discriminator; The first frequency discriminator is electrically connected to the FLL discriminator; The FLL discriminator is electrically connected to the frequency-locked loop; The on-board receiver further includes a second down-converter directly electrically connected to the second analog-to-digital signal sampling unit; The on-board receiver further includes a second frequency processing channel configured according to the following structure: The second down-converter is electrically connected to the second correlator; The second correlator is electrically connected to the second frequency discriminator; The second frequency discriminator is electrically connected to the FLL discriminator; The FLL discriminator is electrically connected to the frequency-locked loop; The FLL discriminator is configured as: When the signal strengths of the first frequency processing channel and the second frequency processing channel are greater than a predetermined threshold, the FLL discriminator outputs an average Doppler.

2. The on-board receiver according to claim 1, characterized in that, The first receiving antenna and the second receiving antenna are respectively attached to the surface of the high-dynamic projectile carrier.

3. The on-board receiver according to claim 1, characterized in that, The on-board receiver further includes: A first down-converter directly electrically connected to the first analog-to-digital signal sampling unit; A first early minus late correlator connected to both the first down-converter and the first pseudo-code generator.

4. The on-board receiver according to claim 3, characterized in that, The on-board receiver includes a first pseudo-code processing channel configured according to the following structure: The first down-converter is electrically connected to the input port of the first early minus late correlator; The first pseudo-code generator is electrically connected to the input port of the first early minus late correlator; The output port of the first early minus late correlator is connected to the DLL discriminator; The DLL discriminator is electrically connected to the code loop.

5. The on-board receiver according to claim 1, characterized in that, The on-board receiver further includes: A second down-converter directly and electrically connected to the second analog-to-digital signal sampling unit; A second early minus late correlator connected to both the second down-converter and the second pseudo-code generator.

6. The on-board receiver according to claim 5, characterized in that, The on-board receiver includes a second pseudo-code processing channel configured in the following structure: The second down-converter is electrically connected to the input port of the second early minus late correlator; The second pseudo-code generator is electrically connected to the input port of the second early minus late correlator; The output port of the second early minus late correlator is connected to the DLL discriminator; The DLL discriminator is electrically connected to the code loop.

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