An internal reference voltage circuit for a DDR3 or DDR4 standard receiving end

Abstract

The application discloses an internal reference voltage circuit for a DDR3 or DDR4 standard receiving end. The circuit comprises an N-bit control logic circuit, a DAC circuit and a driving circuit. The N-bit control logic circuit converts an input N-bit binary code into a 2N-bit quantization code and a 1-bit output control code C0 based on an enable signal EN, wherein N>=8. The DAC circuit is used for generating a reference voltage required by the DDR3 or DDR4 standard receiving end according to the 2N-bit quantization code and the output control code C0. The driving circuit is used for driving the reference voltage generated by the DAC circuit to a reference voltage input end of the DDR3 or DDR4 standard receiving end. The reference voltage circuit provided by the application has the advantages of simple structure, wide output adjustment range, strong anti-interference capability and the ability to select the required reference voltage of the DDR3 or DDR4 standard receiving end according to requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of reference voltage generating circuit, in particular to a reference voltage circuit for a receiving end of DDR3 or DDR4 standard. BACKGROUND

[0002] Double Data Rate (DDR) technology is widely used in high-speed data transmission, especially DDR3 and DDR4 standard protocols have high speed, high reliability and other characteristics. In high-speed data transmission circuit, the receiver mainly undertakes the function of recovering the data and clock from the sending end, and its performance directly relates to whether the data and clock can be correctly recovered. In DDR3 and DDR4 standards, the data and clock signals are identified by the input buffer in the receiver. The input buffer is usually configured in single-ended mode, and a specified reference voltage needs to be input at the same time as the external signal is received.

[0003] The reference voltage of the input buffer is divided into external input reference voltage and internal self-generated reference voltage. The generation circuit of the external input reference voltage usually adopts a resistance voltage division technology related to the power supply, which is realized by discrete components on the PCB. This method is simple to implement, but it needs additional components to generate and is susceptible to environmental interference. The internal self-generated reference voltage is generated by the reference voltage circuit integrated into the chip. The generation circuit of the internal self-generated reference voltage usually has the following two implementation methods:

[0004] 1. A bandgap reference voltage is used as a reference, and the bandgap reference voltage is divided to generate the reference voltage of the input buffer. This reference voltage is not affected by temperature, power supply and process, but an additional control signal is needed to adapt to different DDR standards.

[0005] 2. A resistance voltage division method is used to generate a voltage proportional to the power supply of the interface circuit inside the chip. This method can adapt to different DDR3 standards, but when the DDR4 standard needs dynamic adjustment function, a large amount of logic resources needs to be consumed.

[0006] The reference voltage generated by the above three implementation methods of the receiver reference voltage circuit can only be used for a receiver of a certain DDR standard. When a receiver needs to support both DDR3 and DDR4 standards, the reference voltage circuit needs to be modified, which will greatly increase the complexity of the circuit. SUMMARY

[0007] In view of the above deficiencies in the implementation method of the DDR receiver reference voltage circuit, the present application provides an internal reference voltage circuit for a receiving end of DDR3 and DDR4 standards. The internal reference voltage circuit has a simple control logic structure, a wide output adjustment range and strong anti-interference ability.

[0008] The internal reference voltage circuit provided by the application comprises an N-bit control logic circuit, a DAC circuit and a driving circuit, N>=8; the N-bit control logic circuit converts an input N-bit binary code into 2N-bit quantization code and 1-bit output control code for controlling the DAC circuit based on an enable signal EN; the DAC circuit is used for generating a reference voltage required by a DDR3 or DDR4 standard receiving end according to the 2N-bit quantization code and the 1-bit output control code C0; the DAC circuit is composed of two N-bit R-2R resistance networks, one end of a 2R value resistance controlled by each bit quantization code is connected to VCC1 or VSS1, the standard reference voltage VREF of DDR3 is 0.5*(VCC1-VSS1), the R value resistance corresponding to the highest bit quantization code of the two R-2R resistance networks is connected as an output end of the entire DAC circuit, the output end is connected to VCC1 or VSS1 through a resistance Rc and controlled by the output control code C0; the driving circuit is used for driving the reference voltage generated by the DAC circuit to a reference voltage input end of the DDR3 or DDR4 standard receiving end.

[0009] Further, the N-bit control logic circuit has binary code conversion logic and level conversion function, which converts an N-bit binary code from a power supply domain VCC2 (the power supply of the power supply domain is VCC2) into 2N-bit quantization code and 1-bit output control code C0 for controlling the DAC circuit in a power supply domain VCC3 (the power supply of the power supply domain is VCC3) based on an enable signal EN; wherein the voltage of the power supply VCC3 is higher than the voltage of the power supply VCC2.

[0010] Further, the N-bit control logic circuit is an 8-bit logic control circuit, which realizes the following logic conversion on the input 8-bit binary code MR<0>-MR<7> based on an enable signal EN:

[0011] a<0>-a<1>=EN·VCC3;

[0012] a = EN - (MR<7> - M <i-2>), i is a natural number, and 2≤i≤7;

[0013] b<0>-b<4>=EN·VCC3;

[0014]

[0015] b<7>=EN·VCC3;

[0016] c<0>=EN·VCC3.

[0017] wherein, VCC3 is a power supply of a power domain of the DAC circuit; a<7>-a<0> is any one of 8-bit quantization codes from high to low of a control of a path of the R-2R resistance network; b<7>-b<0> controls 8-bit quantization codes from high to low of a path of the R-2R resistance network; and c<0> is the output control code C0.

[0018] Further, the level conversion function is realized by a plurality of level conversion circuits. The level conversion circuit comprises an inverter INV<40>, INV_H<40>, INV<41>, or a NOR gate NOR<40>, PMOS tubes P0, P1, P2, P3, P4, and NMOS tubes N0, N1, N2. Wherein, the enable signal OE in the power domain VCC3 is connected to the input end of the inverter INV_H<40> and the gate of the PMOS tube P4, the output of the inverter INV_H<40> is connected to one input end of the NOR gate NOR<40>; any one of the 8-bit binary codes MR<0>-MR<7> from the power domain VCC2 is connected to the input end of the inverter INV<40> as the input voltage IN, the output of the inverter INV<40> is connected to the other input end of the NOR gate NOR<40>; the output of the NOR gate NOR<40> is connected to the first end input of the inverter INV<41>, the gate of the PMOS tube P2, and the gate of the NMOS tube N0; the output of the inverter INV<41> is connected to the gate of the PMOS tube P3 and the gate of the NMOS tube N1; the source of the PMOS tube P2 is connected to the drain of the PMOS tube P0, the drain thereof is connected to the gate of the PMOS tube P1, the drain of the PMOS tube P4, the gate of the NMOS tube N2, and the drain of the NMOS tube N0, the source of the NMOS tube N0 is connected to the ground VSS; the source of the PMOS tube P3 is connected to the drain of the PMOS tube P1, the drain thereof is connected to the gate of the PMOS tube P0, the drain of the NMOS tube N2, and the drain of the NMOS tube N1, the sources of the NMOS tubes N1, N2 are connected to the ground VSS; the sources of the PMOS tubes P0, P1, P4 are connected to the power supply VCC3.

[0019] Further, the driving circuit is composed of an amplification stage and a driving stage. The amplification stage is composed of 7 PMOS tubes P10-P16 and 7 NMOS tubes N10-N16. Among them, the sources of PMOS tubes P10, P13 and P14 are connected to the power supply VCC3, the gate of PMOS tube P10 is connected to the first bias voltage, the drain is connected to the sources of PMOS tubes P11 and P12; the gate of PMOS tube P11 is connected to the output end of the driving circuit, the drain is connected to the drain of NMOS tube N3; the gate of PMOS tube P12 is connected to the reference voltage signal output by the DAC circuit, the drain is connected to the drain of NMOS tube N14; the sources of NMOS tubes N13, N14 and N10 are connected to the ground VSS, the gates are connected to the second bias voltage; the drain of NMOS tube N10 is connected to the sources of NMOS tubes N11 and N12, the gate of NMOS tube N11 is connected to the output end of the driving circuit, the drain is connected to the drain of PMOS tube P13, the gate of NMOS tube N12 is connected to the reference voltage signal output by the DAC circuit, the drain is connected to the drain of PMOS tube P14; the gates of PMOS tubes P13 and P14 are connected to the drain of NMOS tube N15, the gates of PMOS tubes P15 and P16 are connected, the source of PMOS tube P15 is connected to the drain of PMOS tube P13, the drain is connected to the drain of NMOS tube N15, the source of PMOS tube P16 is connected to the drain of PMOS tube P14, the drain is connected to the drain of NMOS tube N16; the gates of NMOS tubes N15 and N16 are connected, the source of NMOS tube N15 is connected to the drain of NMOS tube N13, the source of NMOS tube N16 is connected to the drain of NMOS tube N14. The driving stage is composed of PMOS tube P17, NMOS tube N17 and capacitor C C1 、C C2 Among them, the source of PMOS tube P17 is connected to the power supply VCC3, the gate is connected to the drain of NMOS tube N16, the drain is connected to the drain of NMOS tube N12 through capacitor C C1 , the drain of NMOS tube N17 is used as the output end of the driving circuit; the gate of NMOS tube N17 is connected to the second bias voltage, the source is connected to the ground VSS, the drain is connected to the drain of PMOS tube P12 through capacitor C C2 .

[0020] The internal reference voltage circuit provided by the application can generate the required reference voltage of the receiving end of DDR3 and DDR4 standards; and due to the simple structure of the logic control circuit and the high symmetry of the structures of the DAC circuit and the driving circuit, the whole internal reference voltage circuit has the advantages of wide output adjustment range and strong anti-interference ability. BRIEF DESCRIPTION OF DRAWINGS

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Figure 1 The schematic diagram of the internal reference voltage circuit for the receiver supporting DDR3 and DDR4 standards provided in this application.

[0023] Figure 2 This is a circuit schematic of an N-bit control logic circuit in one embodiment.

[0024] Figure 3 This is a circuit schematic of a DAC circuit in one embodiment.

[0025] Figure 4 This is a circuit diagram of a level conversion circuit in one embodiment.

[0026] Figure 5 This is a circuit schematic of the driving circuit in one embodiment. Detailed Implementation

[0027] The technical solutions provided in this application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain this application.

[0028] like Figure 1 As shown, the internal reference voltage circuit 100 for DDR3 and DDR4 standard receivers provided in this application includes: an Nb-bit control logic circuit 101 (i.e., an N-bit control logic circuit), a Na-bit DAC circuit 102 (i.e., a DAC circuit), a driver circuit 103, transmission gate logics 104 and 105, resistors R1 and R2, capacitor C11, and load filter capacitor C. LOAD The Nb-bit control logic circuit 101 converts the input N-bit binary code into 2N-bit quantization code and 1-bit output control code based on the enable signal EN to control the Na-bit DAC circuit 102. The Na-bit DAC circuit 102 is used to generate the reference voltage required by the receiving end of the DDR3 standard or the DDR4 standard according to the 2N-bit quantization code and 1-bit output control code converted by the Nb-bit control logic circuit 101. The driving circuit 103 is used to follow and amplify the analog voltage output by the Na-bit DAC circuit 102 and drive the large-capacitance load. The transmission gates 104 and 105 switch the internal reference and external reference voltages under the action of the control logic. The output path of the Na-bit DAC circuit 102 and the driving circuit path contain resistors R1 and R2 and a capacitor C11. The resistor R1 and the capacitor C11 form a high-frequency filter network for filtering high-frequency noise on the corresponding circuit.

[0029] The Nb-bit logic control circuit 101 includes basic logic gates and voltage switching circuits, and the inputs include N-bit binary code values and two different types of power supply voltages. The N-bit code values are converted by logic, and the high N-1 and N-2 bits are used for mode control selection, and the N-3 to 0 bits are used for control voltage range. The voltage of the code value converted by logic does not meet the control requirements of the DAC, and needs to be switched, i.e. switched from low voltage to high voltage. The Na-bit DAC circuit 102 input includes 2N-bit quantization code and control code C0, power supply voltage and ground VCC1, VSS1. The b<6> and b<5> of the 2N-bit quantization code control the analog output voltage mode, and there are four modes to choose from; the remaining quantization code is used to control the voltage ratio of the DAC circuit 102 output, so that the voltage value of the DAC circuit 102 output is proportional to (VCC1-VSS1).

[0030] The Na-bit DAC circuit 102 is composed of two N-control-bit R-2R resistor networks, and each bit quantization code controls one end of a 2R-value resistor connected to VCC1 or VSS1. The standard reference voltage VREF of DDR3 is 0.5*(VCC1-VSS1), and the highest bit quantization code of the two R-2R resistor networks is connected as the output end of the entire DAC circuit. The output end is connected to VCC1 or VSS1 through the resistor Rc controlled by the output control code.

[0031] In one embodiment, the Nb-bit control logic circuit 101 is as follows Figure 2 As shown, the logic circuit includes inverters, OR gates, AND gates, voltage conversion, etc., the inputs of which include eight-bit binary codes MR<0>-MR<7>, an enable signal EN and OE. Among them, MR<7> and MR<6> in the input signals MR<0>-MR<7> are used to control the output voltage mode, and MR<0>-MR<5> are used to control the output voltage range. OE is connected to the enable end of each voltage switching unit.

[0032] MR<7> is connected to the input end of inverter INV<0> and the first end input of AND gate AND<1>, the output end of inverter INV<0> is connected to the first end input of OR gate OR<0>, the output of OR gate OR<0> is connected to voltage switching unit LS<0>, the output of voltage switching unit LS<0> is connected to AND gate AND_H<7> in the VCC3 domain, and the output of AND gate AND_H<7> is b<5>. MR<6> signal is connected to the input end of inverter INV<1>, the output end of inverter INV<1> is connected to the second end input of AND gate AND<1>, the output end of AND gate AND<1> is connected to the second end input of OR gate OR<0> and the input end of voltage switching unit LS<1>; the output of voltage switching unit LS<1> is connected to AND gate AND_H<8> in the VCC3 domain, and the output of AND gate AND_H<7> is b<6>.

[0033] MR<7> is connected to the input end of inverter INV<0> and the first end input of AND gate AND<1>, the output end of inverter INV<0> is connected to the first end input of OR gate OR<0>, the output of OR gate OR<0> is connected to voltage switching unit LS<0>, the output of voltage switching unit LS<0> is connected to AND gate AND_H<7> in the VCC3 domain, and the output of AND gate AND_H<7> is b<5>. MR<6> signal is connected to the input end of inverter INV<1>, the output end of inverter INV<1> is connected to the second end input of AND gate AND<1>, the output end of AND gate AND<1> is connected to the second end input of OR gate OR<0> and the input end of voltage switching unit LS<1>; the output of voltage switching unit LS<1> is connected to AND gate AND_H<8> in the VCC3 domain, and the output of AND gate AND_H<7> is b<6>. Any signal MR ( Figure 2 In the middle, MR<5:0> indicates MR <5> -MR <0> One of the access gates in the AND gate<i+2> The first input terminal, AND gate<i+2> The other input terminal is connected to M<i+2> The output terminal is connected to the voltage switching circuit LS.<i+2> ( Figure 2 In the middle, LS<7:2> means LS <7> -LS <2> One of the input terminals of the voltage switching circuit LS)<i+2> The output is connected to the AND gate AND_H in the VCC3 domain.<i+2+7> ( Figure 2 AND_H<14:9> in the middle represents AND_H <14> -AND_H <9> One of them), AND gate AND_H<i+2+7> Output signal a<i+2> ( Figure 2 The values ​​of a<7:2> correspond to the MR connections respectively. <5> -MR <0> ).

[0034] Finally, the Nb-bit control logic circuit implements MR. <0> -M <7> Control signal to b <6> -b <5> a <2> -a <7> The conversion is based on the enable signal EN changing the input 8-bit binary code MR. <0> -MR <7> Implement the following logical transformations:

[0035] a <0> -a <1> =EN·VCC3;

[0036] a =EN·(MR<7 >·M <i-2>), i is a natural number, and 2≤i≤7;

[0037] b<0>-b<4>=EN·VCC3;

[0038]

[0039] b<7>=EN·VCC3;

[0040] c<0>=EN·VCC3.

[0041] wherein, VCC3 is the power domain of the DAC control signal; a<0>-a<7>(corresponding to a0-a7 in Figure 3 ) are 8-bit quantization codes from high to low that control one of the R-2R resistance networks; b<0>-b<7>(corresponding to b0-b7 in Figure 3 ) control 8-bit quantization codes from high to low of one of the R-2R resistance networks; c<0> is the output control code C0. b<6>, b<5> control the DAC output voltage mode, and a<2>-a<7> realize the DAC voltage range selection control.

[0042] When MR<7:6>=00, 01, MR<5:0>=000000-111111, the output is unchanged, fixed as the DDR3 standard reference voltage VREF=0.5*(VCC1-VSS1). When MR<7:6>=10, MR<5:0>=000000-111111, the output range is Range1, fixed as the DDR4 standard reference voltage, VREF=Betarange1*(VCC1-VSS1). MR<7:6>=11, MR<5:0>=000000-111111, the output range is Range2, fixed as the DDR4 standard, VREF=Betarange2*(VCC1-VSS1). Betarange1 and Betarange2 correspond to the proportionality coefficient of the DAC output reference voltage and (VCC1-VSS1) under the DDR4 standard.

[0043] As shown in Figure 3 , in this embodiment, the Na-bit DAC circuit 102 is composed of two A and B paths of 8 control bit R-2R resistance networks. The A path R-2R resistance network contains two alternative switches K A0 , K A1 , …, K A6 , K A7 , resistors R A_A0 , R A_A1 , …, R A_A7 , R A_A8 , and resistors R A_B0 , R A_B1 ,..., R A_B6 ,..., R A_B7 . Wherein R A_Ai = 2R (i = 0, 1,..., 7, 8), R A_Bi = R (i = 0, 1,..., 6, 7), R is a unit resistance value. Control signal a 0- a7 controls the switch selection K A0 , K A1 ,..., K A6 , K A7 ; when a 0- a7 there is a logic value "0", the corresponding switch is connected to VSS1, when a0-a7 there is a logic value "1", the corresponding switch is connected to VCC1. Switch K A0 is a three-terminal input device controlled by logic signal a0, its first end is connected to VSS1, the second end is connected to VCC1, and the third end is connected to the second end of resistor R A_A1 . The first end of resistor R A_A1 is connected to node A0, and A0 node is connected to the first end of resistor R A_A0 , and the first end of resistor R A_B0 . The second end of resistor R A_A0 is connected to VSS1, and the second end of resistor R A_B0 is connected to node A1. Node A1 is connected to the first end of resistor R A_A2 , and the first end of resistor R A_B1 . The second end of resistor R A_A2 is connected to the third end of switch K A1 , and switch K A1 is controlled by logic signal a1 to be connected to VSS1 or VCC1. The second end of resistor R A_B1 is connected to node A2, and node A2 is connected to the first end of resistor R A_A3 , and the first end of resistor R A_B2 . The second end of resistor R A_B2 is connected to node A3. The second end of resistor R A_A3 is connected to the third end of switch K A2 , and switch K A2 is controlled by logic signal a2 to be connected to VSS1 or VCC1. The following is sequentially connected according to the above rule until node A7. Node A7 is connected to the first end of resistor R A_A8 , and the first end of resistor R A_B7 . The second end of resistor R A_B7 is connected to output node V DAC , and the second end of resistor R A_A8 is connected to the third end of switch K A7 . Switch K A7 is controlled by control signal a7 to be connected to VSS1 or VCC1. As Figure 2 The circuit connection relationship of the B path R-2R resistance network is symmetrical in topology with the circuit connection relationship of the A path R-2R resistance network. The output node V DAC is connected to the first end of the resistance R C , the second end of the resistance R C is connected to the third end of the switch K C0 , and the resistance R C = 4R. The switch K C0 is controlled by the logic signal C0 to be connected to VSS1 or VCC1.

[0044] The implementation circuit of the voltage switching unit LS is shown in Figure 4 . The circuit realizes the conversion of the input logic low voltage VCC2 to the output high voltage VCC3. Any one of the 8-bit binary codes MR<0>-MR<7> from the power supply domain VCC2 is connected as the input voltage IN to the input end of the inverter INV<40>. The output of the inverter INV<40> is connected to the first end input of the NOR gate NOR<40>. The control signal OE is from the power supply domain VCC3, connected to the first end input of the high voltage inverter INV_H<40> and the gate of the PMOS tube P4, and the output of INV_H<40> is connected to the second end input of the NOR gate NOR<40>. The output of the NOR gate NOR<40> is connected to the first end input of the inverter INV<41>, the gate of the PMOS tube P2 and the gate of the NMOS tube N0. The output of the inverter INV<41> is connected to the gate of the PMOS tube P3 and the gate of the NMOS tube N1. The source of the PMOS tube P2 is connected to the drain of the PMOS tube P0, and the drain thereof is connected to the negative end output ZN, i.e. the drain of the NMOS tube N0, the gate of the PMOS tube P1, the drain of the PMOS tube P4 and the gate of the NMOS tube N2. The source of the NMOS tube N0 is connected to the ground VSS. The source of the PMOS tube P3 is connected to the drain of the PMOS tube P1, and the drain thereof is connected to the positive end output Z, i.e. the gate of the PMOS tube P0, the drain of the NMOS tube N1 and the drain of the NMOS tube N2. The sources of the NMOS tubes N1 and N2 are connected to the ground VSS. The sources of the PMOS tubes P0 and P1 are connected to the power supply VCC3. The source of the PMOS tube P4 is connected to the power supply VCC3. When the input IN is the low voltage logic value high, the output Z is the high voltage logic value high and ZN is the high voltage logic value low. When the input IN is the low voltage logic value low, the output Z is the high voltage logic value low and ZN is the high voltage logic value high.

[0045] The output voltage V DAC of the Na-bit DAC circuit 102 is filtered by the resistance R1 and the capacitance C1 to obtain the voltage V DAC_RC , and the voltage V DAC_RC is amplified by the driving circuit to V INT . Figure 5 An implementation circuit of the driving circuit is given, which is composed of an amplification stage and a driving stage. The amplification stage adopts N-type and P-type inputs to increase the input common mode range and meet the output voltage range of the DAC. The power domain of the driving circuit is VCC3. The source of PMOS tube P10 is connected to the power supply VCC3, the gate is connected to the bias voltage V PBIAS0 , and the drain is connected to the node V TAILP , i.e. the source of PMOS tubes P11 and P12. The gate of PMOS tube P11 is connected to the output node V INT of the driving circuit, and the drain is connected to the node V P1 , i.e. the source of NMOS tube N15 and the drain of NMOS tube N13. The gate of PMOS tube P12 is connected to the output voltage V DAC_RC of the DAC, and the drain is connected to the node V P2 , i.e. the source of NMOS tube N16, the drain of NMOS tube N14 and the first end input of capacitor C C2 . The gates of NMOS tubes N13 and N14 are connected to the bias voltage V NBIAS0 , and the sources are connected to the ground VSS. The gate of NMOS tube N15 is connected to the bias voltage V NBIAS1 , and the drain is connected to the node V INT1 , i.e. the drain of PMOS tube P15, the gate of P13 tube and the gate of P14 tube. The drain of NMOS tube N16 is connected to the node V INT2 , i.e. the drain of PMOS tube P16 and the gate of P17. The gate of NMOS tube N10 is connected to the bias voltage V NBIAS0 , and the drain is connected to the node V TAILN , i.e. the sources of NMOS tubes N11 and N12, and the sources are connected to the ground VSS. The gate of NMOS tube N11 is connected to the node V INT , and the drain is connected to the node V N1 , i.e. the drain of PMOS tube P13 and the source of P15. The gate of NMOS tube N12 is connected to the DAC output V DAC_RC , and the drain is connected to the node V N2 , i.e. the drain of PMOS tube P14, the source of P16 tube and the first end input of capacitor C C1 . PMOS tubes P13 and P14 are connected to the power supply VCC3. The gates of PMOS tubes P15 and P16 are connected to the bias voltage V PBIAS1 . The drain of NMOS tube N17 is connected to the driving output V INT , the drain of PMOS tube P17, the capacitor C C1 and C C2 The second end of the resistor R6 is connected to the input of the PMOS transistor P17, and the source of the PMOS transistor P17 is connected to the power supply VCC3. The PMOS transistor P17 and the NMOS transistor N7 constitute a driving stage, which provides a large current to meet the requirement of the DDR4 standard on the setup time. The capacitor C C1 , C C2 is used as a compensation capacitor to meet the loop stability requirement.

[0046] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those ordinarily skilled in the art should understand: the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. An internal reference voltage circuit for a DDR3 or DDR4 standard receiver, characterized in that, The reference voltage circuit includes: an N-bit control logic circuit, a DAC circuit, and a driver circuit; The N-bit control logic circuit converts the input N-bit binary code into a 2N-bit quantization code and a 1-bit output control code C0, N>=8, based on the enable signal EN. The DAC circuit is used to generate the reference voltage required by the DDR3 or DDR4 standard receiver based on the 2N-bit quantization code and the 1-bit output control code C0. The DAC circuit consists of two R-2R resistor networks with N control bits. Each quantization code controls one end of a 2R resistor connected to VCC1 or VSS1. The standard reference voltage for DDR3 is V... REF =0.5*(VCC1-VSS1); The R-value resistors corresponding to the highest bit quantization code of the two R-2R resistor networks are connected together as the output terminal of the entire DAC circuit. The output terminal is connected to VCC1 or VSS1 through resistor Rc and controlled by the output control code C0. The driving circuit is used to drive the reference voltage generated by the DAC circuit to the reference voltage input terminal of the DDR3 or DDR4 standard receiver. The N-bit control logic circuit has binary code conversion logic and level conversion function. Based on the enable signal EN, it converts the N-bit binary code from the power domain VCC2 into a 2N-bit quantization code and a 1-bit output control code C0 to control the DAC circuit and the power domain VCC3. The voltage of power domain VCC3 is higher than that of power domain VCC2. The N-bit control logic circuit is an 8-bit logic control circuit; it is based on the enable signal EN to control the input 8-bit binary code MR. <0> -MR <7> Implement the following logical transformations: a <0> -a <1> =EN·VCC3; a =EN·(MR <7> ·M <i-2> ), where i is a natural number and 2≤i≤7; b <0> -b <4> =EN·VCC3; b <7> =EN·VCC3; c <0> =EN·VCC3; Where VCC3 is the power supply domain of the DAC control signal; a <7> -a <0> To control one of the R-2R resistor networks, an 8-bit high-to-low quantization code is used; b <7> -b <0> Control the 8-bit high-to-low quantization code of one of the R-2R resistor networks; c <0> The output control code is C0.

2. The internal reference voltage circuit as described in claim 1, characterized in that, The level conversion function is implemented through several level conversion circuits, including an inverter INV. <40> INV_H <40> INV <41> NOR gate <40> It consists of PMOS transistors P0, P1, P2, P3, and P4, and NMOS transistors N0, N1, and N2; wherein, the enable signal OE of the power supply domain VCC3 is connected to the inverter INV_H. <40> The input terminal and the gate of PMOS transistor P4, inverter INV_H <40> The output of the NOR gate is connected. <40> One input terminal; 8-bit binary code MR from power domain VCC2 <0> -MR <7> Any one of the bits is used as the input voltage IN to connect to the inverter INV. <40> The input terminal of the inverter INV <40> Output connection to NOR gate <40> The other input; NOR gate <40> The output is connected to the inverter INV. <41> The first input terminal, the gate of PMOS transistor P2, and the gate of NMOS transistor N0; inverter INV <41> The output is connected to the gate of PMOS transistor P3 and the gate of NMOS transistor N1; the source of PMOS transistor P2 is connected to the drain of PMOS transistor P0 and the drain of PMOS transistor P2 as the inverting output terminal of the level conversion circuit. ZN is connected to the gate of PMOS transistor P1, the drain of PMOS transistor P4, the gate of NMOS transistor N2 and the drain of NMOS transistor N0, and the source of NMOS transistor N0 is connected to ground VSS; the source of PMOS transistor P3 is connected to the drain of PMOS transistor P1 and the drain of PMOS transistor P3 as the non-inverting output terminal of the level conversion circuit. Z is connected to the gate of PMOS transistor P0, the drain of NMOS transistor N2 and the drain of NMOS transistor N1, and the sources of NMOS transistors N1 and N2 are connected to ground VSS; the sources of PMOS transistors P0, P1 and P4 are connected to power supply VCC3.

3. The internal reference voltage circuit as described in claim 1, characterized in that, The driving circuit consists of an amplification stage and a driving stage. The amplification stage comprises seven PMOS transistors (P10-P16) and seven NMOS transistors (N10-N16). The sources of PMOS transistors P10, P13, and P14 are connected to power supply VCC3; the gate of PMOS transistor P10 is connected to a first bias voltage; and the drain of PMOS transistor P10 is connected to the sources of PMOS transistors P11 and P12. The gate of PMOS transistor P11 is connected to the output of the driving circuit, and its drain is connected to the drain of NMOS transistor N3. The gate of PMOS transistor P12 is connected to the reference voltage signal output by the DAC circuit, and its drain is connected to the drain of NMOS transistor N4. The sources of NMOS transistors N13, N14, and N10 are grounded to VSS; their gates are connected to a second bias voltage; and the drain of NMOS transistor N10 is connected to the sources of NMOS transistors N11 and N12. The gate of NMOS transistor N11 is connected to the output terminal of the driver circuit, and the drain of NMOS transistor N11 is connected to the drain of PMOS transistor P13. The gate of NMOS transistor N12 is connected to the reference voltage signal output by the DAC circuit, and the drain of NMOS transistor N12 is connected to the drain of NMOS transistor P14. The gates of PMOS transistors P13 and P14 are connected to the drain of NMOS transistor N15. The gates of PMOS transistors P15 and P16 are connected. The source of PMOS transistor P15 is connected to the drain of PMOS transistor P13, and the drain of PMOS transistor P15 is connected to the drain of NMOS transistor N15. The source of PMOS transistor P16 is connected to the drain of PMOS transistor P14, and the drain of PMOS transistor P16 is connected to the drain of NMOS transistor N16. The gates of NMOS transistors N15 and N16 are connected. The source of NMOS transistor N15 is connected to the drain of NMOS transistor N13, and the source of NMOS transistor N16 is connected to the drain of NMOS transistor N14. The driving stage consists of a PMOS transistor P17, an NMOS transistor N17, and a capacitor C. C1 C C2 The structure consists of PMOS transistor P17, whose source is connected to power supply VCC3, and whose gate is connected to the drain of NMOS transistor N16. The drain of PMOS transistor P17 is connected to capacitor C. C1 The drains of NMOS transistors N12 and N17 are connected as the output terminals of the drive circuit; the gate of NMOS transistor N17 is connected to the second bias voltage, the source of NMOS transistor N17 is grounded to VSS, and the drain of NMOS transistor N17 is connected to capacitor C. C2 Connect to the drain of PMOS transistor P12.

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