Display driving device and method with low power consumption

Abstract

The application discloses a low-power display driving device and method. The low-power display driving device comprises a source driving circuit, a display content detection circuit and a display timing driving circuit. A plurality of pixel switches are arranged between the output end of the source driving circuit and a plurality of sub-pixels of a display panel. The display timing driving circuit is coupled with the source driving circuit and the display content detection circuit, and is used for changing the driving sequence according to the display content detected by the display content detection circuit, controlling the opening time of at least two pixel switches in the plurality of pixel switches to overlap with each other, and simultaneously driving at least two sub-pixels in the plurality of sub-pixels corresponding to the at least two pixel switches.

Description

Technical Field

[0001] The present invention relates to a display driver, and in particular to a low-power display driver device and method. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) display panels offer advantages such as power savings, excellent dark-state performance, and fast response times due to their self-luminous properties. Since their self-luminescence is driven by current, their brightness is proportional to the current flowing through them. AMOLED display panels can include multiple sub-pixels, each with its own dedicated pixel circuitry that controls the driving current to achieve varying display brightness.

[0003] A single screen is composed of a gate signal from the display panel that first selects a column of screens. The source drive lines of the display driver integrated circuit (DDIC) then provide voltage signals carrying display information to each sub-pixel in a column corresponding to that column of screens to update that column of screens. The gate signal and source signal coordinate with each other to sequentially update each column of screens until the entire screen is updated.

[0004] Early DDIC designs connected each red (R), green (G), and blue (B) sub-pixel in a display panel to a corresponding source drive line. For example, if the display panel's RGB resolution was 480, the DDIC would require 1440 source drive lines. This resulted in a larger DDIC and a wider chip-on-film (COF) tape connecting the display panel and the DDIC, hindering both structural design and cost control.

[0005] To overcome this problem, Figure 1 As shown, the improved DDIC is a display panel in which multiple sub-pixels R1, G1, B1, R2, G2, and B2 share the same source driving line S1, thereby significantly reducing the number of source driving lines required by the DDIC.

[0006] like Figure 2As shown, during the pre-charge period (time t0 to t1), the switch control signals MUX1 to MUX6 control the pixel switches SW1 to SW6 for pre-charge. It should be noted that during the pre-charge period (time t0 to t1), all sub-pixels will be reset to a specific voltage regardless of the content displayed on the display panel. During the display data writing period (time t2 to t8), multiple sub-pixels need to be written to the display panel in a time-sharing manner, for example, writing to sub-pixel R1 during time t2 to t3, writing to sub-pixel G1 during time t3 to t4, writing to sub-pixel B1 during time t4 to t5, writing to sub-pixel R2 during time t5 to t6, writing to sub-pixel G2 during time t6 to t7, and writing to sub-pixel B2 during time t7 to t8.

[0007] Although the driving voltages used to drive the six sub-pixels are the same, the driving timing is still to write the data to each sub-pixel of the display panel in sequence. Therefore, during the display data writing period (time t2 to t8), the driving circuit remains in the on state, and the system power consumption cannot be effectively reduced. Further improvement is urgently needed. Summary of the Invention

[0008] Therefore, the present invention provides a low-power display driving device and method to solve the above-mentioned problems encountered in the prior art.

[0009] According to a preferred embodiment of the present invention, a low-power display driver device is provided. In this embodiment, the low-power display driver device includes a source driver circuit, a display content detection circuit, and a display timing driver circuit. The output ends of the source driver circuit are respectively coupled to a plurality of sub-pixels of the display panel, wherein a plurality of pixel switches are respectively provided between the output ends and the plurality of sub-pixels. The source driver circuit is respectively coupled to the display timing driver circuit and the power control circuit. The display content detection circuit is coupled to the display timing driver circuit for detecting display content. The display timing driver circuit is respectively coupled to the source driver circuit and the display content detection circuit for changing the driving sequence according to the display content detected by the display content detection circuit, and controlling the opening time of at least two pixel switches among the plurality of pixel switches to overlap with each other, so as to simultaneously drive at least two sub-pixels among the plurality of sub-pixels corresponding to the at least two pixel switches.

[0010] In one embodiment, the source driving circuit writes a specific voltage into the at least two sub-pixels that are turned on simultaneously according to display content.

[0011] In one embodiment, the power control circuit is coupled to the source driving circuit and the display timing driving circuit respectively, and is used to switch the power of a specific circuit or change a specific bias voltage or driving strength to reduce power consumption.

[0012] In one embodiment, the turn-on times of the at least two pixel switches partially overlap.

[0013] In one embodiment, the turn-on times of the at least two pixel switches completely overlap.

[0014] In one embodiment, the turn-on times of the plurality of pixel switches overlap with each other.

[0015] In one embodiment, the display driving device further includes a partition driving circuit, the display panel includes multiple display areas, the partition driving circuit controls the multiple display areas to have the same driving timing, and the display timing driving circuit controls the opening times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

[0016] In one embodiment, the display driving device further includes a partition driving circuit, the display panel includes multiple display areas, the partition driving circuit controls the multiple display areas to have different driving timings, and the display timing driving circuit controls the opening times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

[0017] Another preferred embodiment of the present invention provides a low-power display driving method. The method includes the following steps: coupling the output terminals of a source driver circuit to a plurality of sub-pixels of a display panel; providing a plurality of pixel switches between the output terminals and the plurality of sub-pixels; and coupling the source driver circuit to a display timing driver circuit and a power control circuit, wherein the display timing driver circuit is coupled to the source driver circuit and a display content detection circuit. The display timing driver circuit changes a driving sequence based on display content, controlling the on-times of at least two of the plurality of pixel switches to overlap, thereby simultaneously driving at least two sub-pixels corresponding to the at least two pixel switches.

[0018] In one embodiment, the method further includes the following step: writing a specific voltage into the at least two sub-pixels that are turned on simultaneously according to display content.

[0019] In one embodiment, the method further includes the following steps: the power control circuit switches a specific circuit on or off or changes a specific bias voltage or driving strength to reduce power consumption.

[0020] In one embodiment, the turn-on times of the at least two pixel switches partially overlap.

[0021] In one embodiment, the turn-on times of the at least two pixel switches completely overlap.

[0022] In one embodiment, the turn-on times of the plurality of pixel switches overlap with each other.

[0023] In one embodiment, the display panel includes multiple display areas, the display driving method controls the multiple display areas to have the same driving timing, and the display timing driving circuit controls the opening time of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

[0024] In one embodiment, the display panel includes multiple display areas, the display driving method controls the multiple display areas to have different driving timings, and the display timing driving circuit controls the opening times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

[0025] Compared to the prior art, the low-power display driver device and method proposed in the present invention utilizes simultaneous writing of at least two sub-pixels corresponding to the same drive voltage to complete the writing operation earlier and shut down certain sub-circuits of the display driver integrated circuit (DDIC). Furthermore, the drive waveform and timing can be arbitrarily adjusted and can be combined with a pre-charge compensation drive timing. Furthermore, the entire display panel can be divided into multiple display blocks, each of which can have the same or different drive timings, thereby effectively achieving the goal of reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 1 is a schematic diagram showing a source driving line coupled to a display panel in the prior art.

[0027] Figure 2 A timing diagram for precharging multiple sub-pixels of a display panel in the prior art.

[0028] Figure 3 FIG. 4 is a functional block diagram of a low-power display driving device in a specific embodiment of the present invention.

[0029] Figure 4 A timing diagram for controlling the overlap of the on-times of at least two pixel switches corresponding to the same driving voltage and thereby controlling the length of their on-times.

[0030] Figure 5 This is a schematic diagram of a power control circuit used to switch the power of a specific circuit or change a specific bias voltage or drive strength.

[0031] Figures 6 to 8 They are timing diagrams of different embodiments of the display driving device of the present invention driving a plurality of sub-pixels of a display panel.

[0032] Figure 9 FIG. 1 is a schematic diagram of a display driving device according to the present invention driving different display areas of a display panel.

[0033] Figure 10 FIG. 4 is a flow chart of a low-power display driving method in another embodiment of the present invention.

[0034] Description of main component symbols:

[0035] DDIC…Display Driver Integrated Circuit

[0036] R1, G1, B1, R2, G2, B2… sub-pixels

[0037] SW1~SW6…Pixel switches

[0038] MUX1~MUX6…switch control signal

[0039] S1…source drive line

[0040] t0~t10…time

[0041] SOUT…output signal

[0042] 4…Display driver

[0043] 40…Display content detection circuit

[0044] 42…Display timing drive circuit

[0045] 44…Source driver circuit

[0046] 46…Power supply control circuit

[0047] PL…Display Panel

[0048] OP_EN…enable signal

[0049] VREF…reference voltage

[0050] VDATA…data voltage

[0051] VDD…operating voltage

[0052] VSS…ground voltage

[0053] SW…switch

[0054] OP…Operational amplifier

[0055] RD...Partition drive circuit

[0056] R2n-1, G2n-1, B2n-1, R2n, G2n, B2n… sub-pixels

[0057] MUX1_L~MUX6_L, MUX1_R~MUX6_R...switch control signals

[0058] SW1n~SW6n…Pixel switches

[0059] S10~S14…steps DETAILED DESCRIPTION

[0060] A preferred embodiment of the present invention provides a low-power display driver device. In this embodiment, the display panel can be an active-matrix organic light-emitting diode (AMOLED) display panel or other types of display panels, without particular limitation. When driven by this device, the power consumption of the display panel can be significantly reduced compared to conventional technologies, but the present invention is not limited thereto.

[0061] Figure 3 This is a functional block diagram of the low power display driving device 4 in this embodiment. Figure 3 As shown, the low-power display driving device 4 is coupled to the display panel PL and is used to drive the display panel PL to display images.

[0062] The low-power display driver device 4 includes a display content detection circuit 40, a display timing driver circuit 42, a source driver circuit 44, and a power control circuit 46. The display content detection circuit 40 is coupled to the display timing driver circuit 42. The display timing driver circuit 42 is coupled to the source driver circuit 44 and the power control circuit 46. The source driver circuit 44 is coupled to the display timing driver circuit 42, the power control circuit 46, and the display panel PL. The power control circuit 46 is coupled to the display timing driver circuit 42 and the source driver circuit 44.

[0063] In this embodiment, the output terminals of the source driver circuit 44 are respectively coupled to a plurality of sub-pixels (eg Figure 1 The six sub-pixels R1, G1, B1, R2, G2, and B2 in the source driver circuit 44 may be provided with a plurality of pixel switches (eg, Figure 1 The six switches SW1 to SW6 correspond to the six sub-pixels R1, G1, B1, R2, G2, and B2, respectively, but the present invention is not limited thereto).

[0064] The display content detection circuit 40 is used to detect changes in display content. The display timing driving circuit 42 is used to change the driving timing (e.g. Figure 4 The driving waveforms of the switch control signals MUX1-MUX6 in the plurality of pixel switches are used to control the on-times of at least two pixel switches (e.g., switches SW1 and SW4-SW5, and switches SW2-SW3, but not limited thereto) corresponding to the same driving voltage to overlap with each other (in practice, the overlap may be complete or partial), thereby controlling the length of their on-times.

[0065] It should be noted that if Figure 4As shown, the length of the on-time is controlled because the writing time required to drive only one sub-pixel at a time is shorter (for example, 1μs), but now multiple sub-pixels need to be driven at a time (for example, switches SW1 and SW4~SW5, switches SW2~SW3, but not limited to this), which makes the load heavier and requires a longer writing time (for example, 1.5μs or 2μs). However, the writing action will still be completed 1.5μs earlier than the traditional method of writing six sub-pixels in sequence.

[0066] When the on-times of the at least two pixel switches (e.g., switches SW1-SW6, but not limited thereto) overlap, the source driver circuit 44 simultaneously drives at least two sub-pixels corresponding to the at least two pixel switches (e.g., sub-pixels R1, G1, B1, R2, G2, and B2 corresponding to switches SW1-SW6, but not limited thereto) among the plurality of sub-pixels using a driving voltage determined based on the display content. A power control circuit 46 is coupled to the source driver circuit 44 and the display timing driver circuit 42 to disable specific circuits or change specific bias voltages or driving strengths after the write operation is completed to reduce power consumption.

[0067] For example, if Figure 5 As shown, the power control circuit 46 can control the conduction of the switch SW via the enable signal OP_EN to switch the operational amplifier circuit OP or change the specific bias voltage or driving strength via the reference voltage VREF, but is not limited thereto.

[0068] Next, if Figures 6 to 8 . Figures 6 to 8 They are timing diagrams of different embodiments of the low-power display driving device 4 of the present invention driving multiple sub-pixels of the display panel PL.

[0069] like Figure 6 As shown, in this embodiment, assuming that the driving voltages of the six sub-pixels R1, G1, B1, R2, G2, and B2 of the display panel PL are all the same, the six switch control signals MUX1~MUX6 provided by the source driving circuit 44 can be at a low level at the same time during the period from time t2 to t3 to control the six pixel switches SW1~SW6 corresponding to the six sub-pixels R1, G1, B1, R2, G2, and B2 to be turned on at the same time during the period from time t2 to t3, so that the source driving circuit 44 only needs to be maintained in the started state during the period from time t1 to t4. Therefore, compared with the prior art in which the six pixel switches SW1~SW6 need to be turned on in sequence in a time-sharing manner, which causes the source driving circuit to be maintained in the started state for a long time, this embodiment can indeed significantly shorten the startup time required for the source driving circuit 44, and thus can effectively reduce power consumption.

[0070] like Figure 7As shown, in this embodiment, assuming that the driving voltages of the sub-pixels R1 and B2 of the display panel PL are the same and the driving voltages of the sub-pixels G1 and G2 are the same, the switch control signals MUX1 and MUX6 provided by the source driver circuit 44 can be at a low level at the same time during the period from time t2 to t3 to control the pixel switches SW1 and SW6 corresponding to the sub-pixels R1 and B2 to be turned on at the same time during the period from time t2 to t3, and the switch control signals MUX2 and MUX5 can be at a low level at the same time during the period from time t5 to t6. The switch control signal MUX4 is at a low level during the period t3 to t4 to control the pixel switch SW4 corresponding to the sub-pixel R2 to be turned on during the period t3 to t4. The switch control signal MUX3 is at a low level during the period t4 to t5 to control the pixel switch SW3 corresponding to the sub-pixel B1 to be turned on during the period t4 to t5. Therefore, the source driver circuit 44 only needs to be maintained in the activated state during the period t1 to t7. Therefore, compared with the prior art, in which all pixel switches SW1 to SW6 need to be turned on sequentially in a time-sharing manner, resulting in the source driver circuit needing to remain in the activated state for a long time, this embodiment can indeed shorten the required activation time of the source driver circuit 44, thereby effectively reducing power consumption.

[0071] In practical applications, in addition to the switch driving waveforms of the pixel switches SW1 to SW6, other arbitrary waveform changes can be combined according to actual conditions. For example, a pre-charge waveform (such as Figure 8 As shown, a pre-charge waveform is added during the period from time t1 to t2, but the present invention is not limited thereto), or the driving polarity is reversed, or the time difference between the pre-charge waveform and the turn-on time of the first pixel switch is changed, or the turn-on sequence of the multiple pixel switches is changed, but the present invention is not limited thereto.

[0072] In another embodiment, the display panel PL may include a plurality of display areas, and the display panel PL may be divided into the plurality of display areas vertically or horizontally, but is not limited thereto.

[0073] In practical applications, the display driving device may further include a partition driving circuit (eg Figure 9 The display driver integrated circuit DDIC includes, but is not limited to, a partition driver circuit RD to control the multiple display areas to have the same driving timing. The display timing driver circuit 42 still controls the on-time of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap (actually, the on-time may be completely or partially overlapping) based on the display content, but is not limited to this.

[0074] Similarly, the partitioned driving circuits can also control the multiple display areas to have different driving timings. The display timing driving circuit 42 still controls the on-times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap (actually, this can be complete or partial overlap), but is not limited to this.

[0075] In other words, no matter how many display areas the display panel PL is divided into, the turn-on times of the pixel switches corresponding to two or more sub-pixels corresponding to the same driving voltage in the display panel PL will completely or partially overlap, thereby achieving the purpose of reducing power consumption.

[0076] For example, if Figure 9 As shown, assuming that the display panel PL includes n display areas, the partition driving circuit RD in the display driver integrated circuit DDIC can drive the n display areas of the display panel PL with the same or different driving timings. Assume that the first display area includes sub-pixels R1, G1, B1, R2, G2, B2, . . . and the n-th display area includes sub-pixels R2n-1, G2n-1, B2n-1, R2n, G2n, and B2n. The switch control signals MUX1_L to MUX6_L from the display driver integrated circuit DDIC are used to control the pixel switches SW1 to SW6 corresponding to the sub-pixels R1, G1, B1, R2, G2, and B2 in the first display area, such that the turn-on times of at least two of the pixel switches SW1 to SW6 overlap. Alternatively, the switch control signals MUX1_R to MUX6_R from the display driver integrated circuit DDIC are used to control the pixel switches SW1n to SW6n corresponding to the sub-pixels R2n-1, G2n-1, B2n-1, R2n, G2n, and B2 in the n-th display area, such that the turn-on times of at least two of the pixel switches SW1n to SW6n overlap. However, the present invention is not limited thereto.

[0077] It should be noted that although the above embodiment is described by taking six sub-pixels and their corresponding six pixel switches as an example, the number of sub-pixels and their corresponding pixel switches in actual applications may depend on actual needs and is not limited to the above embodiment.

[0078] Another preferred embodiment of the present invention is a low-power display driving method. It should be noted that when a display panel is driven by the display driving method of this embodiment, its power consumption can be effectively reduced compared to the prior art, but this is not limiting.

[0079] like Figure 10 , Figure 10 This is a flow chart of the low power display driving method in this embodiment. Figure 10 As shown, the low power display driving method may include the following steps:

[0080] Step S10: coupling the output terminals of the source driver circuit to the plurality of sub-pixels of the display panel respectively;

[0081] Step S12: disposing a plurality of pixel switches between the output terminal and the plurality of sub-pixels; and

[0082] Step S14: The source driving circuit is respectively coupled to the display timing driving circuit and the power control circuit. The display timing driving circuit is respectively coupled to the source driving circuit and the display content detection circuit. The display timing driving circuit changes the driving sequence according to the display content, and controls the opening time of at least two pixel switches among the plurality of pixel switches to overlap with each other, so as to simultaneously drive at least two sub-pixels among the plurality of sub-pixels corresponding to the at least two pixel switches.

[0083] In different embodiments, the method may also write a specific voltage to the at least two sub-pixels that are simultaneously turned on according to the display content, but is not limited to this; the power control circuit may switch specific circuits or change specific bias voltages and drive strengths to reduce power consumption, but is not limited to this; the turn-on times of the at least two pixel switches may partially overlap or completely overlap, but is not limited to this; the turn-on times of the multiple pixel switches may also overlap with each other, but is not limited to this.

[0084] In one embodiment, a display panel may include multiple display areas. The display driving method may control the multiple display areas to have the same driving timing. The display timing driving circuit controls the on-times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap, but the present invention is not limited thereto.

[0085] In another embodiment, the display driving method can control the multiple display areas to have different driving timings. The display timing driving circuit controls the on-times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other, but is not limited thereto.

[0086] Compared to the prior art, the low-power display driver device and method proposed in the present invention utilizes simultaneous writing of at least two sub-pixels corresponding to the same drive voltage to complete the writing operation earlier and shut down certain sub-circuits of the display driver integrated circuit (DDIC). Furthermore, the drive waveform and timing can be arbitrarily adjusted and can be combined with a pre-charge compensation drive timing. Furthermore, the entire display panel can be divided into multiple display blocks, each of which can have the same or different drive timings, thereby effectively achieving the goal of reducing power consumption.

Claims

1. A low-power display driver, characterized in that: include: a source driver circuit having an output terminal coupled to a plurality of sub-pixels of a display panel, wherein a plurality of pixel switches are respectively disposed between the output terminal and the plurality of sub-pixels, and the source driver circuit is respectively coupled to a display timing driver circuit and a power control circuit; a display content detection circuit coupled to the display timing driving circuit for detecting display content; as well as The display timing driving circuit is coupled to the source driving circuit and the display content detection circuit respectively, and is used to change the driving sequence according to the display content detected by the display content detection circuit, thereby controlling the opening times of the multiple pixel switches to overlap with each other, thereby simultaneously driving the multiple sub-pixels corresponding to the multiple pixel switches, and the driving voltages of the multiple sub-pixels are all the same.

2. The display driving device according to claim 1, wherein: The source driving circuit writes a specific voltage to the multiple sub-pixels that are turned on simultaneously according to the display content.

3. The display driving device according to claim 1, wherein: The power control circuit is coupled to the source driving circuit and the display timing driving circuit respectively, and is used to switch the power supply of a specific circuit or change a specific bias voltage and driving strength to reduce power consumption.

4. The display driving device according to claim 1, wherein: The turn-on times of the plurality of pixel switches partially overlap.

5. The display driving device according to claim 1, wherein: The turn-on times of the plurality of pixel switches completely overlap.

6. The display driving device according to claim 1, wherein: It also includes a partition driving circuit, wherein the display panel includes multiple display areas, the partition driving circuit controls the multiple display areas to have the same driving timing, and the display timing driving circuit controls the opening time of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

7. The display driving device according to claim 1, wherein: It also includes a partition driving circuit, wherein the display panel includes multiple display areas, the partition driving circuit controls the multiple display areas to have different driving timings, and the display timing driving circuit controls the opening time of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

8. A low-power display driving method, characterized in that: The following steps are involved: coupling an output terminal of a source driving circuit to a plurality of sub-pixels of a display panel respectively; A plurality of pixel switches are respectively provided between the output terminal and the plurality of sub-pixels; as well as The source driver circuit is respectively coupled to a display timing driver circuit and a power control circuit. The display timing driver circuit is respectively coupled to the power control circuit and a display content detection circuit. The display timing driver circuit changes the driving sequence according to the display content and controls the opening times of the multiple pixel switches to overlap with each other, thereby simultaneously driving the multiple sub-pixels corresponding to the multiple pixel switches, and the driving voltages of the multiple sub-pixels are all the same.

9. The display driving method according to claim 8, wherein: The following steps are also included: A specific voltage is written into the multiple sub-pixels that are turned on simultaneously according to the display content.

10. The display driving method according to claim 8, wherein: The following steps are also included: The power control circuit switches specific circuits or changes specific bias voltages and drive strengths to reduce power consumption.

11. The display driving method according to claim 8, wherein: The turn-on times of the plurality of pixel switches partially overlap.

12. The display driving method according to claim 8, wherein: The turn-on times of the plurality of pixel switches completely overlap.

13. The display driving method according to claim 8, wherein: The display panel includes multiple display areas. The display driving method controls the multiple display areas to have the same driving timing. The display timing driving circuit controls the opening times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

14. The display driving method according to claim 8, wherein: The display panel includes multiple display areas. The display driving method controls the multiple display areas to have different driving timings. The display timing driving circuit controls the opening times of at least two pixel switches corresponding to at least two sub-pixels in at least one display area to overlap with each other.

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