A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a display area, a non-display area at least partially surrounding the display area, and a fan-out area; the display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction, and the first direction intersects with the second direction; the non-display area includes a plurality of pads; the fan-out area is disposed on a side of the display area close to the pads, and at least a part of the fan-out area is disposed in the display area. The fan-out area is provided with a plurality of fan-out traces for connecting the data lines to the corresponding pads; the display area includes a plurality of virtual traces; the virtual traces include a first virtual trace extending in the first direction and a second virtual trace extending in the second direction; in a plane parallel to the plane where the substrate is located, the projection of the virtual traces forms a grid structure; the fan-out traces and the virtual traces are insulated from each other. By providing the virtual traces with a projection in a grid structure, the present invention effectively improves the display uniformity of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] Existing display panels tend to be set to be thinner and lighter. For example, a liquid crystal display panel or an organic light-emitting display panel. Compared with a liquid crystal display panel, an organic light-emitting display panel is thinner and lighter, has a better viewing angle and contrast, etc., and thus has received extensive attention.

[0003] An organic light-emitting display panel includes a display area and a non-display area. Pads for receiving a plurality of signals for displaying an image from an external device may be provided in the non-display area. A plurality of fan-out wirings for transmitting signals may be provided in the non-display area or the display area. When the fan-out wirings are provided in the display area, it is beneficial to implement a narrow bezel setting of the display screen and improve the user viewing experience. However, the fan-out wiring also causes uneven light emission of the display panel and is prone to generate spots in the display area. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device to effectively improve the brightness uniformity of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including:

[0006] The display panel includes a display area and at least a part of a non-display area surrounding the display area; the display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction; the second direction intersects the first direction; the scan lines and the data lines intersect to define respective sub-pixel areas; the non-display area includes a plurality of pads;

[0007] Therefore, the display panel further includes a fan-out area; the fan-out area is provided on a side of the display area close to the pads; at least a part of the fan-out area is provided in the display area;

[0008] The fan-out area is provided with a plurality of fan-out wirings for connecting the data lines to the corresponding pads; the display area includes a plurality of virtual wirings; the virtual wirings include first virtual wirings extending in the first direction and second virtual wirings extending in the second direction;

[0009] In a plane parallel to the plane where the substrate is located, a projection of the virtual wiring forms a grid structure; the fan-out wiring is insulated from the virtual wiring.

[0010] In a second aspect, embodiments of the present invention provide a display device, including the display panel according to any one of the first aspect.

[0011] In the present invention, a display panel is provided. The display panel includes a display area and a non-display area at least partially surrounding the display area; the display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction; the second direction intersects the first direction; the scan lines and the data lines intersect to define respective sub-pixel areas; the non-display area includes a plurality of pads; the display panel further includes a fan-out area; the fan-out area is disposed on a side of the display area close to the pads; at least a part of the fan-out area is disposed in the display area, and the fan-out area is provided with a plurality of fan-out traces for connecting the data lines to the corresponding pads, so as to transmit the data signals output from the pads to the data lines, and at the same time reduce the distance between the fan-out area and the data lines; the display area includes dummy traces insulated from the fan-out traces; the dummy traces include first dummy traces extending in the first direction and second dummy traces extending in the second direction; in a plane parallel to the plane of the substrate, the projection of the dummy traces forms a grid structure. In this embodiment, by introducing dummy traces with a grid-structured projection, the light emission of each sub-pixel area in the display area is made more uniform, thereby effectively improving the display uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 3 is Figure 2 a partial structural diagram of the display panel in

[0015] Figure 4 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0016] Figure 5 is a circuit structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0017] Figure 6 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0018] Figure 7 is a circuit structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0019] Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 9 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 10Schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 11 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 12 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0024] Figure 13 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] Figure 14 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Figure 15 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0027] Figure 16 Schematic diagram of a display device provided by an embodiment of the present invention;

[0028] Figure 17 Schematic diagram of another display panel provided by an embodiment of the present invention. Detailed implementation manners

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only the parts related to the present invention are shown in the drawings, rather than all the structures.

[0030] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 1 shown, the display panel 100 includes: a substrate ( Figure 1(not shown in the figure); the display panel 100 includes a display area 101 and a non-display area 102 that at least partially surrounds the display area 101; the display area 101 includes a plurality of scan lines 103 extending along a first direction (such as the X direction in the figure) and a plurality of data lines 104 extending along a second direction (such as the Y direction in the figure); the second direction Y intersects the first direction X; the scan lines 103 and the data lines 104 intersect to define respective sub-pixel areas 105; the non-display area 102 includes a plurality of pads 106; the display panel 100 further includes a fan-out area 107; the fan-out area 107 is disposed on a side of the display area 101 close to the pads 106; at least a part of the fan-out area 107 is disposed in the display area 101; the fan-out area 107 is provided with a plurality of fan-out traces 1071 for connecting the data lines 104 to the corresponding pads 106, and it can be understood that the fan-out traces are used to transmit data signals; the display area 101 includes a plurality of virtual traces 108; the virtual traces 108 include a first virtual trace 1081 extending along the first direction X and a second virtual trace 1082 extending along the second direction Y; in a plane parallel to the plane of the substrate, the projection of the virtual traces 108 forms a grid structure 109; the fan-out traces 1071 are insulated from the virtual traces 108.

[0031] It should be noted that at least a part of the fan-out area 107 being disposed in the display area 101 can be understood as part of the fan-out traces 1071 being located in the display area 101.

[0032] Among them, the display panel 100 includes a substrate ( Figure 1not shown), a driving circuit layer, a light-emitting layer, etc. are sequentially disposed on the substrate. In the plane of the display panel 100 parallel to the substrate, the display panel 100 includes a display area 101 and a non-display area 102 surrounding the display area 101. The display panel further includes a fan-out area 107. In this embodiment, to effectively save the area occupied by the fan-out area 107 in the non-display area 102, part of the fan-out area 107 is disposed in the display area 101. That is, in this embodiment, part of the fan-out area 107 is disposed in the display area 101 and part is disposed in the non-display area 102, thereby further reducing the set area of the fan-out area 107, which is beneficial to the narrow border design of the panel and improves the user experience of the full-screen display. The non-display area 102 includes a plurality of pads 106, and the fan-out area 107 includes a plurality of fan-out traces 1071. One end of the fan-out trace 1071 is connected to the data line 104 in the display area 101, and the other end of the fan-out trace 1071 is connected to the pad 106. The pad 106 is used to bind a driving chip or a flexible circuit board connected with a driving chip, and then transmit the data signal output by the driving chip to the data line 104 through the fan-out trace 1071. At the same time, since part of the fan-out area 107 in the display panel 100 is located in the display area 101, there is no need to set fan-out traces 1071 with a large bending angle to connect with the data lines 104 at the edge of the display panel, thereby effectively reducing the occupied space of the fan-out traces 1071 in the non-display area 102. The display area 101 includes a plurality of scan lines 103 extending along a first direction X and a plurality of data lines 104 extending along a second direction Y. The second direction Y intersects the first direction X. Optionally, the first direction X and the second direction Y may be perpendicular to each other, so that the scan lines 103 and the data lines 104 are insulated and crossed to define a plurality of sub-pixel areas 105, and the sub-pixel areas 105 are used to implement the screen display of the display panel 100. The display area 101 further includes a plurality of virtual traces 108; the virtual traces 108 include a first virtual trace 1081 extending along the first direction X and a second virtual trace 1082 extending along the second direction Y; in the plane parallel to the plane where the substrate is located, the projection of the virtual traces forms a grid structure 109; the fan-out traces 1071 and the virtual traces 108 are insulated, that is, the fan-out traces 1071 and the virtual traces 108 are disconnected, and the projection of the virtual traces 108 overlaps with the metal trace shielding structure in the display panel 100, avoiding the reduction of the normal display area of the display area 101 due to the setting of the virtual traces 108. For example, the projection of the virtual traces 108 may overlap at least partially with the projection of the data lines 104 or the scan lines 103 to effectively increase the light-emitting area of the sub-pixel areas 105 and avoid the virtual traces 108 from affecting the light emission of the sub-pixel areas 105. The fan-out area 107 includes fan-out traces 1071 extending along the first direction X and the second direction Y, such as Figure 1As shown, the same data line 104 is sequentially connected to the fan-out traces 1071 extending along the first direction X and the fan-out traces 1071 extending along the second direction Y, respectively, so that the data signals transmitted on the pad 106 are sequentially transmitted to the data line 104 through the fan-out traces 1071. By setting the fan-out traces 1071 in different directions, while ensuring the data signal transmission effect, it avoids the situation in the prior art where the data line 104 in the edge area needs its corresponding fan-out trace 1071 to bend at a large angle in the non-display area for connection. Instead, the connection between the pad 106 and the data line 104 in the edge area is realized through multiple segments of fan-out traces 1071 in the display area. For example, for a display panel with a large size in the first direction X, 200 data lines 104 in the edge area can be connected to the data line 104 in the edge area through multiple segments of fan-out traces 1071 in the display area, effectively reducing the occupied area of the fan-out traces in the non-display area. In addition, although the fan-out traces 1071 in the fan-out area 107 in the display area 101 will affect the light emission of the display panel to a certain extent, in this embodiment, virtual traces 108 are also provided in the area other than the fan-out area 107 in the display area 101. The virtual traces 108 have the same effect on the light-emitting area of the display panel as the fan-out traces 1071. Therefore, the light-emitting effect in the entire display area 101 in this embodiment is uniform, improving the display effect.

[0033] In the embodiment of the present invention, by providing multiple fan-out traces and multiple virtual traces in the display panel, the virtual traces and some of the fan-out traces are arranged in the display area. The virtual traces include a first virtual trace extending along the first direction and a second virtual trace extending along the second direction; in a plane parallel to the plane of the substrate, the projection of the virtual traces forms a grid structure; the fan-out traces and the virtual traces are insulated from each other, and are realized by using the virtual traces extending in different directions, so that the data signals transmitted through the pads are transmitted to the corresponding data lines. Furthermore, by introducing the virtual traces with a grid-structured projection, the display effect of the display panel is effectively improved.

[0034] Optionally, Figure 2 is a schematic structural diagram of another display panel provided by the embodiment of the present invention. As Figure 2 shown, each sub-pixel area 105 includes at least part of the first virtual trace 1081 and at least part of the second virtual trace 1082.

[0035] Among them, to ensure the overall display uniformity of the display panel 100, in the plane parallel to the substrate, the projections of the virtual traces 108 are uniformly arranged in the entire display area 101, so that the first virtual traces 1081 extending along the first direction X and the second virtual traces 1082 extending along the second direction Y are arranged in the entire display area 101, that is, each sub-pixel area 105 outside the fan-out area 107 in the display area 101 is provided with the first virtual trace 1081 and the second virtual trace 1082. The signals transmitted in the first virtual trace 1081 and the second virtual trace 1082 in the corresponding sub-pixel area 105 can be the same fixed signal or different fixed signals. The specific signal type can be selected according to actual needs, and the embodiments of the present invention do not make specific limitations. To avoid signal coupling of the first virtual trace 1081 and the second virtual trace 1082 in the state of no signal transmission, which affects the display effect of the display panel 100. It should be noted that in addition to the fan-out traces 1071, the fan-out area 107 in the display area 101 may also include virtual traces 108 insulated from the fan-out traces 1071, so that each sub-pixel area 105 in the fan-out area 107 is provided with virtual traces 108 and / or fan-out traces 1071, thereby further improving the uniformity of the display panel.

[0036] Optionally, Figure 3 For Figure 2 a partial structural schematic diagram of the display panel in, as Figure 3 shown, the sub-pixel area 105 includes at least one light-emitting element 110; in the plane parallel to the substrate 111, the projection of the light-emitting element 110 is located within the mesh of the mesh structure 109.

[0037] Among them, the sub-pixel area 105 includes at least one light-emitting element 110, and different sub-pixel areas 105 correspond to light-emitting elements 110 of different colors to achieve color display of the display panel 100. The first virtual traces 1081 extending along the first direction X and the second virtual traces 1082 extending along the second direction Y are arranged in the display area 101 to ensure the overall display uniformity of the display area 101. At the same time, in the plane parallel to the substrate 111, the projection of the light-emitting element 110 is located within the mesh of the mesh structure 109 to avoid the first virtual trace 1081 and the second virtual trace 1082 from blocking the light-emitting area of the light-emitting element 110 and affecting the display effect of the sub-pixel area 105. Optionally, the first virtual trace 1081 and the second virtual trace 1082 can at least partially overlap with other metal layers, thereby reducing the influence of the virtual trace 1081 on the light output of the display panel.

[0038] Optionally, Figure 4 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present invention, Figure 5 is a circuit structural schematic diagram of a pixel driving circuit provided by an embodiment of the present invention, asFigure 4 and Figure 5 As shown in Figure 5 , the sub-pixel region 105 further includes: a pixel driving circuit 112; the pixel driving circuit 112 is electrically connected to the corresponding light-emitting element 110 for providing an operating voltage to the light-emitting element 110; the pixel driving circuit is connected to at least one of the following: a first power signal output terminal PVDD, a second power signal output terminal PVEE, a first reference voltage signal output terminal VREF1, a second reference voltage signal output terminal VREF2, and a third power signal output terminal DVH; the virtual trace 108 receives at least one of the following signals: a first power signal pvdd, a second power signal pvee, a first reference voltage signal vref1, a second reference voltage signal vref2, and a third power signal dvh.

[0039] Among them, the sub-pixel region 105 further includes: a pixel driving circuit 112; the pixel driving circuit 112 can be a 2T1C circuit, that is, a circuit with 2 thin film transistors and 1 storage capacitor, or a 7T1C circuit, that is, a circuit with 7 thin film transistors and 1 storage capacitor, or an 8T1C circuit, that is, a circuit with 8 thin film transistors and 1 storage capacitor, etc. The embodiments of the present invention do not limit the specific structure of the driving circuit. The pixel driving circuit 112 is electrically connected to the corresponding light-emitting element 110, and the pixel driving circuit 112 is used to provide a working voltage for the light-emitting element 110, thereby ensuring normal display. The pixel driving circuit 112 is at least connected to at least one of the following: a first power signal output terminal PVDD, a second power signal output terminal PVEE, a first reference voltage signal output terminal VREF1, a second reference voltage signal output terminal VREF2, and a third power signal output terminal DVH. The first power signal output terminal PVDD is used to output a first power signal pvdd; the second power signal output terminal PVEE is used to output a second power signal pvee. The first power signal pvdd and the second power signal pvee are driving voltages for driving the light-emitting element 110 to emit light. The first power signal pvdd can be a high-level signal, and the second power signal pvee can be a low-level signal; the first reference voltage signal output terminal VREF1 is used to output a first reference voltage signal vref1; the second reference voltage signal output terminal VREF2 is used to output a second reference voltage signal vref2, and the third power signal output terminal DVH is used to output a third power signal dvh to improve the leakage current in the pixel driving circuit 112. The virtual trace 108 accesses at least one of the following signals: the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, and the third power signal dvh. A plurality of virtual traces 108 are arranged in the display area 101. Each virtual trace 108 can access the same signal, or each virtual trace 108 can access different signals, reducing the current attenuation caused by the trace resistance of different signals and effectively improving the display effect of the display panel 100.

[0040] Optionally, continue to refer to Figure 4 and Figure 5, the display area 101 further includes a plurality of pixel driving circuits 112; the pixel driving circuit 112 is electrically connected to the corresponding light-emitting element 110; the pixel driving circuit 112 includes a driving transistor T1, a light-emitting control module 1121, a data writing module 1122, a threshold detection module 1123, a first reset module 1124, a second reset module 1125, and a storage capacitor Cst; the first reset module 1124 operates in response to the first scan signal SCAN1 to connect the control terminal of the driving transistor T1 to the first reference voltage signal output terminal VREF1; the storage capacitor Cst is used to connect the first power signal output terminal PVDD to the control terminal of the driving transistor T1; the data writing module 1122 operates in response to the second scan signal SCAN2 to connect the first terminal of the driving transistor T1 to the corresponding data line 104; the threshold detection module 1123 operates in response to the second scan signal SCAN2 to connect the control terminal of the driving transistor to the second terminal; the light-emitting control module 1121 operates in response to the light-emitting control signal to connect the first terminal of the driving transistor T1 to the first power signal output terminal PVDD, and at the same time connect the second terminal of the driving transistor T1 to the first terminal of the light-emitting element 110; the second terminal of the light-emitting element 110 is connected to the second power signal output terminal PVEE; the second reset module 1125 operates in response to the second scan signal SCAN2 to connect the first terminal of the light-emitting element 110 to the second reference voltage signal output terminal VREF2; the virtual trace 108 is connected to at least one of the following signals: the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, and the second reference voltage signal vref2.

[0041] Among them, when the exemplary pixel driving circuit 112 is a 7T1C circuit, the pixel driving circuit 112 includes a driving transistor T1, a light emission control module 1121, a data writing module 1122, a threshold detection module 1123, a first reset module 1124, a second reset module 1125, and a storage capacitor Cst; the light emission control module 1121 includes a second transistor T2 and a third transistor T3; the data writing module 1122 includes a fourth transistor T4; the threshold detection module 1123 includes a fifth transistor T5; the first reset module 1124 includes a sixth transistor T6, and the second reset module 1125 includes a seventh transistor T7; the output terminal signals of the sixth transistor T6 are connected, the control terminal of the driving transistor T1 is connected to the second terminal of the sixth transistor T6, the first terminal of the driving transistor T1 is respectively connected to the second terminal of the second transistor T2 and the second terminal of the fourth transistor T4, the second terminal of the driving transistor T1 is respectively connected to the first terminal of the third transistor T3 and the second terminal of the fifth transistor T5, the first terminal of the second transistor T2 is connected to the first power signal output terminal PVDD, the control terminals of the second transistor T2 and the third transistor T3 are both connected to the light emission control signal output terminal EM, the second terminal of the third transistor T3 is respectively connected to the first terminal of the light emitting element 110 and the second terminal of the seventh transistor T7, the second terminal of the light emitting element 110 is connected to the second power signal output terminal PVEE, the control terminal of the fourth transistor T4 is connected to the second scan signal SCAN2, the first terminal of the fourth transistor T4 is connected to the data line 104, the control terminal of the fifth transistor T5 is connected to the second scan signal SCAN2, the first terminal of the fifth transistor T5 is connected to the second terminal of the sixth transistor T6, the control terminal of the sixth transistor T6 is connected to the first scan signal SCAN1, the first terminal of the sixth transistor T6 is connected to the first reference voltage signal output terminal VREF1, the control terminal of the seventh transistor T7 is connected to the second scan signal SCAN2, and the first terminal of the seventh transistor T7 is connected to the second reference voltage signal output terminal VREF2. The specific working process of the pixel driving circuit 112 includes a reset stage, a data writing stage, and a light emission stage. Exemplarily, taking the transistors in the pixel driving circuit 112 as PNP transistors that conduct when the level is high and cut off when the level is low as an example for display. In the reset stage, the sixth transistor T6 conducts, and the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are cut off. The first reference voltage signal vref1 output from the first reference voltage signal terminal VREF1 is written into N1 to initialize the control terminal of the driving transistor T1;During the data writing stage, the driving transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned on, while the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned off. The second reference voltage signal vref2 output from the second reference voltage signal terminal Vref2 is written into N4 to initialize the first terminal of the light-emitting element 110. The data signal Vdata output from the data line DATA flows through the fourth transistor T4 to N2, then through the driving transistor T1 to N3, and then through the fifth transistor to N1. During the light-emitting stage, the driving transistor T1, the second transistor T2, and the third transistor T3 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. A current path is formed between the first power signal output terminal PVDD and the second power signal output terminal PVEE, and the light-emitting element 110 is lit. To ensure the display effect of the light-emitting element 110 in the display area 101, the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, or the second reference voltage signal vref2 is connected into the virtual trace 108 around the projection of the light-emitting element 110, reducing the current attenuation caused by the trace resistance of different signals, thereby effectively improving the display effect of the display panel 100.

[0042] Optionally, Figure 6 FIG. is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present invention. Figure 7 FIG. is a schematic circuit diagram of another pixel driving circuit provided by an embodiment of the present invention, as Figure 6 and Figure 7 shown, the pixel driving circuit 112 further includes: a leakage improvement module 1126; the leakage improvement module 1126 operates in response to the first scan signal SCAN1 to connect the third power signal output terminal DVH to the first terminal of the driving transistor T1; the virtual trace 108 is connected to at least one of the following signals: the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, and the third power signal dvh.

[0043] Wherein, Figure 4 the driving transistor T1, the light-emitting control module 1121, the data writing module 1122, the threshold detection module 1123, the first reset module 1124, the second reset module 1125, and the storage capacitor Cst in the pixel driving circuit 112 in Figure 6 are the same as the driving transistor T1, the light-emitting control module 1121, the data writing module 1122, the threshold detection module 1123, the first reset module 1124, the second reset module 1125, and the storage capacitor Cst of the pixel driving circuit 112 in Figure 6 and Figure 7The pixel driving circuit further includes a leakage improvement module 1126. The leakage improvement module 1126 includes an eighth transistor T8. The control terminal of the eighth transistor T8 is connected to the first scan signal SCAN1. The second terminal of the eighth transistor T8 is respectively connected to the first terminal of the driving transistor T1 and the second terminal of the fourth transistor T4. The first terminal of the eighth transistor T8 is connected to the third power signal output terminal DVH. Exemplarily, taking the transistors in the pixel driving circuit 112 as PNP transistors that conduct when the input is high and cut off when the input is low as an example, in the reset stage, the eighth transistor T8 conducts, and the third power signal dvh is written into N2 to improve the leakage current phenomenon of the driving transistor T1. In the data writing stage and the light emitting stage, the eighth transistor T8 is in the cut-off state, and the remaining working processes are the same as those of the Figure 5 working process of the pixel driving transistor T1 in the above, and will not be elaborated here again. For the light emitting element 110 in the display panel 100, an 8T1C circuit is used for driving. At this time, to ensure the display effect of the light emitting element 110 in the display area 101, the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, or the third power signal dvh is connected into the virtual trace 108 around the projection of the light emitting element 110, reducing the current attenuation caused by the existence of the trace resistance of different signals, and thus effectively improving the display effect of the display panel 100.

[0044] Optionally, Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 8 shown, the first virtual trace 1081 and the second virtual trace 1082 are arranged on the same layer and electrically connected to form a grid structure 109; the virtual trace 108 is connected to the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, or the third power signal dvh.

[0045] Among them, the first virtual trace 1081 and the second virtual trace 1082 are arranged on the same layer and are formed by etching the same layer of metal to form the grid structure 109. At this time, the first virtual trace 1081 and the second virtual trace 1082 are electrically connected; to ensure the normal display of the display area 101 and avoid the current attenuation caused by the existence of the resistance of the virtual trace 108, the first virtual trace 1081 and the second virtual trace 1082 can be connected to the same fixed signal. The fixed signal can be the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, or the third power signal dvh. When ensuring the display effect of the display panel 100, it also effectively reduces the complexity of signal access and simplifies the manufacturing process of the display panel 100.

[0046] Optionally, Figure 9 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 9 shown, a first virtual trace 1081 is disposed on a first metal layer 113; a second virtual trace 1082 is disposed on a second metal layer 114; an insulating layer 115 is disposed between the first metal layer 113 and the second metal layer 114; the first virtual trace 1081 and the second virtual trace 1082 are electrically connected through the insulating layer 115; the virtual trace 108 is connected to a first power signal pvdd, a second power signal pvee, a first reference voltage signal vref1, a second reference voltage signal vref2, or a third power signal dvh.

[0047] Among them, the first virtual trace 1081 and the second virtual trace 1082 may be located on different layers, that is, the first virtual trace 1081 is disposed on the first metal layer 113, and the second virtual trace 1082 is disposed on the second metal layer 114; the first metal layer 113 and the second metal layer 114 may be additionally provided metal film layers, or the first metal layer 113 and the second metal layer 114 may be multiplexed from metal film layers such as the electrode plate layer 118 or the source-drain electrode layer 119 in the display panel 100, avoiding additional metal film layers and reducing the manufacturing cost. Exemplarily Figure 9 Taking the case where both the first metal layer 113 and the second metal layer 114 are additionally provided metal film layers as an example for display, an insulating layer 115 is disposed between the first metal layer 113 and the second metal layer 114. When the same fixed signal is connected to the first virtual trace 1081 and the second virtual trace 1082, holes are drilled in the insulating layer 115 to achieve electrical connection between the first virtual trace 1081 and the second virtual trace 1082, ensuring that the fixed signal can be the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, or the third power signal dvh, and further ensuring that the fixed signal can be transmitted in the first virtual trace 1081 and the second virtual trace 1082, and further ensuring normal display of the display area 101.

[0048] Optionally, continue to refer to Figure 9, the first virtual trace 1081 is disposed on the first metal layer 113; the second virtual trace 1081 is disposed on the second metal layer 114; the first virtual trace 1081 and the second virtual trace 1082 are insulated from each other; the first virtual trace 1081 is connected to the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, or the third power signal dvh; the second virtual trace 1082 is connected to a signal different from that of the first virtual trace 1081 among the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, and the third power signal dvh.

[0049] Among them, the first virtual trace 1081 and the second virtual trace 1082 can be located on different layers, that is, the first virtual trace 1081 is disposed on the first metal layer 113, and the second virtual trace 1082 is disposed on the second metal layer 114. To avoid short - circuit between the first virtual trace 1081 and the second virtual trace 1082, insulation is provided between the first virtual trace 1081 and the second virtual trace 1082. To ensure the display uniformity of the display area 101 in the display panel 100, the above - mentioned fixed signals can be connected to the first virtual trace 1081 and the second virtual trace 1082 to reduce the current attenuation caused by the trace resistance of different signals. At this time, since the first virtual trace 1081 and the second virtual trace 1082 are set on different layers, different fixed signals can be connected to the first virtual trace 1081 and the second virtual trace 1082 respectively. The first virtual trace 1081 and the second virtual trace 1082 are respectively connected to different signals selected from the first power signal pvdd, the second power signal pvee, the first reference voltage signal vref1, the second reference voltage signal vref2, or the third power signal dvh to improve the display effect of the display panel.

[0050] Optionally, Figure 10 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as Figure 10As shown, the display panel 100 includes: a substrate 111; a first gate layer 116 disposed on one side of the substrate 111; a gate layer of a first thin film transistor 117 and a first electrode plate of a storage capacitor Cst provided in a sub-pixel region 105; an electrode plate layer 118 disposed on a side of the first gate layer 116 away from the substrate 111, and a second electrode plate of the storage capacitor Cst is provided; a second reference voltage signal line 12 extending along a first direction X; a source-drain layer 119 disposed on a side of the electrode plate layer 118 away from the substrate 111, and a source and a drain of the first thin film transistor 117 are provided; a third metal layer 120 disposed on a side of the source-drain layer 119 away from the substrate 111, and a first virtual trace 1081 extending along the first direction X is provided; the first virtual trace 1081 is connected to a first reference voltage signal vref1; the absolute value of the first reference voltage signal vref1 is greater than the absolute value of the second reference voltage signal vref2.

[0051] Among them, the substrate 111 can be a flexible substrate or a rigid substrate, and the constituent materials of the substrate 111 include one or more combinations of polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The pixel driving circuit 112 for driving the light-emitting element 110 to emit light includes a first thin-film transistor 117 and a storage capacitor Cst. The first thin-film transistor 117 is a bottom-gate thin-film transistor. The first thin-film transistor 117 includes a first gate layer 116 forming a gate layer and a source-drain layer 119 for source and drain electrodes arranged in sequence. The first gate layer 116 is also multiplexed as the first electrode plate for forming the storage capacitor Cst. An electrode plate layer 118 is provided on the side of the first gate layer 116 away from the substrate 111 to form the second electrode plate of the storage capacitor Cst. At the same time, a reference voltage line can also be provided on the electrode plate layer 118, that is, a second reference voltage signal line 12 extending along the first direction X is provided; a third metal layer 120 is provided on the side of the source-drain layer 119 away from the substrate 111, and a first virtual trace 1081 extending along the first direction X is provided on the third metal layer 120; the first virtual trace 1081 is connected to the first reference voltage signal vref1; since the constituent material of the electrode plate layer 118 forming the storage capacitor Cst is molybdenum, and the constituent material of the third metal layer 120 is titanium-aluminum-titanium composite metal, during the display process of the display panel 100, since the absolute value of the first reference voltage signal vref1 is greater than the absolute value of the second reference voltage signal vref2, for example, the first reference voltage signal vref1 is used to reset the driving transistor in the pixel driving circuit 112, and the second reference voltage signal vref2 is used to reset the first end of the light-emitting element 110. The first reference voltage signal vref1 is -3.5V, and the second reference voltage signal vref2 is -3V. During the signal transmission process, the signal transmission time is the same. The first reference voltage signal vref1 becomes -3V, and the second reference voltage signal vref2 becomes -2.7V. The voltage drop loss of the first reference voltage signal vref1 is relatively large. The conductivity of the third metal layer 120 is higher than that of the electrode plate layer 118. At this time, transmitting the first reference voltage signal vref1 in the third metal layer 120 is beneficial to the reset uniformity of the reset stage during the operation of the pixel driving circuit 112, thereby balancing the charging time of each display area and further improving the display uniformity of the display panel 100.

[0052] Optionally, continuing to refer to Figure 10 , a second reference voltage signal line 12 extending along the second direction Y and a second virtual trace 1082 extending along the second direction Y are further provided on the source-drain layer 119; the second virtual trace 1082 of the source-drain layer 119 is connected to the first reference voltage signal vref1.

[0053] Among them, in addition to setting the source-drain layer, the source-drain layer 119 may also be provided with a plurality of second reference voltage signal lines 12 extending along the second direction Y and second virtual signal lines extending along the second direction Y. At this time, the third metal layer 120 is provided with a first virtual trace 1081 extending along the first direction X, and the source-drain layer 119 is provided with a second virtual trace 1082 extending along the second direction Y. The first reference voltage signal vref1 is connected to both the first virtual trace 1081 and the second virtual trace 1082. At this time, after the first reference voltage signal vref1 is transmitted along the first direction X in the third metal layer 120, it is transmitted along the second direction Y in the source-drain layer 119 through a via. At the same time, the second reference voltage signal vref2 is first transmitted along the first direction X in the electrode plate layer 118 and then transmitted along the second direction Y in the source-drain layer 119 through a via. In a plane parallel to the substrate 111, the projections of the first virtual trace 1081 and the second virtual trace 1082 form a grid structure 109, and the projection of the second reference voltage signal line 12 also forms a grid structure 109. The projection of the virtual trace 108 does not overlap with that of the second reference unit signal line, forming a multi-layer grid structure in space. The multi-layer grid structure 109 is arranged around the light-emitting element 110, effectively reducing the coupling capacitance, preventing crosstalk between signals, and playing a certain shielding role.

[0054] Optionally, Figure 11 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 11 shown, the display panel 100 further includes: an insulating layer 115 disposed on a side of the third metal layer 120 away from the substrate 111; a fourth metal layer 121 disposed on a side of the insulating layer 115 away from the substrate 111, and is provided with a second virtual trace 1082 extending along the second direction Y; at least a part of the second virtual trace 1082 in the fourth metal layer 121 is connected to the first reference voltage signal vref1.

[0055] Based on the above embodiments, a fourth metal layer 121 is disposed on the side of the third metal layer 120 away from the substrate 111, and the third metal layer 120 and the fourth metal layer 121 are insulated by providing an insulating layer 115. A plurality of second virtual traces 1082 extending in the second direction Y are provided in the fourth metal layer 121. When a part of the second virtual traces 1082 in the fourth metal layer 121 is connected to the first reference voltage signal vref1, the first reference voltage signal vref1 connected to the virtual trace 108 first travels along the first direction X in the third metal layer 120, and then travels along the second direction Y in the source-drain layer 119 through a via, and then travels along the second direction Y in the fourth metal layer 121 through a via. In a plane parallel to the substrate 111, the projections of the first virtual trace 1081 and the second virtual trace 1082 form a multi-layer grid structure 109. The virtual traces 108 are connected in parallel to reduce the resistance of the virtual traces 108 and ensure the display effect of the display panel 100.

[0056] Optionally, continue to refer to Figure 11 , a part of the second virtual traces 1082 in the fourth metal layer 121 is connected to the second reference voltage signal vref2; in the fourth metal layer 121, the second virtual traces 1082 connected to the first reference voltage signal vref1 and the second virtual traces 1082 connected to the second reference voltage signal vref2 are insulated from each other.

[0057] Based on the above, a plurality of second virtual traces 1082 extending in the second direction Y are provided in the fourth metal layer 121. When a part of the second virtual traces 1082 in the fourth metal layer 121 is connected to the second reference voltage signal vref2, to avoid signal crosstalk, the second virtual traces 1082 connected to the second reference voltage signal vref2 in the fourth metal layer 121 and the second virtual traces 1082 connected to the first reference voltage signal vref1 in the fourth metal layer 121 are insulated from each other. The second reference voltage signal vref2 first travels along the first direction X in the electrode plate layer 118 and then travels along the second direction Y in the source-drain layer 119 through a via, and then travels along the second direction Y in the fourth metal layer 121 through a via. In a plane parallel to the substrate 111, the projection of the second reference voltage signal line 12 also forms a grid structure 109, which cooperates with the projections of the first virtual trace 1081 and the second virtual trace 1082 to form a multi-layer grid structure 109. The traces of each layer are connected in parallel to reduce the resistance, and at the same time further improve the shielding effect, effectively reduce the coupling capacitance, and ensure the display effect of the display panel 100.

[0058] Optionally, Figure 12 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as shown in Figure 12As shown, in the fourth metal layer 121, the number of second virtual traces 1082 connected to the first reference voltage signal vref1 is greater than the number of second virtual traces 1082 connected to the second reference voltage signal vref2.

[0059] Among them, because the voltage drop loss of the first reference voltage signal vref1 is relatively large during signal transmission, by making the number of second virtual traces 1082 connected to the first reference voltage signal vref1 in the fourth metal layer 121 greater than the number of second virtual traces 1082 connected to the second reference voltage signal vref2, the number of second virtual traces 1082 connected to the first reference voltage signal vref1 is adaptively increased, further reducing the voltage drop loss of the first reference voltage signal vref1, balancing the charging time of each display area, and improving the display uniformity of the display panel 100.

[0060] Optionally, Figure 13 FIG. is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 13 shown, along the first direction X, the second virtual traces 1082 extending along the second direction Y and the second reference voltage signal lines 12 are alternately arranged; along the second direction Y, the first virtual traces 1081 extending along the first direction X and the second reference voltage signal lines 12 are alternately arranged; along the first direction X, the i-th column of sub-pixel regions 105 and the (i + 1)-th column of sub-pixel regions 105 share the first reference voltage signal vref1 output by the second virtual trace 1082; the (i + 1)-th column of sub-pixel regions 105 and the (i + 2)-th column of sub-pixel regions 105 share the second reference voltage signal line 12; 1 ≤ i ≤ N - 2; N is the total number of columns of sub-pixel regions.

[0061] Among them, in the first direction X, a plurality of second virtual traces 1082 and a plurality of second reference voltage signal lines 12 are provided, and the second virtual traces 1082 and the second reference voltage signal lines 12 are alternately arranged. At this time, the first column of sub-pixel regions 105 and the second column of sub-pixel regions 105 share the second virtual trace 1082, and the first reference voltage signal vref1 is transmitted in the second virtual trace 1082. At this time, the first reference voltage signal vref1 can reset the gates of the driving transistors T1 in the first column of sub-pixel regions 105 and the second column of sub-pixel regions 105 respectively; the second column of sub-pixel regions 105 and the third column of sub-pixel regions 105 share the second reference voltage signal line 12, and the second reference voltage signal vref2 is transmitted in the second reference voltage signal line 12. The second reference voltage signal vref2 can reset the first ends of the corresponding light-emitting elements 110 of each sub-pixel region 105 in the second column respectively, effectively saving the layout space of the sub-pixel regions 105. The active layers 21 of adjacent sub-pixel regions 105 can be connected along the first direction X, thereby improving the electrical uniformity of the thin-film transistors in the sub-pixel regions 105. At the same time, the virtual traces 108 are connected in parallel, reducing the resistance of the virtual traces 108 and ensuring the display uniformity of the display panel 100.

[0062] Optionally, Figure 14 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 14 shown, along the first direction X, the second virtual traces 1082 extending along the second direction Y and the second reference voltage signal lines 12 are alternately arranged; along the second direction Y, the first virtual traces 1081 extending along the first direction X and the second reference voltage signal lines 12 are alternately arranged; along the second direction Y, the p-th row of sub-pixel regions 105 share the first reference voltage signal vref1 output by the first virtual trace 1081; the (p + 1)-th row of sub-pixel regions 105 share the second reference voltage signal line 12; 1 ≤ p ≤ M - 1; M is the total number of rows of sub-pixel regions.

[0063] Among them, in the second direction Y, multiple first virtual traces 1081 and multiple second reference voltage signal lines 12 are provided. The first virtual traces 1081 and the second reference voltage signal lines 12 are arranged alternately. At this time, each sub-pixel region 105 in the first row shares the first virtual trace 1081, and the first reference voltage signal vref1 is transmitted in the first virtual trace 1081. At this time, the first reference voltage signal vref1 can reset the first ends of the corresponding light-emitting elements 110 in each sub-pixel region 105 in the first row respectively; each sub-pixel region 105 in the second column shares the second reference voltage signal line 12, and the second reference voltage signal vref2 is transmitted in the second reference voltage signal line 12. The second reference voltage signal vref2 can reset the gates of the corresponding driving transistors T1 in each sub-pixel region 105 in the second column respectively, effectively saving the layout space of the sub-pixel region 105. The active layers 21 of adjacent sub-pixel regions 105 can be connected along the first direction X, thereby improving the electrical uniformity of the thin-film transistors in the sub-pixel region 105; at the same time, each virtual trace 108 is connected in parallel, reducing the resistance of the virtual trace 108 and ensuring the display uniformity of the display panel 100.

[0064] Optionally, Figure 15 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 15 shown, the display panel 100 includes: a substrate 111; a first gate layer 116 disposed on one side of the substrate 111; a gate layer of the first thin-film transistor 117 and a first electrode plate of the storage capacitor Cst are provided in the sub-pixel region; an electrode plate layer 118 disposed on the side of the first gate layer 116 away from the substrate 111, a second electrode plate of the storage capacitor Cst and a reference voltage signal line 13 are provided; a source-drain layer 119 disposed on the side of the electrode plate layer 118 away from the substrate 111, a source and a drain of the first thin-film transistor 117, and a reference voltage signal line 13 are provided; a first planarization layer 122 disposed on the side of the source-drain layer 119 away from the substrate 111; a fifth metal layer 123 disposed on the side of the first planarization layer 122 away from the substrate 111, and a first virtual trace 1081 is provided; a second planarization layer 124 disposed on the side of the fifth metal layer 123 away from the substrate 111; a sixth metal layer 125 disposed on the side of the second planarization layer 124 away from the substrate 111; a second virtual trace 1082 is provided; the first virtual trace 1081 and the second virtual trace 1082 are both connected to the third power signal dvh.

[0065] Among them, when the pixel driving circuit 112 in the sub-pixel region 105 is an 8T1C circuit, the display panel 100 is sequentially provided with a substrate 111, a first gate layer 116, an electrode plate layer 118, a source-drain layer 119, a first planarization layer 122, a fifth metal layer 123, a second planarization layer 124, and a sixth metal layer 125. The first gate layer 116 is provided with the gate of the first thin-film transistor 117 and the first electrode plate of the storage capacitor Cst. The electrode plate layer 118 is provided with the second electrode plate of the storage capacitor Cst and a reference voltage line. The source-drain layer 119 is provided with the source and drain of the first thin-film transistor 117 and a reference voltage line. The first planarization layer 122 and the second planarization layer 124 are used to balance the step difference between the film layers. A plurality of first virtual traces 1081 are provided in the fifth metal layer 123, and a plurality of second virtual traces 1082 are provided in the sixth metal layer 125. In the plane parallel to the substrate 111, the projections of the first virtual traces 1081 and the second virtual traces 1082 form a grid structure 109. The same fixed signal is connected to both the first virtual traces 1081 and the second virtual traces 1082. The fixed signal can be a third power signal dvh, and the third power signal dvh is output from the third power signal output terminal DVH of the eighth transistor T8, thereby ensuring the normal display of the display area 101.

[0066] Optionally, continue to refer to Figure 15 , a second gate layer 126 is further provided between the electrode plate layer 118 and the source-drain layer; a gate layer of the second thin-film transistor 127 in the sub-pixel region is provided; the first thin-film transistor 117 is a P-type thin-film transistor; the second thin-film transistor 127 is an N-type thin-film transistor.

[0067] Among them, a second gate layer 126 is further provided between the electrode plate layer 118 and the source-drain layer 119; the second thin-film transistor 127 in the sub-pixel region includes the second gate layer 126, and the second gate layer 126 is located on the side of the gate layer of the first thin-film transistor 117 away from the substrate 111. The source and drain of the first thin-film transistor 117 and the second thin-film transistor 127 can be fabricated on the same layer. The active layer of the first thin-film transistor 117 is low-temperature polycrystalline silicon, and the first thin-film transistor 117 is a P-type thin-film transistor; the active layer of the second thin-film transistor 127 is an oxide, and the second thin-film transistor 127 is an N-type thin-film transistor.

[0068] Optionally, continue to refer to Figure 15 , the first virtual trace 1081 and the second virtual trace 1082 are electrically connected through the second planarization layer 124.

[0069] Among them, since the first virtual routing line 1081 is disposed on the fifth metal layer 123, the first virtual routing line 1081 is disposed on the sixth metal layer 125, and the first virtual routing line 1081 and the second virtual routing line 1082 are disposed on different layers. To achieve electrical connection between the first virtual routing line 1081 and the second virtual routing line 1082, vias can be disposed in the second planarization layer 124, so as to transmit the same third power signal dvh within the first virtual routing line 1081 and the second virtual routing line 1082.

[0070] Optionally, Figure 16 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 16 shown, the fan-out routing line 1071 in the display area 101 includes a third virtual routing line 1083 extending along the first direction X and a fourth virtual routing line 1084 extending along the second direction Y; the third virtual routing line 1083 is disposed on the same layer as the first virtual routing line 1081; the fourth virtual routing line 1084 is disposed on the same layer as the second virtual routing line 1082; the third virtual routing line 1083 and the fourth virtual routing line 1084 are electrically connected through the second planarization layer 124; the part of the fan-out routing line 1071 extending to the non-display area 102 is transformed to the first gate layer 116 or the electrode plate layer 118.

[0071] Among them, the fan-out routing line 1071 in the display area 101 includes a third virtual routing line 1083 extending along the first direction X and a fourth virtual routing line 1084 extending along the second direction Y; the third virtual routing line 1083 is disposed on the same layer as the first virtual routing line 1081, and the third virtual routing line 1083 and the first virtual routing line 1081 can transmit the same signal or different signals; the fourth virtual routing line 1084 is disposed on the same layer as the second virtual routing line 1082, and the third virtual routing line 1083 and the first virtual routing line 1081 can transmit the same signal or different signals; the third virtual routing line 1083 and the fourth virtual routing line 1084 are disposed on different layers, and the third virtual routing line 1083 and the fourth virtual routing line 1084 are electrically connected through the second planarization layer 124, so that the same signal is transmitted in the mutually electrically connected third virtual routing line 1083 and fourth virtual routing line 1084. The part of the fan-out routing line 1071 extending to the non-display area 102 is transformed to the first gate layer 116 or the electrode plate layer 118. The fan-out routing line 1071 is disposed in the film layer of the display panel 100, ensuring that the fan-out routing line 1071 extends from the non-display area 102 of the display panel 100 to the display area 101 of the display panel 100. By multiplexing the virtual routing line 108 as part of the fan-out routing line 1071 in the display area 101, the difference in the connection distance between the fan-out routing line 1071 and the data lines 104 at different positions is reduced, while ensuring the normal display effect of the display panel 100.

[0072] An embodiment of the present invention further provides a display device, which includes any one of the display panels provided in the above embodiments. Exemplarily, as Figure 17 shown, the display device 200 includes the display panel 100 provided in any embodiment of the present invention. Therefore, the display device also has the beneficial effects of the display panel in the above embodiments. For the same parts, reference may be made to the explanation of the display panel above, and details will not be repeated hereinafter.

[0073] The display device 200 provided by the embodiment of the present invention may be Figure 17 the mobile phone shown, or any electronic product with a display function, including but not limited to the following categories: televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted displays, industrial control devices, medical display screens, touch interaction terminals, etc. The embodiments of the present invention do not make special limitations thereto.

[0074] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it may include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, Comprising: A substrate; The display panel includes a display area and at least a partially non-display area surrounding the display area; the display area includes a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction; the second direction intersects the first direction; the scan lines and the data lines intersect to define respective sub-pixel areas; the non-display area includes a plurality of pads; Therefore, the display panel further includes a fan-out area; the fan-out area is disposed on a side of the display area close to the pads; at least a part of the fan-out area is disposed in the display area; The fan-out area is provided with a plurality of fan-out traces for connecting the data lines to the corresponding pads; the display area includes a plurality of virtual traces, and a part of the virtual traces is multiplexed as a part of the fan-out traces located in the display area; the virtual traces include a first virtual trace extending in the first direction and a second virtual trace extending in the second direction; The virtual trace further includes a third virtual trace extending in the first direction, the third virtual trace is multiplexed as a part of the fan-out traces located in the display area, the third virtual trace and the first virtual trace are disposed on the same layer, and the third virtual trace and the first virtual trace transmit different signals; and / or, the virtual trace further includes a third virtual trace extending in the first direction and a fourth virtual trace extending in the second direction, the third virtual trace and the fourth virtual trace are multiplexed as a part of the fan-out traces located in the display area, the third virtual trace and the first virtual trace are disposed on the same layer, the fourth virtual trace and the second virtual trace are disposed on the same layer, the third virtual trace and the fourth virtual trace transmit the same signal, and the first virtual trace and the second virtual trace transmit the same signal; In a plane parallel to the plane of the substrate, a projection of the virtual trace forms a grid structure; the fan-out traces not multiplexed by the virtual trace are insulated from the virtual trace.

2. The display panel according to claim 1, characterized in that, Each sub-pixel area includes at least a part of the first virtual trace and at least a part of the second virtual trace.

3. The display panel according to claim 1, characterized in that, The sub-pixel area includes at least one light-emitting element; in a plane parallel to the plane of the substrate, a projection of the light-emitting element is located within a mesh of the grid structure.

4. The display panel according to claim 3, characterized in that, The sub-pixel area further includes: a pixel driving circuit; the pixel driving circuit is electrically connected to the corresponding light-emitting element for providing a working voltage for the light-emitting element; The pixel driving circuit is connected to at least one of the following: a first power signal output terminal, a second power signal output terminal, a first reference voltage signal output terminal, a second reference voltage signal output terminal, and a third power signal output terminal; The virtual trace accesses at least one of the following signals: a first power signal, a second power signal, a first reference voltage signal, a second reference voltage signal, and a third power signal.

5. The display panel according to claim 1, characterized in that, The display area further includes a plurality of pixel driving circuits; the pixel driving circuits are electrically connected to the corresponding light-emitting elements; The pixel driving circuit includes a driving transistor, a light-emitting control module, a data writing module, a threshold detection module, a first reset module, a second reset module, and a storage capacitor; the first reset module operates in response to a first scan signal to connect the control terminal of the driving transistor to a first reference voltage signal output terminal; the storage capacitor is used to connect a first power signal output terminal to the control terminal of the driving transistor; the data writing module operates in response to a second scan signal to connect the first end of the driving transistor to a corresponding data line; the threshold detection module operates in response to the second scan signal to connect the control terminal of the driving transistor to the second end; the light-emitting control module operates in response to a light-emitting control signal to connect the first end of the driving transistor to the first power signal output terminal, and at the same time connect the second end of the driving transistor to the first end of the light-emitting element; the second end of the light-emitting element is connected to a second power signal output terminal; the second reset module operates in response to the second scan signal to connect the first end of the light-emitting element to a second reference voltage signal output terminal; The virtual trace accesses at least one of the following signals: a first power signal, a second power signal, a first reference voltage signal, and a second reference voltage signal.

6. The display panel according to claim 5, characterized in that, The pixel driving circuit further includes: a leakage improvement module; the leakage improvement module operates in response to the first scan signal to connect a third power signal output terminal to the first end of the driving transistor; The virtual trace accesses at least one of the following signals: a first power signal, a second power signal, a first reference voltage signal, a second reference voltage signal, and a third power signal.

7. The display panel according to claim 1, characterized in that, The first virtual trace and the second virtual trace are arranged on the same layer and electrically connected to form a grid structure; The virtual trace accesses a first power signal, a second power signal, a first reference voltage signal, a second reference voltage signal, or a third power signal.

8. The display panel according to claim 1, characterized in that, The first virtual trace is arranged on a first metal layer; the second virtual trace is arranged on a second metal layer; an insulating layer is arranged between the first metal layer and the second metal layer; The first virtual trace and the second virtual trace are electrically connected through the insulating layer; The virtual trace accesses a first power signal, a second power signal, a first reference voltage signal, a second reference voltage signal, or a third power signal.

9. The display panel according to claim 1, characterized in that, The first virtual trace is arranged on a first metal layer; the second virtual trace is arranged on a second metal layer; the first virtual trace and the second virtual trace are insulated from each other; The first virtual trace accesses a first power signal, a second power signal, a first reference voltage signal, a second reference voltage signal, or a third power signal; the second virtual trace accesses a signal different from that of the first virtual trace among the first power signal, the second power signal, the first reference voltage signal, the second reference voltage signal, and the third power signal.

10. The display panel according to claim 1, characterized in that, Including: The substrate; A first gate layer, arranged on one side of the substrate; the gate layer of the first thin-film transistor in the sub-pixel area and the first electrode plate of the storage capacitor are provided; The electrode plate layer is disposed on a side of the first gate layer away from the substrate and is provided with a second electrode plate of the storage capacitor; a second reference voltage signal line extending along the first direction; The source-drain layer is disposed on a side of the electrode plate layer away from the substrate and is provided with a source and a drain of a first thin film transistor; The third metal layer is disposed on a side of the source-drain layer away from the substrate and is provided with the first virtual trace extending along the first direction; the first virtual trace is connected to a first reference voltage signal; The absolute value of the first reference voltage signal is greater than the absolute value of the second reference voltage signal.

11. The display panel according to claim 10, wherein, The source-drain layer is further provided with a second reference voltage signal line extending along the second direction and a second virtual trace extending along the second direction; the second virtual trace of the source-drain layer is connected to the first reference voltage signal.

12. The display panel according to claim 10, wherein, It further includes: An insulating layer is disposed on a side of the third metal layer away from the substrate; The fourth metal layer is disposed on a side of the insulating layer away from the substrate and is provided with a second virtual trace extending along the second direction; At least a part of the second virtual traces in the fourth metal layer are connected to the first reference voltage signal.

13. The display panel according to claim 12, wherein, A part of the second virtual traces in the fourth metal layer are connected to the second reference voltage signal; In the fourth metal layer, the second virtual traces connected to the first reference voltage signal are insulated from the second virtual traces connected to the second reference voltage signal.

14. The display panel according to claim 13, wherein, In the fourth metal layer, the number of the second virtual traces connected to the first reference voltage signal is greater than the number of the second virtual traces connected to the second reference voltage signal.

15. The display panel according to claim 11, wherein, Along the first direction, the second virtual traces and the second reference voltage signal lines extending along the second direction are alternately arranged; along the second direction, the first virtual traces and the second reference voltage signal lines extending along the first direction are alternately arranged; Along the first direction, the first reference voltage signal output by the second virtual trace is shared by the i-th column sub-pixel region and the (i + 1)-th column sub-pixel region; the (i + 1)-th column sub-pixel region and the (i + 2)-th column sub-pixel region share the second reference voltage signal line; 1 ≤ i ≤ N - 2; N is the total number of columns of the sub-pixel regions.

16. The display panel according to claim 11, wherein, Along the first direction, the second virtual traces and the second reference voltage signal lines extending along the second direction are alternately arranged; along the second direction, the first virtual traces and the second reference voltage signal lines extending along the first direction are alternately arranged; Along the second direction, the first reference voltage signal output by the first virtual trace is shared by the p-th row sub-pixel regions; the (p + 1)-th row sub-pixel regions share the second reference voltage signal line; 1 ≤ p ≤ M - 1; M is the total number of rows of the sub-pixel regions.

17. The display panel according to claim 1, wherein, It includes: A substrate; The first gate layer is disposed on one side of the substrate; it is provided with a gate layer of a first thin film transistor in the sub-pixel region and a first electrode plate of a storage capacitor; The electrode plate layer is disposed on a side of the first gate layer away from the substrate and is provided with a second electrode plate of the storage capacitor and a reference voltage signal line; A source-drain layer is disposed on a side of the electrode plate layer away from the substrate, and is provided with a source and a drain of a first thin-film transistor, and a reference voltage signal line; A first planarization layer is disposed on a side of the source-drain layer away from the substrate; A fifth metal layer is disposed on a side of the first planarization layer away from the substrate, and is provided with the first virtual trace; A second planarization layer is disposed on a side of the fifth metal layer away from the substrate; A sixth metal layer is disposed on a side of the second planarization layer away from the substrate; and is provided with a second virtual trace; Both the first virtual trace and the second virtual trace are connected to a third power signal.

18. The display panel according to claim 17, wherein, A second gate layer is further disposed between the electrode plate layer and the source-drain layer; A gate layer of a second thin-film transistor in the sub-pixel region is provided; the first thin-film transistor is a P-type thin-film transistor; and the second thin-film transistor is an N-type thin-film transistor.

19. The display panel according to claim 17 or 18, wherein, The first virtual trace and the second virtual trace are electrically connected through the second planarization layer.

20. The display panel according to claim 17, wherein, The fan-out trace in the display area includes a third virtual trace extending along the first direction and a fourth virtual trace extending along the second direction; The third virtual trace is disposed on the same layer as the first virtual trace; the fourth virtual trace is disposed on the same layer as the second virtual trace; The third virtual trace and the fourth virtual trace are electrically connected through the second planarization layer; A part of the fan-out trace extending to the non-display area is transformed to the first gate layer or the electrode plate layer.

21. A display device, characterized in that, A display panel including any one of the above claims 1-20.

Images