A method of forming a semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device forming method, which comprises: providing a substrate having a stack structure thereon; the stack structure comprising a to-be-formed step region, the to-be-formed step region comprising a plurality of sub-step regions, and each of the sub-step regions having a different height; forming a photoresist layer on the to-be-formed step region; and determining a photoetching scheme for the photoresist layer according to a height difference between a highest point and a lowest point of the photoresist layer in the to-be-formed step region. The semiconductor device forming method provided by the embodiments of the present application determines the photoetching scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer, which helps the pattern formed by the photoresist layer to have a better appearance, thereby significantly improving the problem of structural defects of the semiconductor device caused by the deformation of the pattern of the photoresist layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor manufacturing, and particularly relate to a forming method of a semiconductor device. BACKGROUND

[0002] The integration of conventional two-dimensional or planar memory is mainly determined by the area occupied by a unit storage cell. In recent years, the development of planar memory is affected by fine pattern forming technology. On this basis, in order to solve the difficulties encountered by planar memory and pursue higher integration and lower production cost, three-dimensional (3D) memory emerges as the times require.

[0003] Among them, by stacking the storage cells in a three-dimensional mode, a three-dimensional memory with high unit area storage density and high storage cell performance is produced. As the integration becomes higher and higher, the number of stacked layers of the three-dimensional memory also becomes more and more, and the difficulty of using photolithography process to form the required pattern also becomes greater and greater.

[0004] Therefore, how to improve the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device is a technical problem to be solved at present. SUMMARY

[0005] Therefore, embodiments of the present application provide a forming method of a semiconductor device to solve at least one technical problem in the prior art.

[0006] To achieve the above object, the technical scheme of the present application is as follows:

[0007] Embodiments of the present application provide a forming method of a semiconductor device, the forming method comprising:

[0008] providing a substrate, the substrate having a stacked structure thereon;

[0009] The stacked structure comprises a to-be-formed step region, the to-be-formed step region comprises a plurality of sub-step regions, and the height of each sub-step region is different;

[0010] forming a photoresist layer on the to-be-formed step region;

[0011] determining a photolithography scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region.

[0012] In some embodiments of the present application, the determining a photolithography scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region comprises:

[0013] According to a height difference between a highest point and a lowest point of the photoresist layer, the to-be-formed step region is divided into a plurality of sub-region sets; each of the sub-region sets includes a number of sub-step regions greater than or equal to 1;

[0014] The photoresist layer in different sub-region sets is subjected to photolithography processing respectively.

[0015] In some embodiments of the present application, the determination of the photolithography scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region comprises:

[0016] A photolithography focus depth is provided.

[0017] When the height difference between the highest point and the lowest point of the photoresist layer is less than the photolithography focus depth, the photoresist layer in the to-be-formed step region is subjected to photolithography processing simultaneously.

[0018] When the height difference between the highest point and the lowest point of the photoresist layer is greater than the photolithography focus depth, the to-be-formed step region is divided into a plurality of sub-region sets; each of the sub-region sets includes a number of sub-step regions greater than or equal to 1; the photoresist layer in different sub-region sets is subjected to photolithography processing respectively.

[0019] In some embodiments of the present application, the height difference between the highest point and the lowest point of the photoresist layer in the sub-region set is less than the photolithography focus depth.

[0020] In some embodiments of the present application, before the photoresist layer is formed on the to-be-formed step region, the forming method further comprises:

[0021] A hard mask layer is formed on the to-be-formed step region.

[0022] In some embodiments of the present application, after the determination of the photolithography scheme for the photoresist layer, the forming method further comprises:

[0023] The photoresist layer is subjected to trimming processing according to the photolithography scheme to form a trimmed photoresist layer;

[0024] The hard mask layer is etched by the trimmed photoresist layer to form a trimmed hard mask layer;

[0025] The stack structure is etched by the trimmed hard mask layer.

[0026] The trimming and etching steps are repeated to form a plurality of step levels in the sub-step region.

[0027] In some embodiments of the present application, the heights of the sub-step regions in the to-be-formed step region vary irregularly.

[0028] In some embodiments of the present application, each of the sub-step regions has the same number of steps, and the heights of the steps are the same.

[0029] In some embodiments of the present application, the stack structure comprises a plurality of first layers alternating with a plurality of second layers, the second layers comprise a material different from the first layers, and each of the steps has at least one of the first layers and at least one of the second layers.

[0030] In some embodiments of the present application, the semiconductor device comprises a three-dimensional memory.

[0031] Embodiments of the present application provide a forming method of a semiconductor device, the forming method comprising: providing a substrate, the substrate having a stack structure thereon; the stack structure comprising a to-be-formed step region, the to-be-formed step region comprising a plurality of sub-step regions, and the heights of each of the sub-step regions being different; forming a photoresist layer on the to-be-formed step region; and determining a photoetching scheme for the photoresist layer according to a height difference between a highest point and a lowest point of the photoresist layer in the to-be-formed step region. The forming method of the semiconductor device provided by the embodiments of the present application determines the photoetching scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer, which helps the pattern formed by the photoresist layer to have a better topography, thereby significantly improving the problem of structural defects of the semiconductor device caused by the deformation of the pattern of the photoresist layer, and further improving the yield of the semiconductor device and reducing the manufacturing cost of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A flowchart of the forming method of the semiconductor device provided by the embodiments of the present application is shown;

[0033] Figure 2 A cross-sectional structure schematic diagram of the semiconductor device comprising the substrate and the stack structure provided by the embodiments of the present application is shown;

[0034] Figure 3 A three-dimensional structure schematic diagram of the semiconductor device provided by the embodiments of the present application is shown;

[0035] Figure 4 A cross-sectional structure schematic diagram of the semiconductor device provided by the embodiments of the present application is shown;

[0036] Figure 5 A principle schematic diagram of the photoetching process is shown;

[0037] Figure 6Another schematic view of a cross section of a semiconductor device according to an embodiment of the present application is provided;

[0038] The figure comprises: 100 - substrate; 200 - stack structure; 201 - first layer; 202 - second layer; 300 - to-be-formed step region; 301, 302, 303, 304, 305, 306, 307, 308, 309 - sub-step region; 401, 402 - sub-core region; 500 - photoresist layer; 600 - hard mask layer; 700 - lens. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0040] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious for those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present application, some technical features known in the art are not described; that is, all the features of the actual embodiments are not described here, and the known functions and structures are not described in detail.

[0041] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0042] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0043] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description, in order to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can also have other implementation manners.

[0046] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a substrate, such that the array structure extends in a direction perpendicular to the substrate.

[0047] As used herein, the "Z direction" refers to a direction perpendicular to the substrate; the "X direction" refers to a direction parallel to the substrate; the "Y direction" refers to a direction parallel to the substrate, and the "Y direction" and the "X direction" are perpendicular to each other.

[0048] The integration of conventional two-dimensional or planar memory is mainly determined by the area occupied by a unit storage cell. In recent years, the development of planar memory has been affected by fine pattern forming technology. On this basis, in order to solve the difficulties encountered by planar memory and pursue higher integration and lower production cost, three-dimensional memory emerges as the times require.

[0049] Three-dimensional memory adopts a vertically stacked multi-layer gate structure, further improves the storage capacity of the memory by forming a gate with more tiers, and reduces the storage cost per unit storage capacity. The three-dimensional memory structure can include a peripheral circuit region (CMOS) and a storage array region (array). Among them, the peripheral circuit region not only supplies power for the storage array region, but also has the functions of logic operation and static protection. The storage array region can include a core region (core) and a stair case region (stair case). Among them, the core region can include a plurality of channel structures, each channel structure can be coupled to a gate layer to form a corresponding vertical storage cell string. The vertical storage cell string can include one or more bottom selective transistors (BST), a plurality of memory cell transistors (MC), and one or more top selective transistors (TST), which are sequentially arranged on the substrate along the vertical direction of the substrate (i.e., the Z direction). Among them, the stair case region can be located on at least one side of the core region, used to lead out the electrical signal of the gate layer in the storage array region. The gate layer serves as the word line of the storage array region, and performs reading, programming and erasing operations.

[0050] With the increasing integration, the number of stacked layers of the three-dimensional memory is also increasing, and the difficulty of forming the required pattern using a photolithography process is also increasing. Therefore, how to improve the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device is a technical problem to be solved at present.

[0051] Therefore, the embodiment of the present application provides a forming method of a semiconductor device. Wherein, the semiconductor device can include a three-dimensional memory, and the forming method of the three-dimensional memory will be taken as an example in the following description, which should not be construed as a limitation to the protection scope of the present application.

[0052] Reference Figure 1 , Figure 1 The flow chart of the forming method of the semiconductor device provided by the embodiment of the present application is shown.

[0053] As Figure 1 shown, the forming method comprises:

[0054] Step S101, providing a substrate, the substrate having a stacked structure thereon.

[0055] Reference Figure 2 , Figure 2 The cross-sectional structure schematic diagram of the semiconductor device provided by the embodiment of the present application includes a substrate and a stacked structure. As Figure 2 shown, the substrate 100 has a stacked structure 200 thereon. Wherein, the stacked structure 200 includes a to-be-formed step region and a to-be-formed core region. In some embodiments, the to-be-formed step region can be located on both sides of the to-be-formed core region. In other embodiments, the to-be-formed step region can be located in the middle of the two to-be-formed core regions adjacent thereto. It can be understood that the relative positions of the to-be-formed core region and the to-be-formed step region are not limited thereto, and the relative positions of the to-be-formed core region and the to-be-formed step region can be set according to actual needs.

[0056] Specifically, the substrate can be a single-element semiconductor material substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.; or a composite semiconductor material substrate, for example, a silicon-germanium (SiGe) substrate, etc.; or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Wherein, the substrate is preferably a silicon substrate for supporting the device structure thereon.

[0057] In some embodiments of the present application, the stacked structure includes a plurality of first layers alternating with a plurality of second layers, the second layers include a material different from the first layers, and each step has at least one first layer and at least one second layer.

[0058] As shown in Figure 2 , the stack structure 200 includes first layers 201 and second layers 202 which are alternately stacked in a direction perpendicular to the substrate 100 (i.e., Z direction). Wherein, the number of stacked layers of the stack structure can be selected by those skilled in the art according to actual needs, for example, 32 layers, 64 layers, 128 layers, 192 layers or other number of layers. Generally speaking, the more the number of stacked layers, the higher the integration of the three-dimensional memory. Here, Figure 2 only the positional relationship between the first layers and the second layers which are alternately stacked above the substrate is shown, Figure 2 and the step region to be formed included in the stack structure, i.e., the step region formed after at least one photolithography process has been performed on the stack structure, does not constitute a limitation to the scope of protection of the present application.

[0059] In some embodiments of the present application, the first layers can be insulating layers, and the second layers can be sacrificial layers. Specifically, the material of the first layers can include but is not limited to oxide materials, for example, silicon oxide, silicon oxynitride. The material of the second layers can include but is not limited to nitride materials, for example, silicon nitride. The material of the first layers is different from the material of the second layers. In order to form the first layers and the second layers, one or more thin film deposition processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof can be used.

[0060] Still referring to Figure 1 , the forming method includes:

[0061] Step S102, the stack structure includes a step region to be formed, and the step region to be formed includes a plurality of sub-step regions, and each of the sub-step regions has a different height.

[0062] Referring to Figure 3 , Figure 3 A three-dimensional structure of a semiconductor device is provided in embodiments of the present application. As shown in Figure 3 , the stack structure includes a step region to be formed 300, and the step region to be formed 300 includes a plurality of sub-step regions. Here, "a plurality of" means two or more. Here, "a step region to be formed" refers to a step region formed after at least one photolithography process has been performed on the stack structure, but this step region is not the final structure of the semiconductor device, and thus is referred to as "a step region to be formed". Figure 3The illustrated stack structure includes, in sequence along the X direction, sub-core region 401, sub-step regions 301, 302, 303, 304, 305, 306, and sub-core region 402. Figure 3 Only the case where the stack structure includes two sub-core regions and six sub-step regions is shown, and in fact, the number of sub-core regions and the number of sub-step regions in the stack structure are not limited to this, and the relative positional relationship between the sub-core regions and the sub-step regions is also not limited to this.

[0063] Reference Figure 4 , Figure 4 A cross-sectional structure schematic diagram of a semiconductor device provided by an embodiment of the present application is shown. As shown in Figure 4 , the stack structure includes to-be-formed step region 300, which includes sub-step regions 301, 302, 303, 304, 305, 306. Still referring to Figure 4 , the "height of a sub-step region" here refers to the vertical distance between its upper surface and the upper surface of substrate 100, that is, the distance between the upper surface of the sub-step region in the Z direction and the substrate, or the distance between the highest point of the sub-step region in the Z direction and the upper surface of the substrate. Figure 4 The heights of the illustrated sub-step regions 301, 302, 303, 304, 305, 306 are H1, H2, H3, H4, H5, H6 in sequence, respectively, wherein the height of each sub-step region is different.

[0064] Here Figure 3 and Figure 4 The illustrated topography schematic diagram of the semiconductor device is not the final topography schematic diagram of the semiconductor device. The technical solution provided by the embodiment of the present application can be regarded as continuing to form a photoresist layer and then performing at least one photolithography process on the basis of the Figure 3 or Figure 4 illustrated semiconductor device. The formation method of the semiconductor device provided by the embodiment of the present application continues to form a photoresist layer and then performs at least one photolithography process in the case where the height of each of the sub-step regions is different. That is, the process of forming a photoresist layer and performing photolithography in the embodiment of the present application occurs in the middle or late stage of etching to form a step.

[0065] In some embodiments of the present application, the width of each of the sub-step regions can be the same or different, and those skilled in the art can set it according to actual needs. The "width of a sub-step region" here refers to the width of the sub-step region in the X direction.

[0066] In a preferred embodiment of the present application, the widths of the plurality of sub-step regions are the same along the X direction. Still referring to Figure 4The widths of the sub-step regions 301, 302, 303, 304, 305, and 306 are W1, W2, W3, W4, W5, and W6, respectively. The widths of the sub-step regions are set to be the same, so as to simplify the manufacturing process of the semiconductor device.

[0067] Still referring to Figure 1 The forming method comprises:

[0068] In step S103, a photoresist layer is formed on the to-be-formed step region.

[0069] As described above, after the to-be-formed step region and the to-be-formed core region are determined in the stack structure, a photoresist (PR) layer is formed on the to-be-formed step region. At this time, the stack structure has been etched to form steps, and the structure of the semiconductor device can refer to Figure 3 and Figure 4 However, Figure 3 and Figure 4 The topographic schematic diagram of the semiconductor device shown is only a topographic schematic diagram at a middle or late stage of etching to form steps, and is not a final topographic schematic diagram of the semiconductor device. Therefore, the photoresist layer is still formed on the to-be-formed step region.

[0070] Specifically, forming the photoresist layer can include the steps of forming a bottom film in the gas phase, spin coating, and soft baking. The bottom film is formed on the stack structure and is used to increase the adhesion between the subsequently formed photoresist layer and the stack structure; after the photoresist layer is formed using the spin coating method, soft baking is performed to remove the solvent in the photoresist.

[0071] Lithography uses geometric patterns on a reduction reticle to transfer the patterns onto a photoresist layer covering the semiconductor structure through a photochemical reaction. The material of the photoresist layer is a light-sensitive chemical, and according to the chemical reaction mechanism and the developing principle, the photoresist can be divided into two types: positive resist and negative resist. For the positive resist, the exposed part is easily dissolved, and the exposed area is more easily removed in the developing step. For the negative resist, the exposed part is not easily dissolved, and the exposed area will not be removed in the developing step. Therefore, the pattern formed on the positive resist will be the same as the pattern on the reduction reticle, and the pattern formed on the negative resist will be the inverse of the pattern on the reduction reticle.

[0072] In some embodiments of the present application, before the photoresist layer is formed on the to-be-formed step region, the forming method further comprises:

[0073] A hard mask layer is formed on the step region to be formed.

[0074] Specifically, after the hard mask layer is formed on the step region to be formed, a photoresist layer is formed on the hard mask layer. The material of the hard mask layer can include, but is not limited to, titanium nitride, silicon nitride, or silicon dioxide. To form the hard mask layer, one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof can be used.

[0075] As the size of the desired pattern becomes smaller and smaller, it is difficult to provide a fine pattern with excellent profile by transferring the pattern only through the photoresist layer. Therefore, the hard mask layer can be formed between the semiconductor structure and the photoresist layer to provide a fine pattern. First, a pattern is formed on the photoresist layer by a mask, then the pattern on the photoresist layer is transferred to the hard mask layer, and finally the pattern is transferred to the semiconductor structure to be etched through the hard mask layer, thereby achieving fine pattern transfer.

[0076] Still referring to Figure 4 , the height of each sub-step region is different, and the height difference of each sub-step region is large, that is, the maximum height difference of the photoresist layer in the step region to be formed is also large. This means that during one exposure process, the depth of focus (DOF) needs to cover a large height difference. Therefore, when the thickness of the photoresist layer exceeds the depth of focus, after exposure and development, the pattern of the photoresist layer can be deformed, resulting in defects in the semiconductor structure in the subsequent etching process. Because the height difference of the photoresist layer needs to be covered by the DOF during the exposure process, the pattern of the photoresist layer can be deformed, which in turn leads to defects in the etched step in the sub-step region.

[0077] Referring to Figure 5 , Figure 5 is a schematic diagram of the principle of the lithography process. As shown in Figure 5 , the photoresist layer 500 is located on the hard mask layer 600, and the light is diffracted through the small hole pattern on the mask to perform the first Fourier transform, and then focused through the lens 700 to perform the second Fourier transform. The depth of focus refers to a range above and below the focal point, within which the pattern remains clear continuously. Generally speaking, the depth of focus needs to completely cover the height of the photoresist layer, so that one exposure can ensure that the lowest and highest parts of the photoresist layer are within the focus range. Still referring to Figure 4, with the increase of the number of layers of the stacked structure, the height difference of different sub-step regions also increases, and the height difference between the lowest part and the highest part of the photoresist layer may be greater than the focus depth, so that the lowest part of the photoresist layer or the highest part of the photoresist layer is out of the focus depth range, thereby causing the defocus of the pattern. In the photoetching process, when the height difference of the photoresist layer is greater than the DOF, the photoresist layer will be partially defocused, that is, only the part of the photoresist layer from the surface to the thickness within the DOF range can be exposed, and the part beyond the DOF range is the defocused part, which cannot achieve good exposure. Therefore, due to the large height difference of the photoresist layer covered by the DOF in the exposure process, the pattern of the photoresist layer may be deformed, and then the etched step in the sub-step region has defects.

[0078] Still referring to Figure 1 , the forming method comprises:

[0079] Step S104, determining a photoetching scheme for the photoresist layer according to the height difference between the highest part and the lowest part of the photoresist layer in the to-be-formed step region.

[0080] In the forming method of the semiconductor device provided by the present application, the height difference between the highest part and the lowest part of the photoresist layer in the to-be-formed step region is obtained in advance, more specifically, the height difference between the photoresist layers on different sub-step regions is obtained, and the photoetching scheme of the photoresist layer is determined according to the height difference, which helps the pattern formed by the photoresist layer to have a better appearance, thereby significantly improving the problem of structural defects of the semiconductor device caused by the deformation of the pattern of the photoresist layer, and further improving the yield of the semiconductor device and reducing the manufacturing cost of the semiconductor device.

[0081] In some embodiments of the present application, the determination of the photoetching scheme for the photoresist layer according to the height difference between the highest part and the lowest part of the photoresist layer in the to-be-formed step region comprises:

[0082] According to the height difference between the highest part and the lowest part of the photoresist layer, the to-be-formed step region is divided into a plurality of sub-region sets; each of the sub-region sets comprises a number of sub-step regions greater than or equal to 1;

[0083] The photoresist layers in different sub-region sets are respectively subjected to photoetching treatment.

[0084] In the forming method of the semiconductor device provided by the present application, the height difference between the highest part and the lowest part of the photoresist layer in the to-be-formed step region is obtained in advance, more specifically, the height difference between the photoresist layers on different sub-step regions is obtained, and the photoetching scheme of the photoresist layer is determined according to the height difference value. Referring to Figure 6 , Figure 6This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application. Figure 6 As shown, the step region to be formed includes three sub-step regions 307, 308, and 309. The height difference between the highest point (or upper surface) of sub-step region 307 and the upper surface of the substrate along the Z direction is H. 72 The height difference between the lowest point of the sub-step region 307 and the upper surface of the substrate along the Z direction is H. 71 The height difference between the highest point (or upper surface) of the sub-step region 308 and the upper surface of the substrate along the Z direction is H. 82 The height difference between the lowest point of the sub-step region 308 and the upper surface of the substrate along the Z direction is H. 81 The height difference between the highest point (or upper surface) of the sub-step region 309 and the upper surface of the substrate along the Z direction is H. 92 The height difference between the lowest point of the sub-step region 309 and the upper surface of the substrate along the Z direction is H. 91 Therefore, within the step area to be formed, the photolithography process requires the photoresist to completely cover the maximum height difference within the step area, that is, the height difference between the highest and lowest points of the photoresist layer within the step area to be formed is (H). 92 -H 71 Here, the area of ​​steps to be formed can be divided into multiple sub-region sets.

[0085] Here you can Figure 6 The step area to be formed is divided into two sub-region sets: a first sub-region set and a second sub-region set. The first sub-region set includes sub-step area 307, and the second sub-region set includes sub-step areas 308 and 309. At this time, the height difference of the photoresist layer within the first sub-region set is (H... 72 -H 71 The height difference of the photoresist layers within the second sub-region set is (H). 92 -H 81 In the above partitioning scheme, (H) 72 -H 71 ) less than (H 92 -H 71 And (H) 92 -H 81 ) less than (H 92 -H 71 ).

[0086] Alternatively, the area to be formed as a step can be divided into two sub-region sets, namely a first sub-region set and a second sub-region set. The first sub-region set includes sub-step regions 307 and 308, and the second sub-region set includes sub-step region 309. In this case, the height difference of the photoresist layer within the first sub-region set is (H...82 -H 71 ), the height difference of the photoresist layer in the second sub-region set is (H 92 -H 91 ). In the above division scheme, (H 82 -H 71 ) is less than (H 92 -H 71 ) and (H 92 -H 91 ) is less than (H 92 -H 71 ).

[0087] Alternatively, the step region to be formed can be divided into three sub-region sets, namely a first sub-region set, a second sub-region set and a third sub-region set, wherein the first sub-region set includes the sub-step region 307, the second sub-region set includes the sub-step region 308, and the third sub-region set includes the sub-step region 309. At this time, the height difference between the highest and lowest points of the photoresist layer in the first sub-region set is (H 72 -H 71 ), the height difference between the highest and lowest points of the photoresist layer in the second sub-region set is (H 82 -H 81 ), and the height difference between the highest and lowest points of the photoresist layer in the third sub-region set is (H 92 -H 91 ). In the above division scheme, (H 72 -H 71 ) is less than (H 92 -H 71 ) and (H 82 -H 81 ) is less than (H 92 -H 71 ) and (H 92 -H 91 ) is less than (H 92 -H 71 ).

[0088] In the method for forming a semiconductor device provided in the present application, by dividing the step region to be formed into a plurality of sub-region sets, so that the height difference between the highest and lowest points of the photoresist layer in each sub-region set is less than the height difference between the highest and lowest points of the photoresist layer in the step region to be formed, and the photoresist layer in each sub-region set is subjected to photoetching processing respectively, it is helpful for the pattern formed by the photoresist layer to have a better topography.

[0089] In some embodiments of the present application, the photoetching scheme for the photoresist layer is determined according to the height difference between the highest and lowest points of the photoresist layer in the step region to be formed, comprising:

[0090] providing a photoetching focus depth;

[0091] when the height difference between the highest point and the lowest point of the photoresist layer is less than the lithography focus depth, simultaneously performing lithography processing on the photoresist layer in the to-be-formed step region;

[0092] when the height difference between the highest point and the lowest point of the photoresist layer is greater than the lithography focus depth, dividing the to-be-formed step region into a plurality of sub-region sets; each of the sub-region sets includes a number of sub-step regions greater than or equal to 1; and respectively performing lithography processing on the photoresist layer in different sub-region sets.

[0093] In the method for forming a semiconductor device provided in the present application, the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region is obtained in advance, more specifically, the height difference between the photoresist layers on different sub-step regions is obtained, and the lithography scheme of the photoresist layer is determined according to the size relationship between the height difference and the lithography focus depth.

[0094] The focus depth can be calculated according to Formula 1:

[0095]

[0096] wherein λ is the wavelength of the light source, and NA is the numerical aperture of the exposure system.

[0097] As described above, the use of light sources with different wavelengths in the exposure processing determines the focus depth. In the lithography method, from the initial use of a lithography device with a light source having a wavelength of 636 nm (i.e., g line) and 365 nm (i.e., i line), to the use of a lithography device with a wavelength of 248 nm, i.e., a fluorinated krypton (KrF) excimer laser beam. In order to prepare semiconductor devices with smaller critical dimensions, a lithography device using a light source with a wavelength of 193 nm, i.e., a fluorinated argon (ArF) excimer laser beam, has also been developed.

[0098] In the method for forming a semiconductor device provided in the present application, the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region is obtained in advance, more specifically, the height difference between the photoresist layers on different sub-step regions is obtained, and the lithography scheme of the photoresist layer is determined according to the size relationship between the height difference and the lithography focus depth.

[0099] Specifically, when the height difference between the highest point and the lowest point of the photoresist layer is less than the lithography focus depth, at this time, the photoresist layer in the to-be-formed step region is all within the focus range, and the photoresist layer in the to-be-formed step region can be simultaneously subjected to lithography processing. After the lithography processing, the pattern of the photoresist layer has a good morphology.

[0100] Specifically, when the height difference between the highest point and the lowest point of the photoresist layer is greater than the lithography focus depth, at this time, the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region exceeds the focus range. Therefore, the to-be-formed step region can be divided into a plurality of sub-region sets, ensuring that the height difference between the highest point and the lowest point of the photoresist layer in each of the sub-region sets is less than the lithography focus depth, and the photoresist layer in different sub-region sets is subjected to lithography processing respectively, and after the lithography processing, the pattern of the photoresist layer has a good topography.

[0101] In some embodiments of the present application, after the determination of the lithography scheme for the photoresist layer, the forming method further comprises:

[0102] trimming processing of the photoresist layer according to the lithography scheme to form a trimmed photoresist layer;

[0103] etching the hard mask layer through the trimmed photoresist layer to form a trimmed hard mask layer;

[0104] etching the stack structure through the trimmed hard mask layer;

[0105] repeating the trimming and etching steps to form a multi-level step in the sub-step region.

[0106] Specifically, a trim-etch process can be used to form a multi-level step in the sub-step region. Still referring to Figure 6 , first, a hard mask layer and a photoresist layer are formed on the surface of the sub-step regions 307, 308, and 309; then, according to the lithography scheme determined in the foregoing technical solution, for example, the sub-step region 307 is taken as a first sub-region set, and the sub-step regions 308 and 309 are taken as a second sub-region set, the photoresist layer in the first sub-region set and the second sub-region set is subjected to lithography processing respectively to form a patterned photoresist layer. Specifically, the photoresist layer in the sub-region set is subjected to trimming processing, so that the edge of the photoresist layer in the X direction is reduced by one step width in the direction of the center of the sub-step region covered thereby; the hard mask layer is etched through the trimmed photoresist layer, so that the edge of the hard mask layer in the X direction is reduced by one step width in the direction of the center of the sub-step region covered thereby; and the stack structure is etched through the trimmed hard mask layer. By repeatedly performing the trimming and etching steps of the photoresist layer and the hard mask layer multiple times, a multi-level step arranged in the X direction is formed in each sub-step region.

[0107] Still referring to Figure 6 , the heights of the sub-step regions 307, 308, and 309 are H 72 , H 82 , and H 92That is, the distance between the highest point of the sub-step region 307, 308, 309 and the upper surface of the substrate in the Z direction is H 72 , H 82 , H 92 , respectively.

[0108] With continued reference to Figure 6 , the sub-step regions 307 and 309 include multiple steps arranged along the X direction, and the heights of the multiple steps in the sub-step regions 307 and 309 increase successively along the X direction. Here, the "height of the multiple steps" refers to the distance between the upper surface of the step and the upper surface of the substrate in the Z direction. Taking the sub-step region 307 as an example, the heights of the multiple steps arranged along the X direction are S 71 , S 72 , S 73 , successively. That is, the heights of the multiple steps increase successively along the X direction. The sub-step region 308 includes multiple steps arranged along the X direction, and the heights of the multiple steps in the sub-step region 308 decrease successively along the X direction. In general, the heights of the multiple steps in adjacent sub-step regions change in opposite trends along the X direction, that is, the heights of the multiple steps in the sub-step region 307 increase successively along the X direction, the heights of the multiple steps in the sub-step region 308 decrease successively along the X direction, and the heights of the multiple steps in the sub-step region 309 increase successively along the X direction.

[0109] In some embodiments of the present application, the heights of the sub-step regions in the step region to be formed change irregularly. With reference to Figure 4 and Figure 6 , the heights of the sub-step regions are different, and the heights of the sub-step regions change irregularly, so that the upper surface of each sub-step region presents a concave-convex topography in a sectional view.

[0110] In preferred embodiments of the present application, the widths of the multiple sub-step regions are the same along the X direction. Still with reference to Figure 6 , the widths of the sub-step regions 307, 308, 309 are W7, W8, W9, respectively. The widths of the multiple sub-step regions are set to the same width so as to simplify the manufacturing process of the semiconductor device.

[0111] In preferred embodiments of the present application, each of the sub-step regions has the same number of steps, and the heights of the steps are the same. Still with reference to Figure 6 , for example, the sub-step region 308 includes 10 steps, and the heights of the steps are h 81 , h 82 , h 83 , h 84 , h 85 , h 86, h 87 , h 88 , h 89 , h 810 , the height of each step is the same. Here, the height of each step refers to the distance between the highest point of a step and the upper surface of the substrate in the Z direction minus the distance between the lowest point of the step and the upper surface of the substrate in the Z direction. For example, Figure 6 In the sub-step region 308 shown, the distance between the highest point of the step in the dashed circle frame and the upper surface of the substrate in the Z direction is H 83 , the distance between the lowest point of the step in the dashed circle frame and the upper surface of the substrate in the Z direction is H 81 , then the height of the step in the dashed circle frame is (H 83 -H 81 ), that is, Figure 6 h 810 . The number of steps in the plurality of sub-step regions is set to be the same, and the height of each step in the sub-step region is set to be the same, so as to simplify the manufacturing process of the semiconductor device.

[0112] The embodiment of the present application provides a forming method of a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate has a stack structure; the stack structure comprises a to-be-formed step region, the to-be-formed step region comprises a plurality of sub-step regions, and the height of each sub-step region is different; forming a photoresist layer on the to-be-formed step region; and determining a photoetching scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer in the to-be-formed step region. The forming method of the semiconductor device provided by the embodiment of the present application determines the photoetching scheme for the photoresist layer according to the height difference between the highest point and the lowest point of the photoresist layer, which helps the pattern formed by the photoresist layer to have a better appearance, thereby significantly improving the problem of structural defects of the semiconductor device caused by the deformation of the pattern of the photoresist layer, and further improving the delivery rate of the semiconductor device and reducing the manufacturing cost of the semiconductor device.

[0113] It should be understood that the term "in one embodiment" or "in an embodiment" as used throughout this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the application. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the above-mentioned processes is not meant to limit the execution order, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The above-mentioned sequence of the embodiments of the application is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0114] The preferred embodiments of the present application are described above with the aid of drawings, and are not intended to limit the patent scope of the present application. Any equivalent structure variations made according to the content of the specification and drawings of the present application, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A method for forming a semiconductor device, characterized in that, The forming method includes: A substrate is provided, wherein the substrate has a stacked structure; The stacked structure includes a step area to be formed, which includes multiple sub-step areas, and each sub-step area has a different height. A photoresist layer is formed on the step area to be formed; Based on the relationship between the height difference between the highest and lowest points of the photoresist layer in the step area to be formed and the photolithography focusing depth, a photolithography scheme for the photoresist layer is determined. When the height difference between the highest and lowest points of the photoresist layer is greater than the photolithography focusing depth, the step region to be formed is divided into multiple sub-region sets; each sub-region set includes a number greater than or equal to 1 sub-step region; photolithography is performed on the photoresist layer in different sub-region sets respectively.

2. The forming method as described in claim 1, characterized in that, The step of determining the photolithography scheme for the photoresist layer based on the relationship between the height difference between the highest and lowest points of the photoresist layer within the step area to be formed and the photolithography focusing depth includes: When the height difference between the highest and lowest points of the photoresist layer is less than the photolithography focusing depth, the photoresist layer in the step area to be formed is simultaneously photolithographically processed. When the height difference between the highest and lowest points of the photoresist layer is greater than the photolithography focusing depth, the step region to be formed is divided into multiple sub-region sets; each sub-region set includes a number greater than or equal to 1 sub-step region; photolithography is performed on the photoresist layer in different sub-region sets respectively.

3. The forming method as described in claim 1, characterized in that, The height difference between the highest and lowest points of the photoresist layer within the sub-region set is less than the photolithographic focusing depth.

4. The forming method as described in claim 1, characterized in that, Before forming a photoresist layer on the step area to be formed, the formation method further includes: A hard mask layer is formed on the step area to be formed.

5. The forming method as described in claim 4, characterized in that, After determining the photolithography scheme for the photoresist layer, the formation method further includes: The photoresist layer is trimmed according to the photolithography scheme to form a trimmed photoresist layer; The hard mask layer is etched through the trimmed photoresist layer to form the trimmed hard mask layer; The stacked structure is etched using the trimmed hard mask layer; Repeat the trimming and etching steps described above to form multi-level steps in the sub-step area.

6. The forming method as described in claim 1, characterized in that, The height of the sub-step regions within the area of ​​the step to be formed varies irregularly.

7. The forming method as described in claim 5, characterized in that, Each of the sub-step regions has the same number of steps, and the steps have the same height.

8. The forming method as described in claim 5, characterized in that, The stacked structure includes a plurality of first layers alternating with a plurality of second layers, the second layers comprising a material different from the first layers, and each step having at least one first layer and at least one second layer.

9. The forming method as described in claim 5, characterized in that, The semiconductor device includes a three-dimensional memory.

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