Silicon Controlled Rectifier

Abstract

The present invention provides a thyristor rectifier, comprising: a substrate of a first conductivity type, a deep well region of a second conductivity type, a well region of a first conductivity type, a well region of a second conductivity type, first, second, and third heavily doped active regions of a first conductivity type, first, second, and third heavily doped active regions of a second conductivity type, and first, second, and third shallow trench isolation structures. By embedding a reverse diode formed by a third heavily doped active region of a second conductivity type and a well region of a first conductivity type in the well region of a first conductivity type, and forming a forward diode between the first heavily doped active region of a first conductivity type and the well region of a second conductivity type. By sharing the third heavily doped active region of a second conductivity type that straddles well regions of different conductivity types, two back-to-back diodes are formed. Therefore, the ESD current can be discharged through the circuit formed by the surface diodes, so as to increase the holding voltage of the device and reduce the length of the discharge current path.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor electrostatic protection, and particularly to a silicon-controlled rectifier (SCR) for unidirectional electrostatic discharge (ESD) protection. Background Art

[0002] With the continuous progress of integrated circuit technology, electrostatic discharge (ESD) events have become a serious problem affecting the reliability of integrated circuits. Among the problems causing the reliability of integrated circuits, more than one-third are brought by ESD events, severely restricting the reliability of semiconductor products. Therefore, it is very necessary to design effective ESD protection for integrated circuits.

[0003] In the chip ESD protection design, traditional ESD protection designs occupy a relatively large chip area, bringing great cost pressure. In order to achieve reliable ESD protection within the smallest possible area, a silicon-controlled rectifier (SCR) is an effective choice, which has extremely high unit robustness and occupies an extremely small chip area. However, the holding voltage (Vh) of the SCR is usually very low. If the holding voltage is lower than the operating voltage V of the chip DD , it brings a serious problem - latch-up. In order to avoid the reliability problems caused by the latch-up problem, it is usually required that the holding voltage of the ESD protection device be higher than the operating voltage V DD .

[0004] A commonly used ESD protection device is the MLSCR (modified lateral silicon-controlled rectifier) as Figure 1A shown, which includes a substrate 100, a deep N-well region, an N-well region, a P-well region, N+ regions 102a, 102b, and 102c, P+ regions 104a and 104b, and a shallow trench isolation structure STI for isolating each active region. The N+ region 102c bridging between the N-well region and the P-well region can effectively reduce the trigger voltage of the device. Figure 1B Show Figure 1A The equivalent circuit diagram of the MLSCR shown, which shows two discharge paths P1 and P2. Due to the surface parasitic transistor discharge (discharge path P1) formed by the bridging N+ region 102c, the holding voltage of the MLSCR is higher than that of the traditional SCR, but in most cases it is still not sufficient to achieve latch-up immunity. Summary of the Invention

[0005] The present invention is directed to a thyristor rectifier having an ESD current discharge path formed by a surface (gate-controlled) diode, which can significantly increase the holding voltage of the device. Moreover, by adjusting the width of the active region of the (gate-controlled) diode, the holding voltage of the device can be flexibly adjusted.

[0006] According to an embodiment of the present invention, the thyristor rectifier includes: a substrate of a first conductivity type, a deep well region of a second conductivity type, a well region of the first conductivity type, a well region of the second conductivity type, a first heavily doped active region of the second conductivity type, a first heavily doped active region of the first conductivity type, a second heavily doped active region of the second conductivity type, a second heavily doped active region of the first conductivity type, a third heavily doped active region of the second conductivity type, and a third heavily doped active region of the first conductivity type. The deep well region of the second conductivity type is formed in the substrate. The well region of the first conductivity type and the well region of the second conductivity type are formed side by side in the deep well region. The first heavily doped active region of the second conductivity type and the first heavily doped active region of the first conductivity type are disposed in the well region of the second conductivity type and are connected to the anode, and a first shallow trench isolation structure is provided therebetween. The second heavily doped active region of the second conductivity type and the second heavily doped active region of the first conductivity type are disposed in the well region of the first conductivity type and are connected to the cathode, and a second shallow trench isolation structure is provided therebetween. The third heavily doped active region of the second conductivity type straddles the well region of the first conductivity type and the well region of the second conductivity type, wherein the third heavily doped active region of the second conductivity type is spaced apart from the first heavily doped active region of the first conductivity type by a first distance, and the first heavily doped active region of the first conductivity type and the well region of the second conductivity type form a forward diode. The third heavily doped active region of the first conductivity type is disposed in the well region of the first conductivity type between the second heavily doped active region of the second conductivity type and the third heavily doped active region of the second conductivity type, wherein a third shallow trench isolation structure is provided between the second heavily doped active region of the second conductivity type and the third heavily doped active region of the first conductivity type, the third heavily doped active region of the second conductivity type is spaced apart from the third heavily doped active region of the first conductivity type by a second distance, and the third heavily doped active region of the second conductivity type and the well region of the first conductivity type form a reverse diode.

[0007] In the thyristor rectifier according to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0008] In the thyristor rectifier according to an embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0009] In the thyristor rectifier according to an embodiment of the present invention, the first distance satisfies the minimum distance requirement of the design rule of the gate.

[0010] In the thyristor rectifier according to an embodiment of the present invention, the second distance meets the minimum distance requirement of the design rule of the gate.

[0011] In the thyristor rectifier according to an embodiment of the present invention, the third heavily doped active region of the first conductivity type is in a floating state.

[0012] In the thyristor rectifier according to an embodiment of the present invention, it further includes a first gate and a second gate. The first gate is formed on the substrate between the first heavily doped active region of the first conductivity type and the third heavily doped active region of the second conductivity type. The second gate is formed on the substrate between the third heavily doped active region of the first conductivity type and the third heavily doped active region of the second conductivity type. The first gate, the second gate are electrically connected to the third heavily doped active region of the second conductivity type.

[0013] In the thyristor rectifier according to an embodiment of the present invention, it further includes a self-aligned silicide block (SAB) and a second gate. The SAB is formed on the substrate between the first heavily doped active region of the first conductivity type and the third heavily doped active region of the second conductivity type. The second gate is formed on the substrate between the third heavily doped active region of the first conductivity type and the third heavily doped active region of the second conductivity type. The second gate is electrically connected to the third heavily doped active region of the second conductivity type.

[0014] Based on the above, the thyristor rectifier of the present invention embeds a reverse diode in the well region of the first conductivity type, removes one of the shallow trench isolation structures in the well region of the second conductivity type in the previous MLSCR to form a forward diode, and forms two back-to-back diodes by sharing the common third heavily doped active region of the second conductivity type. Therefore, the ESD current can be discharged from the circuit composed of the surface diode to increase the holding voltage of the device, and the current path length of the diode is reduced by the setting of the forward diode. In addition, by changing the reverse diode to a gate-controlled reverse diode, it is also possible to achieve lower triggering and faster response time under ESD stress without using other triggering devices.

[0015] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0016] Figure 1A is a cross-sectional view of an existing MLSCR.

[0017] Figure 1B is Figure 1A the equivalent circuit diagram of the MLSCR.

[0018] Figure 2A A cross-sectional view of an SCR in the first embodiment of the present invention.

[0019] Figure 2B is Figure 2A the equivalent circuit diagram of the SCR.

[0020] Figure 3A A cross-sectional view of an SCR in the second embodiment of the present invention.

[0021] Figure 3B is Figure 3A the equivalent circuit diagram of the SCR.

[0022] Figure 4A A cross-sectional view of an SCR in the third embodiment of the present invention.

[0023] Figure 4B is Figure 4A the equivalent circuit diagram of the SCR.

[0024] Figure 5A The current simulation density distribution diagram at the turn-on moment of the reverse gate-controlled diode D2 of the SCR in the second embodiment.

[0025] Figure 5B The current simulation density distribution diagram at the turn-on moment of the parasitic NPN of the SCR in the second embodiment.

[0026] Figure 5C The current simulation density distribution diagram at the conduction moment of the SCR in the second embodiment.

[0027] Description of reference numerals

[0028] 100, 200: Substrate

[0029] 102a, 102b, 102c: N+ region

[0030] 104a, 104b: P+ region

[0031] 202: Deep well region

[0032] 203: Well region of the second conductivity type

[0033] 204: Well region of the first conductivity type

[0034] 206a: First heavily doped active region of the second conductivity type

[0035] 206b: Second heavily doped active region of the second conductivity type

[0036] 206c: Third heavily doped active region of the second conductivity type

[0037] 208a: First heavily doped active region of the first conductivity type

[0038] 208b: The second heavily doped active region of the first conductivity type

[0039] 208c: The third heavily doped active region of the first conductivity type

[0040] 210a, 210b, 210c, STI: Shallow trench isolation structure

[0041] 300: The first gate

[0042] 302: The second gate

[0043] 400: Self-aligned silicide blocking layer

[0044] D1: Forward diode

[0045] D2: Reverse diode

[0046] P1, P2: Discharge path

[0047] PNP, NPN, N+PN: Parasitic transistor

[0048] Rnw: N-well region resistance

[0049] Rpw: P-well region resistance

[0050] s1: The first distance

[0051] s2: The second distance Detailed implementation manners

[0052] Hereinafter, embodiments of the present invention will be described in detail. However, these embodiments are illustrative, and the disclosure of the present invention is not limited thereto. In addition, the drawings are for illustrative purposes only and are not drawn to the original scale. Whenever possible, the same reference numerals are used in the drawings and the description to represent the same or similar parts.

[0053] Figure 2A It is a cross-sectional view of a silicon-controlled rectifier (SCR) in the first embodiment of the present invention.

[0054] Please refer to Figure 2A, the SCR of the first embodiment is an Enhanced Diode-Triggered Silicon-Controlled Rectifier (EDTSCR), which includes a substrate 200 of the first conductivity type, a deep well region 202 of the second conductivity type, a well region 204 of the first conductivity type, a well region 203 of the second conductivity type, first, second, and third heavily doped active regions 208a, 208b, and 208c of the first conductivity type, first, second, and third heavily doped active regions 206a, 206b, and 206c of the second conductivity type, and first, second, and third shallow trench isolation structures 210a, 210b, and 210c. In the substrate 200, the well region 204 of the first conductivity type and the well region 203 of the second conductivity type are formed side by side in the deep well region 202. The first heavily doped active region 206a of the second conductivity type and the first heavily doped active region 208a of the first conductivity type are disposed in the well region 203 of the second conductivity type, and both the first heavily doped active region 206a of the second conductivity type and the first heavily doped active region 208a of the first conductivity type are connected to the anode. A first shallow trench isolation structure 210a is disposed between the first heavily doped active region 206a of the second conductivity type and the first heavily doped active region 208a of the first conductivity type. The second heavily doped active region 206b of the second conductivity type and the second heavily doped active region 208b of the first conductivity type are disposed in the well region 204 of the first conductivity type, and both the second heavily doped active region 206b of the second conductivity type and the second heavily doped active region 208b of the first conductivity type are connected to the cathode. A second shallow trench isolation structure 210b is disposed between the second heavily doped active region 206b of the second conductivity type and the second heavily doped active region 208b of the first conductivity type.

[0055] In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type. However, the present invention is not limited thereto; in another embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0056] Please continue to refer to Figure 2A, the third heavily doped active region 206c of the second conductivity type straddles the well region 204 of the first conductivity type and the well region 203 of the second conductivity type, and the first heavily doped active region 208a of the first conductivity type and the well region 203 of the second conductivity type form a forward diode D1. The third heavily doped active region 206c of the second conductivity type is spaced apart from the first heavily doped active region 208a of the first conductivity type by a first distance s1, and no shallow trench isolation structure is provided therebetween. Therefore, the first distance s1 only needs to meet the minimum distance requirement of the gate design rule, so the length of the current path (discharge path P1) can be greatly shortened. Taking a semiconductor manufacturing process below 0.25 microns as an example, the minimum width of the shallow trench isolation structure is about 0.4 to 4 microns. Therefore, the ESD protection device without the shallow trench isolation structure can basically shorten the current path by 0.4 to 4 microns. The third heavily doped active region 208c of the first conductivity type is disposed in the well region 204 of the first conductivity type between the second heavily doped active region 206b of the second conductivity type and the third heavily doped active region 206c of the second conductivity type, and the third heavily doped active region 208c of the first conductivity type in this embodiment is in a floating state. A third shallow trench isolation structure 210c is disposed between the second heavily doped active region 206b of the second conductivity type and the third heavily doped active region 208c of the first conductivity type. The third heavily doped active region 206c of the second conductivity type and the well region 204 of the first conductivity type form a reverse diode D2. To facilitate the turn-on of the reverse diode D2, the second distance s2 between the third heavily doped active region 206c of the second conductivity type and the third heavily doped active region 208c of the first conductivity type preferably meets the minimum distance requirement of the gate design rule.

[0057] Figure 2B For Figure 2A the equivalent circuit diagram of the SCR, with the P type as the first conductivity type and the N type as the second conductivity type. Please also refer to Figure 2A and Figure 2B , since the turn-on voltage of the forward diode D1 is very low (such as 0.7V), when the ESD stress arrives, avalanche breakdown first occurs at the N+ / PW junction (the junction between the third heavily doped active region 206c of the second conductivity type and the well region 204 of the first conductivity type), and then D1, D2, and the PW discharge path P1 are turned on. To maintain the conduction of the reverse diode D2, avalanche breakdown will continuously occur at the N+ / PW junction, resulting in an increase in the holding voltage of the EDTSCR.

[0058] After the parasitic transistor NPN is turned on, the generated electrons form a voltage drop across the NW junction. When the voltage of the P+ / NW junction (the junction between the first heavily doped active region 208a of the first conductivity type and the well region 203 of the second conductivity type) exceeds 0.7V, the parasitic transistor PNP is turned on. A positive feedback will be generated between the parasitic transistors NPN and PNP, thereby turning on the SCR. The charge injection generated by the positive feedback will cause the resistance of the SCR to exhibit a negative differential resistance state, that is, the doping increases and the resistance decreases, so that the SCR will have an obvious hysteresis.

[0059] Figure 3A FIG. is a cross-sectional view of an SCR in the second embodiment of the present invention, where the same or similar components are denoted by the same reference numerals as those in the first embodiment, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and the present embodiment will not be repeated here. Figure 3B is Figure 3A the equivalent circuit diagram of the SCR.

[0060] Referring simultaneously to Figure 3A and Figure 3B , the SCR of the second embodiment is an Enhanced Gated-Diode-Triggered Silicon-Controlled Rectifier (EGDTSCR for short). Compared with the first embodiment, the EGDTSCR further includes a first gate 300 and a second gate 302. The first gate 300 is formed on the substrate 200 between the first heavily doped active region 208a of the first conductivity type and the third heavily doped active region 206c of the second conductivity type; the second gate 302 is formed on the substrate 200 between the third heavily doped active region 208c of the first conductivity type and the third heavily doped active region 206c of the second conductivity type, wherein the first gate 300, the second gate 302 are electrically connected to the third heavily doped active region 206c of the second conductivity type.

[0061] Taking the P type as the first conductivity type and the N type as the second conductivity type as an example, when an ESD stress arrives, avalanche breakdown first occurs at the N+ / PW junction, and the reverse (gate-controlled) diode D2 is immediately turned on. Then the ESD current discharges to the cathode through the reverse diode D2 and PW. The ESD current in PW will converge in the floating P+ region (the third heavily doped active region 208c of the first conductivity type) because the floating P+ region has a very high doping concentration. In addition, the ESD current will apply a voltage to the second gate 302 through the bridging N+ region (the third heavily doped active region 206c of the second conductivity type), which will improve the discharge ability of the reverse diode D2 and accelerate the turn-on of the conducting reverse diode D2.

[0062] For the reverse diode D2, the RC gate coupling effect formed by the gate capacitance and the N-well resistance helps to trigger the device. The gate capacitance consists of the second gate 302, and the resistance consists of the N+ region resistance and the N-well (the well region 203 of the second conductivity type) resistance. The generated gate voltage further enhances this effect, thereby improving the current discharge capabilities of the forward (gate-controlled) diode D1 and the reverse (gate-controlled) diode D2. Therefore, the SCR of the second embodiment can achieve lower triggering and faster response time under ESD stress without using other triggering devices. Once the reverse diode D2 is turned on, the surface gate-controlled diode path (discharge path P1) starts to discharge the ESD current, and the parasitic transistor NPN will also turn on. After the parasitic transistors NPN and PNP are successively turned on, the SCR path (discharge path P2) is finally triggered to discharge the main ESD current.

[0063] Compared with the existing MLSCR, the EGDTSCR embeds a reverse diode D2 in the well region 204 of the first conductivity type, and combines the forward diode D1 in the well region 203 of the second conductivity type with the first gate 300 to form a gate-controlled diode. By sharing the thirdly doped active region 206c of the second conductivity type, two back-to-back gate-controlled diodes are formed. The first gate 300 and the second gate 302 can be connected to the thirdly doped active region 206c of the second conductivity type through metal to form an ESD current discharge path composed of surface gate-controlled diodes, which can greatly improve the holding voltage of the device. Moreover, by adjusting the width of the active region of the gate-controlled diode, the holding voltage of the device can be flexibly adjusted.

[0064] Figure 4A FIG. is a cross-sectional view of an SCR in the third embodiment of the present invention, where the same or similar components are denoted by the same reference numerals as those in the first embodiment, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, and the description of this embodiment will not be repeated here. Figure 4B is Figure 4A the equivalent circuit diagram of the SCR.

[0065] Refer simultaneously to Figure 4A and Figure 4B, the difference between the SCR of the third embodiment and the first embodiment is that a self-aligned silicide block (SAB) 400 is disposed on the substrate 200 between the first heavily doped active region 208a of the first conductivity type and the third heavily doped active region 206c of the second conductivity type, and a second gate 302 is disposed on the substrate 200 between the third heavily doped active region 208c of the first conductivity type and the third heavily doped active region 206c of the second conductivity type, and the second gate 302 is electrically connected to the third heavily doped active region 206c of the second conductivity type. Therefore, the third embodiment can also shorten the trigger path of D1, and the working process can refer to the first embodiment, which will not be repeated in this embodiment.

[0066] The following lists simulation experiments to verify the implementation effect of the present invention, but the present invention is not limited to the following content.

[0067] In the simulation experiment, taking P-type as the first conductivity type and N-type as the second conductivity type as an example, use Figure 3A of the EGDTSCR to conduct an ESD current experiment, and obtain the current simulation density distribution diagram of the EGDTSCR at different times, where Figure 5A is the current simulation density distribution diagram at the turn-on moment of the reverse gate-controlled diode D2. It can be seen that the ESD current discharges to the cathode through the reverse diode D2 and PW, and the ESD current in PW will converge in the floating P+ region. Figure 5B is the current simulation density distribution diagram at the turn-on moment of the parasitic NPN, Figure 5C shows the current simulation density distribution diagram at the moment when the SCR conducts.

[0068] In summary, the thyristor of the present invention forms two back-to-back diodes in the heavily doped active regions sharing a cross-connection, enabling the ESD current to be discharged from the circuit composed of the surface diodes to increase the holding voltage of the device, and reducing the current path length of the diodes through the setting of the forward diode. Moreover, by replacing the back-to-back diodes with gate-controlled diodes, a lower trigger and faster response time can be achieved under ESD stress without using other triggering devices. And by adjusting the width of the gate-controlled diode active region, the holding voltage of the device can be flexibly adjusted.

[0069] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thyristor rectifier, characterized in that, it includes: A substrate of the first conductivity type; A deep well region of the second conductivity type formed within the substrate; A well region of the first conductivity type and a well region of the second conductivity type formed side by side within the deep well region; A first heavily doped active region of the second conductivity type and a first heavily doped active region of the first conductivity type are disposed within the well region of the second conductivity type. Both the first heavily doped active region of the second conductivity type and the first heavily doped active region of the first conductivity type are connected to the anode, and a first shallow trench isolation structure is provided therebetween; A second heavily doped active region of the second conductivity type and a second heavily doped active region of the first conductivity type are disposed within the well region of the first conductivity type. Both the second heavily doped active region of the second conductivity type and the second heavily doped active region of the first conductivity type are connected to the cathode, and a second shallow trench isolation structure is provided therebetween; A third heavily doped active region of the second conductivity type straddles the well region of the first conductivity type and the well region of the second conductivity type. The third heavily doped active region of the second conductivity type is spaced apart from the first heavily doped active region of the first conductivity type by a first distance, and the first heavily doped active region of the first conductivity type and the well region of the second conductivity type form a forward diode; A third heavily doped active region of the first conductivity type is disposed within the well region of the first conductivity type between the second heavily doped active region of the second conductivity type and the third heavily doped active region of the second conductivity type. A third shallow trench isolation structure is provided between the second heavily doped active region of the second conductivity type and the third heavily doped active region of the first conductivity type. The third heavily doped active region of the second conductivity type is spaced apart from the third heavily doped active region of the first conductivity type by a second distance, and the third heavily doped active region of the second conductivity type and the well region of the first conductivity type form a reverse diode; A first gate formed on the substrate between the first heavily doped active region of the first conductivity type and the third heavily doped active region of the second conductivity type; and A second gate formed on the substrate between the third heavily doped active region of the first conductivity type and the third heavily doped active region of the second conductivity type, wherein the first gate, the second gate are electrically connected to the third heavily doped active region of the second conductivity type.

2. The thyristor rectifier according to claim 1, characterized in that, the first conductivity type is P-type and the second conductivity type is N-type.

3. The thyristor rectifier according to claim 1, characterized in that, the first conductivity type is N-type and the second conductivity type is P-type.

4. The thyristor rectifier according to claim 1, characterized in that, the first distance meets the minimum distance requirement of the design rules of the gate.

5. The thyristor rectifier according to claim 1, characterized in that, the second distance meets the minimum distance requirement of the design rules of the gate.

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