Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate being formed with a gate structure, source-drain doped layers being formed in the substrate on both sides of the gate structure, and an etching stop layer being formed on the sidewall of the gate structure; modifying the etching stop layer on the part of the height of the sidewall of the gate structure to form a sacrificial layer at the position close to the top of the gate structure, the etching resistance of the sacrificial layer being less than that of the etching stop layer; forming source-drain plugs between adjacent sacrificial layers and electrically connecting with the source-drain doped layers; removing the sacrificial layer to form a trench surrounded by the sidewall of the gate structure, the remaining etching stop layer and the source-drain plugs; forming a sealing layer on the top of the gate structure, the sealing layer also sealing the top of the trench to form an air gap sidewall surrounded by the gate structure, the source-drain plugs, the remaining etching stop layer and the sealing layer. The present application saves the space occupied by the sidewall and is easy to form the air gap sidewall under the development trend of the continuously reduced distance between adjacent gate structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As integrated circuits become increasingly dense and semiconductor process technology nodes shrink, the distance between adjacent devices becomes smaller. On the same chip, the decreasing distance between the gate structures of different transistors leads to a larger parasitic capacitance between adjacent gate structures. This parasitic capacitance increases capacitive coupling between gate structures, thereby increasing energy consumption and raising the resistance-capacitance (RC) time constant. This affects the chip's operating speed and severely impacts the reliability of the devices on the chip.

[0003] In the prior art, low-k materials are typically used to form sidewalls on the sidewall surface of the gate structure to reduce the parasitic capacitance between adjacent gate structures, thereby improving the performance of the transistor.

[0004] As the spacing between gate structures decreases further, the difficulty of forming low-k sidewalls on both sides of the gate structure increases. At the same time, the sidewalls formed by traditional low-k materials cannot further reduce the dielectric constant. The existing methods have limited effect on improving parasitic capacitance, and the performance of transistors needs to be further improved.

[0005] Currently, the dielectric constant of the sidewalls is further reduced by introducing air gaps into the sidewalls of the gate structure. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source / drain doped layers located in the substrate on both sides of the gate structure; a source / drain plug located on the source / drain doped layers; an etch stop layer located between the source / drain plug and an adjacent gate structure, wherein the etch stop layer covers a portion of the sidewall of the gate structure near the bottom of the gate structure; a sealing layer located on the gate structure, wherein the sealing layer also seals the top of a trench formed by the sidewall of the gate structure, the etch stop layer, and the source / drain plug; and an air gap sidewall located between the sidewall of the gate structure and the source / drain plug, wherein the air gap sidewall is formed by the gate structure, the source / drain plug adjacent to the gate structure, the etch stop layer, and the sealing layer.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source / drain doped layers are formed in the substrate on both sides of the gate structure, and an etch stop layer is formed on the sidewall of the gate structure, the etch stop layer further extending to cover the top of the source / drain doped layers; modifying the etch stop layer at a portion of the height of the sidewall of the gate structure near the top of the gate structure to form a sacrificial layer, wherein the etch resistance of the sacrificial layer is less than that of the etch stop layer; forming a source / drain plug between adjacent sacrificial layers, the source / drain plug penetrating the etch stop layer at the top of the source / drain doped layer and electrically connected to the source / drain doped layer; removing the sacrificial layer to form a trench surrounded by the sidewall of the gate structure, the remaining etch stop layer and the source / drain plug; forming a sealing layer on the top of the gate structure, the sealing layer further sealing the top of the trench to form an air gap sidewall surrounded by the gate structure, the source / drain plug, the remaining etch stop layer and the sealing layer.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] This invention provides a semiconductor structure including an etch stop layer located between a source / drain plug and an adjacent gate structure, wherein the etch stop layer covers a portion of the sidewall of the gate structure near the bottom of the gate structure. It also includes a sealing layer on the gate structure, which seals the top of a trench formed by the gate structure sidewall, the etch stop layer, and the source / drain plug. The gate structure, the adjacent source / drain plug, the etch stop layer, and the sealing layer form an air gap sidewall. The air gap sidewall is located above the etch stop layer and occupies only the space of the etch stop layer. Therefore, compared to solutions that form a trench by removing the sidewall, this method... In contrast, the embodiments of the present invention do not require the formation of a stacked sidewall structure to form an air gap sidewall, thus saving the space occupied by the sidewall. It is also easier to form an air gap sidewall under the trend of continuously shrinking spacing between adjacent gate structures. At the same time, since the air gap sidewall is surrounded by an etch stop layer, the height of the air gap sidewall can be determined by the height of the etch stop layer. Therefore, the height of the air gap sidewall is adjustable, which is beneficial to adjust the height of the etch stop layer according to different process requirements, thereby adjusting the height of the air gap sidewall. This helps to meet different performance requirements of the semiconductor structure and improve the performance of the semiconductor structure.

[0011] In the formation method provided by this embodiment of the invention, a portion of the etch stop layer located near the top of the gate structure sidewall is modified to form a sacrificial layer. The sacrificial layer has lower etch resistance than the etch stop layer. A source / drain plug is formed between adjacent sacrificial layers, penetrating the etch stop layer above the source / drain doped layer and electrically connected to it. The sacrificial layer is then removed, forming a trench surrounded by the gate structure sidewall, the remaining etch stop layer, and the source / drain plug. A sealing layer is formed at the top of the gate structure, also sealing the top of the trench, thus forming an air gap sidewall surrounded by the gate structure, the source / drain plug, the remaining etch stop layer, and the sealing layer. In this embodiment, a portion of the etch stop layer is converted into a sacrificial layer, and then the sacrificial layer is removed to form the air gap sidewall. Therefore, the air gap sidewall only occupies the space of the etch stop layer. Therefore, compared to the method of forming trenches by removing sidewalls, the embodiments of the present invention do not require the formation of a stacked sidewall structure to form the air gap sidewalls, thus saving the space occupied by the sidewalls. It is also easy to form air gap sidewalls under the trend of continuously shrinking spacing between adjacent gate structures. At the same time, the air gap sidewalls are surrounded by etch stop layers, and the trenches are formed by converting a portion of the etch stop layer into a sacrificial layer and then removing the sacrificial layer. Therefore, the height of the air gap sidewalls can be determined by the height of the sacrificial layer (i.e., the amount by which the height of the etch stop layer is reduced). Thus, the height of the air gap sidewalls is adjustable, which is beneficial for adjusting the height of the sacrificial layer according to different process requirements, thereby adjusting the height of the air gap sidewalls. This is beneficial for meeting different performance requirements of semiconductor structures and improving the performance of semiconductor structures. Attached Figure Description

[0012] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 8 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0016] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1A substrate 10 is provided, on which a gate structure 11 is formed, and active and drain doped layers 13 are formed in the substrate 10 on both sides of the gate structure 11; a first sidewall material layer 21 is formed on the substrate 10 to conformally cover the gate structure 11; and a sacrificial material layer 20 is formed to conformally cover the first sidewall material layer 21.

[0018] refer to Figure 2 Remove the first sidewall material layer 21 and the sacrificial material layer 20 located on the top of the substrate 10 and the top of the gate structure 11, retain the remaining first sidewall material layer 21 located on the sidewall of the gate structure 11 as the first sidewall 31, and retain the remaining sacrificial material layer 20 located on the sidewall of the first sidewall 31 as the sacrificial layer 30; form a second sidewall material layer 22 that conformally covers the gate structure 11, the first sidewall 31, the sacrificial layer 30 and the substrate 10.

[0019] refer to Figure 3 Remove the second sidewall material layer 22 located on top of the gate structure 11 and the substrate 10, and retain the remaining second sidewall material layer 22 located on the sidewall of the sacrificial layer 30 as the second sidewall layer 32.

[0020] The first sidewall layer 31, the sacrificial layer 30, and the second sidewall layer 32 are used to form the sidewall 33 of the stacked structure.

[0021] After forming the sidewall 33 of the stacked structure, the method further includes: removing the gate structure 11 and forming a metal gate structure 12 at the location of the gate structure 11; forming source / drain plugs 41 that are electrically connected to the source / drain doped layers 13 on both sides of the metal gate structure 12.

[0022] refer to Figure 4 After forming the bottom source / drain plug 41, an interlayer dielectric layer (not shown) is formed covering the bottom source / drain plug 41 and the metal gate structure 12; a gate plug 50 is formed that penetrates the interlayer dielectric layer and is connected to the top of the metal gate structure 12, and a top source / drain plug 51 is formed that penetrates the interlayer dielectric layer and is connected to the bottom source / drain plug 41.

[0023] Continue to refer to Figure 4 Remove the interlayer dielectric layer (not shown) and form an opening 52 between the gate plug 50 and the adjacent top source / drain plug 41, the opening 52 exposing the top of the sidewall 33.

[0024] refer to Figure 5 Remove the sacrificial layer 30 exposed by the opening 52 to form an air gap 34 surrounded by the first sidewall layer 31 and the second sidewall layer 32.

[0025] refer to Figure 6A covering medium layer 60 is formed, which seals the top of the air gap 34 and forms an air gap sidewall 35.

[0026] To reduce the dielectric constant of the sidewall 33 and form the air gap sidewall 35, a stacked sidewall 33 needs to be formed first. The stacked sidewall 33 tends to occupy too much space in the semiconductor structure. Under the current development trend, the distance between adjacent gate structures 11 is getting smaller and smaller, making it difficult to leave enough space to form the stacked sidewall 33. It is difficult to form the air gap sidewall 35 using the stacked sidewall 33, thus making it difficult to reduce the dielectric constant of the sidewall 33 and consequently making it difficult to improve the performance of the semiconductor structure.

[0027] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, source / drain doped layers are formed in the substrate on both sides of the gate structure, and an etch stop layer is formed on the sidewall of the gate structure, the etch stop layer further extending to cover the top of the source / drain doped layers; modifying a portion of the etch stop layer located at a height near the top of the gate structure's sidewall to form a sacrificial layer, wherein the etch resistance of the sacrificial layer is less than that of the etch stop layer; forming a source / drain plug between adjacent sacrificial layers, the source / drain plug penetrating the etch stop layer at the top of the source / drain doped layers and electrically connected to the source / drain doped layers; removing the sacrificial layer to form a trench surrounded by the sidewall of the gate structure, the remaining etch stop layer, and the source / drain plug; forming a sealing layer on the top of the gate structure, the sealing layer further sealing the top of the trench to form an air gap sidewall surrounded by the gate structure, the source / drain plug, the remaining etch stop layer, and the sealing layer.

[0028] In the formation method provided by this embodiment of the invention, a portion of the etch stop layer is converted into a sacrificial layer, and then the sacrificial layer is removed to form an air gap sidewall. The air gap sidewall occupies only the position of the etch stop layer. Therefore, compared to the method of forming a trench by removing the sidewall, this embodiment of the invention does not require forming a stacked sidewall structure to form the air gap sidewall, thus saving space occupied by the sidewall. It is also easier to form the air gap sidewall under the trend of continuously shrinking spacing between adjacent gate structures. Furthermore, since the air gap sidewall is surrounded by the etch stop layer, and the trench is formed by converting a portion of the etch stop layer into a sacrificial layer and then removing the sacrificial layer, the height of the air gap sidewall can be determined by the height of the sacrificial layer (i.e., the reduction in the height of the etch stop layer). Therefore, the height of the air gap sidewall is adjustable, which is beneficial for adjusting the height of the sacrificial layer according to different process requirements, thereby adjusting the height of the air gap sidewall. This helps to meet different performance requirements of the semiconductor structure and improve the performance of the semiconductor structure.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0031] The semiconductor structure includes: a substrate 101; a gate structure 201 located on the substrate 101; a source / drain doped layer 111 located in the substrate 101 on both sides of the gate structure 201; a source / drain plug 701 located on the source / drain doped layer 111; and an etch stop layer 301 located between the source / drain plug 701 and an adjacent gate structure 201, wherein the etch stop layer 301 covers a portion of the sidewall of the gate structure 201 near the bottom of the gate structure 201; A sealing layer 801 is located on the gate structure 201, and the sealing layer 801 also seals the top of the trench formed by the sidewall of the gate structure 201, the etch stop layer 301 and the source / drain plug 701; an air gap sidewall 331 is located between the sidewall of the gate structure 201 and the source / drain plug 701, and the air gap sidewall 331 is formed by the gate structure 201, the source / drain plug 701 adjacent to the gate structure 201, the etch stop layer 301 and the sealing layer 801.

[0032] The air gap sidewall 331 is located above the etch stop layer 301. The air gap sidewall 331 only occupies the position of the etch stop layer 301. Therefore, compared with the solution of forming a trench by removing the sidewall, this embodiment does not require the formation of a stacked sidewall structure to form the air gap sidewall 331, thus saving the space occupied by the sidewall. It is also easy to form the air gap sidewall 331 under the trend of the continuous reduction of the spacing between adjacent gate structures 201. At the same time, the air gap sidewall 331 is surrounded by the etch stop layer 301, so the height of the air gap sidewall 331 can be determined by the height of the etch stop layer 301. Therefore, the height of the air gap sidewall 331 is adjustable, which is beneficial to adjust the height of the etch stop layer 301 according to different process requirements, thereby adjusting the height of the air gap sidewall 331, and thus meeting different performance requirements of the semiconductor structure, while improving the performance of the semiconductor structure.

[0033] The substrate 101 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes planar transistors, FinFETs, or gate-all-around (GAA) transistors.

[0034] In this embodiment, taking a finned field-effect transistor as an example, the substrate 101 includes a substrate and fins protruding from the substrate. The substrate is made of silicon. In other embodiments, the substrate material can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate can also be other types of substrates such as silicon-on-insulator (SiI) or germanium-on-insulator (CHI). The substrate material can be a material suitable for process requirements or easy to integrate. As an example, the fin material is the same as the substrate material.

[0035] In this embodiment, the gate structure 201 includes a metal gate structure. In this embodiment, the metal gate structure includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0036] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0037] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0038] The gate electrode layer is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0039] In other embodiments, depending on process requirements, the gate structure may also be other types of device gate structures such as polysilicon gate structures.

[0040] The source / drain doped layer 111 serves as the source or drain region of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped layer 111 is the same as the channel conductivity type of the corresponding transistor.

[0041] In this embodiment, the semiconductor structure further includes a sidewall 211 located on the sidewall of the gate structure 201. The sidewall 211 is used to protect the sidewall of the gate structure 201. In this embodiment, the sidewall 211 is a single-layer structure, and the material of the sidewall 211 is silicon nitride. In other embodiments, the material of the sidewall may also be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0042] In this embodiment, the semiconductor structure further includes a gate cap layer 221 located on top of the gate structure 201, wherein sidewalls 211 are also located on the sidewalls of the gate cap layer 221. The gate cap layer 221 serves to protect the gate structure 201 during the manufacturing process, and the sidewalls also protect the sidewalls of the gate cap layer 221. In this embodiment, the gate cap layer 221 is a dielectric material. Specifically, the material of the gate cap layer 221 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 221 is silicon nitride.

[0043] The source / drain plug 701 is used for electrical connection with the source / drain doped layer 111. In this embodiment, the source / drain plug 701 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0044] During the formation of the semiconductor structure, the etch stop layer 301 is used to stop the etch in the 701 process of forming the source and drain plug, thereby reducing the probability of the source and drain doped layer 111 being over-etched. At the same time, in this embodiment, the etch stop layer 301 located on the sidewall of the gate structure 201 is also used to occupy space for the air gap sidewall 331. That is, the air gap sidewall 331 is obtained by removing a portion of the height of the etch stop layer 301 on the sidewall of the gate structure 201.

[0045] In this embodiment, the etching stop layer 301 covers part of the sidewall of the sidewall 211, thereby providing the spatial location of the air gap sidewall 331.

[0046] The distance d from the top of the etch stop layer 301 to the top of the source / drain doped layer 111 cannot be too small. If this distance d is too small, the protective effect of the etch stop layer 301 on the underlying source / drain doped layer 111 is weakened, increasing the probability of damage to the source / drain doped layer 111 during the process, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance d from the top of the etch stop layer 301 to the top of the source / drain doped layer 111 is greater than or equal to...

[0047] The distance d from the top of the etch stop layer 301 to the top of the source / drain doped layer 111 should not be too large. If this distance d is too large, the air gap sidewall 331 will be located above the etch stop layer 301, resulting in a smaller height for the air gap sidewall 331. This will correspondingly worsen the effect of reducing the capacitance between the gate structure 201 and the source / drain plug 701, making it difficult to improve the performance of the semiconductor structure. Therefore, in this embodiment, the distance d from the top of the etch stop layer 301 to the top of the source / drain doped layer 111 is... to For example, the distance d from the top of the etch stop layer 301 to the top of the source / drain doped layer 111 is...

[0048] In this embodiment, the material of the etch stop layer 301 includes one or more of SiN, SiCN, and SiBCN. The high hardness of SiN, SiCN, and SiBCN helps ensure the protective effect of the etch stop layer 301 on other film layers during the manufacturing process.

[0049] The sealing layer 801 is used to seal the top of the trench (not shown) formed by the sidewall of the gate structure 201, the etch stop layer 301 and the source / drain plug 701, and the sealing layer 801 serves as the top of the air gap sidewall 331.

[0050] In this embodiment, the sealing layer 801 is located on top of the gate cap layer 221. The gate cap layer 221 is located on top of the gate structure 201, and the top of the source / drain plug 701 is typically higher than the top of the gate structure 201. By placing the sealing layer 801 on top of the gate cap layer 221, it is advantageous to ensure that the sealing layer 801 can seal the top of the trench. In this embodiment, the top of the sealing layer 801 is higher than the top of the source / drain plug 701.

[0051] The top of the sealing layer 801 is higher than the top of the source / drain plug 701, which is beneficial for sealing the top of the trench and provides space for the source / drain cap layer 711 located on top of the source / drain doping 701. In other words, during the formation of the source / drain cap layer 711, the probability of the air gap sidewall 331 being exposed is reduced, thereby reducing the probability that the material of the source / drain cap layer 711 will fill into the air gap sidewall 331.

[0052] In this embodiment, the material of the sealing layer 801 includes one or more of SiN, SiO2, and SiC. SiN, SiO2, and SiC have high density, thus possessing good sealing performance. They are also difficult to fill small gaps, which is beneficial for sealing the top of the trench while leaving a relatively high air gap sidewall 331 between the sealing layer 801 and the etching stop layer 301.

[0053] In this embodiment, the semiconductor structure further includes a source / drain capping layer 711, located on top of the source / drain plug 701, with the top of the source / drain capping layer 711 flush with the top of the sealing layer 801. The source / drain capping layer 711 protects the source / drain plug 701 during the subsequent formation of the gate plug. Correspondingly, the gate plug can be located above the gate structure 201 in the active region. The gate plug is an active gate contact plug (COAG). Compared to the scheme where the gate plug contacts the gate structure located in the isolation region, this embodiment eliminates the portion of the gate structure 201 located in the isolation region, which helps save chip area and further reduce chip size. Moreover, since the source / drain capping layer 711 is formed by etching back the source / drain plug 701, the top of the source / drain capping layer 711 is flush with the top of the sealing layer 801, which helps improve the flatness of the top surface of the sealing layer 801 and provides a good platform foundation for subsequent process manufacturing.

[0054] In this embodiment, the source / drain capping layer 711 is a dielectric material. Specifically, the material of the source / drain capping layer 711 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the source / drain capping layer 711 is silicon carbide.

[0055] In other embodiments, the gate capping layer and source / drain capping layer may not be provided in the semiconductor structure.

[0056] The air gap sidewall 331 has a low dielectric constant. Compared with the scheme where the etch stop layer covers the entire sidewall of the gate structure, this embodiment is beneficial to reduce the capacitance between the gate structure 201 and the source / drain plug 701, thereby improving the performance of the semiconductor structure.

[0057] In this embodiment, a sidewall 211 is formed on the sidewall of the gate structure 201. Therefore, the air gap sidewall 331 is formed by the sidewall 211, the source / drain plug 701 adjacent to the gate structure 201, the etch stop layer 301, and the sealing layer 801. It should be noted that, since the sidewall 211 is formed on the sidewall of the gate structure 201, the sidewall 211 protects the sidewall of the gate structure 201 during the formation of the air gap sidewall 331, thereby reducing the impact of the process of forming the air gap sidewall 331 on the sidewall of the gate structure 201.

[0058] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0059] Figures 8 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0060] refer to Figure 8A substrate 100 is provided, on which a gate structure 200 is formed. Source and drain doped layers 110 are formed in the substrate 100 on both sides of the gate structure 200. An etch stop layer 300 is formed on the sidewall of the gate structure 200, and the etch stop layer 300 extends to cover the top of the source and drain doped layers 110.

[0061] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a planar transistor, a fin field-effect transistor, or a gate-enclosed transistor. In this embodiment, taking a fin field-effect transistor as an example, the substrate 100 includes a substrate and fins protruding from the substrate. In this embodiment, the substrate is made of silicon, and the fins are made of the same material as the substrate. For a detailed description of the substrate fins and the fins themselves, please refer to the corresponding descriptions in the foregoing embodiments; they will not be repeated here.

[0062] In this embodiment, the gate structure 200 includes a metal gate structure. In this embodiment, the metal gate structure includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer. Specific descriptions of the high-k gate dielectric layer, the work function layer, and the gate electrode layer can be found in the corresponding descriptions in the foregoing embodiments, and will not be repeated here. In other embodiments, depending on process requirements, the gate structure may also be other types of device gate structures such as a polysilicon gate structure.

[0063] The source / drain doped layer 110 serves as the source or drain region of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0064] Subsequently, a source / drain plug connected to the source / drain doped layer 110 will be formed on top of the source / drain doped layer 110. The etch stop layer 300 is used to stop the etch during the process of forming the source / drain plug, thereby protecting other film layers. The etch stop layer 300 also extends to cover the top of the source / drain doped layer 110, which is used to protect the source / drain doped layer 110 when removing part of the etch stop layer 300 and modifying the etch stop layer 300. At the same time, the etch stop layer 300 also occupies space for the subsequent formation of air gap sidewalls.

[0065] In this embodiment, the etching stop layer 300 is made of one or more of SiN, SiCN, and SiBCN. SiN, SiCN, and SiBCN have high hardness, which is beneficial for protecting other film layers during the etching process.

[0066] In this embodiment, during the step of providing the substrate 100, a sidewall 210 is further formed between the sidewall of the gate structure 200 and the etch stop layer 300, wherein the etch stop layer 300 conformally covers the sidewall 210. The sidewall 210 protects the sidewall of the gate structure 200, thus reducing damage to the gate structure 200 during subsequent removal of part of the etch stop layer 300. In this embodiment, the sidewall 210 is a single-layer structure, and the material of the sidewall 210 is silicon nitride. In other embodiments, the material of the sidewall may also be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0067] In this embodiment, during the step of providing the substrate 100, a gate cap layer 220 is also formed on the top of the gate structure 200, wherein the etch stop layer 300 also covers the sidewall of the gate cap layer 220.

[0068] The gate cap layer 220 is used to protect the gate structure 200 during the process. The etch stop layer 300 also covers the sidewall of the gate cap layer 220. The etch stop layer 300 maximizes its height, which is more conducive to the subsequent formation of a taller air gap sidewall.

[0069] In this embodiment, the gate cap layer 220 is a dielectric material. Specifically, the material of the gate cap layer 220 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 220 is silicon nitride.

[0070] In this embodiment, during the step of providing the substrate 100, an interlayer dielectric layer 400 covering the etch stop layer 300 is also formed between adjacent gate structures 200. The interlayer dielectric layer 400 serves as an isolation layer between adjacent devices. Furthermore, the subsequent removal of a portion of the interlayer dielectric layer 400 defines the height of the etch stop layer 300 to be removed. The material of the interlayer dielectric layer 400 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0071] In this embodiment, during the step of providing the substrate 100, a covering dielectric layer 500 is also formed on the top of the gate structure 200, and the covering dielectric layer 500 covers the top of the interlayer dielectric layer 400.

[0072] The covering dielectric layer 500 is used to protect the top of the gate structure 200 to further reduce the probability of damage to the gate structure 200. In addition, by forming the covering dielectric layer 500, the process window of the planarization process (e.g., chemical mechanical polishing process) can be increased during the subsequent formation of the source / drain plugs 700 between adjacent sacrificial layers 310.

[0073] The material of the covering dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the covering dielectric layer 500 is the same as the material of the interlayer dielectric layer 400. It should be noted that in other embodiments, the step of forming the covering dielectric layer may be omitted.

[0074] In this embodiment, the formation method further includes: forming a hard mask layer 600 on the cover dielectric layer 500, wherein an opening 610 is formed in the hard mask layer 600. The hard mask layer 600 serves as an etching mask when subsequently removing the cover dielectric layer 500 above the source / drain doped layer 110 and a portion of the interlayer dielectric layer 400.

[0075] In this embodiment, the hard mask layer 600 is a non-metallic mask layer, and the material of the hard mask layer 600 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 600 can be a single-layer structure or a stacked structure. As an example, the material of the hard mask layer 600 is silicon nitride, that is, the hard mask layer 600 is a single-layer structure.

[0076] Reference Figure 9 and Figure 10 Near the top of the gate structure 200, the etch stop layer 300, located at a certain height of the sidewall of the gate structure 200, is modified to form a sacrificial layer 310, wherein the etch resistance of the sacrificial layer 310 is less than that of the etch stop layer 300.

[0077] In this embodiment of the invention, a portion of the etch stop layer 300 is transformed into a sacrificial layer 310, and then the sacrificial layer 310 is removed to form an air gap sidewall. The air gap sidewall occupies only the space of the etch stop layer 300. Therefore, compared to forming a trench by removing the sidewall, this embodiment of the invention does not require forming a stacked sidewall structure to form the air gap sidewall, thus saving space occupied by the sidewall. This makes it easier to form air gap sidewalls in the context of the continuously decreasing spacing between adjacent gate structures 200. Furthermore, the air gap sidewall is formed by the etch stop layer 300. The trench is formed by converting a portion of the etch stop layer 300 into a sacrificial layer 310 and then removing the sacrificial layer 310. Therefore, the height of the air gap sidewall can be determined by the height of the sacrificial layer (i.e., the reduction in the height of the etch stop layer 300). Thus, the height of the air gap sidewall is adjustable, which is beneficial for adjusting the height of the sacrificial layer 310 according to different process requirements, thereby adjusting the height of the air gap sidewall. This helps to meet different performance requirements of the semiconductor structure and improve the performance of the semiconductor structure.

[0078] In this embodiment, the modification process includes ion implantation or plasma processing. Ion implantation or plasma processing can achieve localized treatment, thereby altering the characteristics of the etch stop layer 300, while also minimizing the impact on other film layers.

[0079] In this embodiment, the implanted ions in the ion implantation process include hydrogen ions, and the reaction gas in the plasma process includes hydrogen-containing gas.

[0080] Since the material of the etching stop layer 300 typically includes nitrogen and silicon, the electrostatic attraction between hydrogen and nitrogen atoms easily pulls nitrogen atoms away from silicon atoms, increasing the bond length of the silicon-nitrogen bond and correspondingly reducing the bond energy of the silicon-nitrogen bond, thus making the sacrificial layer 310 easier to etch.

[0081] In this embodiment, the modification process using plasma technology is used as an example for illustration.

[0082] The plasma process can be either anisotropic or isotropic. Specifically, the plasma process includes one or more of the following: inductively coupled plasma (ICP), capacitively coupled plasma (CCP), electron cyclotron resonance (ECR), and remote plasma.

[0083] In this embodiment, the process parameters of the plasma process include: the reactant gas includes one or both of H2 and NH3, the catalytic gas includes N2, and the stabilizing gas includes He. Using one or both of H2 and NH3 as the reactant gas is beneficial for altering the characteristics of the etching stop layer 300 through hydrogen atoms; N2 is beneficial for improving the reaction efficiency of the process; and He is used to increase the stability of the process.

[0084] In this embodiment, the process parameters of the plasma process include: a gas flow rate of 10 sccm to 180 sccm, a source RF power of 500W to 1000W, and a bias voltage of 0V to 500V. By reasonably adjusting the gas flow rate, source RF power, and bias voltage, the hydrogen concentration in the etch stop layer 300 affected by the modification treatment is adjusted, thereby obtaining a better modification treatment effect, changing the etching resistance of the sacrificial layer 310, and thus improving the etching selectivity ratio between the sacrificial layer 310 and the etch stop layer 300.

[0085] The flow rate of the reactant gas must be neither too high nor too low. If the flow rate is too high, it may affect the etch stop layer 300 that does not require modification during the modification process, and may cause unnecessary process waste. If the flow rate is too low, the plasma density may be too low, making it difficult to completely modify part of the etch stop layer 300, making it difficult to form the sacrificial layer 310 with low etch resistance, and the effect and uniformity of the modification process may deteriorate. This is also detrimental to improving the etch selectivity ratio between the sacrificial layer 310 and the etch stop layer 300, thereby affecting the subsequent removal of the sacrificial layer 310 and consequently affecting the formation of the air gap sidewall. Therefore, in this embodiment, the flow rate of the reactant gas is 10 sccm to 180 sccm. For example, the flow rate is 50 sccm or 100 sccm.

[0086] The source RF power cannot be too high or too low. The source RF power is used to plasmaize the reactive gas. If the source RF power is too high, the plasma density will be too high, making it easy for the plasma to penetrate the etch stop layer 300 and damage other film layers. This also increases process costs and is subject to process limitations. If the source RF power is too low, the plasmaization effect of the reactive gas will be poor, and the plasma density will be too low, making it difficult to completely modify part of the etch stop layer 300. This makes it difficult to form the sacrificial layer 310 with low etch resistance, and the uniformity of the modification process will easily deteriorate. Furthermore, it is not conducive to improving the etch selectivity ratio between the sacrificial layer 310 and the etch stop layer 300, thus affecting the subsequent removal of the sacrificial layer 310 and consequently affecting the formation of the subsequent air gap sidewall. Therefore, in this embodiment, the source RF power is 500W to 1000W. For example, the source RF power is 700W or 800W.

[0087] The bias voltage must not be too high or too low. Under the influence of the bias voltage, the plasma can acquire the kinetic energy to bombard the partial etching stop layer 300. If the bias voltage is too low, the kinetic energy provided to the plasma will be insufficient, which may easily lead to a decrease in the effect and uniformity of the modification treatment, thereby affecting the subsequent removal of the sacrificial layer 310 and consequently affecting the formation of the subsequent air gap sidewalls. If the bias voltage is too high, it may easily damage other film layers. Therefore, in this embodiment, the bias voltage is 0V to 500V. For example, the bias voltage is 100V, 200V, or 300V.

[0088] The etch selectivity ratio of the sacrificial layer 310 to the etch stop layer 300 cannot be too small. If the etch selectivity ratio of the sacrificial layer 310 to the etch stop layer 300 is too small, it will be difficult to retain the remaining etch stop layer 300 when removing the sacrificial layer 310, increasing the probability of damaging the source / drain doped layer 110 and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the etch selectivity ratio of the sacrificial layer 310 to the etch stop layer 300 is greater than 10:1.

[0089] Specifically, refer to Figure 9 Before the modification process, a portion of the interlayer dielectric layer 400 above the source / drain doped layer 110 is removed to expose a portion of the etch stop layer 300 located on the sidewall of the gate junction 200.

[0090] The interlayer dielectric layer 400 with a portion of its thickness above the source / drain doped layer 110 is removed to expose a portion of the etch stop layer 300 located on the sidewall of the gate junction 200, in preparation for modification of a portion of the etch stop layer 300, and to define the height of the subsequent sacrificial layer 310.

[0091] In this embodiment, a dry etching process is used to remove a portion of the thickness of the interlayer dielectric layer 400.

[0092] The dry etching method has anisotropic characteristics, which helps to reduce damage to other film layers when removing a portion of the interlayer dielectric layer 400. Furthermore, the dry etching method is more directional, which helps to precisely control the etching amount of the interlayer dielectric layer 400.

[0093] After removing a portion of the interlayer dielectric layer 400, the distance d from the top of the remaining interlayer dielectric layer 400 to the top of the source / drain doped layer 110 cannot be too small. If the distance d is too small, the protection provided by the remaining interlayer dielectric layer 400 to the underlying source / drain doped layer 110 is weakened during modification of the exposed interlayer dielectric layer 400 and removal of the sacrificial layer 310, increasing the probability of damage to the source / drain doped layer 110 during the process and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance d from the top of the remaining interlayer dielectric layer 400 to the top of the source / drain doped layer 110 is greater than or equal to...

[0094] The distance d from the top of the remaining interlayer dielectric layer 400 to the top of the source / drain doped layer 110 should not be too large. If the distance d is too large, the height of the exposed etch stop layer 300 will be too small, resulting in a correspondingly small height of the subsequently formed air gap sidewalls. This will worsen the effect of reducing the capacitance between the gate structure 201 and the source / drain plug 701, making it difficult to improve the performance of the semiconductor structure. Therefore, in this embodiment, the distance d from the top of the remaining interlayer dielectric layer 400 to the top of the source / drain doped layer 110 is... to For example, the distance d from the top of the remaining interlayer dielectric layer 400 to the top of the source / drain doped layer 110 is...

[0095] In this embodiment, before removing a portion of the interlayer dielectric layer 400, the method further includes removing the cover dielectric layer 500 located on top of the interlayer dielectric layer 400. Removing the cover dielectric layer 500 located on top of the source / drain doped layers 110 exposes the top of the interlayer dielectric layer 400 to be removed, preparing for the removal of the portion of the interlayer dielectric layer 400. Specifically, using the hard mask layer 600 as a mask, the cover dielectric layer 500 and the portion of the interlayer dielectric layer 400 are sequentially etched along the opening 610.

[0096] refer to Figure 10 In the modification process, the etch stop layer 300 exposed by the remaining interlayer dielectric layer 400 is modified.

[0097] The etch stop layer 300 exposed on the remaining interlayer dielectric layer 400 is modified to form a sacrificial layer 310, in preparation for the subsequent removal of the sacrificial layer 310.

[0098] In this embodiment, after the modification treatment, the process further includes: removing the hard mask layer 600.

[0099] Combined with references such as Figure 11 and Figure 12 A source / drain plug 700 is formed between adjacent sacrificial layers 310. The source / drain plug 700 penetrates the etch stop layer 300 at the top of the source / drain doped layer 110 and is electrically connected to the source / drain doped layer 110.

[0100] The source / drain plug 700 is used to electrically connect to the source / drain doped layer 110. At the same time, the source / drain plug 700 is also used to provide a process basis for the subsequent formation of air gap sidewalls.

[0101] In this embodiment, the source / drain plug 700 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0102] Specifically, refer to Figure 11 After modification treatment, before forming source / drain plugs between adjacent sacrificial layers 310, the process further includes: removing the remaining interlayer dielectric layer 400 (e.g., ...) at the top of the source / drain doped layer 110. Figure 10 (As shown).

[0103] The remaining interlayer dielectric layer 400 at the top of the source / drain doped layer 110 is removed, exposing the etch stop layer 300 at the top of the source / drain doped layer 110. This etch stop layer 300 is used to prepare for the formation of source / drain plugs that penetrate the top of the source / drain doped layer 110. In this embodiment, a dry etching process is used to remove the remaining interlayer dielectric layer 400 at the top of the source / drain doped layer 110.

[0104] Reference Figure 11 and Figure 12 The step of forming the source / drain plug 700 includes: forming a contact hole (not shown) between adjacent sacrificial layers 310, the contact hole penetrating the etch stop layer 300 at the top of the source / drain doped layer 110; filling the contact hole with a conductive material to form the source / drain plug 700 located in the contact hole.

[0105] In this embodiment, the remaining interlayer dielectric layer 400 and the etching stop layer 300 on top of the source / drain doped layer 110 are etched sequentially using the same etching step to form a contact hole.

[0106] In this embodiment, during the step of forming the source / drain plug 700, the source / drain plug 700 is also formed in the covering medium layer 500, that is, the top of the source / drain plug 700 is flush with the top of the covering medium layer 500.

[0107] The covering dielectric layer 500 needs to be removed to form a sealing layer. The source / drain plug 700 is also formed in the covering dielectric layer 500, that is, the top of the source / drain plug 700 is higher than the top of the gate structure 200. This prepares for the subsequent removal of a portion of the thickness of the source / drain plug 700 and the formation of a source / drain cap layer on top of the remaining source / drain plug 700, so that the source / drain cap layer can be formed in the covering dielectric layer 500, reducing the impact on the air gap.

[0108] refer to Figure 13 Remove the sacrificial layer 310 (e.g.) Figure 12 As shown, a trench 320 is formed by the sidewalls of the gate structure 200, the remaining etch stop layer 300, and the source / drain plug 700.

[0109] The groove 320 is formed to provide space for the subsequent formation of the air gap sidewall.

[0110] It should be noted that the etching selectivity of the sacrificial layer 310 compared to other film layers is relatively high, thereby improving the flexibility of the process for removing the sacrificial layer 310. Both isotropic and anisotropic etching processes can be selected.

[0111] In this embodiment, the process for removing the sacrificial layer 310 includes wet etching, SiCoNi etching, or plasma dry etching. In this embodiment, the parameters of the wet etching process include: the etching solution comprises a diluted hydrofluoric acid solution, wherein the volume concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is 0.15% to 1%. A fluorine-containing solution is beneficial for improving the etching selectivity ratio between the sacrificial layer 310 and the etch stop layer 300.

[0112] The volume concentration of hydrofluoric acid in the diluted hydrofluoric acid solution must not be too high or too low. If the volume concentration is too high, the etching power of the diluted hydrofluoric acid solution will be too great, easily damaging the remaining etch stop layer 300, source / drain plugs 700, and sidewalls 210. If the volume concentration is too low, the etching power will be too weak, making it difficult to completely remove the sacrificial layer 310. Therefore, in this embodiment, the volume concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is 0.15% to 1%. For example, the volume concentration is 0.18%.

[0113] In this embodiment, the process parameters of the plasma dry etching process include: the reaction gas includes a mixture of NF3 and CH4, a mixture of NF3 and H2, or a mixture of NF3, H2, and CH4. NF3 is a necessary reaction gas for the process, and H2 and CH4 are used to increase process efficiency.

[0114] In this embodiment, the sidewall 210 covers the sidewalls of the gate structure 200 and the gate cap layer 220. Therefore, in the step of removing the sacrificial layer 310, the trench 320 is formed by the sidewall of the sidewall 210, the remaining etch stop layer 300 and the source / drain plug 700.

[0115] In this embodiment, after forming the source / drain plug 700 and before removing the sacrificial layer 310, the method further includes: removing the remaining covering dielectric layer 500 (e.g., ...). Figure 12 (As shown). The cover dielectric layer 500 is removed to expose the top of the sacrificial layer 310, in preparation for the removal of the sacrificial layer 310. In this embodiment, a wet etching process is used to remove the cover dielectric layer 500.

[0116] refer to Figure 14 A sealing layer 800 is formed on top of the gate structure 200, and the sealing layer 800 also seals the trench 320 (e.g., Figure 13On the top of the gate structure 200, source / drain plug 700, remaining etch stop layer 300 and sealing layer 800, an air gap sidewall 330 is formed.

[0117] The air gap sidewall 330 has a low dielectric constant. Compared with the scheme where the etch stop layer covers the entire sidewall of the gate structure 200, this embodiment is beneficial to reduce the capacitance between the gate structure 200 and the source / drain plug 700, thereby improving the performance of the semiconductor structure.

[0118] In this embodiment, an air gap sidewall 330 is formed, consisting of a sidewall 210, a source / drain plug 700, a remaining etch stop layer 300, and a sealing layer 800. Since the sidewall 210 covers the sidewall of the gate structure 200, the air gap sidewall 330 is formed by the sidewall 210, the source / drain plug 700, the remaining etch stop layer 300, and the sealing layer 800.

[0119] In this embodiment, the sealing layer 800 covers the top of the gate cap layer 220. The gate cap layer 220 is located on top of the gate structure 200, and the sealing layer 800 is located on top of the gate cap layer 220, which helps to seal the trench 320 formed by the sidewalls of the gate structure 200.

[0120] In this embodiment, the sealing layer 800 covers the sidewall of the source / drain plug, which helps to ensure the top of the sealing trench 320 and provides a process basis for the subsequent formation of the source / drain cap layer. In this embodiment, the process for forming the sealing layer 800 includes chemical vapor deposition (CVD) or furnace tube processes. CVD or furnace tube processes have relatively low filling capacity and high process stability, which helps to seal the top of the trench 320 and form an air gap sidewall 330 with a height that meets process requirements.

[0121] refer to Figure 15 After the sealing layer 800 is formed, a portion of the height of the source / drain plug 700 is removed to form a groove (not shown) surrounded by the sealing layer 800 and the top of the remaining source / drain plug 700; a source / drain cap layer 710 is formed in the groove.

[0122] The source / drain capping layer 710 is used in the subsequent process of forming the gate plug to protect the source / drain plug 700. Correspondingly, the gate plug can be located above the gate structure 200 in the active region. The gate plug is an active gate contact plug. Compared to the scheme where the gate plug contacts the gate structure located in the isolation region, this embodiment can eliminate the portion of the gate structure 200 located in the isolation region, which helps save chip area and thus achieves further reduction in chip size. Moreover, since the source / drain capping layer 710 is formed by etching back the source / drain plug 700, the top of the source / drain capping layer 710 is flush with the top of the sealing layer 800, which helps improve the flatness of the top surface of the sealing layer 800 and provides a good platform foundation for subsequent process steps.

[0123] In this embodiment, the source / drain capping layer 710 is a dielectric material. Specifically, the material of the source / drain capping layer 710 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the source / drain capping layer 710 is silicon carbide.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, include: A substrate is provided on which a gate structure is formed, and source / drain doped layers are formed in the substrate on both sides of the gate structure. An etch stop layer is formed on the sidewall of the gate structure, and the etch stop layer extends to cover the top of the source / drain doped layers. Near the top of the gate structure, the etch stop layer at a certain height located on the sidewall of the gate structure is modified to form a sacrificial layer, wherein the etch resistance of the sacrificial layer is less than that of the etch stop layer; A source / drain plug is formed between adjacent sacrificial layers, the source / drain plug penetrating the etch stop layer at the top of the source / drain doped layer and being electrically connected to the source / drain doped layer; Remove the sacrificial layer to form a trench surrounded by the gate structure sidewalls, the remaining etch stop layer, and the source / drain plugs; A sealing layer is formed on top of the gate structure, and the sealing layer also seals the top of the trench, forming an air gap sidewall surrounded by the gate structure, source / drain plugs, remaining etch stop layer and sealing layer.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, an interlayer dielectric layer covering the etch stop layer is also formed between adjacent gate structures; Before performing the modification process, the formation method further includes: removing a portion of the interlayer dielectric layer above the source / drain doped layer to expose a portion of the etch stop layer located on the sidewall of the gate structure; In the modification process, the etch stop layer exposed by the remaining interlayer dielectric layer is modified. After the modification treatment, before forming source / drain plugs between adjacent sacrificial layers, the formation method further includes: removing the remaining interlayer dielectric layer on top of the source / drain doped layers.

3. The method of forming a semiconductor structure of claim 2, wherein, In the step of providing the substrate, a cover dielectric layer is further formed on top of the gate structure, and the cover dielectric layer covers the top of the interlayer dielectric layer; Before removing a portion of the interlayer dielectric layer, the method further includes: removing the overlay dielectric layer located on top of the source / drain doped layers; In the step of forming the source / drain plug, the source / drain plug is also formed in the covering medium layer; After forming the source / drain plug and before removing the sacrificial layer, the process further includes removing the remaining cover medium layer.

4. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, a gate capping layer is further formed on the top of the gate structure, wherein the etch stop layer further covers the sidewall of the gate capping layer; In the step of forming the sealing layer, the sealing layer covers the top of the gate cap layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a sealing layer on top of the gate structure, the sealing layer covers the sidewalls of the source / drain plug; After forming the sealing layer, the forming method further includes: removing a portion of the height of the source / drain plug to form a groove surrounded by the sealing layer and the top of the remaining source / drain plug; A source / drain cap layer is formed in the groove.

6. The method of forming a semiconductor structure according to claim 1 or 2, wherein The step of forming the source / drain plug includes: forming a contact hole between adjacent sacrificial layers, the contact hole penetrating an etch stop layer on top of the source / drain doped layers; filling the contact hole with a conductive material to form a source / drain plug located in the contact hole.

7. The method of forming a semiconductor structure of claim 1, wherein, The modification process includes ion implantation or plasma processing.

8. The method of forming a semiconductor structure of claim 7, wherein, The implanted ions in the ion implantation process include hydrogen ions, and the reaction gas in the plasma process includes hydrogen-containing gas.

9. The method of forming a semiconductor structure of claim 7, wherein, The plasma process includes one or more of the following: inductively coupled plasma process, capacitively coupled plasma process, electron cyclotron resonance process, and remote plasma process.

10. The method of forming a semiconductor structure of claim 7, wherein, The process parameters of the plasma process include: the reactive gas includes one or both of H2 and NH3, the catalytic gas includes N2, and the stabilizing gas includes He.

11. The method of forming a semiconductor structure of claim 7, wherein, The process parameters of the plasma process include: a gas flow rate of 10 sccm to 180 sccm for the reaction gas, a source RF power of 500 W to 1000 W, and a bias voltage of 0 V to 500 V.

12. The method of forming a semiconductor structure of claim 1, wherein, The process for removing the sacrificial layer includes wet etching, SiCoNi etching, or plasma dry etching.

13. The method of forming a semiconductor structure of claim 12, wherein, The parameters of the wet etching process include: the etching solution includes a diluted hydrofluoric acid solution, wherein the volume concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is 0.15% to 1%.

14. The method of forming a semiconductor structure of claim 12, wherein, The process parameters of the plasma dry etching process include: the reaction gas includes a mixture of NF3 and CH4, a mixture of NF3 and H2, or a mixture of NF3, H2 and CH4.

15. The method of forming a semiconductor structure of claim 2, wherein, A portion of the interlayer dielectric layer is removed using a dry etching process.

16. The method of forming a semiconductor structure of claim 1, wherein, The process for forming the sealing layer includes chemical vapor deposition or furnace tube process.

17. The method of forming a semiconductor structure of claim 1, wherein, The etch selectivity ratio of the sacrificial layer to the etch stop layer is greater than 10:

1.

18. A semiconductor structure, characterized by The semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 17, the semiconductor structure comprising: Base; A gate structure is located on the substrate; Sidewall, located on the sidewall of the gate structure; Source and drain doped layers are located in the substrate on both sides of the gate structure; Source / drain plugs are located on the source / drain doped layer; An etch stop layer is located between the source / drain plug and the adjacent sidewall, and the etch stop layer covers a portion of the sidewall near the bottom of the gate structure; A sealing layer is located on the gate structure, and the sealing layer also seals the top of the trench formed by the sidewalls of the gate structure, the etch stop layer and the source / drain plugs; An air gap sidewall is located between the sidewall of the gate structure and the source / drain plug, and the air gap sidewall is formed by the gate structure, the source / drain plug adjacent to the gate structure, the etch stop layer, and the sealing layer.

19. The semiconductor structure of claim 18, wherein, The semiconductor structure further includes a gate cap layer located on top of the gate structure, wherein the sealing layer is located on top of the gate cap layer.

20. The semiconductor structure of claim 18, wherein, The top of the sealing layer is higher than the top of the source / drain plug; The semiconductor structure further includes a source / drain cap layer located on top of the source / drain plug, the top of the source / drain cap layer being flush with the top of the sealing layer.

21. The semiconductor structure as claimed in claim 18, characterized in that, The distance from the top of the etch stop layer to the top of the source / drain doped layer is greater than or equal to 50 Å.

22. The semiconductor structure of claim 21, wherein, The distance from the top of the etch stop layer to the top of the source / drain doped layer is 50 Å to 120 Å.

23. The semiconductor structure of claim 18, wherein, The material of the etch stop layer includes one or more of SiN, SiCN, and SiBCN.

24. The semiconductor structure of claim 18, wherein, The material of the sealing layer includes one or more of SiN, SiO2, and SiC.

25. The semiconductor structure of claim 18, wherein, The gate structure includes a metal gate structure.

Images