Semiconductor device and method for manufacturing semiconductor device

Abstract

Embodiments relate to a semiconductor device and a manufacturing method of a semiconductor device. A semiconductor device of an embodiment has a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a conductive portion, a first insulating portion, a gate electrode, a second insulating portion, and a third insulating portion. The first semiconductor region is provided between the first electrode and the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the second semiconductor region and the second electrode. The conductive portion has a first conductive portion and a second conductive portion provided on the second electrode side and having a lower impurity concentration than the first conductive portion. The first insulating portion is provided between the first conductive portion and the first semiconductor region. The gate electrode is provided between the second semiconductor region and the second conductive portion. The second insulating portion is provided between the second conductive portion and the gate electrode. The third insulating portion is provided between the second semiconductor region and the gate electrode.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-37198 (filed on March 9, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods mainly relate to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0004] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are used as switching elements. In semiconductor devices, it is required to suppress damage and reduce resistance during conduction. Summary of the Invention

[0005] The embodiments provide a semiconductor device capable of suppressing damage and a method for manufacturing the semiconductor device.

[0006] The semiconductor device of the embodiment includes: a first electrode; a second electrode; a first semiconductor region of a first conductivity type disposed between the first electrode and the second electrode and electrically connected to the first electrode; a plurality of second semiconductor regions of a second conductivity type disposed between the first semiconductor region and the second electrode; a third semiconductor region of a first conductivity type disposed between the second semiconductor region and the second electrode and electrically connected to the second electrode; a conductive portion disposed between the first electrode and the second electrode, and comprising: a first conductive portion disposed on the first electrode side of the conductive portion in a first direction from the first electrode toward the first semiconductor region; a second conductive portion disposed on the second electrode side of the conductive portion in the first direction, located between the second semiconductor regions in a second direction intersecting the first direction, and having an impurity concentration lower than that of the first conductive portion; a first insulating portion disposed between the first conductive portion and the first semiconductor region; a gate electrode disposed between the second semiconductor region and the second conductive portion in the second direction; a second insulating portion disposed between the second conductive portion and the gate electrode; and a third insulating portion disposed between the second semiconductor region and the gate electrode.

[0007] Further, a manufacturing method of a semiconductor device of an embodiment forms a trench in a first semiconductor region of a first conductivity type in a first direction from a surface of the first semiconductor region; forms a first insulating portion on a surface of the trench; forms a first conductive portion on the first insulating portion in the trench; forms a second conductive portion in the first direction between the first conductive portion and the first insulating portion, the second conductive portion being in contact with the first conductive portion and having an impurity concentration smaller than that of the first conductive portion; removes a part of the first insulating portion to expose a part of the second conductive portion and a part of an inner wall of the trench in a second direction intersecting the first direction; forms a second insulating portion by oxidizing a surface of the second conductive portion; forms a third insulating portion by oxidizing the exposed inner wall of the trench; forms a gate electrode between the second insulating portion and the third insulating portion; forms a second semiconductor region of a second conductivity type in the first semiconductor region so as to oppose the gate electrode in the second direction with the third insulating portion interposed therebetween; and forms a third semiconductor region of the first conductivity type between the surface and the second semiconductor region. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1A is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 1B is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 1A is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 1C is a cross-sectional view of a semiconductor device 100 of the first embodiment.

[0009] FIG. 2A is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 2B is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 2A is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 2C is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 2A is a cross-sectional view of a semiconductor device 100 of the first embodiment.

[0010] FIG. 3A - FIG. 10B is a cross-sectional view of a semiconductor device 100 of the first embodiment.

[0011] FIG. 11 is a cross-sectional view of a semiconductor device 100 of the first embodiment.

[0012] FIG. 12A is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 12B is a cross-sectional view of a semiconductor device 100 of the first embodiment. FIG. 12A is a cross-sectional view of a semiconductor device 100 of the first embodiment.

[0013] FIG. 13A - FIG. 14B is a cross-sectional view of a semiconductor device 100 of the first embodiment.

[0014] FIG. 15A is a sectional view of the semiconductor device 200 of the second embodiment. FIG. 15B is a sectional view of the dashed line F portion of FIG. 15A .

[0015] FIG. 16A - FIG. 16B is a sectional view of the semiconductor device 200 of the second embodiment.

[0016] FIG. 17A is a plan view of the semiconductor device 400 of the comparative example. FIG. 17B is a sectional view at H-H' of FIG. 17A . FIG. 17C is a sectional view at I-I' of FIG. 17A .

[0017] FIG. 18A is a plan view of the semiconductor device 200 of the second embodiment. FIG. 18B is a sectional view at J-J' of FIG. 18A .

[0018] FIG. 19 is a plan view of the semiconductor device 201 having a field plate structure of a point trench type.

[0019] FIG. 20A is a sectional view of the semiconductor device 300 of the third embodiment. FIG. 20B is a sectional view of the dashed line M portion of FIG. 20A .

[0020] FIG. 21A - FIG. 22B is a sectional view of the semiconductor device 300 of the third embodiment.

[0021] FIG. 23 is a sectional view of another manufacturing method of the semiconductor device 300 of the third embodiment. DETAILED DESCRIPTION

[0022] Embodiments of the present application will be explained below with reference to the drawings. In the explanation, common parts are denoted by common reference numerals in all the drawings. In addition, the dimensional ratios of the drawings are not limited to the illustrated ratios. In addition, the present embodiments are not limited to the present application.

[0023] [First Embodiment]

[0024] (Structure of Semiconductor Device 100)

[0025] Referring to FIG. 1A , FIG. 1B , FIG. 1C , FIG. 2A , FIG. 2B and FIG. 2CA detailed configuration of the semiconductor device 100 of the first embodiment will be described. FIG. 1A is a cross-sectional view of the semiconductor device 100 of the first embodiment, FIG. 1B is a cross-sectional view of the dashed line A portion of FIG. 1A FIG. 1C is a cross-sectional view of the semiconductor device 100 of the first embodiment. FIG. 2A is a plan view of the semiconductor device 100 of the first embodiment, FIG. 2B is a cross-sectional view of FIG. 2A C-C' of FIG. 2C is a cross-sectional view of FIG. 2A D-D' of

[0026] Hereinafter, a case where the first conductive type is n-type and the second conductive type is p-type will be described. In the following description, n + , n + , and p + , p + indicate the relative levels of impurity concentrations in each conductive type. That is, n + indicates that the impurity concentration of the n-type is relatively high compared to n + indicates that the impurity concentration of the n-type is relatively low compared to n + indicates that the impurity concentration of the p-type is relatively high compared to p + indicates that the impurity concentration of the p-type is relatively low compared to p + type, n - type are simply described as n-type, p + type, p - type are simply described as p-type.

[0027] The impurity concentration in the semiconductor region can be measured, for example, by a Time of Flight-Secondary Ion Mass Spectrometry (TOF-SIMS). In addition, the relative levels of impurity concentrations can be determined, for example, from the levels of carrier concentrations obtained by a Scanning Capacitance Microscopy (SCM). In addition, the distances such as the depths, thicknesses, and the like of the impurity regions can be obtained by a TOF-SIMS. In addition, the distances such as the depths, thicknesses, widths, intervals, and the like of the impurity regions can be obtained from a composite image of an SCM image and an Atomic Force Microscope (AFM) image.

[0028] ​Further, the impurity concentration included in the insulating layer can be measured, for example, by an energy dispersive X-ray spectroscopy (EDX).

[0029] FIG. 1A 、 FIG. 1B and FIG. 1C The semiconductor device 100 of the first embodiment shown in FIG. 1 is a MOSFET. The semiconductor device 100 has a drain electrode 10 (first electrode), a gate electrode 13, a source electrode 14 (second electrode), an n-type first semiconductor region 20, a p-type second semiconductor region 23, an n + -type third semiconductor region 26, a conductive portion 30, and an insulating layer 40.

[0030] A direction from the drain electrode 10 toward the n-type first semiconductor region 20 is set as a Z direction (first direction). Further, a direction orthogonal to the Z direction is set as an X direction (second direction). Further, a direction orthogonal to the X direction and the Z direction is set as a Y direction (third direction). FIG. 1A 、 FIG. 1B and FIG. 1C The semiconductor device 100 shown in FIG. 1 represents a cross-sectional view of an X-Z plane. Further, the X direction, the Y direction, and the Z direction are shown in an orthogonal relationship in the present embodiment, but are not limited to the orthogonal relationship, and can be a relationship in which they cross each other. Further, for the sake of explanation, a direction from the drain electrode 10 toward the n-type first semiconductor region 20 is referred to as "up", and an opposite direction thereof is referred to as "down".

[0031] The n-type first semiconductor region 20, the p-type second semiconductor region 23, and the n + -type third semiconductor region 26 include silicon (Si) or silicon carbide (SiC) as a semiconductor material. In a case where silicon is used as the semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) can be used as an n-type impurity. Boron (B) can be used as a p-type impurity.

[0032] The n-type first semiconductor region 20 has an n + -type drain region 21 and an n - -type drift region 22. The n + -type drain region 21 is provided on the drain electrode 10 and is electrically connected to the drain electrode 10. The n - -type drift region 22 is provided above the n + -type drain region 21 in the Z direction. The n - -type drift region 22 is electrically connected to the drain electrode 10 via the n + -type drain region 21.

[0033] The p-type second semiconductor region 23 has a p-type substrate region 24 and a p-type substrate region 24. + The contact region 25 is p-type. Multiple p-type second semiconductor regions 23 are provided. Multiple p-type substrate regions 24 are separated in the X direction. The p-type substrate regions 24 are located on the n-type... - Above the drift region 22 of the type. + The contact area 25 of the n-type is disposed on the base area 24 of each p-type. + The third semiconductor region 26 of type n + The source region of type n. + The third semiconductor region 26 of the p-type is disposed on the substrate region 24 of the p-type.

[0034] FIG. 1B It is FIG. 1A The enlarged cross-sectional view of the area shown by the dashed line A.

[0035] The insulating layer 40 has a first insulating portion 41, a second insulating portion 42, a third insulating portion 43, and a fourth insulating portion 44. FIG. 1B In the diagram, the first insulating portion 41 is indicated by a double-dotted line, the second insulating portion 42 and the third insulating portion 43 are indicated by dashed lines, and the fourth insulating portion 44 is indicated by a single-dotted line. The first insulating portion 41, the second insulating portion 42, the third insulating portion 43, and the fourth insulating portion 44 are formed integrally. The insulating layer 40 comprises an insulating material such as silicon oxide. The first insulating portion 41, the second insulating portion 42, the third insulating portion 43, and the fourth insulating portion 44 may also contain impurities (e.g., boron). The specific structure of the insulating layer 40 will be described later.

[0036] The conductive portion 30 and the gate electrode 13 comprise a conductive material such as polysilicon. Impurities such as phosphorus are added to the conductive material. The conductive portion 30 is disposed between the drain electrode 10 and the source electrode 14. The conductive portion 30 is a field plate electrode. The conductive portion 30 has a first conductive portion 31 and a second conductive portion 32. The first conductive portion 31 is disposed on n - In the drift region 22 of the type. In the first conductive part 31 and n - A first insulating portion 41 is provided between the drift regions 22 of the type. A first conductive portion 31 is provided in the Z direction on the drain electrode 10 side of the conductive portion 30. A second conductive portion 32 is provided on top of the first conductive portion 31. The lower part of the second conductive portion 32 is provided on the n - In the drift region 22 of the type. At the lower part of the second conductive part 32 and n - A first insulating portion 41 is provided between the drift regions 22 of the type. The upper part of the second conductive portion 32 is provided at n - In the drift region 22 of the type. At the upper part of the second conductive part 32 and n -A second insulating portion 42 is provided between the drift regions 22 of the first conductive portion 30. A second conductive portion 32 is disposed in the Z-direction closer to the source electrode 14 than the conductive portion 30. The second conductive portion 32 is disposed in the Z-direction on the source electrode 14 side of the first conductive portion 31. The impurity concentration of the second conductive portion 32 is lower than that of the first conductive portion 31. The first insulating portion 41 is a field plate insulating film. The first insulating portion 41 is disposed between the first conductive portion 31 and the first semiconductor region 20. The first insulating portion 41 is disposed between the lower part of the second conductive portion 32 and the first semiconductor region 20. The first insulating portion 41 insulates the conductive portion 30 from the gate electrode 13, the first semiconductor region 20, the second semiconductor region 23, and the third semiconductor region 26. The second insulating portion 42 insulates the conductive portion 30 from the gate electrode 13, the first semiconductor region 20, the second semiconductor region 23, and the third semiconductor region 26. The gate electrode 13 is disposed on the first insulating portion 41. The specific structure near the gate electrode 13 will be described later.

[0037] Source electrode 14 is disposed at n + Type 26 source region and p + Above the contact area 25 of the type. Source electrode 14 and conductive portion 30, n + Type 26 source region and p + The contact area 25 is electrically connected. A fourth insulating portion 44 is disposed between the gate electrode 13 and the source electrode 14. The gate electrode 13 and the source electrode 14 are electrically separated by the fourth insulating portion 44.

[0038] like FIG. 1A and FIG. 1B As shown, the gate electrode 13 is disposed in the X direction between the p-type substrate region 24 and the second conductive portion 32. The gate electrode 13 is disposed in the X direction on the n-type substrate region 24. + Between the source region 26 and the second conductive portion 32 of the p-type. Between the base region 24 and the gate electrode 13 of the p-type and the n-type. + A third insulating portion 43 is provided between the source region 26 and the gate electrode 13 of the n-type electrode. The substrate region 24 of the p-type electrode is electrically separated from the gate electrode 13 by the third insulating portion 43. + The source region 26 and the gate electrode 13 are electrically separated by a third insulating portion 43. A second insulating portion 42 is provided between the gate electrode 13 and the second conductive portion 32. The gate electrode 13 and the second conductive portion 32 are electrically separated by the second insulating portion 42.

[0039] In addition, such as FIG. 1C , FIG. 1A and FIG. 1Bsix gate electrodes 13 are provided. In this case, another gate electrode 13 is provided between the p-type base region 24 different from the above-described p-type base region 24 and the second conductive portion 32. Further, another gate electrode 13 is provided between the n + -type source region 26 different from the above-described n + -type source region 26 and the second conductive portion 32. The second conductive portion 32 and the other gate electrode 13 are electrically separated by a second insulating portion 42 provided between the second conductive portion 32 and the gate electrode 13. A third insulating portion 43 is provided between the other gate electrode 13 and the p-type base region 24. Further, a third insulating portion 43 is provided between the other gate electrode 13 and the n + -type source region 26.

[0040] As described above, FIG. 1C , FIG. 1C and FIG. 2A the semiconductor device 100 has a configuration in which the p-type base region 24 (or the n + -type source region 26), the third insulating portion 43, the gate electrode 13, the second insulating portion 42, the second conductive portion 32, the second insulating portion 42, the gate electrode 13, the third insulating portion 43, the p-type base region 24 (or the n + -type source region 26) are arranged in the X direction in this order. Further, the above-described configuration of the semiconductor device 100 is repeatedly provided in the X direction as FIG. 1A described above.

[0041] FIG. 1B a plan view of the semiconductor device 100 is shown, FIG. 1C , FIG. 2A and FIG. 2A the source electrode 14 is omitted. Further, the boundary portion of the p-type base region 24 (or the n + -type source region 26) and the third insulating portion 43 is indicated by a broken line. As FIG. 1A described above, the p + -type contact region 25 extends in the Y direction. Similarly to the p + -type contact region 25, each region of the semiconductor device 100, for example, the p-type base region 24, the n + -type source region 26, the conductive portion 30, and the gate electrode 13 respectively extend in the Y direction.

[0042] Further, in a cross section of B-B' of FIG. 1A , the semiconductor device 100 has a configuration as FIG. 2C described above. The semiconductor device 100 has FIG. 2AThe area shown is the component region through which current flows. In a portion of the semiconductor device 100, a gate pad 53, connected to an external power supply (or gate controller), is provided separately from the component region. The region surrounding the component region and not through which current flows is called the termination region. The semiconductor device 100 has a component region and a termination region. Gate wiring is electrically connected to the gate pad 53. The gate wiring is located in... FIG. 2B The gate electrode 13 is located on the fourth insulating portion 44. The gate wiring is electrically separated from the source electrode 14. The gate wiring is disposed on the surface of the semiconductor device 100.

[0043] FIG. 2A The cross-sectional view at C-C' is FIG. 2C The conductive portion 30, extending along the Y direction, is electrically connected to the source electrode 14 via the source contact portion 51 in the terminal region of the semiconductor device 100. The conductive portion 30 contacts the source contact portion 51. The source contact portion 51 contacts the source electrode 14. The conductive portion 30 is electrically led out to the surface side of the semiconductor device 100 through the source contact portion 51 and is electrically connected to the source electrode 14.

[0044] in addition, FIG. 3A - FIG. 10B The cross-sectional view at point D-D' is FIG. 3A - FIG. 10B The gate electrode 13, extending along the Y direction, is electrically connected to the gate wiring (i.e., the gate pad 53) via the gate contact 52 in the terminal region of the semiconductor device 100. The gate electrode 13 is electrically led out to the surface side of the semiconductor device 100 through the gate contact 52 and electrically connected to the gate wiring (i.e., the gate pad 53).

[0045] Furthermore, in this embodiment, the source contact 51 is located closer to the terminal region side of the semiconductor device 100 than the gate contact 52. The positions where the source contact 51 and the gate contact 52 are formed can be changed by appropriately modifying the design of the gate electrode 13 and the second conductive portion 32. The gate contact 52 may also be located further to the terminal region side than the source contact 51.

[0046] (Operation of semiconductor device 100)

[0047] The operation of the semiconductor device 100 will be explained.

[0048] First, the turn-on operation will be explained. With a positive voltage applied to the drain electrode 10, a voltage exceeding a threshold voltage is applied to the gate electrode 13. This forms a channel (inversion layer) in the p-type substrate region 24 adjacent to the gate electrode 13, separated by the third insulating portion 43, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 14 to the drain electrode 10 through the channel. That is, when the semiconductor device 100 is turned on, current flows from the drain electrode 10 to the source electrode 14.

[0049] Next, the turn-off operation will be explained. When a voltage lower than the threshold voltage is applied to the gate electrode 13, the channel in the p-type substrate region 24 disappears, and the semiconductor device 100 becomes off.

[0050] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 10 increases. On the other hand, a negative voltage (e.g., ground) is applied to the source electrode 14 opposite to the drain electrode 10. As a result, the depletion layer is released from the first insulating portion 41 and n disposed around the conductive portion 30 which acts as a field plate electrode. - The interface between the drift regions 22 of the type faces n - The drift region 22 of the type expands. Through the expansion of this depletion layer, n - The electric field concentration within the drift region 22 is suppressed, thereby improving the breakdown voltage of the semiconductor device 100. Furthermore, by extending this depletion layer, the n-value can be increased while maintaining the breakdown voltage of the semiconductor device 100. - The concentration of n-type impurities in the drift region 22 of the type reduces the on-resistance of the semiconductor device 100.

[0051] (Manufacturing method of semiconductor device 100)

[0052] FIG. 3A This is a process cross-sectional view showing the manufacturing process of the semiconductor device 100 according to the first embodiment. (Refer to...) FIG. 3B This describes an example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0053] First, prepare n + Semiconductor substrate 21 of type n. Semiconductor substrate 21 is n + Semiconductor region 21 of type 2. For example... FIG. 4A As shown, in the Z direction, through n + An epitaxial growth is performed on the semiconductor region 21 of the type to form an n - Semiconductor region 22 of type n. Additionally, n - The n-type impurity concentration of the semiconductor region 22 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 1×10 16 cm -3 the following.

[0054] By reactive ion etching (RIE), such as FIG. 4B As shown, in n - Multiple trenches T extending along the Y direction are formed on the upper surface of the semiconductor region 1a of the type.

[0055] like FIG. 5AAs shown, along n - A first insulating layer 41a is formed on the upper surface of the semiconductor region 22 and the inner surface of the trench T. The first insulating layer 41a is formed by n - The semiconductor region 22 is formed by thermal oxidation. Alternatively, the first insulating layer 41a can also be formed by depositing the first insulating layer 41a using chemical vapor deposition (CVD). The first insulating layer 41a comprises silicon oxide.

[0056] like FIG. 5B As shown, a conductive layer 31a is formed on the first insulating layer 41a by CVD in a manner that fills the trench T. The conductive layer 31a is, for example, polycrystalline silicon and contains, for example, phosphorus or boron as conductive impurities.

[0057] By reactive ion etching (RIE), such as FIG. 6A As shown, the conductive layer 31a formed on the first insulating layer 41a is partially removed to form the first conductive portion 31.

[0058] like FIG. 6B As shown, a conductive layer 32a is formed over the first conductive portion 31 and the first insulating layer 41a using a CVD method. This conductive layer 32a is, for example, polycrystalline silicon. The conductive layer 32a may contain conductive impurities (e.g., phosphorus). The concentration of conductive impurities in the conductive layer 32a is lower than the impurity concentration in the first conductive portion 31.

[0059] A portion of the upper surface of the conductive layer 32a is removed by chemical dry etching (CDE) or similar methods. Thus, as... FIG. 7A As shown, a second conductive portion 32 is formed, and conductive portions 30, composed of a first conductive portion 31 and a second conductive portion 32, are respectively disposed within a plurality of trenches T. Furthermore, the impurity concentration of the conductive portion 30 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 the following.

[0060] By wet etching or CDE, a portion of the first insulating layer 41a is removed, causing the upper surface of the first insulating layer 41a to recede, forming the first insulating portion 41. Thus, as... FIG. 7B As shown, the upper part of the second conductive portion 32, including the upper surface and the side surface, is exposed. Additionally, n - The upper surface of the semiconductor region 22 is exposed. - The side of the semiconductor region 22 is exposed on the inner wall of the trench T.

[0061] Through oxidation treatment, n - The upper and side surfaces of the semiconductor region 22 and the upper and side surfaces of the second conductive portion 32 are oxidized. For example... FIG. 8AAs shown, a portion of the second conductive portion 32 is oxidized, thereby forming the second insulating portion 42. A portion of the unoxidized second conductive portion 32 remains as a conductive layer with a reduced width. (Through n) - The oxidation of the surface of the semiconductor region 22 forms the third insulating part 43.

[0062] like FIG. 8B As shown, on the first insulating part 41, n - A conductive layer 13a is formed by CVD over the drift region 22 and between the second insulating portion 42 and the third insulating portion 43. This conductive layer comprises polycrystalline silicon. The conductive layer 13a may contain conductive impurities (e.g., phosphorus).

[0063] A portion of the conductive layer 13a is removed using CDE or similar methods, causing the upper surface of the conductive layer 13a to retract. Thus, as... FIG. 9A As shown, a gate electrode 13 is formed in the trench T.

[0064] like FIG. 9B As shown, in n - Ions are implanted into the upper part of the semiconductor region 22 to form a p-type substrate region 24. Then, n-type impurities are implanted to form an n-type substrate region 24. + Type 26 source pole region.

[0065] like FIG. 10A As shown, a structure is formed covering the gate electrode 13, the second insulating portion 42, the third insulating portion 43, and n. + The fourth insulating layer 44a of each of the source regions 26 of the type.

[0066] like FIG. 10B As shown, n + Part of the source region 26 of type p + A portion of the contact area 25 of the type and n + A portion of the fourth insulating layer 44a on the upper part of the source region 26 of the type is removed. This forms a layer through n + The source region 26 of the n-type polarity reaches the opening OP of the base region 24 of the p-type polarity. Thus, n... + A portion of the source region 26 of the p-type and a portion of the base region 24 of the p-type are exposed.

[0067] like FIG. 1A As shown, p-type impurities are implanted into the exposed p-type substrate region 24 to form p-type substrates. + The contact area of ​​the type is 25.

[0068] like FIG. 1B As shown, a source electrode 14 is formed on the fourth insulating portion 44 and embedded in the opening OP. In n -A drain electrode 10 is formed below the drift region of the type. Through the above processes, a manufacturing process is completed. FIG. 1C , FIG. 11 and FIG. 3B The semiconductor device 100 shown.

[0069] As described above, the second insulating portion 42 is formed, for example, by oxidizing the second conductive portion 32, which contains impurities such as phosphorus. The impurity concentration contained in the second conductive portion 32 is 1×10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 Below. On the other hand, the first insulating part 41 and the third insulating part 43 are for n - The semiconductor region 22 is formed by oxidation. +- The n-type impurity concentration in semiconductor region 22 is 1×10⁻⁶. 15 cm -3 Above and 1×10 16 cm -3 Therefore, the impurity concentration contained in the second insulating portion 42 is greater than the impurity concentration contained in the first insulating portion 41 and the impurity concentration contained in the third insulating portion 43.

[0070] (Effects of the first implementation method)

[0071] use FIG. 12A The effects of the semiconductor device 400 of the comparative example shown on the semiconductor device 100 of the first embodiment will be explained.

[0072] The semiconductor device 400 of the first comparative example differs from the semiconductor device 100 of the first embodiment in that the conductive portion 30 is formed only by the first conductive portion 31.

[0073] Both the semiconductor device 100 of the first embodiment and the semiconductor device 400 of the first comparative example have a structure in which a portion of the conductive portion 30 in the X direction is located between the gate electrodes 13. In the case of a semiconductor device, for example, having a withstand voltage of 100V or higher, in order to increase the width of the insulating layer 40 in the X direction, it is necessary to extend the manufacturing process described above. FIG. 12Bthe width of the trench T. At this time, in the case of a configuration in which one gate electrode 13 is provided in one trench T, that is, in the case of a configuration in which a part of the conductive portion 30 in the X direction is not located between two gate electrodes 13, the width of the gate electrode 13 in the X direction becomes wide, and thus the filling of the gate electrode 13 can not be sufficient. On the other hand, by adopting a configuration in which a part of the conductive portion 30 in the X direction is located between two gate electrodes 13, that is, a configuration in which two gate electrodes 13 are formed in one trench T, the width of each of the gate electrodes 13 becomes small, and thus the filling accuracy of the gate electrode 13 can be improved.

[0074] In the comparative example, the second insulating portion 42 between the gate electrode 13 and the conductive portion 30 is formed, for example, by oxidation of the conductive portion 30. As described above, the conductive portion 30 is electrically connected to the source electrode 14, and thus in order to reduce the connection resistance (wiring resistance) of the conductive portion 30 to the source electrode 14, a high concentration of impurities is contained in the conductive portion 30.

[0075] However, polycrystal silicon with a high impurity concentration easily makes the crystal grain (particle) size uneven, and easily mixes large-size and small-size crystal grains. If polycrystal silicon with uneven crystal grain size is oxidized, the large-size crystal grains push out the small-size crystal grains, and thus the small-size crystal grains can be introduced into the oxide film. At the portion where the small crystal grains enter, the insulating film (oxide film) is formed thin in the crystal grain size. Thus, the film thickness of the second insulating portion 42 becomes uneven, and the insulating film resistance between the gate electrode 13 and the conductive portion 30 decreases. As a result, in repeated on-off operations of the semiconductor device 400, the second insulating portion 42 between the gate electrode 13 and the conductive portion 30 can be damaged, and a short circuit between the gate electrode and the source electrode can occur.

[0076] As one example of making the film thickness of the second insulating portion 42 uniform and securing the insulating film resistance, a method of reducing the width of the conductive portion 30 in the X direction is considered. If the width of the conductive portion 30 in the X direction is reduced, in the formation of the conductive portion 30, the crystal grains of the polycrystal silicon can grow only to the width of the trench. The generation and growth of polycrystal silicon with uneven crystal grain size are suppressed, and thus the crystal grain size of the polycrystal silicon easily becomes uniform. As a result, it is relatively difficult to form small-size silicon crystal grains, and thus the possibility of small crystal grains being introduced into the oxide film decreases. However, in the case where the conductive portion 30 is formed by CVD, if the thickness of the conductive portion 30 in the X direction is reduced, the filling of the polycrystal silicon deteriorates, and can become a cause of voids. Thus, from the viewpoint of the reliability of the semiconductor device, it is preferable that the conductive portion 30 secure a certain thickness in the X direction.

[0077] On the basis of the above, the effects of the semiconductor device 100 of the first embodiment are described. In the semiconductor device 100, the second insulating portion 42 between the gate electrode 13 and the second conductive portion 32 is formed by oxidation of the second conductive portion 32. The impurity concentration of the second conductive portion 32 is lower than the impurity concentration of the first conductive portion 31, and thus the uneven formation of the grain size of the polysilicon is suppressed. Therefore, when a part of the second conductive portion 32 is oxidized, the introduction of the grain into the second insulating portion 42 is suppressed.

[0078] As a result, the semiconductor device 100 of the first embodiment can maintain the width of the conductive portion 30 in the X direction, and suppress the film thickness deviation of the second insulating portion 42 between the gate electrode 13 and the second conductive portion 32. Further, since the impurity concentration of the first conductive portion 31 is high, the connection resistance of the conductive portion 30 and the source electrode 14 can be reduced. Therefore, the semiconductor device 100 can maintain the withstand voltage of the insulating film between the gate electrode 13 and the conductive portion 30, and thus can suppress the element destruction at the time of operation. In addition, the semiconductor device 100 can reduce the connection resistance of the conductive portion 30 and the source electrode 14, and thus promote the formation of the depletion layer at the time of breaking operation, and can ensure the withstand voltage.

[0079] [Modified example of the first embodiment]

[0080] Reference FIG. 12A , FIG. 12B The semiconductor device 101 of the modified example of the first embodiment is described. FIG. 12A is a cross-sectional view of the semiconductor device 101 of the modified example of the first embodiment, FIG. 4A is a cross-sectional view of the broken line E portion of FIG. 13A .

[0081] The semiconductor device 101 of the modified example of the first embodiment has a plurality of third conductive portions 33 in addition to the first embodiment. The plurality of third conductive portions 33 are provided around the lower portion of the second conductive portion 32. The plurality of third conductive portions 33 are provided separately from each other in the X direction. The third conductive portion 33 is provided between the lower portion of the second conductive portion 32 and the first insulating portion 41 in the X direction. In addition, the third conductive portion 33 is in contact with the first conductive portion 31. In addition, the third conductive portion 33 is in contact with the first insulating portion 41. The sum of the width of the second conductive portion 32 in the X direction and the width of the third conductive portion 33 is larger than the width of the second conductive portion 32 in the X direction sandwiched between the two gate electrodes 13. The third conductive portion 33 is composed of, for example, polysilicon. In addition, the third conductive portion 33 can be replaced with an insulating layer such as silicon nitride (SiN). Here, the description is omitted with respect to the points repeated with the semiconductor device 100 of the first embodiment.

[0082] A manufacturing method of the semiconductor device 101 of the modification of the first embodiment will be described. In the manufacturing method of the semiconductor device 100 of the first embodiment, after the first conductive portion 31 is formed as shown in FIG. 1A, the conductive layer 33a is formed over the surface of the first insulating layer 41a and a part of the surface of the first conductive portion 31 each by the CVD method as shown in FIG. 1B. FIG. 13B FIG. 14A

[0083] FIG. 14B

[0084] FIG. 7A

[0085] FIG. 15A

[0086] FIG. 15B

[0087]

[0088] ​​​​​​​​​​​Further, the first conductive portion 31 can maintain a constant width in the X direction, and thus burying formation is easily performed in the manufacturing process. Therefore, the amount of insulating film between the gate electrode 13 and the conductive portion 30 can be ensured, and a semiconductor device 101 having a small connection resistance between the conductive portion 30 and the source electrode 14 can be manufactured.

[0089] [Second Embodiment]

[0090] Reference FIG. 15A , FIG. 15B The semiconductor device 200 of the second embodiment will be described. FIG. 15A is a cross-sectional view of the semiconductor device 200 of the second embodiment, FIG. 9A is a cross-sectional view of a broken line F portion of FIG. 16A .

[0091] The semiconductor device 200 of the second embodiment differs from the semiconductor device 100 of the first embodiment in that a region directly above the second conductive portion 32 is connected to the source electrode 14. More specifically, between n + type source regions 26 adjacent in the X direction, a portion of the source electrode 14 connected to the second conductive portion 32 is formed. Points repeated with the semiconductor device 100 of the first embodiment are omitted. Two gate electrodes 13 are adjacent, for example, with the second insulating portion 42 interposed therebetween. Further, two gate electrodes 13 are adjacent, for example, with the source electrode 14 interposed therebetween. Alternatively, two gate electrodes 13 are adjacent, for example, with the second conductive portion 32 and the source electrode 14 interposed therebetween.

[0092] The manufacturing method of the semiconductor device 200 of the second embodiment will be described.

[0093] In the manufacturing method of the semiconductor device 100 of the first embodiment, as shown in FIG. 16B , after the fourth insulating portion 44 covering the gate electrode 13 is formed, as shown in FIG. 15A , a portion of the fourth insulating layer 44a is removed. At this time, in addition to a portion of the fourth insulating layer 44a of the upper portion of the n + type source region 26, a portion of the n + type source region 26, and a portion of the p + type contact region 25, a portion of the fourth insulating layer 44a formed on the upper portion of the second conductive portion 32 is also removed. Thus, the fourth insulating portion 44 is formed. Further, a first opening OP1 reaching the p-type semiconductor region 24 through the n + type semiconductor region 26 and a second opening OP2 reaching the second conductive portion 32 through the fourth insulating portion 44 are formed.

[0094] As FIG. 15BAs shown, p-type impurities are implanted into the p-type semiconductor region 24 through the first opening OP1 to form p-type semiconductors. + Type of semiconductor region 25.

[0095] A source electrode 14 is formed on the fourth insulating portion 44 by burying the first opening OP1 and the second opening OP2. In n + A drain electrode 10 is formed below the drain region 21 of the type. Through the above processes, a drain electrode 10 is manufactured. FIG. 17A , FIG. 11 The semiconductor device 200 shown.

[0096] The semiconductor device 200 of the second embodiment is constructed in the same way as the semiconductor device 100 of the first embodiment, except for the points described above. Furthermore, the manufacturing method of the semiconductor device 200 is the same as that of the semiconductor device 100, except for the points described above. In addition, the semiconductor device 200 has the same effects as the semiconductor device 100.

[0097] Here, when the MOSFET is switched off, phenomena such as dynamic avalanche, where undischarged holes remain in the semiconductor layer and the MOSFET's breakdown voltage decreases, may occur. Furthermore, MOSFETs exhibiting dynamic avalanche also experience current loss and degraded switching efficiency.

[0098] On the other hand, for example, there is a configuration such as the semiconductor device 400 of the comparative example, in which a field plate electrode is provided in the semiconductor layer, thereby maintaining the withstand voltage by allowing the depletion layer to expand in the semiconductor layer when the MOSFET is turned off. However, if the voltage fluctuates drastically when the MOSFET is turned off, a surge current may flow from the drain electrode 10 to the conductive portion 30 through the insulating layer 40. In this case, the voltage applied to the conductive portion 30 increases. Normally, the voltage applied to the source electrode (field plate electrode) is 0V, thus promoting the formation of the depletion layer when the MOSFET is turned off. However, if the voltage applied to the conductive portion 30 increases, the formation of the depletion layer is suppressed. Therefore, the aforementioned dynamic avalanche becomes more significant.

[0099] In the case of the semiconductor device 200 of the second embodiment, the region directly above the second conductive portion 32 is directly connected to the source electrode 14, thus reducing the resistance of the conductive portion 30 in the Z direction. That is, holes that enter the conductive portion 30 during a disconnection operation can be effectively discharged from the source electrode 14. As a result, the generation of dynamic avalanche in the semiconductor device 200 during a disconnection operation can be suppressed. Therefore, the semiconductor device 200 can achieve improved withstand voltage, reduced current loss, and improved switching efficiency.

[0100] The effect of the semiconductor device 200 of the second embodiment will be described using the semiconductor device 400 of the foregoing comparative example.

[0101] FIG. 17B A plan view of the semiconductor device 400 of the comparative example is shown, omitting FIG. 17A the source electrode 14. FIG. 17C is FIG. 17A a cross-sectional view at H-H' of FIG. 17A is FIG. 11 a cross-sectional view at I-I' of FIG. 17A A cross-sectional view at G-G' of FIG. 17B is a cross-sectional view of the semiconductor device 400 of the comparative example. In addition, in FIG. 18A , a boundary portion between the p-type base region 24 (or the n + -type source region 26) and the third insulating portion 43 is indicated by a broken line.

[0102] As FIG. 15A shown, the semiconductor device 400 of the comparative example is a semiconductor device in which the field plate electrode 30 is formed in a stripe shape. Therefore, in order to electrically connect the field plate electrode 30 and the source electrode 14, it is necessary to form a source contact portion 51. The source contact portion 51 is provided at a terminal region of the field plate electrode 30.

[0103] FIG. 15B A plan view of the semiconductor device 200 of the second embodiment is shown, omitting FIG. 18B , FIG. 18A the source electrode 14. FIG. 18A A cross-sectional view at J-J' of FIG. 15A is shown. FIG. 15B A cross-sectional view at K-K' of FIG. 17A , FIG. 19 is a cross-sectional view of the semiconductor device 200 of the second embodiment.

[0104] In the case of the semiconductor device 200 of the second embodiment, the upper portion of the second conductive portion 32 is directly connected to the source electrode 14 in the Z direction. In the case of the semiconductor device 200 of the second embodiment, the source electrode 14 and the second conductive portion 32 are connected in the element region. Thus, as FIG. 19 shown in the semiconductor device 400 of the comparative example, it is not necessary to provide the source contact portion 51. The p-type base region 24, the n + -type source region 26, and the p +The contact area 25 is not formed in the source contact portion 51. Therefore, the source contact portion 51 becomes an ineffective region where no current flows during the turn-on operation. The semiconductor device 200 of the second embodiment does not require the source contact portion 51, thus increasing the effective area through which current flows during the turn-on operation. Therefore, the semiconductor device 200 of the second embodiment can reduce the on-resistance.

[0105] [Modifications of the Second Embodiment]

[0106] Reference FIG. 19 The semiconductor device 201 of the modified embodiment of the second embodiment will be described. FIG. 15A A top view showing a semiconductor device 201 with a dotted trench field plate structure. FIG. 15B In the middle, the following was omitted. FIG. 19 , FIG. 15A The source electrode 14 is shown. Additionally... FIG. 15B The cross-sectional view at L-L' and FIG. 20A , FIG. 20B The cross-sectional view of the semiconductor device 200 of the second embodiment shown is the same.

[0107] The semiconductor device 201 of the second embodiment has a dot trench type field plate structure. Similar to the semiconductor device 200, the upper part of the second conductive portion 32 of the semiconductor device 201 is directly connected to the source electrode 14 in the Z direction, so it can be a dot trench type field plate structure like this embodiment.

[0108] Similar to the semiconductor device 200 of the second embodiment, the semiconductor device 201 of the modified example of the second embodiment can also increase the effective area through which current flows during the turn-on operation.

[0109] [Third Implementation Method]

[0110] Reference FIG. 20A , FIG. 20B The semiconductor device 300 of the third embodiment will be described. FIG. 20A This is a cross-sectional view of the semiconductor device 300 according to the third embodiment. FIG. 21A It means FIG. 21B A cross-sectional view of the dashed M section.

[0111] The semiconductor device 300 of the third embodiment further has a fourth conductive portion 34 with respect to the second embodiment. The fourth conductive portion 34 is provided extending in the Z direction from the upper portion of the first conductive portion 31. In addition, the second conductive portion 32 is provided between the fourth conductive portion 34 and the first insulating portion 41 in the X direction. In addition, the second conductive portion 32 is provided between the fourth conductive portion 34 and the gate electrode 13 in the X direction. In addition, the second conductive portion 32 is provided between the fourth conductive portion 34 and the second insulating portion 42 in the X direction. The second conductive portion 32 is composed of polysilicon or silicon nitride (SiN). The impurity concentration of the second conductive portion 32 is lower than the impurity concentration of the fourth conductive portion 34.

[0112] Also, similarly to the semiconductor device 200, the region directly above the second conductive portion 32 of the semiconductor device 300 is connected to the source electrode 14. Here, with respect to the points repeated with the semiconductor device 100 of the second embodiment, the description is omitted.

[0113] The manufacturing method of the semiconductor device 300 of the third embodiment is described.

[0114] FIG. 22A is a cross-sectional view showing the manufacturing method of the semiconductor device 300 of the third embodiment, FIG. 22B is a cross-sectional view showing the manufacturing method of the semiconductor device 300 of the third embodiment. In addition, FIG. 23 is a cross-sectional view showing the manufacturing method of the semiconductor device 300 of the third embodiment, FIG. 5A is a cross-sectional view showing the manufacturing method of the semiconductor device 300 of the third embodiment. Furthermore, FIG. 21A is a cross-sectional view showing another manufacturing method of the semiconductor device 300 of the third embodiment. In the manufacturing method of the semiconductor device 100 of the first embodiment, after the first conductive portion 31 is formed as shown in FIG. 21B , the conductive layer 32a is formed by the CVD method as shown in FIG. 22A . Further, the conductive layer 34a is formed on the conductive layer 32a by the CVD method.

[0115] A part of the upper surface of the conductive layer 32a and a part of the upper surface of the conductive layer 34a are removed by chemical dry etching (CDE) or the like. Thus, the second conductive portion 32 and the fourth conductive portion 34 are formed as shown in FIG. 22B . The conductive portions 30 composed of the first conductive portion 31, the second conductive portion 32, and the fourth conductive portion 34 are respectively provided in the plurality of trenches T.

[0116] A part of the first insulating layer 41a is removed by wet etching or CDE, and the upper surface of the first insulating layer 41a is retreated, and the first insulating portion 41 is formed. Thus, as shown in FIG. 16BAs shown, the upper portion of the second conductive portion 32 including the upper surface and the side surface, the upper portion of the fourth conductive portion 34, and the upper surface of the n - The upper surface of the semiconductor region 22 of the n - The side surface of the semiconductor region 22 of the n

[0117] By the oxidation treatment, the upper surface and the side surface of the semiconductor region 22 of the n - The upper surface and the side surface of the semiconductor region 22 of the n FIG. 23 As shown, a portion of the second conductive portion 32 and a portion of the fourth conductive portion 34 are oxidized, thereby forming the second insulating portion 42. In addition, a portion of the second conductive portion 32 and the fourth conductive portion 34 which are not oxidized are formed.

[0118] In addition, the fourth conductive portion 34 can also dope the second conductive portion 32 with impurities and be formed wider in the X direction. In this case, in the manufacturing method of the semiconductor device 200 of the second embodiment, as with the ​ As shown, the fourth insulating layer 44a formed on the upper portion of the second conductive portion 32 and the fourth conductive portion 34 is partially removed to form the second opening OP2. Thereafter, as shown in ​ As shown, the fourth insulating layer 44a formed on the upper portion of the second conductive portion 32 and the fourth conductive portion 34 is partially removed to form the second opening OP2. Thereafter, as shown in

[0119] The semiconductor device 300 of the third embodiment is the same in structure as the semiconductor device 200 of the second embodiment except for the points described above. In addition, the manufacturing method of the semiconductor device 300 is the same as the manufacturing method of the semiconductor device 200 except for the points described above.

[0120] The semiconductor device 300 of the third embodiment is the same in structure as the semiconductor device 200 of the second embodiment except for the points described above. In addition, the manufacturing method of the semiconductor device 300 is the same as the manufacturing method of the semiconductor device 200 except for the points described above.

[0121] Further, the semiconductor device 300 of the third embodiment is provided with the second conductive portion 32 having a lower impurity concentration than the fourth conductive portion 34 between the fourth conductive portion 34 and the gate electrode 13 and between the fourth conductive portion 34 and the second insulating portion 42 in the X direction. Thus, the variation in the grain size of the polysilicon of the second conductive portion 32 can be further suppressed. Thus, the variation in the film thickness of the second insulating portion 42 formed by oxidizing a part of the second conductive portion 32 can be further suppressed. Thus, the semiconductor device 300 can maintain the resistance of the insulating film between the gate electrode 13 and the conductive portion 30 and can reduce the on-resistance.

[0122] The embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications are included in the scope or gist of the application and are included in the scope of the application and equivalents as recited in the claims.

Claims

1. A semiconductor device comprising: a first electrode; a second electrode; a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode and electrically connected to the first electrode; a plurality of second semiconductor regions of a second conductivity type provided between the first semiconductor region and the second electrode; a third semiconductor region of the first conductivity type provided between the second semiconductor regions and the second electrode and electrically connected to the second electrode; a conductive portion provided between the first electrode and the second electrode and including a first conductive portion provided on the first electrode side of the conductive portion in a first direction from the first electrode toward the first semiconductor region and a second conductive portion provided on the second electrode side of the conductive portion in the first direction, located between the second semiconductor regions in a second direction intersecting the first direction, and having an impurity concentration smaller than that of the first conductive portion; a first insulating portion provided between the first conductive portion and the first semiconductor region; a gate electrode provided between the second semiconductor regions and the second conductive portion in the second direction; a second insulating portion provided between the second conductive portion and the gate electrode; and a third insulating portion provided between the second semiconductor regions and the gate electrode.

2. The semiconductor device according to claim 1, wherein: a fourth insulating portion is further provided between the second electrode and the gate electrode and between the second electrode and the third semiconductor region, a portion of the second electrode is further provided in a region adjacent to the third semiconductor region with the fourth insulating portion interposed therebetween in the second direction, and the portion of the second electrode is connected to the second conductive portion.

3. The semiconductor device according to claim 1, wherein: the semiconductor device has an element region and a terminal region surrounding the element region, and in the element region, the second electrode is connected to the second conductive portion.

4. The semiconductor device according to claim 1, wherein: in the first direction, a portion of the second conductive portion on the first electrode side is adjacent to the first insulating portion, and the semiconductor device further has a third conductive portion provided between the portion of the second conductive portion and the first insulating portion.

5. The semiconductor device according to claim 4, wherein: the sum of the widths of the second conductive portion and the third conductive portion in the second direction is greater than the width of the second conductive portion in the second direction between the gate electrodes.

6. The semiconductor device according to claim 2, wherein: a fourth conductive portion having an impurity concentration greater than that of the second conductive portion is further provided, the fourth conductive portion is connected to the second electrode, and in the second direction, the second conductive portion is provided between the second insulating portion and the fourth conductive portion.

7. The semiconductor device according to claim 6, wherein: the second conductive portion extends in the first direction in a manner having a portion adjacent to the first insulating portion, and the fourth conductive portion extends in the second direction in a manner having a portion adjacent to the second insulating portion. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The second conductive portion adjacent to the first insulating portion has a width in the second direction that is greater than a width in the second direction of the second conductive portion adjacent to the second insulating portion.

8. The semiconductor device according to claim 1, wherein The second insulating portion contains impurities at a higher concentration than the first insulating portion or the third insulating portion.

9. A method for manufacturing a semiconductor device, forming a trench in the first semiconductor region from a surface of the first semiconductor region in a first direction; forming a first insulating portion on a surface of the trench; forming a first conductive portion on the first insulating portion in the trench; forming a second conductive portion between the first insulating portion and the first conductive portion in the first direction, the second conductive portion being in contact with the first conductive portion and having an impurity concentration lower than that of the first conductive portion; removing a portion of the first insulating portion to expose a portion of the second conductive portion and a portion of an inner wall of the trench in a second direction intersecting the first direction; forming a second insulating portion by oxidizing a surface of the second conductive portion; forming a third insulating portion by oxidizing the exposed inner wall of the trench; forming a gate electrode between the second insulating portion and the third insulating portion; forming a second semiconductor region of the second conductivity type in the first semiconductor region, the second semiconductor region of the second conductivity type being opposed to the gate electrode across the third insulating portion in the second direction; forming a third semiconductor region of the first conductivity type in the first semiconductor region on the second semiconductor region along the first direction.

10. The method for manufacturing a semiconductor device according to claim 9, wherein The second conductive portion is composed of polysilicon, and the second insulating portion is formed by thermal oxidation of the second conductive portion.

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