High efficiency circuit for controlling the output of pulsed power with constant input current

Abstract

The application discloses a kind of high-efficiency circuit and control strategy for controlling input current constant when pulse power output, the circuit includes DC power supply, staggered parallel Boost circuit and LLC resonant circuit in phase series;The driving signal of the parallel two branches of staggered parallel Boost circuit is 180 ° complementary and inductance current works in critical continuous mode with partial negative current;The primary side of LLC resonant circuit is half-bridge structure, and the secondary side is full-wave rectification, and the driving of upper and lower switch tubes on the primary side half-bridge is fixed operating frequency.The circuit of the application can be applied to output pulse power occasions such as active phased array radar, pulse electrochemical wastewater, etc., the output load is constant amplitude pulse power, the output voltage of energy storage capacitor decreases in the time with pulse power, the output voltage of energy storage capacitor rises in the time without load, the input current of circuit is kept constant in the whole cycle time, which is conducive to the reliability improvement of power supply DC power supply and the improvement of overall conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronic conversion, and relates to a DC / DC conversion circuit, in particular to a circuit structure with low input current fluctuation and high conversion efficiency for a pulse power output occasion and control measurement thereof. BACKGROUND

[0002] Switching power supply has been widely used in the fields of aviation, aerospace, ship, weapon and other national defense fields. New application requirements emerge as new technologies continue to emerge. With the wide use of active phased array radars in the field of national defense, the demand for power supply for the active transmitting / receiving component (T / R component) array of the active phased array radars is increasing, and most of them are low-voltage power supply. The commonly used supply voltage values are 8V, 12V, 28V, 36V and other levels. For the T / R component, it transmits electromagnetic pulses at certain time intervals, at which time high power is consumed, and the output of the power supply is large pulse current. When it receives electromagnetic wave signals, only weak power is needed, and the output current of the power supply is very small. For the power supply of the T / R component, the output is a typical pulse load: the reciprocal of the interval time between two pulses is the pulse current frequency of the load, and the ratio of the pulse power duration to the interval time is the duty cycle (D). The transmit efficiency and heat dissipation of the T / R component limit the duty cycle, which is generally not greater than 30%. The T / R component generally has the following requirements for the power supply pulse power supply: 1) during transmission, the output voltage drop in the pulse period is small enough to ensure the normal operation of the active radar transmitting component; 2) high power density to reduce volume and weight to match the miniaturized active radar T / R component; 3) the input current does not change dramatically with the pulse load current, especially in solar cell and various battery application occasions.

[0003] The traditional T / R component power supply adopts a single-pole structure with large-capacity energy storage capacitors in parallel on the output side. In order to reduce the input current fluctuation, the power supply bandwidth is usually designed to be very low to prevent low-frequency pulse output current from being transmitted to the input side, and the pulse component is provided by the output energy storage capacitor. When the pulse repetition frequency is low and the pulse width is large, in order to ensure that the output voltage drop caused by the pulse current is small enough, the output capacitance value and volume are very large, which reduces the overall power density, and it is also difficult to reduce the fluctuation range of the input current waveform.

[0004] In order to solve the above problems of low power density and large input current fluctuation range, many research institutions have proposed a two-stage circuit structure, using two independent closed-loop controls: the front-stage circuit and its closed-loop control realize reducing input current fluctuation, while the output capacitor of the front-stage is used as an energy storage capacitor; the rear-stage circuit and its closed-loop control convert the output voltage of the front-stage into a stable low voltage required by the T / R component and provide instantaneous pulse power. Since the energy storage capacitor is placed in the middle of the front-stage and the rear-stage, the voltage fluctuation of the energy storage capacitor has no direct impact on the final output voltage, and the voltage across the energy storage capacitor can fluctuate in a large range, so the capacitance and quantity can be greatly reduced, thereby improving the power density. However, the two-stage circuit structure still has the following problems: 1) when the front-stage adopts common circuits such as half-bridge converter, full-bridge converter, etc., the output voltage fluctuates in a large range, resulting in high voltage stress of the switching devices of the secondary rectifier circuit, large conduction loss and switching loss, and low overall conversion efficiency; 2) in order to realize input current control, the control bandwidth of the front-stage circuit is low, the dynamic response speed is slow, and in order to ensure stable operation within the dynamic response time, the output energy storage capacitor is difficult to realize minimum design, and there is further space for reducing power density. SUMMARY

[0005] The purpose of the present application is to solve the problems of low conversion efficiency and poor output dynamic characteristics of the front-stage and its closed-loop control of the two-stage circuit structure, and to provide a high-efficiency circuit and its control strategy for converting input DC high voltage into DC low voltage with a magnitude varying with pulse load, while suppressing input current pulsation when outputting pulse power. The high-efficiency circuit includes an interleaved parallel Boost circuit and a fixed-frequency operating LLC resonant circuit.

[0006] The technical solution for achieving the purpose of the present application is as follows: in order to realize high-efficiency conversion, the present application adopts the following technical solution: a low-input-current-pulsation high-efficiency circuit for pulse power output includes a DC power supply, an interleaved parallel Boost circuit and an LLC resonant circuit, the interleaved parallel Boost circuit and the LLC resonant circuit are connected in series, the driving signals of the two branches of the interleaved parallel Boost circuit are 180° complementary and the inductor currents work in critical continuous mode; the primary side of the LLC resonant circuit is a half-bridge structure, the secondary side is a full-wave rectifier, and the driving of the upper and lower switching tubes of the primary side half-bridge is fixed at a working frequency.

[0007] The interleaved parallel Boost voltage-boosting circuit works in the inductor current critical continuous state, the diodes in the two groups of bridge arms work in the zero-current turn-off mode, and the MOS transistors work in the zero-voltage zero-current turn-on mode, so that the working frequency is low at full load, and the reverse recovery loss of the diode and the turn-on loss of the MOS transistor are effectively reduced; the LLC resonant circuit works in the fixed frequency mode, the working frequency is the resonant frequency of the resonant capacitor and inductor, and the secondary side rectifier diode only bears the reverse voltage of the double (full-wave rectification) output voltage amplitude, so that a diode with a lower withstand voltage can be selected, and the conduction loss is small; meanwhile, the primary side MOS transistor in the LLC resonant circuit works in the zero-voltage turn-on state, and the secondary side rectifier diode works in the zero-current turn-off state, so that the reverse recovery loss of the diode and the turn-on loss of the MOS transistor are effectively reduced. In summary, the whole circuit can obtain high conversion efficiency.

[0008] In order to realize constant input current when the output is loaded with a pulse and improve the output voltage response speed to ensure the normal work of the subsequent circuit, the following control scheme is adopted in the application.

[0009] (A) The phase difference of the driving signals of the two groups of bridge arms of the interleaved parallel Boost converter is 180°, and after the inductor current is monitored to be zero and the inductor current is reversed to be negative after a "dead time" delay, the control circuit gives the driving signal again, realizes the zero-voltage turn-on of the MOS transistors Q1 and Q2, and turns off the driving signal until the inductor current linearly rises to a reference value, and then linearly decreases until it is zero, and the next period begins;

[0010] (B) The LLC circuit works in the fixed frequency mode, the driving signals of the upper and lower transistors are 50% duty cycle square waves with a phase difference of 180° and a fixed dead time, the driving signal frequency is equal to the resonant frequency of the resonant inductor and capacitor, and at this frequency, the LLC resonant converter is equivalent to a fixed turn ratio DC transformer, and its gain is equivalent to the turn ratio of the transformer;

[0011] (C) A voltage and current double-loop system is adopted to control the output voltage and input current, the output voltage is amplified by the control circuit as the reference of the input current control loop, and the input current control loop is amplified by the control circuit as the reference of the input inductor current, and the conduction and turn-off of the MOS transistors in the interleaved parallel Boost circuit are controlled;

[0012] (D) In order to realize constant input current and suppress the output pulse frequency fluctuation, the bandwidth (crossing frequency) of the voltage outer loop in the above-mentioned double-loop system should be lower than one tenth of the lowest output pulse load frequency, so that the error signal output of the voltage outer loop is approximately direct current;

[0013] (E) In order to have better dynamic response characteristics when the output voltage suddenly adds load, and to ensure the normal work of the subsequent circuit, the control quantity of the voltage outer loop in the above-mentioned double-loop system is the peak value of the output voltage, and the sampling time of the peak value voltage is when the pulse power starts or is sampled at the longest pulse power output cycle interval;

[0014] (F) In order to have better dynamic response characteristics when the output voltage suddenly adds load, and to ensure the normal work of the subsequent circuit, the sampling output pulse load current information is used for load current feedforward, and the load current feedforward signal should not contain the output pulse power frequency and its odd multiple components, and the feedforward pulse load current signal sampling uses the way of higher value of low-pass filtering and single-cycle integration of the current signal to take the peak value.

[0015] Compared with the prior art, the present application has the following advantages:

[0016] (1) The interleaved parallel Boost circuit works in the critical continuous state of the inductor current band with partial negative current, the diodes in the two bridge arms work in the zero-current turn-off mode, and the MOS transistors work in the zero-voltage zero-current turn-on mode, so that the working frequency is low at full load, and the reverse recovery loss of the diode and the turn-on loss of the MOS transistor are effectively reduced.

[0017] (2) The LLC resonant circuit works in the fixed frequency mode, and the working frequency is the resonant frequency of the resonant capacitor and inductor, and the secondary side rectifier diode only bears the reverse voltage of twice (full-wave rectification) output voltage amplitude, so that a diode with lower voltage resistance can be selected, and the conduction loss is small. At the same time, the primary side MOS transistor in the LLC resonant circuit works in the zero-voltage turn-on state, and the secondary side rectifier diode works in the zero-current turn-off state, so that the reverse recovery loss of the diode and the turn-on loss of the MOS transistor are effectively reduced.

[0018] (3) The output current signal is collected and then subjected to low-pass filtering sampling processing and single-cycle integration peak sampling, and the outputs of the two samplings are connected in parallel with high redundancy, so that the problems of slow response speed of low-pass filtering and low single-cycle integration sampling value when the output is a high-frequency pulse load are solved, and at the same time, the use of a multiplier-divider is avoided, which is conducive to the realization of the hardware circuit.

[0019] The application will be described in further detail below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is a main power circuit diagram.

[0021] Figure 2 It is a control strategy block diagram.

[0022] Figure 3 It is a typical working waveform diagram.

[0023] Figure 4The single-cycle integral peak sampling load current feedforward information schematic diagram.

[0024] Figure 5 The single-cycle integral peak sampling load current feedforward signal schematic diagram.

[0025] Figure 1 In the figure: 1 - interleaved parallel critical continuous Boost converter, 2 - fixed frequency LLC resonant converter; L1, L2 - Boost inductor, Q1, Q2, Q3, Q4 - MOSFET, D1, D2 - Boost circuit freewheeling diode, C1 - Boost circuit output high-frequency filter capacitor, C2, C3 - fixed frequency LLC circuit resonant capacitor; L3 - fixed frequency LLC circuit resonant inductor, T1 - high-frequency transformer, D3, D4 - LLC secondary rectifier diode, C4 - output energy storage filter capacitor.

[0026] Figure 2 In the figure: G v (s) is the voltage loop regulator, G i (s) is the current loop regulator, H pv (s) is the output voltage peak sampling transfer function, H i (s) is the input inductor current sampling transfer function, R d is the inductor parasitic equivalent resistance, G pwm is the pulse width modulator gain, i Lf is the inductor current (i.e. input current), K is the fixed frequency LLC isolation converter equivalent gain, v o is the output voltage, i o is the output current, K io (s) is the output pulse load current feedforward signal sampling transfer function, V ref is the output voltage feedback reference, V ref1 is the output overvoltage protection fast loop reference, C o is the output equivalent capacitance.

[0027] Figure 3 In the figure: v o is the output voltage, v ps is the output voltage peak sampling voltage, i o is the output current, p o is the pulse output power, t1 to t2 is the start-up stage, t2 to t3 is the output idle stage, and t3 is the sudden rated output pulse load stage.

[0028] Figure 5 In the figure: p o is the pulse output power, i o is the output current, v ifb is the output pulse current feedforward signal, vifb_max The maximum value of the output pulse current feedforward signal is outputted. DETAILED DESCRIPTION

[0029] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0030] In combination Figure 1 The present application provides a high-efficiency circuit for controlling input current constant when outputting pulse power, which comprises a direct-current power supply, an interleaved parallel Boost circuit 1 and an LLC resonant circuit 2, the interleaved parallel Boost circuit 1 is connected in series with the LLC resonant circuit 2, the driving signals of the two parallel branches of the interleaved parallel Boost circuit 1 are 180° complementary and the inductance current works in a critical continuous mode with partial negative current, thereby realizing the reverse recovery loss of low freewheeling diodes D1 and D2 and realizing the zero-voltage turn-on of MOS transistors Q1 and Q2, and reducing the turn-on loss of MOS transistors Q1 and Q2; the primary side of the LLC resonant circuit 2 is a half-bridge structure, the secondary side is a full-wave rectifier, and the driving of the upper and lower switch tubes on the primary side half-bridge is a fixed working frequency, and the zero-voltage turn-on of MOS transistors Q3 and Q4 and the reverse recovery loss of low secondary rectifier diodes D3 and D4 in the full load range of the LLC circuit are realized by reasonably configuring the circuit parameters.

[0031] Further, in one of the embodiments, a constant-amplitude low-frequency pulse power is added to the output side of the circuit, and the frequency of the low-frequency pulse power is not higher than 10 kHz.

[0032] Further, in one of the embodiments, the output capacitor C1 of the interleaved parallel Boost circuit 1 is used to filter high-frequency ripples, and the capacitance value can be small, generally less than 10 μF.

[0033] Further, in one of the embodiments, the output capacitor C4 of the LLC resonant circuit 2 is used for output voltage filtering and provides pulse power decoupling through a large range of voltage changes thereon, and the calculation formula of the capacitance value is:

[0034]

[0035] In the formula, P o is the amplitude of the output pulse power, T p is the period of the output pulse power, D p is the duty ratio of the output pulse power, V o_max is the highest value of the output voltage when the pulse output is stable, V o_min is the lowest value of the output voltage when the pulse output is stable.

[0036] Further, in one of the embodiments, the control strategy of keeping the input current constant in the pulse load state is: using a voltage and current double-loop control system with output pulse load current feedforward to control the output voltage and input current, the output voltage after error amplification by the control system is used as the input current control loop reference, the input current control loop after error amplification by the control system is used as the reference of the input inductor current, and the conduction and turn-off of the MOS tube in the interleaved parallel Boost circuit (1) is controlled.

[0037] Further, in one of the embodiments, the feedback error signal output of the voltage outer loop in the voltage and current double-loop control system is used as the reference of the input current inner loop, and the bandwidth of the voltage outer loop needs to be no higher than one tenth of the lowest output pulse load frequency.

[0038] Further, in one of the embodiments, the control quantity of the voltage outer loop in the voltage and current double-loop control system is the peak value of the output voltage, and the sampling time of the peak voltage is the output pulse power start time when the load is empty or the sampling according to the longest pulse power period.

[0039] Further, in one of the embodiments, the feedforward pulse load current signal cannot contain alternating components of the output pulse load frequency and its odd multiple frequencies.

[0040] Further, in one of the embodiments, the sampling of the feedforward pulse load current signal is performed by using low-pass filtering and taking the higher value of the peak value obtained by single-cycle integration of the current signal.

[0041] The application will be further described in detail below.

[0042] Figure 1 is the main power circuit diagram of the low-input-current pulse power output high-efficiency circuit, which is composed of two-phase parallel Boost conversion circuit and half-bridge LLC resonant circuit, and the two are cascaded in front and back.

[0043] The phase difference of the two groups of bridge arm drive signals of the two-phase parallel Boost conversion circuit is 180°, and the inductor current works in the critical continuous mode with partial negative current, and the working frequency changes with the output average power and output voltage, and is a variable frequency working mode. When the inductor current linearly decreases to zero, the freewheeling diode in the Boost circuit naturally realizes zero-current turn-off, avoiding the reverse recovery loss of the diode; then, the MOS tube is turned on after a certain "dead time", and in the "dead time", the MOS tube junction capacitor and the Boost inductor resonate, the voltage across the MOS tube decreases, creating the zero-voltage turn-on condition of the MOS tube. The power consumption of the freewheeling diode and the MOS tube is effectively reduced, and the conversion efficiency of the Boost circuit is improved.

[0044] The half-bridge LLC resonant converter works in fixed frequency mode, and its operating frequency is set at the resonant frequency of the resonant inductor and capacitor. The driving signals of the upper and lower tubes are 50% duty cycle square waves with a phase difference of 180° and a fixed dead time. At this frequency, the LLC resonant converter is equivalent to a fixed turns ratio DC transformer, and its gain is approximately equivalent to the turns ratio of the transformer. According to the working principle of the resonant converter, the primary MOS tubes Q3 and Q4 can realize zero-voltage turn-on, and the secondary rectifier diodes can realize zero-current turn-off, thereby effectively reducing the losses on the MOS tubes and rectifier diodes and improving the conversion efficiency. In addition, due to the avoidance of reverse recovery, the reverse voltage peak of the rectifier diode is small, and when full-wave rectification is performed, only the output voltage value is borne, a low-voltage diode with a lower conduction voltage drop can be selected or a MOS tube working in a synchronous rectification mode can be used to replace it, which can further improve the conversion efficiency.

[0045] Figure 2 The control logic block diagram of the low input current ripple high efficiency circuit for pulse power output is composed of a current inner loop for controlling the input current and a voltage outer loop for controlling the output voltage. The control quantity of the voltage outer loop is the peak value of the output voltage, H pv (s) is the sampling transfer function of the output voltage peak value, which samples the output voltage peak value and outputs v o_p signal, v o_p signal is compared with the reference signal V ref The error signal after comparison is the input signal of the voltage loop regulator G v (s), and the output signal of the voltage loop regulator G v (s) is the reference i ref of the current inner loop. H i (s) is the sampling transfer of the input current, which samples the input inductor current and compares it with the output i ref of the voltage loop, and the error signal is the input signal of the current loop regulator G i (s). The output of the current loop regulator is the reference of the peak value of the inductor current, which controls the turn-off time of the MOS tube and determines the input inductor current value. Then, the input inductor current is converted to the secondary side through the fixed frequency LLC resonant conversion circuit equivalent isolation transformer (gain K), and after the difference operation with the output pulse current, the output energy storage capacitor is charged to form the output voltage v o .

[0046] In order to make the input current fluctuation peak-to-peak value low when the pulse load is brought, the output i v of the voltage loop regulator G ref (s) should be close to a DC signal, that is, the bandwidth of the voltage loop regulator should be much lower than the frequency of the output pulse load, which is designed to be one tenth of the lowest pulse load frequency. The too low bandwidth leads to slow dynamic response of the voltage loop, and when the pulse load is suddenly added, the voltage loop regulator Gv The output i of (s) ref The slow adjustment means the input power cannot quickly keep up with the average output power, causing the output voltage to drop rapidly below the minimum required level. To address this, an output pulse load current feedforward branch was added to the control system. Figure 2 As shown, the key operating waveforms at the lowest pulse frequency and the maximum duty cycle are as follows: Figure 3 As shown.

[0047] Figure 4 The diagram shows the acquisition block for the output pulse load current feedforward signal. After the output current signal is acquired, it undergoes low-pass filtering and sampling, followed by single-cycle integral peak sampling. The outputs of the two samplings are connected in parallel for high redundancy, solving the problems of slow response speed of low-pass filtering and low single-cycle integral sample value when outputting high-frequency pulse loads. This also avoids the use of multipliers and dividers, which is beneficial for hardware circuit implementation. The schematic diagram of single-cycle integral peak sampling is shown below. Figure 5 As shown, the feedforward signal is the integrated peak value of the current signal from the previous cycle. When the integrated value of the current sampling signal in the current cycle is detected to be greater than the feedforward value, the feedforward value is set to the value corresponding to the maximum load condition to prevent the output voltage from being too low due to sudden load changes. At the end of the pulse, the feedforward value is corrected to the integrated peak value of the load current in the current cycle. Similarly, when the output pulse width decreases, the feedforward signal needs to be corrected only at the end of the pulse. From the above analysis, it can be seen that when the load of the output pulse changes, the feedforward value of the load current feedforward signal may be higher than the required value, which will cause the output voltage to exceed the required peak voltage. Therefore, a fast voltage loop for the output voltage is connected in parallel on the outer voltage loop to prevent the output voltage from being too high before the load current feedforward signal is corrected.

[0048] The circuit of this invention can be applied to applications such as active phased array radar and pulsed electrochemical wastewater, where the output load is a pulsed power of constant amplitude. During the pulsed power period, the output voltage of the energy storage capacitor decreases, and during the no-load period, the output voltage of the energy storage capacitor increases. Throughout the entire cycle, the circuit maintains low pulsation of the input current, which is beneficial to improving the reliability of the DC power supply and the overall conversion efficiency.

[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention without departing from its spirit and scope should be included within the protection scope of the present invention.

Claims

1. A high-efficiency circuit that controls the constant input current when outputting pulse power, the circuit comprising a DC power supply, an interleaved parallel Boost circuit (1) and an LLC resonant circuit (2), wherein the interleaved parallel Boost circuit (1) and the LLC resonant circuit (2) are connected in series, characterized in that, The parallel two-branch drive signals of the interleaved parallel Boost circuit (1) are 180° complementary and the inductor current operates in the critical continuous mode with partial negative current; the primary side of the LLC resonant circuit (2) is a half-bridge structure, the secondary side is full-wave rectification, and the drive of the upper and lower switches of the primary half-bridge is a fixed operating frequency. The output capacitor C4 of the LLC resonant circuit (2) is used for output voltage filtering and to provide pulse power decoupling through a wide range of voltage changes. The formula for calculating its capacitance value is: In the formula, The amplitude of the output pulse power. The period of the output pulse power. This represents the proportion of output pulse power. To ensure stable pulse output, the highest value of the output voltage is achieved. To ensure the lowest possible output voltage when the pulse output is stable; The control strategy for keeping the input current constant under pulse load conditions is as follows: a voltage and current dual-loop control system with output pulse load current feedforward is used to control the output voltage and input current. The output voltage is amplified by the control system and used as the reference for the input current control loop. The input current control loop is amplified by the control system and used as the reference for the input inductor current. The switching on and off of the MOS transistor in the interleaved parallel Boost circuit (1) is controlled.

2. The high-efficiency circuit with constant input current when controlling pulse power output according to claim 1, characterized in that, The circuit outputs a low-frequency pulse power of constant amplitude, the frequency of which is no higher than 10kHz.

3. The high-efficiency circuit with constant input current when controlling pulse power output according to claim 1, characterized in that, The output capacitor C1 of the interleaved parallel Boost circuit (1) has a capacitance value of less than 10μF.

4. The high-efficiency circuit with constant input current when controlling pulse power output according to claim 1, characterized in that, In the voltage and current dual-loop control system, the feedback error signal output of the voltage outer loop serves as the reference for the input current inner loop, and the bandwidth of the voltage outer loop is no higher than one-tenth of the lowest output pulse load frequency.

5. The high-efficiency circuit with constant input current when controlling pulse power output according to claim 4, characterized in that, In the voltage and current dual-loop control system, the control quantity of the outer voltage loop is the peak value of the output voltage. The sampling timing of the peak voltage is the start time of the output pulse power under no-load conditions or sampling according to the longest pulse power cycle.

6. The high-efficiency circuit with constant input current when controlling pulse power output according to claim 5, characterized in that, The feedforward pulse load current signal does not contain the AC components of the output pulse load frequency and its odd harmonics.

7. The high-efficiency circuit with constant input current when controlling pulse power output according to claim 6, characterized in that, The sampling of the feedforward pulse load current signal is performed using low-pass filtering and by taking the higher of the peak values ​​obtained by integrating the current signal over a single cycle.

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