High-bandwidth module

Abstract

A module includes a substrate having a plurality of contact regions and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies and a spacer wafer, each semiconductor die having a plurality of electrical interconnect posts and a plurality of contact pads. The at least first and second semiconductor dies are fixed to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring that electrically couples the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. A plurality of electrical interconnect posts extend through the holes and are fixed to contact regions on the substrate.

Description

Technical Field

[0001] The present invention relates to the fields of electrical, electronic, and computer, and more specifically, to communication between semiconductor dies and the like. Background Art

[0002] Semiconductor dies have continuously become more complex and larger in size. The defect density on the wafer causes these larger dies to have a greater chance of being affected by random defects, thus resulting in a lower yield. To reduce production losses, the dies are diced in size, but now a larger number of input / output (I / O) are required to communicate between chips at a fast enough rate.

[0003] For example, applications in artificial intelligence (AI) require high power, and signal integrity becomes a greater problem. These aspects of power and signal integrity pose more requirements for solving thermal problems particularly related to thermal interface degradation and uniform bonding wires. This is exacerbated by having multiple dies and multiple types of dies on a single module. Therefore, there is a need in the art to solve the above problems. Summary of the Invention

[0004] In a first aspect, the present invention provides a module, comprising: a substrate having a plurality of contact areas; and a spacer-chip assembly, the spacer-chip assembly further comprising: at least first and second semiconductor dies, each having a plurality of electrical interconnect posts and a plurality of contact pads; a spacer wafer to which the at least first and second semiconductor dies are fixed, the spacer wafer comprising at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies, the spacer wafer comprising a wiring for electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads; the spacer wafer having a plurality of holes formed therethrough, the plurality of electrical interconnect posts extending through the holes and being fixed to the contact areas on the substrate.

[0005] From another aspect, the present invention provides a method comprising: providing a spacer wafer having an inner surface and an outer surface, the spacer wafer including at least first and second semiconductor circuit features and wiring adjacent the outer surface; forming a plurality of trenches partially through the spacer wafer, the trenches being spaced from the at least first and second semiconductor circuit features and the wiring; providing first and second semiconductor dies, each having a plurality of electrical interconnect posts and a plurality of contact pads, the electrical interconnect posts having distal ends; attaching the first and second semiconductor dies to the spacer wafer via the plurality of contact pads, the interconnect posts extending into the trenches, and the contact pads being coupled to the wiring and the semiconductor circuit features to form a spacer-chip assembly; processing the inner surface of the spacer wafer to open the trenches and expose the distal ends of the posts; applying a conductive connection material to the distal ends of the posts; and attaching the spacer-chip assembly to a substrate via the conductive connection material on the distal ends of the posts.

[0006] The principles of the present invention provide techniques and manufacturing processes for high-bandwidth module structures. In one aspect, an exemplary module includes a substrate having a plurality of contact regions; and a spacer-chip assembly. The spacer-chip assembly further includes at least first and second semiconductor dies, each semiconductor die having a plurality of electrical interconnect posts and a plurality of contact pads; and a spacer wafer. The at least first and second semiconductor dies are attached to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring that electrically couples the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. A plurality of electrical interconnect posts extend through the holes and are attached to the contact regions on the substrate.

[0007] In another aspect, an exemplary method includes providing a spacer wafer having an inner surface and an outer surface. The spacer wafer includes at least first and second semiconductor circuit features and wiring adjacent to the outer surface. Further steps include forming a plurality of trenches that partially penetrate the spacer wafer, the plurality of trenches being spaced apart from the at least first and second semiconductor circuit features and the wiring; providing first and second semiconductor dies, each semiconductor die having a plurality of electrical interconnect posts and a plurality of contact pads, the electrical interconnect posts having distal ends; and securing the first and second semiconductor dies to the spacer wafer via the plurality of contact pads, wherein the interconnect posts extend into the trenches, and wherein the contact pads are coupled to the wiring and the semiconductor circuit features to form a spacer-chip assembly. Still further steps include processing the inner surface of the spacer wafer to open the trenches and expose the distal ends of the posts; applying a conductive connection material to the distal ends of the posts; and securing the spacer-chip assembly to a substrate via the conductive connection material on the distal ends of the posts.

[0008] As used herein, an "facilitating" action includes performing the action, making the action easier, helping perform the action, or causing the action to be performed. Thus, by way of example and not limitation, instructions executed on one processor may facilitate an action performed by instructions executed on a remote processor by sending appropriate data or commands to prompt or help perform the action. To avoid doubt, where an actor facilitates an action by performing an action other than the action, the action is still performed by some entity or combination of entities.

[0009] The techniques of the present invention can provide substantially beneficial technical effects. For example, one or more embodiments provide one or more of the following: enabling a direct connection between a processor die and a bottom substrate, which is beneficial for high-power applications; enabling signals to be directly attached to the substrate without contacting Si - this avoids crosstalk between signals that may occur in TSVs (through-silicon vias); reducing or eliminating the height difference between dies; enabling a module to have a substantially unlimited number of dies; reducing or eliminating short-circuit problems during chip bonding operations; allowing a combination of multiple overhangs and large windows with separate holes for each controlled collapse chip connection (C4); being able to support a cantilever beyond the substrate or a die larger than the substrate but having support at all corners; being able to add glass for high-heat chips and add microchannels or waveguides on the same substrate.

[0010] These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments of the invention read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will now be described by way of example only with reference to the preferred embodiments, as shown in the following drawings:

[0012] FIG. 1 shows a first high-bandwidth module design according to the prior art;

[0013] FIG. 2 shows a second high-bandwidth module design according to the prior art;

[0014] FIG. 3 shows a third high-bandwidth module design according to the prior art;

[0015] Figure 4 shows the complexity of the bridge technology when used with a multi-chip module (MCM);

[0016] Figure 5 shows a multi-chip module design with spacers;

[0017] Figure 6 shows a view of the spacer of the design of FIG. 3;

[0018] Figure 7 shows Figure 5 a view of the spacer of the design of;

[0019] Figures 8 - 19 shows the steps in an exemplary manufacturing process according to one aspect of the present invention;

[0020] Figure 20 shows Figure 19 an alternative arrangement of possible top views of;

[0021] Figures 21 - 23 shows alternative steps in an exemplary manufacturing process according to one aspect of the present invention; and

[0022] Figures 24 - 26 shows alternative steps in an exemplary manufacturing process according to one aspect of the present invention, which uses glass to allow high heat flux SiC chips. DETAILED DESCRIPTION

[0023] As described above, semiconductor dies have continued to become more complex and larger in size. The defect density on the wafer causes these larger dies to have a greater chance of being affected by random defects, thus resulting in a lower yield. To reduce production losses, the dies are diced in size, but now a greater number of input / output (I / O) are required in order to communicate between the chips at a sufficiently fast rate.

[0024] For example, applications in artificial intelligence (AI) require high power, and signal integrity becomes a greater issue. These power and signal integrity aspects pose more requirements for solving thermal problems particularly related to thermal interface degradation and uniform bond wires. This is exacerbated by having multiple dies and multiple types of dies on a single module.

[0025] To enable fast communication between dies, the wiring dimensions achievable in semiconductor manufacturing processes are helpful. Silicon (Si) bridges have been tried in the past, however these have led to significant challenges in assembly. Si interposers have been evaluated. Through-Silicon Vias (TSVs) used in such interposers affect signal integrity and power delivery. They also pose challenges as a source of stand-alone components. Si interposers result in supply chain availability issues and also have bonding and assembly challenges.

[0026] One or more embodiments advantageously provide a structure that allows communication across entities having silicon-based wiring between dies without the need for TSVs or double-sided plating. One or more embodiments provide a connectivity type structure where ultimately large Si or glass features (refer to the following discussion of Figure 20 ) will be in the area occupied on a stack close to multiple dies. Instead of creating Si or glass interposers with TSVs, only the formation of communication features and bumps in those areas with capture pads occurs.

[0027] In one or more embodiments, a large Si entity is first formed at the wafer level to have a high density area with high bandwidth communication between closely spaced dies. Then, the wafer is patterned to micro-bumps for communication between dies and also as anchor points to connect the die(s) to the wafer. Before attaching the die to the wafer, holes are formed to allow large pillars on the die to pass through. Then the die is attached to the wafer, followed by underfilling each die.

[0028] Then, the wafer is overmolded to encapsulate all the dies into the wafer. At this time, the wafer is ground at the top to reduce the die / overmolded thickness from the wafer surface to about 400 μm or less. Then, the wafer is partially diced along the final substrate (refer to the following discussion of Figure 15 ). At this time, the wafer is flipped and the wafer is ground, followed by Chemical Mechanical Polishing (CMP) and ashing to simultaneously expose the Cu pillars and singulate the entity.

[0029] There are multiple embodiments and variations that can occur. For example, if the substrate is Si, MIM (Metal-Insulator-Metal) capacitors or deep trench (DT) capacitors can be added to provide a decoupling solution for the wafer core, which can address frequency noise in the range of 1 to 10 GHz. If the substrate is glass, thin-film capacitors can be added first and then patterned to create high-density communication paths between chips. If it is desired to combine SiC die technology and Si technology on the same substrate, glass islands can also be added to the Si substrate first to have thermal isolation regions. These glass regions can also include microchannels for cooling within the package or waveguide for optical or photonics applications. Dicing can also be performed after grinding, and C4 bumps can be formed on the tips of the copper pillars after the copper pillars are exposed.

[0030] Figures 1 - 3 illustrate many possible prior art high-bandwidth module designs. Figure 1 shows design 101 with an embedded bridge 103 (embedded in substrate 106). Advantageously, no special treatment of the die is required. However, it is difficult to use more than two dies; trench lamination is required; a source for lamination is needed; available wiring space between the dies and around the trenches may be lost; the cost of lamination increases by about 2 times; and large C4s will pull dies 105, 107 away from the bridge area 103, resulting in a very low yield. When slotting 103 in substrate 106, due to reference requirements and physical loss of even more space than the bridge itself, the slotted area and the area around the trench cannot be used for Cu wiring. The thickness of the Cu wire is typically about 15 μm, while the thickness of the vias is typically 25 - 30 μm. The thickness of the bridge 103 can be about 300 - 400 μm, resulting in a loss of available wiring area. Note the large solder balls 102 and small solder balls 104.

[0031] Figure 2 shows design 121 with an external bridge 123. Advantageously, standard lamination can be employed, which ensures that dies 125, 127 are correctly connected to the bridge, all components can be easily obtained, and the design maintains the full ability to route everywhere. However, it is difficult to use more than two dies; handling may break the bridge; special fixtures are required; and it may be necessary to plate Cu pillars on the dies to increase the gap. Note the large solder balls 122 and small solder balls 124.

[0032] Figure 3 shows design 141 with spacers 143. Advantageously, standard lamination can be employed, which ensures that dies 145, 147 are correctly connected to the spacers, all components can be easily obtained, the design maintains the full ability to route everywhere, and four or more dies can be used without problems. However, electroplating of copper pillars 149 with a thickness of 150 to 200 μm is typically required (for clarity, only some of the pillars are numbered). Also note the solder balls 144.

[0033] Reference Figure 4 , aligning and utilizing multiple thin bridges 161 with a high bonding and assembly (BA) yield adds complexity. A proper BA process would be such that there would be no problem in putting everything together; ideally, a method with a final yield of at least 98% should be used. During BA, the alignment process itself may result in a 1% loss. The process of alignment and flipping can have an additional 1% settlement. If there are any problems along the way, due to non-wetting and poor electrical response, it can result in an additional 5 to 10% settlement. Figure 4 The situation in may also limit the available thermal solutions as a permanent carrier may be required. Note dies 162-1, 162-2, 162-3, and 162-4. View 163 is a detail of die 162-4. In a non-limiting example, the width W is 19,500 μm, the height H is 25,600 μm, and the bridging coverage area is shown at 165; their long dimension can be, for example, 9626 μm.

[0034] Figure 5 Design 181 with spacers 183 is shown. Advantageously, standard lamination can be employed. This design ensures that dies 185, 187 are correctly connected to the spacers, all components can be easily obtained, this design maintains the full ability to route everywhere, and this design enables all dies to be physically attached and easy to handle. Additionally, there can be four or more dies without problems, reducing or eliminating the alignment tolerance issues with holes, larger C4s for power and ground and smaller C4s for signals can be transferred, and the need for high aspect ratio photoresist plating is reduced. However, electroplating of copper pillars 149 with a thickness of 150 to 200 μm is typically required, and some modifications to the dies may be needed compared to the configuration in Figure 3. Also note solder balls 157.

[0035] Figure 6 A top view of spacer 143 of design 141 of Figure 3 related to dies 145, 147, 146, 148 is shown. This view is looking "up" in Figure 3, omitting substrate 106 (see cross-section line VI-VI). Figure 6 The bottom of shows detail 191 of spacer 143 including holes 142 for accommodating copper pillars 149. This design can include, for example, 15,000 holes; 80-μm copper pillars in the under bump metal (UBM); and holes with a diameter of approximately 100 μm. Advantageously, there is no impact on the die design. However, sidewall passivation is important, and the method is limited by the resolution of the photoresist process.

[0036] Figure 7 Shows Figure 5Top view of spacer 183 of design 181 related to dies 185, 187, 186, 188. This view is "looking up" in Figure 5 and the substrate 106 is omitted (see cross-section line VII-VII). Figure 7 The bottom of Figure 6 shows details 192 of spacer 183, which includes large (relative to

[0037] ) holes 193 to accommodate hybrid UBM 195 suitable for AI applications. Such a design can include, for example, four large holes; 100+μm copper pillars in the under-bump metallurgy (UBM); and square holes of about 900μm on each side. Advantageously, sidewall passivation is not as important, and the method is not limited by the resolution of the photoresist process.

[0038] Now consider using a spacer with heterogeneous integration (HI). HI refers to assembling and packaging multiple separately manufactured components onto a single chip to improve functionality and enhance operating characteristics. Heterogeneous integration allows packaging components of different functions, different process technologies, and sometimes separate manufacturers. The combined device can vary in terms of functionality (e.g., processor, signal processor, cache, sensor, photonic device, RF, and MEMS) and technology (e.g., one device optimized for die size and another optimized for low power). Refer to Figure 8 and note wafer 231 from which one or more spacers are fabricated. The diameter of the wafer can be, for example, 6 inches, 8 inches, or 12 inches (15, 20, or 30 cm respectively). It should also be noted that the high-density wiring 233, contacts 232, and capacitors 235 can be, for example, 35μm thick. In Figure 9 , it is patterned and ashed (e.g., using standard lithography and ashing processes) to create trenches (holes) 237 that can be, for example, 80μm deep. As seen at 239, in one or more embodiments, the wafer edge is kept at full thickness. In Figure 10 , two-pass electroplating is used for one or more dies 241 with 100μm electrical interconnect (copper) pillars 243 and pads 245. It should be noted that the specific dimensions provided herein are exemplary, and other embodiments may have different dimensions. In Figure 11 , one or more dies 241 are bonded to wafer 231. The electrical interconnect pillars 243 are placed within the trenches (holes) 237, while the pads 245 are bonded to the capacitors 235. In Figure 12 , underfill 247 is applied to the trenches (holes) 237 (for clarity, the holes are not numbered in Figure 13 ). In Figure 13In , overmolding 249 is applied. The wiring 233 can be fabricated, for example, using a dual-damascene technique; e.g., within an oxide having a nitride cap thereon. For example, contacts (pads) can be formed by opening only the nitride under the pads

[0039] 232. The contacts (pads) 232 are bonded to the pads 245 (depicted as a single entity after bonding). Various conventional underfill and overmolding materials can be used.

[0040] In Figure 14 , the upper surface is ground such that the overmolding now exists only between the dies 241 and at the outer edges. In Figure 15 (“pre-grind dicing” process), partial dicing (e.g., by a standard mechanical dicing process, optionally using a laser) is performed as shown at 251. In Figure 16 , the lower surface is (back) ground and chemical mechanical polishing (CMP) and ashing are performed to singulate into individual spacer / chip assemblies 253 (see the singulation resulting in Figure 17 ) and to expose the lower ends of the electrical interconnect posts 243. Figure 17 shows the singulated spacer / chip assemblies 253. In Figure 18 , an impregnable paste 255 is applied to the lower ends of the electrical interconnect posts 243. In Figure 19 , attachment to the substrate 257 is effected via the impregnable paste 255 on the lower ends of the electrical interconnect posts 243 (not numbered in Figure 20 to avoid clutter). Figure 20 shows alternative floorplans 259, 261, 263 with differently arranged dies 241. Note that the overmolding 249 (seen in the floorplan and essentially the outline of the spacer-chip assembly as discussed elsewhere herein) is larger in outline than the dies 241 themselves. In contrast, prior art silicon bridge methods have small bridge entities between the dies that are much smaller in outline than the dies themselves. Prior art silicon interposer designs can have dimensions similar to those of the embodiments shown in Figure 20 , but require through-silicon vias (TSVs) that are prone to signal crosstalk, are too small to carry significant power, and undesirably require power redistribution within the silicon. Additionally, one or more embodiments are capable of using an impregnable paste in place of C4 electroplating, which is significantly cost-effective. It should be noted that in some cases, the electrical interconnect posts 243 do not need to be provided with an impregnable paste or C4; instead, all solder is placed on the substrate 257. However, this presents challenges regarding the use of a suitable compatible flux material (capable of removing both copper oxide and the oxide of the solder material) or a formic acid environment. Observed in the floorplan (i.e., in Figure 19Looking downwards (in the middle), the electrical interconnect posts 243 can occupy, for example, 30% of the planar shape area, and the remaining (70%) of the planar shape area is filled with underfill 247. However, due to surface tension, underfilling may not be able to penetrate gaps less than about 20 μm. We have found that in one or more embodiments, a gap of about 60 μm is suitable. For example, in Figure 16 the middle, the electrical interconnect posts 243 can protrude from the surface by about 60 μm. When making the electrical interconnect posts 243 from a photoresist material, a depth-to-width ratio (length: diameter) of about 4:1 may be the maximum achievable. This effectively limits the minimum diameter of the posts. In some embodiments, an impregnable copper paste is used. In one or more embodiments, a lead-free impregnable solder paste is used, such as SnBi paste, tin-silver-copper (SAC) impregnable paste, etc. A suitable source of paste is Dycotec Materials Ltd, Swindon, Wiltshire, SN57 SW England. We have found that copper joints can be brittle, while solder can better withstand the coefficient of thermal expansion (CTE) mismatch.

[0041] It is noted that in some embodiments, plasma cutting is performed before grinding to create a curved edge.

[0042] Please refer to Figure 21 , in another method, the lower surface is ground and chemical mechanical polishing (CMP) and ashing are performed without cutting to expose the lower ends of the electrical interconnect posts 243. In Figure 22 the middle, C4 electroplating is performed to obtain solder joints 265 at the ends of the posts (the posts in Figure 22 are not numbered to avoid confusion). Then in Figure 23 the middle, singulation is performed to obtain individual spacer / chip assemblies 253. Conventional C4 materials can be used in one or more embodiments. Different from the 100-μm-thin stand-alone interposers that require a carrier to support, one or more spacer embodiments disclosed herein have the thickness of the die plus the spacer; for example, about 500 μm thick after exposing the Cu posts for electroplating. This advantageously eliminates the need for a carrier and a subsequent release layer.

[0043] In an alternative method, passivation can be performed before removing the resist utilized in the ashing process; for example, by nitride or oxide deposition, especially if holes rather than windows are to be added.

[0044] Refer to Figure 24 , in an alternative method, the bag region 271 is ashed and glass 273 with a permanent adhesive is added before microbumps. In Figure 25 the middle, the glass 273 ( Figure 25 is not numbered in the middle) is plasma ashed to form holes 275. In Figure 26In [description], one or more SiC chips 277-2 are attached using Cu pillars 279 located on holes 275; the Si chip 277-1 can be attached, for example, by pillars passing through other holes formed as described above (holes not marked in [description] to avoid confusion). Thus, for example, the first chip 277-1 can be a silicon chip and the second chip 277-2 can be an SiC chip. Any suitable type of glass or adhesive known in the art can be used; in one or more embodiments, glass with a coefficient of thermal expansion (CTE) similar to that of Si is desirable. Epoxy resin can be used to avoid the need for fillers as these would have a comparable CTE. Figure 26 In [description], the substrate (the base carrier to which one or more embodiments are attached) can be made of, for example, semiconductor material, glass, or ceramic. In some cases, the substrate 257 can have the same CTE as the element 231. In such a case, for example, Cu-to-Cu bonding is feasible because less attention is paid to having a bond that can deform during shrinkage of the two relative to each other. If, for example, plasma cutting (as opposed to blade cutting) is used before grinding (e.g., in [description]), then holes, windows, and angled edges can be easily formed. One or more embodiments include contacts (micro pads) 232 on the die side for connecting die-to-die communication and anchoring to the substrate. One or more embodiments include electrical interconnect (copper) pillars 243 on the die side with or without solder, which are 50 μm higher than the thickness of the substrate. Decoupling capacitors 235 can be located within the substrate or placed on the substrate (depending on the configuration, it can be on the top or bottom). In addition to Cu pillars, the pillars can be Cu pillars with Ni caps. They can also be no-flow solders, for example, using Cu / Ni layers. Technically, only Ni pillars can be used, although a long (duration) plating process is required.

[0045] In [description], the substrate (the base carrier to which one or more embodiments are attached) can be made of, for example, semiconductor material, glass, or ceramic. In some cases, the substrate 257 can have the same CTE as the element 231. In such a case, for example, Cu-to-Cu bonding is feasible because less attention is paid to having a bond that can deform during shrinkage of the two relative to each other. If, for example, plasma cutting (as opposed to blade cutting) is used before grinding (e.g., in [description]), then holes, windows, and angled edges can be easily formed. One or more embodiments include contacts (micro pads) 232 on the die side for connecting die-to-die communication and anchoring to the substrate. One or more embodiments include electrical interconnect (copper) pillars 243 on the die side with or without solder, which are 50 μm higher than the thickness of the substrate. Decoupling capacitors 235 can be located within the substrate or placed on the substrate (depending on the configuration, it can be on the top or bottom). In addition to Cu pillars, the pillars can be Cu pillars with Ni caps. They can also be no-flow solders, for example, using Cu / Ni layers. Technically, only Ni pillars can be used, although a long (duration) plating process is required. Figure 15 In [description], one or more embodiments advantageously eliminate the height difference between various dies; allow an infinite number of dies; avoid the problem of short circuits during chip bonding; and / or allow multiple overhangs and a combination of large windows and individual holes for each C4 connection.

[0046] One or more embodiments advantageously eliminate the height difference between various dies; allow an infinite number of dies; avoid the problem of short circuits during chip bonding; and / or allow multiple overhangs and a combination of large windows and individual holes for each C4 connection.

[0047] One or more embodiments provide a high-bandwidth module with high-density wiring for die-to-die communication with a mixture of large window openings and small openings in order to accommodate hundreds to thousands of C4s assembled at the wafer level using heterogeneous integration; can support dies with cantilevers extending beyond the substrate or larger than the substrate but supporting all corners; and / or is capable of adding glass for high-heat-generating chips on the same substrate and for adding microchannels or waveguides.

[0048] In fact, one or more embodiments provide a solution for assembling multiple dies using Si technology within the confines of a Si interposer. One or more embodiments enable self-alignment with large openings for interconnection passage.

[0049] One or more embodiments provide a heterogeneous integration structure and a method of manufacturing the same. Related aspects include: 1) a method of manufacturing low-cost silicon / glass / molded vertical interconnection pathways as opposed to expensive TSVs, and 2) using an impregnable paste as opposed to conventional solder plating, which aids in bonding and assembly.

[0050] One or more embodiments provide die-to-die connections in a horizontal plane, pillars for connection to low-cost openings for vertical connection, and / or the use of an impregnable solder paste for final connection. One or more embodiments employ conventional low-cost connections that are formed on the active side of the device as compared to the sides of the device. Some embodiments allow for face-to-face connection with another piece of Si. In addition to Si decoupling capacitors, the spacer may also have phase change memory or other memory therein, enabling use in a graphics processing unit (GPU) and / or accelerator. In one or more embodiments, by underfilling the pillars during the manufacturing process, the pillars can then be recessed sufficiently using standard CMP and ashing processes to allow for the use of an impregnable solder paste. In fact, in one or more embodiments, the pillars are embedded in the underfill and the tips of the pillars are exposed for the impregnable solder paste. One or more embodiments are formed without using conventional stacked dies and / or plated vias for interconnection (e.g., in glass). One or more embodiments are formed without using wafer-to-wafer or PCB-to-PCB bonding (PCB = printed circuit board).

[0051] The discussion has been presented thus far, and for example with reference to Figure 19 , it will be understood that according to one aspect of the present invention, an exemplary module includes a substrate 257 having a plurality of contact regions 258. Also included is a spacer-chip assembly, which in turn includes at least first and second semiconductor dies 241. Each die has a plurality of electrical interconnection pillars 243 and a plurality of contact pads 245. The spacer-chip assembly also includes a spacer wafer 231. At least the first and second semiconductor dies are fixed to the spacer wafer. For example, the spacer wafer includes at least first and second semiconductor circuit features (such as decoupling capacitors 235) coupled to a first portion of the contact pads of at least the first and second semiconductor dies. The spacer wafer also includes wiring (e.g., high-density wiring 233) that electrically couples at least the first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. A plurality of electrical interconnection pillars extend through the holes and are fixed to the contact regions 258 on the substrate.

[0052] In addition to decoupling capacitors or other capacitors, semiconductor circuit features can include a range of semiconductor-based items, including inductors, memories, phase change memories, etc. The spacer is not limited to being a support entity. For example, it can be used in GPU / accelerator applications, etc.

[0053] One or more embodiments also include underfill 247 disposed in the holes. These holes are formed by opening the trenches 237 as described above and are not individually numbered in Figure 20 One or more embodiments further include overmolding 249 located between at least the first and second semiconductor dies 241.

[0054] It is noted that in Figure 19 the substrate 257 can also include contact points (not shown) coupled to the electrical interconnect posts 243 using vias, and can also include a land grid array (not shown) on the bottom coupled to a socket (not shown) on the board. For example, the board can have, for example, 4 - 8 Figure 19 modules as shown. Applications include, for example, powerful hosts such as the IBM z15 TM host. Such a system can have, for example, 4 - 8 drawers, each drawer including a board. IBM and z15 are trademarks of International Business Machines Corporation, registered in many jurisdictions worldwide.

[0055] For example, as Figure 6 shown, in some cases, the holes are sized to accommodate a single post. On the other hand, as Figure 7 shown, in some cases, the holes are sized to accommodate multiple posts. In the latter case, for example, the posts include under bump metal (UBM).

[0056] Referring to Figures 24 - 26 some embodiments also include a glass-filled pocket region (note the glass 273 in pocket region 271) formed in the spacer wafer 231. At least a portion of the holes are formed in the glass (see trench 275). The first semiconductor die 277 - 1 includes a silicon chip, and the second semiconductor die 277 - 2 includes a silicon carbide chip. Those interconnect posts 279 associated with the silicon carbide chip 277 - 2 extend into those holes in the glass.

[0057] Referring to Figures 24 - 26 SiC runs very hot, while other types of dies typically cannot withstand the heat. The glass 273 helps isolate the heat load of the SiC chip 277 - 2 from the rest of the structure. Referring to Figure 26, the SiC chip 277-2 has connection points to the conventional chip 277-1 (e.g., the high-density wiring discussed elsewhere); in one or more embodiments, these should be underfilled with a thermally non-conductive underfill material such that heat from the SiC chip 277-2 is transferred through its pillars 279 rather than laterally into the chip 277-1. In cases where needed, various laser manufacturing techniques that create channels within the glass can be used to form cooling microchannels in the glass 273.

[0058] In some cases, multiple electrical interconnect pillars 243 are fixed to contact areas on the substrate 257 via an impregnable paste 255.

[0059] In some cases, multiple electrical interconnect pillars 243 are fixed to contact areas on the substrate via controlled collapse chip connection (C4) 265.

[0060] In some cases, the spacer wafer 231 includes glass and the decoupling capacitor 235 includes a thin-film capacitor. In other cases, the spacer wafer 231 includes silicon and the decoupling capacitor 235 is selected from the group consisting of deep trench capacitors and MIM (metal-insulator-metal) capacitors.

[0061] It will be appreciated that in one or more embodiments, advantageously, instead of creating a Si or glass interposer with TSVs, only bump formation occurs for the communication features and those areas with capture pads. In Figure 19 for example, the copper wires / wires in the silicon under 249 include high-density wiring for die-to-die communication. For example, some pads are connected to capacitors while other pads can be provided only for anchoring to hold the die to the spacer. Notably, some prior art designs employ a silicon interposer with silicon vias extending from the top to the bottom, where C4 connections are on the bottom and microbumps are on the top. There is typically one TSV for each C4 bump, but there are many more microbumps on the top, greater than the number of C4s, such that horizontal electrical wiring is required within the silicon interposer to connect to the microbumps. This requires an undesirable redistribution layer within the Si interposer. A significant amount of power can be carried in large C4s - for example 4kA / cm 2 . Advantageously, one or more embodiments do not require a redistribution layer within the silicon.

[0062] On the other hand, starting from Figure 8 it will be understood that according to one aspect of the present invention, an exemplary method includes the step of providing a spacer wafer 231. The spacer wafer has an inner surface 234 and an outer surface 236, and the spacer wafer includes at least first and second semiconductor circuit features 235 and high-density wiring 233 adjacent to the outer surface 236. As Figure 9As seen, another step includes forming a plurality of trenches 237 that partially penetrate the spacer wafer and are spaced apart from at least the first and second semiconductor circuit features and the high-density wiring. Refer to Figure 10 and 11 , a further step includes providing first and second semiconductor dies 241, each die having a plurality of electrical interconnect posts 243 and a plurality of contact pads 245. The electrical interconnect posts have distal ends (the downward-pointing ends, not the ends attached to the die 241), and another step includes securing the first and second semiconductor dies 241 to the spacer wafer 231 via the plurality of contact pads 245, wherein the electrical interconnect posts 243 extend into the trenches 237 and the contact pads 245 are coupled to the high-density wiring 233 and the semiconductor circuit features (such as decoupling capacitors 235) to form a spacer-chip assembly. The high-density wiring can include, for example, wiring such as used in semiconductor manufacturing processes, which can include from 5-micron line and pitch to sub-micron line and pitch.

[0063] Refer to Figure 16 , a further step includes processing the inner surface 234 of the spacer wafer 231 to open the trenches and expose the distal ends of the electrical interconnect posts 243. As Figure 18 shown, another step includes applying a conductive connection material (such as an impregnable paste 255 of C4) to the distal ends of the posts. As Figure 19 shown, another step includes securing the spacer-chip assembly to a substrate 257 via the impregnable paste on the distal ends of the posts.

[0064] As Figure 12 shown, one or more embodiments also include applying underfill 247 to the trenches after securing. Additionally, as Figure 13 seen, one or more embodiments further include applying overmolding 249 over and between the first and second semiconductor dies after applying the underfill.

[0065] As Figure 14 seen, one or more embodiments also include processing (such as grinding) the overmolding to be flush with the outer surface 248 of the semiconductor die 241. This process is capable of removing a bit of the back side of the chip, for example, from a few microns to as thin as desired, such as more than 685 μm for a 785-μm chip. One purpose is to ensure that there is no overmolding material on the back side of the die to ensure successful heat flux from the back side. It is also desirable to have all the dies in the same plane for successful lid contact. One or more embodiments use RIE to etch back some of the overmolding to ensure that it does not interfere with the lid capping operation.

[0066] As Figure 12As shown, in one or more embodiments, the providing further includes providing third and fourth semiconductor dies 241, each semiconductor die having a plurality of electrical interconnect posts 243 and a plurality of contact pads 245. In such cases, the fixing further includes fixing the third semiconductor die and the fourth semiconductor die to the spacer wafer via the plurality of contact pads, wherein the interconnect posts extend into the trenches, and wherein the contact pads are coupled to the high-density wiring to form the spacer-chip assembly. Another step includes singulating the spacer wafer to form a first spacer / chip assembly (module) 253 including the first and second semiconductor dies and a second spacer / chip assembly (module) 253 including the third and fourth semiconductor dies.

[0067] In a non-limiting example, singulation includes partially cutting the spacer-chip assembly by forming a notch 251 from the outside into the spacer wafer before processing the inner surface, as Figure 16 shown. As Figure 17 shown, the processing of the inner surface of the spacer wafer enables singulation by contacting the notch.

[0068] In Figure 16 , one or more embodiments grind until just before reaching the distal end of the electrical interconnect posts 243. IR-detectable (e.g., metal) features 242 may be included in the silicon and an IR (infrared) sensor may be employed. The sensor does not "observe" the silicon but "observes" the metal features 242. For example, grind approximately 10 μm before hitting the underfill region. Use a slurry-impregnated fabric for CMP (chemical mechanical planarization), followed by reactive ion etching (RIE) to preferentially remove material from the spacer wafer 231 without removing material from the electrical interconnect posts 243, and ashing until the posts are exposed in the desired amount as in Figure 16 .

[0069] In an alternative method that does not use pre-grind dicing (e.g., suitable for applications that do not use copper slurry), expose the TSVs approximately 10 microns, deposit a nitride-oxide-nitride triple layer, open the TSVs only in the desired regions, sputter, apply photoresist, electroplate large C4s, and connect to the substrate.

[0070] Referring to Figures 24 - 26, one or more embodiments also include forming a pocket region 271 in the spacer wafer 231; and adhering glass 273 into the pocket region. The formation of the plurality of trenches includes forming at least a portion of the trenches 275 in the glass. The first semiconductor die 277-1 includes a silicon chip and the second semiconductor die 277-2 includes a silicon carbide chip. In the step of fixing the first and second semiconductor dies to the spacer wafer via a plurality of contact pads, wherein the interconnect posts extend into the trenches, those interconnect posts 279 associated with the silicon carbide chip 277-2 extend into the trenches 275 in that glass 273. In some embodiments, all of the posts 279 protruding from the chip 277-2 pass through holes in the glass. Some of the posts 279 protruding from the SiC chip 277-2 will carry a significant amount of power and can be made to have a larger diameter than the posts 279 protruding from the chip 277-1. For example, looking at the plan view, the die 277-1 (e.g., not SiC) can be about 20×25 mm and can dissipate about 600 W, while a similarly sized SiC die 277-2 can dissipate 1200 W or more. There can also be signal input / output (I / O) connections to the chip 277-2 that do not dissipate a large amount of power. Such as Figure 7 the solutions in can employ posts of different diameters according to the power dissipation. If desired, the low-power small-diameter posts 279 can bypass the glass 273.

[0071] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or technical improvements made to the technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A module, comprising: a substrate having a plurality of contact regions; and a spacer-chip assembly, which further comprises: at least first and second semiconductor dies, each having a plurality of electrical interconnect posts and a plurality of contact pads; a spacer wafer to which the at least first and second semiconductor dies are fixed, the spacer wafer comprising at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies, the spacer wafer comprising wiring for electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads; the spacer wafer having a plurality of holes formed therethrough, the plurality of electrical interconnect posts extending through the holes and being fixed to the contact regions on the substrate.

2. The module according to claim 1, wherein the semiconductor circuit features comprise decoupling capacitors.

3. The module according to claim 2, further comprising underfill disposed in the holes.

4. The module according to claim 3, wherein, it further comprises overmolding between the at least first and second semiconductor dies.

5. The module according to claim 4, wherein the holes are sized to accommodate a single one of the electrical interconnect posts.

6. The module according to claim 4, wherein the holes are sized to accommodate a plurality of the electrical interconnect posts.

7. The module according to claim 6, wherein the electrical interconnect posts comprise under bump metallurgy (UBM).

8. The module according to any one of claims 4 to 7, further comprising a glass-filled pocket region formed in the spacer wafer, wherein: at least a portion of the holes are formed in the glass; the first semiconductor die comprises a silicon chip; the second semiconductor die comprises a silicon carbide chip; and those of the electrical interconnect posts associated with the silicon carbide chip extend into those of the holes in the glass.

9. The module according to any one of claims 4 to 7, wherein the plurality of electrical interconnect posts are fixed to the contact regions on the substrate via an impregnable paste.

10. The module according to claim 9, wherein the electrical interconnect posts comprise copper and the impregnable paste comprises copper.

11. The module according to claim 9, wherein the electrical interconnect posts comprise copper and the impregnable paste comprises a lead-free solder.

12. The module according to any one of claims 4 to 7, wherein the plurality of electrical interconnect posts are fixed to the contact regions on the substrate via controlled collapse chip connection (C4).

13. The module according to any one of claims 4 to 7, wherein the spacer wafer comprises glass and the decoupling capacitors comprise thin film capacitors.

14. The module according to any one of claims 4 to 7, wherein, the spacer wafer comprises silicon and the decoupling capacitors are selected from the group consisting of deep trench capacitors and metal-insulator-metal (MIM) capacitors.

15. A method, comprising: Provide a spacer wafer having an inner surface and an outer surface, the spacer wafer including at least first and second semiconductor circuit features and wiring adjacent to the outer surface; Form a plurality of trenches partially through the spacer wafer, the plurality of trenches being spaced apart from the at least first and second semiconductor circuit features and the wiring; Provide first and second semiconductor dies, each having a plurality of electrical interconnect posts and a plurality of contact pads, the electrical interconnect posts having distal ends; Attach the first and second semiconductor dies to the spacer wafer via the plurality of contact pads, wherein the electrical interconnect posts extend into the trenches, and the contact pads are coupled to the wiring and the semiconductor circuit features to form a spacer-chip assembly; Process the inner surface of the spacer wafer to open the trenches and expose the distal ends of the electrical interconnect posts; Apply a conductive connection material to the distal ends of the electrical interconnect posts; And Attach the spacer-chip assembly to a substrate via the conductive connection material on the distal ends of the electrical interconnect posts.

16. The method according to claim 15, wherein, Applying the conductive connection material includes applying an impregnable paste.

17. The method according to claim 16, wherein the semiconductor circuit features include decoupling capacitors.

18. The method according to claim 17, further comprising applying an underfill material into the trenches after the attachment.

19. The method according to claim 18, further comprising applying overmolding over and between the first and second semiconductor dies after applying the underfill.

20. The method according to claim 19, further comprising processing the overmolding to be flush with the outer surfaces of the semiconductor dies.

21. The method according to claim 20, wherein: The providing further includes providing third and fourth semiconductor dies, each having a plurality of electrical interconnect posts and a plurality of contact pads; The attaching further includes attaching the third and fourth semiconductor dies to the spacer wafer via the plurality of contact pads, wherein the electrical interconnect posts extend into the trenches, and the contact pads are coupled to the wiring to form the spacer-chip assembly; Further comprising singulating the spacer wafer to form a first module including the first and second semiconductor dies and a second module including the third and fourth semiconductor dies.

22. The method according to claim 21, further comprising partially cutting the spacer-chip assembly by forming a cut from the outside into the spacer wafer before processing the inner surface, wherein the processing of the inner surface of the spacer wafer effects the singulation via contacting the cut.

23. The method according to claim 22, wherein the partial cutting includes plasma cutting.

24. The method according to any one of claims 19 to 23, further comprising: Forming a pocket region in the spacer wafer; And Adhering glass into the pocket region; wherein: Forming the plurality of trenches includes forming at least a portion of the trenches in the glass; The first semiconductor die includes a silicon chip; The second semiconductor die includes a silicon carbide chip; and In the step of fixing the first and second semiconductor dies to the spacer wafer via the plurality of contact pads, wherein the electrical interconnect posts extend into the trenches, at least a portion of those electrical interconnect posts associated with the silicon carbide chip extends into the trenches in those glasses.

25. The method according to any one of claims 15 to 23, wherein applying the conductive connection material includes applying controlled collapse chip connection (C4) solder joints.

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