Switched capacitor amplifier and pipelined analog-to-digital converter comprising the same

Abstract

A switched capacitor amplifier comprises a comparator (110), a sampling capacitor and an amplification capacitor (120, 130), and a controller (140) for controlling discharge and charge current sources (135, 136) in dependence on an output signal of the comparator. A closed loop control circuit (151, 152, 153) is configured to determine a delay of the comparator (110), and to control an offset of the comparator in response to the determined delay.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a switched-capacitor amplifier. In particular, the present disclosure relates to a switched-capacitor amplifier comprising a comparator coupled to a sampling and amplification capacitor, wherein the sampling capacitor is charged and discharged by a corresponding switch depending on an output signal of the comparator. The present disclosure further relates to a pipeline analog-to-digital converter comprising at least two converter stages, said converter stages comprising an analog-to-digital converter, a digital-to-analog converter, a subtractor, and a switched-capacitor amplifier to amplify a residual signal. BACKGROUND

[0002] Signal amplifiers are widely used in electronic devices to amplify electronic signals. The analog amplifier concept can use a transconductance amplifier that integrates a current gm over a capacitor at a fixed time. However, such an analog concept can be affected by variations in manufacturing process, power supply voltage, and operating temperature (PVT - Process, Voltage, Temperature), such that the gain can spread over the PVT, leading to non-linearities. This requires calibration of the amplifier, which is a time-consuming and costly process.

[0003] There is a comparator-based switched-capacitor amplifier concept, wherein an input signal is transferred on a sampling capacitor and the charge is removed from it until a virtual ground node close to a reference voltage of the comparator is detected by a component, which can be a ground potential. The comparator exhibits a switching delay until a transition detected on the input side appears on the output side. Therefore, the comparator-based switched-capacitor amplifier comprises a coarse current source for discharging the sampling capacitor and a fine current source for recharging the sampling capacitor afterwards to reduce errors due to a charging overshoot caused by the comparator delay. However, due to the relatively low charging current, the recharging phase can take a significantly long time, which slows down the operation of the conventional comparator-based switched-capacitor amplifier. The comparator can have an adjustable threshold to reduce the overshoot, however, this requires the comparator delay over the PVT to be known, which is difficult or almost impossible.

[0004] The comparator-based switched-capacitor amplifier can be used in a pipeline analog-to-digital converter (ADC) to amplify a residual signal of a preceding stage to full strength to forward it to a next stage. Among various types of ADC concepts, a feasible class of ADCs to be used in stages of a pipeline ADC can employ a successive approximation register algorithm.

[0005] There is a need to increase the speed of operation of a comparator-based switched-capacitor amplifier to increase the conversion speed of an ADC, e.g. a pipeline ADC, since the conversion speed of an ADC is significantly determined by the speed of operation of the residual amplifier. Furthermore, there is a need to prevent PVT variations from affecting the speed and accuracy of the amplifier to increase the accuracy of a pipeline ADC using a comparator-based switched-capacitor residual amplifier.

[0006] It is an object of the present disclosure to provide a comparator-based switched-capacitor amplifier that operates faster.

[0007] It is another object of the present disclosure to provide a comparator-based switched-capacitor amplifier that is less dependent on manufacturing process variations and operating condition variations such as power supply voltage and temperature.

[0008] It is yet another object of the present disclosure to provide a pipelined analog-to-digital converter that operates faster and with higher accuracy. SUMMARY

[0009] One or more of the above objects are achieved by the switched-capacitor amplifier of the present invention.

[0010] According to one embodiment, the comparator-based switched-capacitor amplifier comprises a comparator having one or more input terminals and an output terminal. A sampling capacitor is coupled through a switch to one of the input terminals. An amplification capacitor is also coupled through a corresponding switch to an input terminal of the comparator and to a current source for discharging the sampling capacitor and to a current source for charging the sampling capacitor. The charging current source delivers a smaller current than the discharging current source. A controller is configured to operate the switches in dependence on the output signal of the comparator. A load capacitor can be coupled to the amplification capacitor to store an amplified output charge, wherein a ratio of capacitances of the amplification and sampling capacitors determines an amplification factor of the amplification process. The amplifier can have a single-ended configuration or a differential configuration.

[0011] According to the principles of the present disclosure, a closed-loop control circuit is provided that closes a loop from the output of the comparator to the input of the comparator. The closed-loop control circuit is configured to determine a delay of the comparator and to control or determine an offset of the comparator in response to the determined delay. The closed-loop control circuit can be included in both single-ended as well as differential configurations.

[0012] The closed loop control circuit allows for dynamic control of the comparator offset such that the comparator delay is significantly reduced or compensated. Thereby, after detection of a virtual ground condition, the sample capacitor discharge overshoot to a signal other than the reference signal of the comparator (e.g. ground potential) is significantly reduced or close to zero. Thereafter, the sample capacitor charging time by the charge current source is short until the next virtual ground condition is detected. The control loop ensures that the sample capacitor discharge overshoot is small and the sample capacitor charging thereafter is short such that the amplification operation of the switched capacitor amplifier is fast. The closed loop control circuit operates iteratively and dynamically such that in steady state the overshoot remains as small as possible. Thereby, the regulation loop also compensates for PVT dependent parameters of the involved electronic components such that the amplification speed is significantly independent of PVT variations. In this regard, no calibration during device testing is required, e.g. using parameter measurements to incorporate or trim components within the amplifier as it can be the case for conventional amplifiers. Furthermore, calibration drifts are inherently avoided.

[0013] The amplifier operates digitally to amplify an analog input signal using comparators, switches, capacitors and current sources. The amplification factor of the amplifier is mainly determined by the ratio between the capacitances of the amplification capacitor and the sample capacitor. All these components can be easily scaled to smaller feature sizes such that the amplifier design is scalable. Therefore, it is simple to transfer the proven design and size settings of an amplifier according to the principles of the present disclosure to a new process using smaller feature sizes by scaling, while it can be expected to maintain the performance. This is an important benefit for using the amplifier in a larger system, e.g. an analog-to-digital converter. Also, the robustness of the amplifier against PVT variations is maintained.

[0014] According to embodiments, the closed loop control circuit can use digital components and can operate mainly digitally. The closed loop control circuit can comprise a time-to-digital converter (TDC) to determine a signal dependent on the comparator delay, wherein information of the return signal is returned and fed back to the comparator to set the offset of the comparator. The digital implementation using a TDC converter has a high PVT robustness. The TDC can determine the charging time of the sampling capacitor during the fine charging phase, which represents the comparator delay, since the charging time depends on the overshoot, which depends on the comparator delay. The TDC can determine a digital signal for the time from the start of the fine charging phase until the termination of the fine charging phase, which is determined by the comparator in response to detecting the virtual ground condition. The TDC can use a fixed preset signal slightly above zero to allow for negative feedback values when the TDC output can be zero. This can occur when starting with a positive initial comparator offset with only direct deactivation of the fine charging phase. Accordingly, the negative feedback values in the closed loop control circuit help to leave the corresponding dead zone. For a bidirectional comparator offset adjustment, the digital preset signal subtracted from the signal dependent on the comparator delay allows for negative feedback values when the TDC output is zero or greater than zero. After the feedback loop has accumulated a control signal high enough, the loop can continue to operate with the preset signal being reduced or set to zero or close to zero to allow for further fine adjustment of the comparator offset, assuming for example that there is an integrator within the loop to push the comparator offset into the negative range. Once the loop has converged and is in a converged state or steady state, the digital preset signal can be set to zero. The signal to be integrated is a linear signal, such that the control loop operates, stabilizes and provides zero error in a linear manner.

[0015] The integrator can be connected between the time-to-digital converter and the input terminal of the comparator. The integrator can be a digitally operating integrator, for example a discrete time integrator. The discrete time integrator can also be implemented as an accumulator. Alternatively, a digital gain module can be utilized. The integrator shapes the time signal to close the control loop and allows to set the offset of the comparator. The offset of the comparator can be set in various ways known to the skilled person, for example by a reference input of the comparator or by an auxiliary terminal of the comparator which allows to set the offset.

[0016] The comparator can comprise a first input terminal to be connected to the sampling capacitor and to an amplification or feedback capacitor. A second input terminal of the comparator can have the function of a reference input connectable to a reference potential, for example to a ground potential. The first input terminal of the comparator can be a negative input terminal and the second input terminal can be a positive input terminal of the comparator. Also other configurations are useful, in which the first input terminal is a positive input and the second input terminal is a negative input. The controller operates a switch, through which a discharge and a charge of the sampling capacitor takes place. The controller can be configured such that the sampling capacitor is discharged until the comparator detects a virtual ground condition and the sampling capacitor is charged until the comparator detects another virtual ground condition.

[0017] According to an embodiment, the comparator can comprise a preamplifier stage at the input side of the comparator, which allows to set an offset by adding a current dependent on a signal provided from the closed loop control circuit. The preamplifier stage of the comparator can be a differential preamplifier with first and second branches. The digital to analog converter can be controlled in response to the determined comparator delay, since it is controlled by the digital signal output from the integrator. The digital to analog converter generates a current dependent on a signal provided by the closed loop control circuit, which is applied or added to one of the branches of the differential preamplifier stage of the comparator. One of the branches can be adjusted by the digital to analog converter by a negative feedback signal and the other branch can be adjusted by another digital to analog converter by a positive feedback signal. Various possibilities can be considered for the digital to analog converter for generating a current in response to a digital signal, for example from the digital signal output of the integrator.

[0018] A time to digital converter (TDC) can comprise a chain of delay circuits. The chain can have an input for receiving a start signal propagating through the stages of the chain of delay circuits. The start signal can represent the start of the charging of the sampling capacitor. Pulses entering the chain propagate through the chain and the position of the pulse in the chain when the virtual ground condition is met is read out and encoded to generate a digital output signal of the TDC. The virtual ground condition is communicated to the TDC by a corresponding stop pulse. The output signal of the TDC represents the charging time of the sampling capacitor, which is a measure for the delay of the comparator.

[0019] In one embodiment, one or more or all of the delay stages of the delay chain can comprise a current starved inverter, wherein a current source transistor is connected between the CMOS inverter and the power supply potential terminal. The current through the inverter in the transition switching phase of the inverter is limited by the current source transistor, such that the transition switching operation is delayed and the inverter utilizes a defined delay. Another inverter is connected downstream of the current starved inverter to shape the output signal and to adjust the polarity. The current source transistor of the current starved inverter can be part of a current mirror supplied with a bias current to limit the current of the current starved inverter to the power supply potential rail.

[0020] According to yet another embodiment, the closed loop control circuit can be implemented as an analog control loop. In this regard, the closed loop control circuit can comprise a capacitor that charges in dependence of the delay of the comparator. The charging of this capacitor can be implemented in parallel and simultaneously to the charging of the sampling capacitor, which is indicative of the delay of the comparator. The signal determined by the capacitor from the closed control loop can be shaped and forwarded to the comparator to set its offset.

[0021] The analog closed loop control circuit can comprise a subtractor to subtract a reference signal from the signal dependent on the delay. An integrator connected downstream of the subtractor can integrate the output signal from the subtractor and forward the integrated signal to the input terminal of the comparator to generate the offset of the comparator. The offset can be generated since the output of the integrator is connected to the reference input of the comparator or an auxiliary terminal of the integrator to set the comparator offset. Instead of an integrator, an amplifier can be used. The analog comparator delay compensation control loop involves active circuit elements, e.g. the subtractor. Despite the fact that active circuit elements can be subject to PVT variations, the dynamic operation of the control loop can compensate for the comparator delay.

[0022] The switched capacitor amplifier can be implemented in a differential configuration. In the differential configuration, a further sampling capacitor can be connected by switches to a further input terminal of the comparator and a further amplification capacitor can be connected to the further input of the comparator to generate a symmetric circuit shape that allows the differential operation of the circuit. Charging and discharging current sources are connected between the amplification capacitors to allow the charging and discharging of the sampling capacitors. Instead of using a corresponding sampling capacitor connected to each of the input terminals of the comparator, one sampling can be differentially connected between the input terminals of the comparator.

[0023] The switched capacitor amplifier as described above can be used in a pipelined analog-to-digital converter (ADC) to amplify a residual signal from a preceding stage to a full strength signal to be forwarded to a following stage. The pipelined ADC can comprise at least two or more converter stages. The converter stages are connected in series to each other. At least one or more of the converter stages comprises a terminal for an input signal for an analog signal to be converted, an analog-to-digital converter connected to the input terminal, and a digital-to-analog converter connected downstream of the analog-to-digital converter. A subtractor implements a subtraction between the analog input signal and an analog reconversion signal from the DAC. The switched capacitor amplifier is connected to the output terminal of the subtractor to amplify the residual signal provided by the subtractor. The output signal of the amplifier is forwarded to the input terminal of the next stage. The next stage can be another stage with the same structure as described above or the final stage of the pipelined ADC comprising a single ADC.

[0024] In a pipelined ADC, the switched-capacitor amplifier used to amplify the residual signal provides the speed and power bottleneck and is critical for the accuracy of the conversion. Using a switched-capacitor amplifier according to the principles of the present disclosure improves the speed of operation of the ADC by minimizing the delay by means of offset compensation. The offset compensation is implemented in a closed control loop, making it PVT robust. The ratio of the capacitances between the amplification and sampling capacitors determines the amplification factor. This ratio of capacitances can be easily reproduced, making it ensure accuracy. Furthermore, it is scalable, making the amplifier design reusable in other manufacturing processes and other technology applications.

[0025] The analog-to-digital converter in one or more of the converter stages can be a successive approximation register (SAR) ADC. Each of the SAR ADCs includes a plurality of capacitors to convert the most significant bits in the preceding stage and a plurality of least significant bits in the one or more stages that follow. The switched-capacitor amplifier according to the principles of the present disclosure is connected between the output of the preceding stage and the input of the stage that follows, thereby amplifying the residual signal provided by the preceding stage. In the SAR ADC concept, the comparator of the residual amplifier can be used in multiple functions, including comparator-based switched-capacitor amplification of the residual signal, and as the comparator in the SAR algorithm, since both operations are implemented at different times.

[0026] According to one embodiment of the pipelined ADC, the time-to-digital converter of the digital closed-loop control circuit of the switched-capacitor amplifier can also be used to determine the time at which the sampling capacitor is discharged. This time is indicative of the range of the analog signal, so that the TDC output signal can be forwarded to the following converter stage to set the zoom range of the next converter stage. Specifically, the TDC detects the time during the discharge of the sampling capacitor until a virtual ground condition is detected, which includes the comparator delay. The TDC output signal is forwarded to the next stage connected downstream to preset at least a subset of the capacitors in the next stage according to the determined discharge time, which is the output signal of the TDC. The effect of presetting the most significant capacitors of the next stage is to set the zoom range for the residual conversion implemented by the next stage. The TDC in the digital closed-loop control circuit can thereby be reused to enhance the conversion speed in the pipelined ADC concept.

[0027] According to yet another embodiment, the accuracy of the pipelined ADC can be enhanced by correlating the reference signals to each other. According to the SAR concept, the capacitors of the SAR ADC are alternately provided with a reference voltage potential and the analog input signal to be sampled. A circuit can be used to correlate this reference voltage potential to the charging and amplification circuit in the switched-capacitor amplifier. The correlation circuit can generate a reference current from the reference voltage potential, and a current mirror circuit can be used to generate the charging and discharging circuit for the switched-capacitor amplifier from the reference current.

[0028] In one embodiment, the corresponding circuit can include a transistor, an ohmic resistor connected between a source terminal and a ground terminal of the transistor, and a control loop including an error amplifier. A drain terminal of the transistor absorbs a reference current, from which a charging current and a discharging current are derived. The error amplifier takes a signal from the resistor and compares it to a reference voltage that is also applied to the SAR converter capacitor. The error amplifier provides a regulation such that the reference current is directly related to the reference voltage. The ohmic resistor is substantially temperature invariant, such that the relation between the reference voltage and the reference current is temperature stable. The error amplifier can be offset compensated to further improve the relation accuracy. In the case of a scaled reference current generation circuit, it is generally possible to scale the ohmic resistor predictably to maintain a proper relation between the reference voltage and the reference current.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide a framework for understanding the nature and character of the claims. The drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s) and, together with the description, serve to explain principles and operation of the various embodiments. Like reference numerals in different drawings denote like elements. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A comparator-based switched-capacitor amplifier using a digital closed-loop control circuit according to the principles of the present disclosure is shown;

[0031] Figure 2 A waveform diagram of signals and voltages from the amplifier of Figure 1 ;

[0032] Figure 3 Circuitry for setting the offset of the comparator of the amplifier of Figure 1 ;

[0033] Figure 4 A block diagram of the time-to-digital converter of the amplifier of Figure 1 and a detailed circuit diagram of one of the delay stages is shown;

[0034] Figure 5 Another embodiment of a comparator-based switched-capacitor amplifier using an analog closed-loop control circuit according to the principles of the present disclosure is shown;

[0035] Figure 6 A block diagram of a pipeline analog-to-digital converter is shown;

[0036] Figure 7 A block diagram of a pipeline analog-to-digital converter is shown; Figure 6part of a pipelined analog-to-digital converter, showing a comparator-based switched-capacitor amplifier and related circuit elements in detail;

[0037] Figure 8 shows Figure 1 one embodiment of a comparator-based switched-capacitor amplifier of

[0038] Figure 9 shows Figure 8 waveform diagrams of signals and voltages from the amplifier of

[0039] Figure 10 shows a schematic circuit diagram of the principle of a SAR ADC that allows setting a zoom range;

[0040] Figure 11 shows the concept of utilizing a SAR zoom range in the circuit of Figure 10

[0041] Figure 12

[0042] Figure 13 shows a detailed diagram of a pipelined SAR ADC using a zoom range;

[0043] Figure 14 shows

[0044] Figure 15 shows a comparator-based switched-capacitor amplifier according to the principles of the present disclosure using a digital closed-loop control circuit in a differential configuration; and

[0045] Figure 16 shows a single-sampling capacitor to be used in a differential configuration of a comparator-based switched-capacitor amplifier. DETAILED DESCRIPTION

[0046] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. The disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the disclosure to skilled persons. The drawings are not necessarily to scale, but are set forth to illustrate the disclosure.

[0047] Figure 1 ​​A block diagram of a comparator-based switched-capacitor amplifier is shown. The amplifier comprises a comparator 110 as central component, the input terminals of which are coupled to a sampling capacitor 120 and an amplification capacitor 130. In particular, a terminal of the sampling capacitor 120 is switchably connected to an input terminal of the comparator 110. A switch 122 is connected between the terminal of the sampling capacitor 120 and the input terminal of the sampling capacitor 120. A terminal of the amplification capacitor 130 is connected to an input terminal of the comparator 110. The terminal of the amplification capacitor 130 is also connected to the switch 122, which is connected to the terminal of the sampling capacitor 120. An output terminal of the comparator 110 is coupled to a controller 140, which generates control signals El and E2 for operating switches 141, 142. Switch 141 is connected in series with a current source 135, which is connected to a positive supply potential VDD. Switch 142 is connected in series with a current source 136, which is connected to a ground potential GND. The current sources 135, 136 and the corresponding switches 141, 142 are connected to the terminal of the amplification capacitor 130. A load capacitor 160 is connected to a node between the current sources 135, 136 and the amplification capacitor 130. The load capacitor represents a capacitor load CL connected to the output of the amplifier.

[0048] A number of switches are provided for operating the amplifier and implementing the switched-capacitor operation. The terminal of the sampling capacitor 120 can be alternately connected to an input terminal 125, to which an input voltage vin to be amplified is supplied, and to a ground potential, by means of corresponding switches 121 and 123, respectively. The other terminal of the sampling capacitor 120 can be alternately connected to one of the input terminals of the comparator 110 and to a ground potential, by means of corresponding switches 122 and 124, respectively. The switches are operated by non-overlapping clock signals φl, φ2. In Figure 1 In the circuit shown, the negative input terminal "-" of the comparator 110 is connected to the sampling and amplification capacitors 120, 130, while the positive input terminal "+" is connected to the ground potential GND. It is also possible to reverse the polarity and connect the positive input to the capacitors 120, 130 and the negative input to the ground potential. Figure 1 The amplifier shown has a single-ended configuration, in which the input signal is provided by the sampling capacitor 120, which is connected in a single-ended manner.

[0049] During operation, the sampling capacitor 120 is loaded with the input voltage vin and the amplification capacitor 130 and the load capacitor 160 are short-circuited and discharged during the active phase of the signal φl. Then, during the active phase of the signal φ2, the sampling capacitor is disconnected from the input terminal 125 and connected between the ground potential and the input terminal of the comparator 110. The first control signal El is activated to close the switch 141 and discharge the sampling capacitor 120 through the amplification capacitor 130. As in the case of the amplifier shown in Fig. 1, the second control signal E2 is activated to close the switch 142 and discharge the load capacitor 160 through the current source 136. Figure 2As shown in the waveform diagram, by supplying a current icoarse from current source 135 until the comparator detects the dummy ground condition 210, the voltage vn at the negative input node "-" of comparator 110 rises. During the dummy ground condition, the input voltage vn at the negative input of comparator 110 is equal to the voltage at the positive input of comparator 110, which is as follows: Figure 2 The ground potential GND is shown at point 210. Charge is removed from the sampling capacitor 120 by the current icoarse from the current source 135 until the comparator detects a virtual ground vn close to GND. Because the discharge current flows through the feedback capacitor 130, the voltage across the sampling capacitor 120 appears to be amplified by the capacitance ratio Csample / Camp of capacitors 130 and 120. Therefore, the gain ideally depends only on the capacitance ratio. However, in practice, comparator delay causes an overshoot 211 of the input voltage vn at the negative input terminal of comparator 110.

[0050] Then, following the first coarse discharge phase of signal E1 is a second fine charge phase generated by the second control signal E2 from controller 140. This second fine charge phase uses a lower charging current ifine, which results in another dummy ground condition 220 for the input voltage vn at the negative input of comparator 110. However, due to the relatively low current, another small overshoot may exist at the dummy ground point 220, which is negligible. The second fine current phase, when activated by the second control signal E2, can consume a significant amount of time. Figure 2 As shown, the duration t2 of the fine charging phase is approximately three times the duration t1 of the coarse discharging phase. Signals E1 and E2 are supplied by the controller 140 in response to the voltage Vc at the output terminal of the comparator 110. During the discharging phase, switch 141 is closed, supplying current icoarse from the discharging current source 135, while switch 142 is open. During the fine charging phase, switch 142 is closed, supplying current ifine through current source 136, while switch 141 is open.

[0051] According to the principles of this disclosure, a closed-loop control circuit is configured to compensate for overshoot and thereby shorten the fine-charging phase of the sampling capacitor. The closed-loop control circuit is connected between the output 141 of the controller 140 and the input terminal 115 of the comparator 110. The closed-loop control circuit generates a signal Doffset for controlling the offset of the comparator 110. The control loop runs repeatedly, making the overshoot as close to zero as possible. Figure 2At the region 230 shown in the middle, it can be seen that the overshoot is much smaller at the next execution of the charge / boost phase. Correspondingly, the signal Doffset supplied to the input 115 of the comparator 110 decreases with increasing run time. In steady state, the charge phase with the fine circuit ifine is much shorter, accelerating the boost operation. The closed loop control circuit operates dynamically and adjusts the offset of the comparator 110 each time the boost circuit is started Figure 1 Correspondingly, by the closed loop control circuit, any intrinsic variations of the circuit caused by variations of the manufacturing process of the switched capacitor boost circuit or variations caused by variations of the supply voltage VDD or variations generated by other environmental conditions, such as temperature (so-called PVT variations) are reduced to as close to zero as possible.

[0052] The closed loop control circuit comprises a time-to-digital converter (TDC) 151 which measures the time t2 of the control signal E2, which time characterizes the fine charge phase of the fine charge current ifine supplied to the current source 136 through the closing phase of the switch 142. The time-to-digital converter 151 generates an output signal DTDC which is a digital representation of this time period. This time period corresponds to the delay of the comparator 110, which is the propagation time from the detection of the virtual ground condition at its input to the setting of the corresponding output signal Vc at the comparator output. Downstream of the TDC 151, an integrator 153 is connected, which integrates the digital signal DTDC to the offset control signal Doffset to be supplied to the terminal 115 of the comparator 110. The integrator 153 can be a digital integrator. Alternatively, also a digital gain block can be utilized instead of the digital integrator 153. Moreover, a subtractor 152 can be provided between the TDC 151 and the integrator 153 to subtract a constant signal Dc at the terminal 155 from the digital time information DTDC. The digital signal Dc is set to slightly above zero to allow for positive feedback when the TDC output signal DTDC is zero. This is for the positive initial comparator offset, which occurs when the fine phase is disabled immediately after start-up. Thus, allowing for negative feedback values helps to get out of this dead zone. The subtractor 152 and the digital preset signal Dc allow for negative feedback values for a bidirectional comparator offset adjustment. The bidirectional control loop is thus stabilized. It is thus guaranteed that the output signal of the TDC 151 is always at least zero or greater than zero. The digital signal Dc is injected into the loop to allow for positive feedback values. Such a situation can be made when the TDC output is zero. Once the loop has converged, the digital signal Dc is set to zero. This leaves an overshoot of zero, allowing for a linear control loop in which the integral linear signal is integrated, where the control loop is stabilized and provides zero error.

[0053] Figure 3One embodiment of the comparator 110 is shown, which shows in detail the preamplifier stage and a digital-to-analog converter (DAC) for each of the branches of the differential preamplifier for setting the offset of the preamplifier. The DAC is controlled by a signal Doffset that depends on the time signal DTDC provided by the TDC 151, converts the signal into a corresponding current that is applied to one of the branches. The applied current introduces an asymmetry in the differential preamplifier stage, resulting in an offset. Closing the control loop results in such an offset that approximately compensates for the delay of the comparator.

[0054] Figure 3 The preamplifier stage 310 is shown in more detail, which has a negative branch 311 and a positive branch 312 of the differential preamplifier stage. A digital-to-analog converter 320 generates a current at a terminal 321 that is added to the current that passes through the branch 311. The DAC 320 receives a negative value of the signal Doffset, while a corresponding DAC 330 adds a corresponding current to the positive branch 312 when the signal Doffset has a positive value. Numerous possibilities of current generating DACs are conceivable. Figure 3 One example of a DAC is shown that comprises a sequence of binary weighted currents IU,2IU,...,2 M-1 The switches are connected in series with each of the current sources, where each switch is controlled by a digital value Doffset such that it contributes a binary weighted current at the output 321 of the DAC 320 that depends on the signal that controls the switch. The DAC 320 is used for negative digital control values, while the DAC 330 has a corresponding structure where the switches are controlled by positive digital control values. The digital code Doffset programs the offset of the comparator in discrete steps. Since the comparator delay depends on the input slope, the offset compensation is performed based on the results from the coarse current phase when the sampling capacitor discharges. In the fine current phase when the sampling capacitor charges, the required offset is different, but the influence of the offset and the delay is negligible due to the slow charging.

[0055] Figure 4 One embodiment of the time-to-digital converter 151 is shown. In response to a (rising) edge of the control signal E2, the TDC receives a start pulse TDCstart that is generated in response to a switch of the output signal Vc of the comparator 110 that is generated in response to a virtual ground detection of the comparator 110. The pulse TDCstart is generated in response to the start of the fine charging phase of the sampling capacitor. The pulse TDCstart can be formed by a pulse forming circuit 145 that receives the control signal E2 that forms a pulse when the signal E2 has a rising or falling edge as shown. The pulse TDCstart passes through a number of, for example 2 Figure 1 M ​The delay chain 410 of the series connection of the delay circuits 420, 421, 422 propagates the start pulse. Each delay circuit applies the delay of TD to the propagating pulse. A pulse of the stop signal TDCstop triggers an encoder 440 connected to the output of each of the delay circuits 420,..., 422 to freeze the current state of the start pulse propagating in the delay chain. The encoder 440 provides a digital output signal DTDC to be forwarded into the closed loop control circuit. The stop signal pulse TDCstop is generated in response to a further (falling) edge of the control signal E2, which is generated in response to a switch of the output signal Vc of the comparator 110, which is generated in response to a further virtual ground detection of the comparator 110. The pulse TDCstop is generated in response to the stop of the fine charging phase of the sampling capacitor. The pulse TDCstop is generated in response to the stop of the fine charging phase of the sampling capacitor. The start pulse TDCsart propagates through the chain of delay circuits of the time-to-digital converter. When the stop pulse TDCstop is received, the output signal DTDC is generated. The output signal DTDC determines the current switching state of the chain of delay circuits given by the propagating state of the start pulse through the chain of delay circuits, which indicates the time length of the stop pulse propagating through the chain of delay circuits. The output signal DTDC indicates the state of the chain of delay circuits at the time of receiving the stop pulse. The output signal DTDC is a measure of the time length of the fine charging phase and indicates the time length of the fine charging phase, thereby a measure of the delay of the comparator.

[0056] In the present embodiment, Figure 4 The time-to-digital converter shown uses the start and stop pulses TDCstart, TDCstop related to the switching events of the comparator 110, which are indicated by the rising and falling edges of the second control signal E2 determining the fine charging phase of the sampling capacitor. This time period t2 indicates and is proportional to the switching delay of the comparator 110.

[0057] In Figure 4In the right part of the figure, one or more or all embodiments of the delay circuits 420, 421, 422 of the delay chain 410 are shown. The delay circuits comprise a current starved inverter cell, which comprises a first inverter 431 comprising current limiting transistors on both sides of the supply voltage terminal. On the ground potential GND side, a current mirror 432 is connected between the NMOS transistor 433 of the first inverter and the ground potential terminal, for example. The current mirror is controlled by a current Ibias, which is mirrored into the supply path of the first inverter 431. In the path to the supply potential VDD of the inverter 431, a corresponding current mirror is provided, which limits the current to Ibias. When the first inverter 431 is switched from high to low or from low to high, the switching current is limited by the current Ibias, resulting in a delay of the switching operation. Downstream of the first inverter 431, a second inverter 441 is connected, in order to generate a sharp edge and to generate the appropriate polarity of the propagating pulse.

[0058] The delay circuits 420, 421, 422 of the delay chain 410 can be subject to significant PVT variations, since they are implemented as dynamic circuits. However, for the present topology of the closed loop control circuit, this is irrelevant, since the closed loop configuration drives the output signal DTDC of the time-to-digital converter to zero, so that the operation of the controller does not depend on precise absolute accuracy. It is sufficient that the effective step size of the delay chain remains within the stable range of the control loop, which can be achieved by designing the delay chain and the control loop with sufficient margins. Subject to the PVT distribution of the time-to-digital converter is the effective loop convergence time, which only influences the initial period after the circuit is powered on. Once the closed control loop has stabilized, the actual comparator-based amplifier performance is independent of the characteristics of the time-to-digital converter.

[0059] Figure 1 The comparator-based switched-capacitor amplifier and its main components shown in Figure 3 and 4 The digital closed loop control shown in the figures only requires dynamic power consumption, so that the power consumption in steady state is relatively low. The circuits operate completely digitally, so that they can be scaled to smaller process feature sizes and smaller process nodes. The closed loop control concept dynamically adjusts the comparator delay to zero or almost zero. The control loop operates completely digitally, so that no active gain-dependent elements are included, which allows the circuits to be easily scaled. The same circuit design can be used in manufacturing processes with reduced feature sizes, in which the correct operation of the circuit is guaranteed.

[0060] Reference is now made to Figure 5 , which shows another closed loop control solution for compensating the comparator delay of a comparator-based switched-capacitor amplifier, which is an alternative to the solution shown in Figure 1 .Figure 5 The circuit shown includes a delay capacitor 521 that is charged by a current source 522 when the second control signal E2 is activated. Information from the voltage signal VD at capacitor 521 is forwarded to the input of comparator 510 to control its offset. A subtractor 523 is provided at its positive input to receive the voltage signal VD. A fixed voltage potential Vc is supplied to the negative input of subtractor 523. The function of voltage Vc corresponds to… Figure 1 The function of the digital preset signal Dc is shown at terminal 155. An integrator 524 is connected between the output of subtractor 523 and the positive input of comparator 510. Subtractor 523 and integrator 524 are analog devices that may include active components, such that these devices may be subject to PVT variations. However, offset control of comparator 510 is performed in a dynamic closed-loop control system, such that, in steady state, the compensated switching delay of the comparator is independent of PVT variations.

[0061] The offset control of comparators 110 and 510 can be implemented in different ways. The offset setting signal can be through the positive and negative input terminals of the comparator or through an auxiliary input that causes the offset to be set. The above has been combined with... Figure 3 An example of setting an offset in the numerical case is explained.

[0062] Such as combination Figure 1 and 5 The switched-capacitor amplifier shown can be combined with a pipelined analog-to-digital converter (ADC) as a residual amplifier. Figure 6 A general example of a pipelined ADC is shown. The pipelined ADC includes multiple converter stages 610, 620, 630 connected in series. Each stage has a substantially identical current structure as described for stage 610. Stage 610 receives the analog input signal vin at terminal 616. A sample-and-hold (S&H) stage can be useful. The input signal is stored on a sampling capacitor Csample, and an analog-to-digital converter 611 converts, for example, a subset of N bits into the digital domain. The N converted bits are forwarded to a combiner stage 640 shared by all stages. The digital bits from ADC 611 are reconverted into the analog domain by a digital-to-analog converter 612. At a subtractor 613, the reconverted analog signal is subtracted from the analog input signal vin. Accordingly, subtractor 613 is connected to the output and input terminals 616 of DAC 612. The output of subtractor 613 is connected to a capacitor 615 storing the residual charge of this stage. The charge is converted to a full signal swing by a residual amplifier 614, which can be one of the amplifier embodiments described above, such as... Figure 1 and 5 The diagram shows a comparator-based switched-capacitor amplifier that includes a closed-loop control circuit for compensating for comparator delay.

[0063] The pipelined topology requires amplification of the residue signal of the previous stage, e.g. 610, to a full strength signal, which is the input signal of the next stage, e.g. 620. Stage 620 performs a similar conversion of another subset of M bits as described in connection with stage 610. All additional outputs of stages 610, 620,..., 630 are forwarded to a combiner 640, which generates the complete converted digital signal. While the previous sample of the input signal is converted in the next stage, the previous stage can convert another sample of the input signal, such that a pipelined operation occurs. In such a pipelined ADC, the residue amplifier, e.g. amplifier 614, is a bottleneck for power consumption and conversion speed. According to the principles explained in connection with Figure 1 and 5 The residue amplifier according to the principles of the present disclosure provides linear settling, while the comparator delay does not affect accuracy and PVT robustness. Using a residue amplifier according to the principles of the present disclosure speeds up the overall conversion time in a pipelined ADC, without affecting PVT tolerance and accuracy.

[0064] Figure 7 It is shown to use a comparator-based switched-capacitor amplifier as a residue amplifier in a pipelined ADC in an ADC as shown in, e.g. Figure 6 The residue signal of the previous stage 710 is stored in a residue capacitor 711, which is used as a sampling capacitor for a comparator-based switched-capacitor amplifier 720. The sampling capacitor 711 is the sum of all DAC capacitors holding the residue charge. The output charge capacitor of amplifier 720 is the sampling capacitor 731 of the next stage 730.

[0065] One embodiment of a comparator-based switched-capacitor amplifier useful for pipelined ADC configurations is shown in Figure 8 Figure 8 A comparator-based switched-capacitor amplifier is depicted in Figure 1 which has a digital closed-loop control including a time-to-digital converter 851, which is further configured to determine the time at which the sampling capacitor 820 is to be discharged by a coarse current source icoarse during an activation phase of the first control signal E1. The discharge time includes a ramping up of the input voltage vn of the comparator 810 until a virtual ground condition 910 is achieved, which includes the comparator delay. The discharge time of the sampling capacitor 820 is indicated by the start and stop pulses TDCstart1, TDCstop1 by the TDC 851, which is further configured to determine the time at which the sampling capacitor 820 is to be discharged by the fine current source ifine during a deactivation phase of the first control signal E1. The discharge time includes a ramping down of the input voltage vn of the comparator 810 until a virtual ground condition 920 is achieved, which includes the comparator delay. The discharge time of the sampling capacitor 820 is indicated by the start and stop pulses TDCstart2, TDCstop2 by the TDC 851. Figure 9 ​). The OR gate 830 generates an OR operation between the control signals E1, E2, so that both signals E1, E2 are forwarded to the TDC 851. The output signal TDCout of the TDC 851 is used to set the zoom range of a next stage, e.g. 620, in the pipelined ADC, wherein the TDCout value is taken from a previous stage, e.g. stage 610. Since the sampling capacitor 820 is discharged by the constant current icoarse of the coarse current source 835, the total discharge time depends on the signal. Accordingly, the discharge time contains information about the residual voltage. The discharge time measured by the TDC 851 is reused to convert the discharge time into a number. Since the discharge time depends on the signal, it can be used in a later converter stage of the pipelined ADC to set the zoom range in combination with Figure 10 and 11 the zoom range explained in more detail.

[0066] Figure 10 One embodiment of an analog-to-digital converter, e.g. ADC 611, in one of the converter stages of the pipelined ADC is shown. Figure 10 A successive approximation register (SAR) ADC 1001 performing an analog-to-digital conversion according to a successive approximation algorithm is shown. The ADC comprises a plurality of capacitors, e.g. capacitors 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017. The capacitors 1010,..., 1017 can have a binary weighting, although other weighting principles are feasible. The capacitors are pre-charged with a reference voltage vref, which are then connected to the voltage vin to be sampled. The terminal 1041 provides the reference voltage vref, and the terminal 1042 provides the input voltage vin. The comparator 1030 makes the decision for the successive approximation algorithm performed by the SAR controller 1060.

[0067] According to the principles of the present disclosure, the zoom range selector 1040 is provided with the output signal TDCout from the TDC 851 shown. The signal TDCout characterizes the discharge time of the discharge operation of the sampling capacitor 820 by the coarse current source 835 as explained in combination with Figure 8 Figure 8 and 9 The zoom range selector 1040 presets the charge into one or more of the zoom capacitors 1014, 1015, 1016, 1017. In the example shown, four zoom bits, bit 4[1 :0], bit 3[1 :0], are used. Figure 10

[0068] Figure 11 ​​The ranges associated with the four zoom bits are shown. In this example, seven zoom ranges are distinguished using seven combinations of zoom bits. Using zoom bits and setting zoom ranges allows the output signal TDCout of the TDC 851 to provide an estimate of the range above and below. This provides an error tolerance without requiring more conversion cycles. Using zoom bits is especially useful when the ADC in the pipeline ADC has a SAR construction. The TDC range distribution for the zoom bits generated from the output of the time-to-digital converter is subject to tolerances. To achieve the required tolerances, the current of the current sources used in the amplifier circuit should be related to the reference voltage used for the SAR sampling process. The circuit 1050 used to achieve the necessary tolerance between the reference voltage vref provided at terminal 1041 to the sampling capacitor and the input voltage vin to be sampled at terminal 1042 alternately should be related to the coarse and fine currents icoarse, ifine for the charging and discharging current sources 835, 836.

[0069] Figure 12 The association circuit 1050 that allows the association between the voltage vref and the currents icoarse, ifine is shown. The circuit comprises a MOS transistor 1230 whose source terminal is connected to the ground potential GND through an ohmic resistor 1240. The voltage at the resistor 1240 is fed back to an error amplifier 1210 that determines the difference between the voltage at the resistor 1240 and the reference voltage vref from terminal 1041. The output of the error amplifier 1210 controls the gate terminal of the transistor 1230. The reference current iref at the drain terminal of the MOS transistor 1230 is closely related to the reference voltage vref. The currents to be used in the switched capacitor amplifier, e.g. the coarse and fine current sources 135, 136, 835, 836 are generated from the reference current iref by corresponding current mirrors 1251, 1252. The circuit 1050 uses an ohmic resistor 1240 that is subject to PVT variations. However, the design and manufacturing of ohmic resistors is a well-controlled process. When scaling the circuit to smaller feature sizes, it is also easy to redesign the resistor 1240, if needed, in a predictable way, such that Figure 12 The circuit shown is also scalable in a predictable way, although it comprises active components and PVT-dependent components, e.g. the resistor 1240.

[0070] Figures 13 and 14 show a two-stage pipeline analog-to-digital converter using a comparator-based switched capacitor amplifier as a residue amplifier according to the principles of the present disclosure. Figure 13 shows the circuit structure, Figure 14The waveforms of the relevant signals of the current of Figure 13 are shown. The AC uses a SAR architecture to generate a 12-bit [bitO...bitll] output signal. The first stage 1310 converts the five most significant bits (MSBs), while the second stage 1330 converts the amplified residue from the first stage with the seven least significant bits (LSBs). A residue amplifier 1320 is connected between the first and second stages 1310, 1330 and receives the output signal vn from the first stage 1310 to amplify it to full strength Vresidue to be forwarded and sampled by the subsequent stage 1330. A controller 1340 generates control signals to implement the appropriate first and second stage operations, switched capacitor operation of the amplifier, and collection of the converted digital bits.

[0071] The controller is configured to perform zoom range detection and zoom range control in conjunction with the TDC of the residue amplifier 1320 and the zoom range capacitor of the second stage 1330. The TDC of the offset control loop of the switched capacitor amplifier 1320 is reused to generate an output signal TDCout indicative of the discharge time of the sampling capacitor from the first stage 1310. The discharge time is the length of time between the start of the discharge of the sampling capacitor to the reaching of the virtual ground condition plus the comparator delay as indicated by the activation phase of the signal El between the pulses TDCstartl to TDCstopl. This TDCout value obtained by the first stage 1310 is used to set the zoom range capacitor of the second stage 1330 to represent, for example, four bits of bit5[l:0], bit6[l:0]. In a first step, the first stage 1310 can be operatively connected to the residue amplifier 1320. In a subsequent second step, the second stage 1330 can be operatively connected to the residue amplifier 1320, wherein the zoom range is set in response to the TDCout value obtained when the first stage 1310 was previously connected to the residue amplifier 1320.

[0072] FIG. 13 shows a circuit with increased operating speed because the comparator-based switched-capacitor amplifier 1320 uses closed-loop control to compensate for offset to reduce overshoot in response to comparator delay. The circuit operates entirely digitally, so it can be directly scaled to different feature sizes of CMOS fabrication processes. The circuit uses zoom bits allowed by the time-to-digital converter in the digital closed control loop for offset compensation of the comparator used for the amplifier, which enables error tolerance without more conversion cycles because it allows a range above and below the estimate obtained by the TDC's determination of discharge time. The amplifier operates entirely digitally, so it is PVT-tolerant and more robust to PVT variations. The gain of the amplifier can be set relatively accurately by the ratio of the discharge and sampling capacitors. The residual amplifier allows high speed, scalability, and PVT tolerance. Zoom range detection for the second stage of the pipelined SAR ADC allows higher resolution for the same conversion time without significant circuit overhead.

[0073] Figure 15 A differential configuration of a comparator-based switched-capacitor amplifier is shown. The current includes a first amplification capacitor 1530 connected to the negative input terminal "-" of the comparator 1510, and a second amplification capacitor 1531 connected to the positive input terminal "+" of the comparator 1510. Between the first and second amplification capacitors 1530, 1531 are connected a coarse discharge current source 1535 and a fine charge current source 1536, and corresponding switches 1541, 1542 operated by control signals El, E2 generated by a controller 1540 in response to an output signal from the comparator 1510, respectively. The current sources 1535 and 1536 generate currents with different opposite orientations and different strengths. The output signal is a differential signal between a first charge capacitor 1560 and a second charge capacitor 1561, each connected to one of the amplification capacitors. On the input side, a differential input signal Vin is provided between positive and negative input terminals 1525, 1526, each connected to a corresponding sampling capacitor 1520, 1521 through a corresponding switch. The sampling capacitors are connected to the positive and negative input terminals of the comparator through corresponding switches. Also, each terminal of the sampling capacitors is connected to a ground potential terminal through corresponding switches operated alternately. Control signals φl, φ2 cause the sampling capacitors to be charged by the differential input signal during the active phase of the switch control signal φl, and cause the input terminals connected to the comparator 1510 and charge transfer during the active phase of the control signal φ2.

[0074] Figure 15 The closed-loop control circuit 1550 of the differential amplifier circuit of Figure 1the single-ended case of the current of the differential circuit. Also, Figure 2 The time diagram of the single-ended amplifier circuit shown above applies correspondingly to the operation of the differential circuit. Figure 15

[0075] Figure 16 An input part of a differential comparator-based switched-capacitor amplifier is shown, in which a single sampling capacitor 1620 is used instead of two sampling capacitors 1520, 1521 in the current of the differential circuit, for example. Figure 15 Between the positive and negative input terminals of the comparator 1510, the sampling capacitor 1620 is connected through corresponding switches. Further switches are provided that connect the terminals of the sampling capacitor 1620 to the terminals 1525, 1526 that connect the differential input voltage Vin. The switches that connect the sampling capacitor 1620 to the terminals of the input voltage Vin or to the input terminals of the comparator are operated alternately by the control signals φ1, φ2.

[0076] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure as set forth in the appended claims. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments incorporating the spirit and substance of the disclosure can occur to those skilled in the art, the disclosure should be construed to encompass all such variations as being within the scope of the following claims.​

Claims

1. A switched-capacitor amplifier comprising: - a comparator (110) having input terminals and an output terminal; - a sampling capacitor (120) coupled to one of said input terminals; - an amplification capacitor (130) coupled to said one of said input terminals, to a discharge current source (135) through a first switch (141) and to a charge current source (136) through a second switch (142); - a controller (140) configured to operate said first and second switches (141, 142) as a function of an output signal (Vc) of said comparator (110); and - a closed-loop control circuit (151, 152, 153) configured to determine a delay of said comparator (110) and to control an offset of said comparator in response to said determined delay, - wherein said closed-loop control circuit (151, 152, 153) comprises a time-to-digital converter (151) for determining a signal (DTDC) that depends proportionally on said delay of said comparator (110), wherein said signal is fed back to said comparator for setting said offset of said comparator, - wherein said closed-loop control circuit further comprises an integrator (153) connected between said time-to-digital converter (151) and comparator (110).

2. The switched-capacitor amplifier of claim 1, wherein, said closed-loop control circuit further comprises a terminal (155) for presetting a signal (Dc) to be subtracted from said signal (DTDC) that depends on said delay of said comparator.

3. The switched-capacitor amplifier of claim 2, wherein, said preset signal (Dc) to be subtracted from said signal (DTDC) that depends on said delay of said comparator is preset to zero when said closed-loop control circuit is in a converging state.

4. The switched-capacitor amplifier of claim 1, wherein, said comparator (110) comprises a further input terminal configured to be operatively supplied with a reference potential, said controller (140) is configured to cause said sampling capacitor (120) to be discharged until said comparator detects a virtual ground condition (210), and said controller is configured to cause said sampling capacitor (120) to be charged until said comparator detects a further virtual ground condition (220).

5. The switched-capacitor amplifier of claim 1, wherein, said comparator (110) comprises a differential preamplifier stage (310) and at least one digital-to-analog converter (320, 330) controlled as a function of said signal (DTDC) that depends on said delay of said comparator and converting said signal into a current signal applied to one of branches (311, 312) of said differential preamplifier stage.

6. The switched-capacitor amplifier of claim 1, wherein, said time-to-digital converter comprises a chain (410) of delay circuits (420, 421, 422) configured to operatively receive a start signal (TDCstart) in response to a start of a charging of said sampling capacitor (120).

7. The switched-capacitor amplifier of claim 4, wherein, The time-to-digital converter (151) comprises a chain (410) of delay circuits (420, 421, 422) and is configured to receive a start pulse (TDCstart) in response to a virtual ground condition (210) being detected by the comparator (110) and to receive a stop pulse (TDCstop) in response to another virtual ground condition (220) being detected by the comparator (110), wherein the time-to-digital converter (151) is further configured to let the start pulse (TDCstart) propagate through the chain of delay circuits (420, 421, 422) and to generate an output signal (DTDC) indicative of a state of the chain of delay circuits in response to receiving the stop pulse (TDCstop).

8. The switched-capacitor amplifier of claim 6 or 7, wherein, Each of the delay circuits comprises a first inverter (431) and a current source transistor connected between the first inverter (431) and a power supply potential terminal (VDD, GND), and a second inverter (441) connected downstream of the first inverter.

9. The switched-capacitor amplifier of claim 1, wherein, The closed loop control circuit comprises a capacitor (521) to be charged depending on a delay of the comparator (510) to generate a signal (VD) depending on the delay of the comparator, wherein the signal is fed back to the comparator to set an offset of the comparator (510).

10. The switched-capacitor amplifier of claim 9, wherein, The closed loop control circuit further comprises a subtractor (523) for subtracting a reference signal (Vc) from the signal (VD) depending on the delay of the comparator, and an integrator (524) connected downstream of the subtractor, wherein an output of the integrator is connected to a further input terminal of the comparator (510) to generate the offset of the comparator.

11. The switched-capacitor amplifier of claim 1, further comprising a further amplification capacitor (1531) coupled to the other one of the input terminals of the comparator (1510), wherein, The discharge current source (1535) and the charge current source (1536) are connected between the amplification capacitor (1530) and the further amplification capacitor (1531), and wherein the sampling capacitor (1520) or a further sampling capacitor (1521) is coupled to the other one of the input terminals of the comparator (1510).

12. A pipeline analog-to-digital converter comprising at least two converter stages (610, 620, 630) connected in series to each other, at least one of the converter stages comprising: - an input terminal (616) for an analog input signal (Vin); - an analog-to-digital converter (611) connected to the input terminal and a digital-to-analog converter (612) connected downstream of the analog-to-digital converter (611); - a subtractor (613) connected to the input terminal of the converter stage and to an output terminal of the digital-to-analog converter (612); - a switched capacitor amplifier (614) according to claim 1 connected to an output terminal of the subtractor (613) to amplify a residual signal provided by the output terminal of the subtractor.

13. The pipelined analog-to-digital converter of claim 12, wherein, The analog-to-digital converters of the at least two converter stages (1001, 1310, 1330) are configured to perform successive approximation digital-to-analog conversion, and each analog-to-digital converter comprises a plurality of capacitors (1010,..., 1017), wherein a first one of the at least two converter stages (1310) is configured to determine a plurality of most significant bits, and another one of the at least two converter stages (1001, 1330) is configured to determine a plurality of least significant bits, the switched-capacitor amplifier (1320) is configured to amplify a residue signal (Vn) of the first one of the at least two converter stages (1310) and to forward the amplified residue signal (Vresidue) to the other one of the at least two converter stages (1001, 1330).

14. The pipelined analog-to-digital converter of claim 13, wherein, The time-to-digital converter (851) of the switched-capacitor amplifier (1320) is configured to determine a signal (TDCout) depending on a time of discharging the sampling capacitor (820) when operatively connected to the first one of the at least two converter stages (1310) until the comparator detects a virtual ground condition (910), wherein a subset of the plurality of capacitors (1014,..., 1017, 1330) of the other one of the at least two converter stages (1330) is configured to be pre-charged with a charge in response to the signal (TDCout) depending on the time of discharging the sampling capacitor.

15. The pipelined analog-to-digital converter of claim 13, wherein, Each of the analog-to-digital converters (1001, 1310, 1330) of the at least two converter stages further comprises: - a terminal (1041) for a reference voltage potential (Vref) and a terminal (1042) for an input voltage potential (Vin) to be sampled, the terminals (1041, 1042) being configured to be alternately coupled to one or more of the plurality of capacitors (1010,..., 1017); - a circuit (1050) for generating a reference current (Iref) from the reference voltage (Vref); and - a circuit (1251) for generating a current (icoarse) of the charging current source from the reference current (Iref) and a circuit (1252) for generating a current (ifine) of the discharging current source from the reference current (Iref).

16. The pipelined analog-to-digital converter of claim 15, wherein, The circuit (1050) for generating a reference current comprises a transistor (1230) with a source terminal connected to a terminal for a ground potential (GND) through a resistor (1240) and a drain terminal providing the reference current (Iref), and an error amplifier (1210) connected to a terminal for a reference voltage potential (Vref) and the resistor (1240), wherein the error amplifier (1210) controls the transistor (1230).

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