Firmware Loading Method Supporting Multiple NAND Particles and Solid State Drive Thereof

Abstract

The present invention provides a firmware loading method supporting multiple NAND particles and a solid state hard disk thereof, the method comprising: when the chip of the solid state hard disk is powered on, the BootRom code solidified on the chip is run; the Timing parameters of each different NANDFlash particle contained in the solid state hard disk are read from the Efuse module to configure the Timing parameters of the NANDFlash controller; S40, after the Timing parameter configuration of the NANDFlash controller is completed, the solid state hard disk performs firmware loading and operation. The beneficial effect of the present invention is that when the chip of the solid state hard disk is powered on, the BootRom startup first reads the pre-burned Timing parameters from the Efuse module, and for different NANDFlash particles, the Timing parameters burned into the Efuse module are also different, so that the redundancy of BootRom for different NANDFlash particles can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of firmware loading of solid state drives, and in particular to a firmware loading method supporting multiple NAND particles and a solid state drive thereof. Background Art

[0002] The SSD loading system is usually loaded and run by loading and running the BootRom that is solidified in the ROM space inside the SSD main control chip. NorFlash has relatively good stability. The Bootloader program stored on NorFlash is loaded and run through BootRom; then the Bootloader program loads and runs the FW firmware on NAND Flash. In order to save costs, NorFlash is usually removed, and both the Bootloader program and the FW firmware are stored on NAND Flash, so that BootRom loads and runs the Bootloader program from NAND Flash. However, different NAND Flash particles have different Timing parameter configurations, and BootRom is solidified in the ROM space and cannot be modified again, which makes BootRom unable to adapt to a variety of NAND Flash particles. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a firmware loading method supporting multiple NAND particles and a solid state hard disk thereof.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a firmware loading method supporting multiple NAND particles, comprising the steps of:

[0005] When the chip of the solid-state drive is powered on, the BootRom code fixed on the chip runs;

[0006] Read the timing parameters of each different NAND Flash particle contained in the solid-state drive from the Efuse module to configure the timing parameters of the NAND Flash controller;

[0007] After the timing parameters of the NAND Flash controller are configured, the SSD starts loading and running the firmware.

[0008] Furthermore, the timing parameters of each different NAND Flash particle in the solid-state drive are read from the Efuse module to configure the timing parameters of the NAND Flash controller, including:

[0009] Determine whether the NAND Flash chip is in SDR mode when powered on;

[0010] If so, configure the relevant Timing parameters of the NAND Flash controller in SDR mode;

[0011] After configuring the relevant Timing parameters of the NAND Flash controller in SDR mode, determine whether the status of the NAND Flash die is normal;

[0012] If normal, make the NAND Flash die work in DDR / Toggle / NVDDR mode through Set Featue;

[0013] Configure the relevant Timing parameters of the NAND Flash controller in DDR / Toggle / NVDDR mode;

[0014] After configuring the relevant Timing parameters of the NAND Flash controller in DDR / Toggle / NVDDR mode, determine whether the status of the NAND Flash die is normal;

[0015] If normal, end the Timing parameter configuration.

[0016] Furthermore, during the Timing parameter configuration process, if it is determined that the status of the NAND Flash die is abnormal, the chip of the solid state drive is powered on again.

[0017] Furthermore, before the chip of the solid state drive is powered on, it also includes the steps of

[0018] Burn the Timing parameters of each different NAND Flash die included in the solid state drive into the Efuse module of the solid state drive.

[0019] Furthermore, after the Timing parameter configuration of the NAND Flash controller is completed, the firmware loading and running of the solid state drive specifically includes

[0020] Load the Bootloader program from the NAND Flash;

[0021] After the Bootloader program is loaded, run the Bootloader program;

[0022] After the Bootloader program runs, load the FW firmware from the NAND Flash;

[0023] After the FW firmware is loaded, run the FW firmware.

[0024] The present invention also provides a solid state drive supporting multiple NAND dies, including

[0025] The BootRom code running module is used to run the BootRom code solidified on the chip when the chip of the solid state drive is powered on;

[0026] The Timing parameter configuration module is used to read the Timing parameters of each different NAND Flash particle contained in the solid-state drive from the Efuse module to configure the Timing parameters of the NAND Flash controller;

[0027] The firmware loading module is used to load and run the firmware on the solid-state drive after the timing parameter configuration of the NAND Flash controller is completed.

[0028] Furthermore, the Timing parameter configuration module specifically includes:

[0029] A first judgment unit is used to judge whether the state of the NAND Flash particle is in the SDR mode state when powered on;

[0030] A first parameter configuration unit, configured to configure relevant timing parameters of the NAND Flash controller in the SDR mode;

[0031] The second judgment unit is used to judge whether the state of the NAND Flash particle is normal after configuring the relevant timing parameters of the NAND Flash controller in the SDR mode;

[0032] The mode conversion unit is used to make the NAND Flash particles work in DDR / Toggle / NVDDR mode by Set Featue if it is normal;

[0033] The second parameter configuration unit is used to configure the relevant timing parameters of the NAND Flash controller in the DDR / Toggle / NVDDR mode;

[0034] The third judgment unit is used to judge whether the status of the NAND Flash particle is normal after configuring the relevant timing parameters of the NAND Flash controller in the DDR / Toggle / NVDDR mode;

[0035] The process ending unit is used to end the Timing parameter configuration if it is normal.

[0036] Furthermore, the Timing parameter configuration module also includes an exception handling unit, which is used to re-power on the chip of the solid state drive if it is determined that the state of the NAND Flash particle is abnormal during the Timing parameter configuration process.

[0037] Furthermore, before the BootRom code running module, there is also included

[0038] a parameter programming module, which is used to program the Timing parameters of each different NAND Flash particle included in the solid-state drive into the Efuse module of the solid-state drive.

[0039] Furthermore, the firmware loading module specifically includes

[0040] a Bootloader program loading unit, which is used to load the Bootloader program from the NAND Flash;

[0041] a Bootloader program running unit, which is used to run the Bootloader program after the Bootloader program is loaded;

[0042] an FW firmware loading unit, which is used to load the FW firmware from the NAND Flash after the Bootloader program runs;

[0043] an FW firmware running unit, which is used to run the FW firmware after the FW firmware is loaded.

[0044] The beneficial effect of the present invention is that when the chip of the solid-state drive is powered on, BootRom starts to read the pre-programmed Timing parameters from the Efuse module first, and then loads and runs the Bootloader program from the NAND Flash. For different NAND Flash particles, the Timing parameters programmed into the Efuse module are also different, which can improve the redundancy of BootRom for different NAND Flash particles. Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the mechanisms shown in these drawings.

[0046] Figure 1 It is a flowchart of a firmware loading method for supporting multiple NAND particles according to an embodiment of the present invention;

[0047] Figure 2 It is another flowchart of a firmware loading method for supporting multiple NAND particles according to an embodiment of the present invention;

[0048] Figure 3A Timing parameter configuration flow chart of an embodiment of the present invention;

[0049] Figure 4 This is a firmware loading and running flow chart of an embodiment of the present invention;

[0050] Figure 5 A block diagram of a solid-state hard disk module supporting multiple NAND particles according to an embodiment of the present invention;

[0051] Figure 6 It is a block diagram of another solid-state hard disk module supporting multiple NAND particles according to an embodiment of the present invention;

[0052] Figure 7 This is a block diagram of a Timing parameter configuration module according to an embodiment of the present invention;

[0053] Figure 8 This is a block diagram of a firmware loading module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0056] like Figure 1 As shown, the first embodiment of the present invention is: a firmware loading method supporting multiple NAND particles, comprising the steps of:

[0057] S20, when the chip of the solid state drive is powered on, the BootRom code solidified on the chip runs;

[0058] S30, reading the timing parameters of each different NAND Flash particle contained in the solid state drive from the Efuse module to configure the timing parameters of the NAND Flash controller;

[0059] S40. After the Timing parameter configuration of the NAND Flash controller is completed, the solid-state drive performs firmware loading and operation.

[0060] As Figure 3 shown, in step S30, reading the Timing parameters of each different NAND Flash particle in the solid-state drive from the Efuse module and configuring the Timing parameters of the NAND Flash controller specifically includes

[0061] S31. Determine whether the state of the NAND Flash particle is in the SDR mode state when powered on;

[0062] S32. If so, configure the relevant Timing parameters of the NAND Flash controller in the SDR mode;

[0063] S33. After configuring the relevant Timing parameters of the NAND Flash controller in the SDR mode, determine whether the state of the NAND Flash particle is normal;

[0064] S34. If normal, make the NAND Flash particle work in the DDR / Toggle / NVDDR mode through Set Featue;

[0065] S35. Configure the relevant Timing parameters of the NAND Flash controller in the DDR / Toggle / NVDDR mode;

[0066] S36. After configuring the relevant Timing parameters of the NAND Flash controller in the DDR / Toggle / NVDDR mode, determine whether the state of the NAND Flash particle is normal;

[0067] S37. If normal, end the Timing parameter configuration.

[0068] Among them, during the Timing parameter configuration process, if it is determined that the state of the NAND Flash particle is abnormal, the chip of the solid-state drive is powered on again.

[0069] As Figure 2 shown, in a specific embodiment, before the chip of the solid-state drive is powered on, it further includes steps

[0070] S10. Burn the Timing parameters of each different NAND Flash particle contained in the solid-state drive into the Efuse module of the solid-state drive.

[0071] As Figure 4As shown, in step S40, after the timing parameter configuration of the NAND Flash controller is completed, the solid state drive performs firmware loading and operation, specifically including:

[0072] S41, load the Bootloader program from NAND Flash;

[0073] S42, after the Bootloader program is loaded, run the Bootloader program;

[0074] S43, after the Bootloader program runs, load the FW firmware from the NAND Flash;

[0075] S44. After the FW firmware is loaded, run the FW firmware.

[0076] The beneficial effect of this embodiment is that when the chip of the solid-state hard disk is powered on, the BootRom starts by first reading the pre-burned Timing parameters from the Efuse module, and then loads and runs the Boot loader program from the NAND Flash. For different NAND Flash particles, the Timing parameters burned into the Efuse module are also different, which can improve the redundancy of the BootRom for different NAND Flash particles.

[0077] like Figure 5 As shown, another embodiment of the present invention is a solid state drive supporting multiple NAND particles, including:

[0078] The BootRom code running module 20 is used to run the BootRom code solidified on the chip when the chip of the solid state drive is powered on;

[0079] The Timing parameter configuration module 30 is used to read the Timing parameters of each different NAND Flash particle contained in the solid state drive from the Efuse module to configure the Timing parameters of the NAND Flash controller;

[0080] The firmware loading module 40 is used to load and run the firmware on the solid state drive after the timing parameter configuration of the NAND Flash controller is completed.

[0081] like Figure 7 As shown, the Timing parameter configuration module 30 specifically includes:

[0082] The first judgment unit 31 is used to judge whether the state of the NAND Flash particle is in the SDR mode state when powered on;

[0083] The first parameter configuration unit 32 is used to configure the relevant Timing parameters of the NAND Flash controller in SDR mode if so;

[0084] The second judgment unit 33 is used to judge whether the status of the NAND Flash chip is normal after configuring the relevant Timing parameters of the NAND Flash controller in SDR mode;

[0085] The mode conversion unit 34 is used to make the NAND Flash chip work in DDR / Toggle / NVDDR mode through Set Featue if it is normal;

[0086] The second parameter configuration unit 35 is used to configure the relevant Timing parameters of the NAND Flash controller in DDR / Toggle / NVDDR mode;

[0087] The third judgment unit 36 is used to judge whether the status of the NAND Flash chip is normal after configuring the relevant Timing parameters of the NAND Flash controller in DDR / Toggle / NVDDR mode;

[0088] The process end unit 37 is used to end the Timing parameter configuration if it is normal.

[0089] Among them, the Timing parameter configuration module 30 further includes an exception handling unit, which is used to power on the chip of the solid-state drive again if it is judged that the status of the NAND Flash chip is abnormal during the Timing parameter configuration process.

[0090] As Figure 6 shown, in a specific embodiment, before the BootRom code running module 20, there is also included

[0091] The parameter burning module 10 is used to burn the Timing parameters of each different NAND Flash chip included in the solid-state drive into the Efuse module of the solid-state drive.

[0092] As Figure 8 shown, the firmware loading module 40 specifically includes

[0093] The Bootloader program loading unit 41 is used to load the Boot loader program from the NAND Flash;

[0094] The Bootloader program running unit 42 is used to run the Bootloader program after the Bootloader program is loaded.

[0095] The FW firmware loading unit 43 is used to load the FW firmware from the NAND Flash after the Bootloader program runs;

[0096] The FW firmware running unit 44 is used to run the FW firmware after the FW firmware is loaded.

[0097] The above are only embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A firmware loading method supporting multiple NAND flash chips, characterized in that: Including steps, When the chip of the solid-state drive is powered on, the BootRom code fixed on the chip runs; Read the timing parameters of each different NAND Flash particle contained in the solid-state drive from the Efuse module to configure the timing parameters of the NAND Flash controller; After the timing parameters of the NAND Flash controller are configured, the SSD starts loading the firmware. Read the Timing parameters of each NAND Flash particle in the SSD from the Efuse module to configure the Timing parameters of the NAND Flash controller, including: Determine whether the NAND Flash chip is in SDR mode when powered on; If yes, configure the relevant timing parameters of the NAND Flash controller in SDR mode; After configuring the relevant timing parameters of the NAND Flash controller in SDR mode, determine whether the status of the NAND Flash particles is normal; If normal, use Set Featue to make the NAND Flash particles work in DDR / Toggle / NVDDR mode; Configure the relevant timing parameters of the NAND Flash controller in DDR / Toggle / NVDDR mode; After configuring the relevant timing parameters of the NAND Flash controller in DDR / Toggle / NVDDR mode, determine whether the status of the NAND Flash particles is normal; If normal, the Timing parameter configuration ends.

2. The firmware loading method supporting multiple NAND flash chips according to claim 1, characterized in that: During the Timing parameter configuration process, if the status of the NAND Flash particles is determined to be abnormal, the chip of the solid-state drive is powered on again.

3. The firmware loading method supporting multiple NAND flash chips according to claim 1, characterized in that: Before the SSD chip is powered on, there are also steps: Burn the timing parameters of each different NAND Flash particle contained in the solid-state drive to the Efuse module of the solid-state drive.

4. The firmware loading method supporting multiple NAND flash chips according to claim 1, characterized in that: After the NAND Flash controller's Timing parameters are configured, the SSD firmware loading and operation specifically includes: Load the Bootloader program from NAND Flash; After the Bootloader program is loaded, run the Bootloader program; After the Bootloader program runs, the FW firmware is loaded from the NAND Flash; After the FW firmware is loaded, run the FW firmware.

5. A solid state drive supporting multiple NAND flash chips, characterized in that: include, The BootRom code running module is used to run the BootRom code solidified on the chip when the chip of the solid state drive is powered on; The Timing parameter configuration module is used to read the Timing parameters of each different NAND Flash particle contained in the solid-state drive from the Efuse module to configure the Timing parameters of the NAND Flash controller; A firmware loading module, which is used to load and run the firmware of the solid-state drive after the Timing parameters of the NAND Flash controller are configured; The Timing parameter configuration module specifically includes: A first judgment unit, which is used to judge whether the state of the NAND Flash particle is the SDR mode state when powering on; A first parameter configuration unit, which is used to configure the relevant Timing parameters of the NAND Flash controller in the SDR mode if so; A second judgment unit, which is used to judge whether the state of the NAND Flash particle is normal after the relevant Timing parameters of the NAND Flash controller in the SDR mode are configured; A mode conversion unit, which is used to make the NAND Flash particle work in the DDR / Toggle / NVDDR mode through Set Featue if it is normal; A second parameter configuration unit, which is used to configure the relevant Timing parameters of the NAND Flash controller in the DDR / Toggle / NVDDR mode; A third judgment unit, which is used to judge whether the state of the NAND Flash particle is normal after the relevant Timing parameters of the NAND Flash controller in the DDR / Toggle / NVDDR mode are configured; A process end unit, which is used to end the Timing parameter configuration if it is normal.

6. The solid-state drive supporting multiple NAND flash memory chips as claimed in claim 5, wherein: The Timing parameter configuration module further includes an exception handling unit, which is used to power on the chip of the solid-state drive again if it is judged that the state of the NAND Flash particle is abnormal during the Timing parameter configuration process.

7. The solid-state drive supporting multiple NAND flash memory chips as claimed in claim 5, wherein: Before the BootRom code running module, there is also: A parameter programming module, which is used to program the Timing parameters of each different NAND Flash particle included in the solid-state drive into the Efuse module of the solid-state drive.

8. The solid-state drive supporting multiple NAND flash memory chips as claimed in claim 5, wherein: The firmware loading module specifically includes: A Bootloader program loading unit, which is used to load the Bootloader program from the NAND Flash; A Bootloader program running unit, which is used to run the Bootloader program after the Bootloader program is loaded; An FW firmware loading unit, which is used to load the FW firmware from the NAND Flash after the Bootloader program runs; An FW firmware running unit, which is used to run the FW firmware after the FW firmware is loaded.

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