Display with variable resolution

Abstract

This disclosure relates to a display with variable resolution. Electronic devices, such as head-mounted devices, may have a display. The display may have regions of lower (L) resolution and higher (M, H) resolution to reduce the data bandwidth and power consumption of the display while maintaining satisfactory image quality. Data lines may be shared by the lower-resolution and higher-resolution portions of the display, or different portions of the display with different resolutions may have different numbers of data lines. The length of the data lines in the transition region between the lower-resolution and higher-resolution portions of the display may vary to reduce visible discontinuities between the lower-resolution and higher-resolution portions. The lower-resolution and higher-resolution portions of the display can be dynamically adjusted using a dynamically adjustable gate driver circuitry and a dynamically adjustable data line driver circuitry.

Description

[0001] This application is a divisional application of the invention patent application filed on August 14, 2017, with application number 201780052309.7 and entitled "Display with Variable Resolution". Background Technology

[0002] The present invention relates generally to displays, and more specifically, to displaying content on a display at different resolutions in different display areas.

[0003] Electronic devices may include displays. For example, head-mounted devices may have displays for showing images to a user. Displaying images on a display in a head-mounted device can be challenging. High-resolution images are visually appealing, but may be difficult or impossible to present to a user without using significant image data bandwidth and consuming substantial power. Summary of the Invention

[0004] Electronic devices such as head-mounted devices may have a display that the observer's eye can see through lenses. The display may have areas of lower and higher resolution to reduce the display's data bandwidth and power consumption while maintaining satisfactory image quality.

[0005] In some configurations, dynamically adjustable gate driver circuitry and dynamically adjustable data line driver circuitry allow for dynamic adjustment of the lower-resolution and higher-resolution portions of the display. Data lines can be shared by the lower-resolution and higher-resolution portions of the display, or different portions of the display with different resolutions can have different numbers of data lines. In this type of arrangement, the data line length and pixel size can vary in the transition region between the lower-resolution and higher-resolution portions of the display to reduce visible discontinuities between them. Attached Figure Description

[0006] Figure 1 This is a simplified diagram of an exemplary electronic device with a display according to an implementation scheme.

[0007] Figure 2 This is a simplified diagram illustrating how an electronic device according to an embodiment may have a pair of displays, each display having a lower resolution area and a higher resolution area.

[0008] Figure 3 This is a simplified diagram illustrating how an electronic device according to an embodiment may have a display having a high-resolution central area and lower-resolution peripheral areas on its sides.

[0009] Figure 4 This is a circuit diagram of an exemplary display according to the implementation scheme.

[0010] Figure 5 This is a simplified diagram of an exemplary display according to an embodiment, the display having a lower resolution area and a higher resolution area driven by data line driver circuitry on opposite edges of the display.

[0011] Figure 6 This is a simplified diagram of an exemplary display according to an implementation scheme, the display having a lower resolution area and a higher resolution area using a shared data line.

[0012] Figure 7 This is a simplified diagram illustrating how a display with a lower resolution area and a higher resolution area according to an embodiment can have a transition area with data lines having staggered lengths.

[0013] Figure 8 This is a simplified diagram illustrating how different parts of a display according to an embodiment can present images with different resolutions.

[0014] Figure 9 This is a simplified diagram illustrating how a pixel array with sawtooth data lines according to an embodiment can have data lines, each controlling a sub-pixel of only a single color, to allow different areas of the display to be configured with different resolutions using a dynamically adjustable gate line driver circuitry.

[0015] Figure 10 This is a simplified diagram illustrating how subpixels can be grouped in different ways to form dynamically resizable pixels when areas of a display operate at different resolutions, according to an embodiment.

[0016] Figure 11 This is a simplified diagram illustrating how, according to an embodiment, a cross-connection can be provided to a pixel array through sub-pixel columns in the array to facilitate operation in modes with different resolutions.

[0017] Figure 12 This is a circuit diagram of an exemplary gate driver circuit system that, according to an embodiment, can provide gate line signals to different areas of a display with different resolutions.

[0018] Figure 13 It is a simplified diagram of the signals associated with the gate driver circuitry operating in different modes according to the implementation scheme.

[0019] Figure 14 This is a simplified diagram of a data line driver circuit system, according to an implementation scheme, which can be used to control data lines in a display having different areas with different resolutions.

[0020] Figure 15 and Figure 16It is based on the implementation plan and operates in different modes. Figure 14 An exemplary timing diagram of the signals associated with the data line driver circuit system.

[0021] Figure 17 This is a circuit diagram of a data line driver circuit system with a switch for merging data lines, according to the implementation scheme.

[0022] Figure 18 This is a simplified diagram of an exemplary data line driver circuit system including an adjustable mode shift register according to an implementation scheme.

[0023] Figure 19 This is a simplified diagram of an exemplary gate line driver circuit system comprising a gate block operable in multiple modes, according to an embodiment. Detailed Implementation

[0024] Figure 1 An exemplary system is illustrated that can be used to display images in different areas of a display with different resolutions. System 10 may include portable electronic devices such as portable electronic device 14. Device 14 may be a head-mounted device such as a head-mounted display. Device 14 may include one or more displays such as display 20 mounted in a support structure such as support structure 12. Display 20 may sometimes be referred to as a display module or display unit. Structure 12 may have the shape of a pair of glasses (e.g., a support frame), may be formed with a helmet-shaped shell, may be formed with goggles, or may have other configurations to help mount and secure components of device 14 to a user's head.

[0025] Display 20 may be a liquid crystal display, an organic light-emitting diode display, or other types of display. Optical system components such as lens 22 allow an observer (e.g., see observer eye 16) to view an image on display 20. Two lenses 22 may be associated with corresponding left and right eyes 16. Each lens 22 may include one or more lens elements (as an example) through which light from the pixel array in display 20 passes. A single display 20 may produce images for both eyes 16, or as... Figure 1 As shown in the example, a pair of displays 20 can be used to display images. As an example, the displays 20 may include a left display aligned with the left lens 22 and the observer's left eye, and a right display aligned with the right lens 22 and the observer's right eye. In a configuration with multiple displays, the focal length and position of the lens 22 can be selected such that any gaps between the displays are invisible to the user (i.e., to allow the images from the left and right displays to overlap seamlessly).

[0026] In a configuration where device 14 is a pair of virtual reality glasses, display 20 can blur the observer's view of their surroundings. In a configuration where device 14 is a pair of augmented reality glasses, display 20 can be transparent and / or display 14 can be equipped with an optical mixer such as a semi-silvered mirror to allow observer 16 to simultaneously view an image on display 20 and external objects in the surrounding environment, such as object 18.

[0027] Device 14 may include a control circuit system 26. The control circuit system 26 may include processing circuit systems such as microprocessors, digital signal processors, microcontrollers, baseband processors, image processors, application-specific integrated circuits with processing circuit systems, and / or other processing circuit systems, and may include random access memory, read-only memory, flash memory, hard disk storage devices, and / or other storage devices (e.g., non-transitory storage media for storing computer instructions for software to run on the control circuit system 26).

[0028] Device 14 may include input / output circuitry such as touch sensors, buttons, microphones for collecting voice input and other inputs, sensors, and other devices for collecting input (e.g., user input from observer 16), and may include light-emitting diodes, display 20, speakers, and other devices for providing output (e.g., output for observer 16). If desired, device 14 may include wireless circuitry and / or other circuitry to support communication with a computer or other external device (e.g., a computer providing image content to display 14). If desired, sensors such as accelerometers, compasses, ambient light sensors or other light detectors, proximity sensors, scanning laser systems, and other sensors may be used to collect input during operation of display 14. These sensors may include digital image sensors such as camera 24. Camera 24 may collect images of the environment surrounding observer 16 and / or may be used to monitor observer 16. As an example, control circuitry 26 may use camera 24 to collect images of the pupil and other parts of the observer's eye. The position of the observer's pupil and its position relative to the rest of the observer's eye can be used to determine the location of the center of the observer's eye (i.e., the center of the user's pupil) and the direction of the observer's gaze (gaze direction).

[0029] During operation, the control circuitry system 26 may provide image content to the display 20. The content may be received remotely (e.g., from a computer or other content source coupled to the display 14) and / or may be generated by the control circuitry system 26 (e.g., text, other computer-generated content, etc.). The content provided to the display 20 by the control circuitry system 26 may be observed by the observer 16.

[0030] Observers are most sensitive to image details in their primary field of view. Therefore, the peripheral regions of the display may be provided with less image detail than parts of the display in the observer's gaze direction. By including lower-resolution regions in the display, image processing burdens, such as those imposed by image data bandwidth usage and power consumption, can be minimized. If necessary, the display resolution can be reduced across all peripheral portions of display 20 (e.g., portions of display 20 near the edges of display 20). If necessary, display 20 can be provided with a dynamically adjustable resolution. In a display with a dynamically reconfigurable display resolution, gaze detection techniques (e.g., using camera 24) can be used to determine which portion of the dynamically reconfigurable display the observer 16 is directly observing and therefore should have the highest resolution, and to determine which portions of the dynamically reconfigurable display are within the observer's peripheral line of sight and should have lower resolution.

[0031] Figure 2 This is a simplified diagram illustrating how device 14 may have a pair of displays 20 for the observer's left eye 16 and right eye 16, respectively. The left-hand display 20 may have a left-hand low-resolution peripheral region 20L and a right-hand high-resolution region 20H. The right-hand display 20 may have a right-hand low-resolution peripheral region 20L and a left-hand high-resolution region 20H. Any gaps between the displays 20 can be hidden from the view by selecting a lens 22 with appropriate magnification (e.g., so that the images on the displays 20 merge in the observer's line of sight).

[0032] Figure 3 The diagram illustrates how device 14 can have a single display 20, wherein a single, higher-resolution central portion 20H is side-mounted on the opposite left and right edges of a lower-resolution portion 20L.

[0033] The lower resolution areas of the display 20 may have resolutions such as 10-600 pixels per inch, 10-300 pixels per inch, less than 150 pixels per inch, more than 10 pixels per inch, etc. The higher resolution areas may have resolutions such as 400-2000 pixels per inch, more than 150 pixels per inch, more than 500 pixels per inch, more than 1000 pixels per inch, less than 2000 pixels per inch, etc. These are merely exemplary examples. Typically, the lower and higher resolution areas of the display 20 can have any suitable resolution (pixels per inch).

[0034] Figure 4 This is a circuit diagram of an exemplary display. (e.g.) Figure 4As shown, the display 20 may have a control circuitry 30 that receives image data (e.g., serial image data) from a data source in the control circuitry 26 or other suitable data source via path 36. An image corresponding to the image data received on path 36 may be displayed on a pixel array formed by rows and columns of pixels. The display driver circuitry 30 may be formed of one or more integrated circuits and may include a timing controller circuitry (TCON) such as circuitry 32 (sometimes referred to as a digital-to-analog converter circuitry) and a data line driver circuitry (sometimes referred to as a column driver or column buffer circuitry) such as data line driver circuitry 34. Control signals may be provided by the display driver circuitry 30 to other display driver circuitry such as gate line driver circuitry 38 via path such as path 40. Gate line driver circuitry such as gate driver circuitry 38 may be present on one or both edges of the display 14 (see, for example, an exemplary right-hand gate line driver circuitry 38').

[0035] During operation, the display driver circuitry 30 can use data lines D to provide image data to the pixel array formed by the pixels 42, while simultaneously instructing the gate driver circuitry 38 to provide one or more control signals (sometimes also referred to as gate signals, gate line signals, scan signals, emit enable signals, etc.) on the gate lines G to the rows of pixels 42. Any suitable number of gate lines G may exist for each row of pixels 42. A configuration with a single gate line G per row may sometimes be described herein as an example.

[0036] Figure 5 This is a simplified diagram illustrating how a display 20 may have a lower resolution portion 20L and a higher resolution portion 20H driven by respective gate driver circuits 38L and 38H and corresponding display driver circuits 30L and 30H. The display driver circuits 30L and 30H have corresponding data line driver circuits 34. The density of data lines D in the display portion 20L is lower than that in the portion 20H because there are fewer pixels per gate line loading data in the portion 20L compared to the portion 20H. If desired, the pixel area of ​​each pixel 42 can be varied in the transition region between the display portions 20L and 20H to help visually hide the interface between the regions 20L and 20H. The pixel area can be changed, for example, by changing the anode area in the light-emitting diode of each pixel 42 in an organic light-emitting diode display (and thus changing the emitting area).

[0037] exist Figure 6 In the exemplary configuration, the long data line DL extends through regions 20L and 20H, and the interlaced short data lines DNL extend only through the high-resolution region 20H.

[0038] Figure 7 This illustrates how the length of the short data lines DNL can be varied (interlaced) in the transition region between the lower-resolution portion 20L and the higher-resolution portion 20H of display 20. This helps to visually eliminate any appearance differences between portions 20H and 20L, making the interface between regions 20L and 20H inconspicuous to the observer. If desired, pixel sizes and / or other properties can be varied in the transition region between portions 20H and 20L to minimize visual differences between portions 20H and 20L.

[0039] If needed, the resolution of display 20 (e.g., a selected area of ​​display 20) can be dynamically adjusted. Using this type of arrangement, each display 20 can have two or more, or three or more, different areas with different corresponding resolutions. Figure 8 As shown, for example, display 20 may have a first portion (e.g., a portion directly in the user's line of sight) having a high resolution such as a high-resolution portion H, may have a second portion (e.g., a more peripheral portion) having a medium resolution such as a medium-resolution portion M, and may have a lower-resolution peripheral portion such as a lower-resolution portion L. The shape, size, and position of portions H and M may change dynamically (e.g., based on information from a gaze detection system (e.g., camera 24) indicating the current direction in which the user's gaze is directed).

[0040] Using an exemplary configuration, the gate lines of display 20 are controlled independently (in high-resolution regions) and in two or more groups (in lower-resolution regions). With this arrangement, when used to control pixels of display 20 in higher-resolution regions, the gate lines are not shorted together (coupled together), and when used to control pixels of display 20 in lower-resolution regions, the gate lines are shorted together (coupled together) and driven by a common gate line signal. If desired, any suitable subpixel pattern can be used to support displays with dynamic resolution capabilities such as these.

[0041] exist Figure 9 In the example, display 20 has data lines D connected in a zigzag pattern to red (R), blue (B), and green (G) subpixels 42S. Using this type of pattern, each data line is specifically coupled to a subpixel of a single color and is used only to load data for that same color subpixel. By driving a common gate line signal into multiple adjacent gate lines, the gate line resolution for this type of display can be reduced without compromising image coloring. The data driver frequency can be high when data is being loaded in high-resolution areas and low when data is being loaded in lower-resolution areas.

[0042] like Figure 10 As shown in the exemplary subpixel arrangement, which involves applying dynamically adjusted gate line signals and dynamically adjusted data line signals, the display 20 may have pixels 42 with RGB subpixels 42S, which can be configured into different pixel shapes (tile shapes) and sizes depending on the desired resolution. When a high (native) resolution is desired, each pixel 42 may include a single red subpixel, a single green subpixel, and a single blue subpixel, as shown in pixel HR. When a medium resolution is desired, each pixel 42 may include two red subpixels, two green subpixels, and two blue subpixels, as shown in pixel MR. Larger pixel layouts such as pixel LR can be used in the low-resolution areas of the display 20. Figure 10 As shown, for example, each low-resolution pixel (LR) can have four red sub-pixels, four green sub-pixels, and four blue sub-pixels.

[0043] Figure 11 An exemplary display 20 has rows with alternating green and blue subpixels or alternating red and green subpixels. Each data line D controls only subpixels of a common color (e.g., all red subpixels, all blue subpixels, or all green subpixels) to allow dynamic gate line signaling to selectively control the display resolution. Every other blue or red data line, a cross-routing path, such as path 50, is used to couple pixel circuitry (e.g., exemplary switching transistor TS and exemplary driving transistor TD) that receives data from that data line to appropriately colored LEDs 54 in the adjacent column. For example, a data line associated with a blue subpixel, such as exemplary data line DB, can be used to load data into a blue pixel circuitry adjacent to (immediately to the left of) line DB. Some of these pixel circuitry, such as pixel circuit BPC, can be used to control the current applied through the blue LEDs 54 in the blue pixel circuitry. Other blue pixel circuitry, such as blue pixel circuit BPC', is used to provide drive current to blue LEDs, such as blue LEDs 54', via the associated cross-routing path 50. The pixel circuit BPC' is located right next to the DB line, so the cross routing path 50 crosses the green sub-pixel data line (i.e., the non-blue data line) before reaching the blue LED 54'.

[0044] If needed, the gate driver circuitry 38 can be used to independently identify gate lines G for high-resolution regions, and can also be used to identify gate lines G in dynamically adjustable groups (e.g., groups of two or four, etc.) in lower-resolution regions. Figure 12An exemplary gate driver circuit system 38 supporting the dynamic gate line resolution capability of display 20 is shown. The gate driver circuit system 38 includes a shift register circuit formed by a series of coupled register circuits 56, each of which provides a gate line signal to a corresponding gate line G. The shift registers are loaded in series (e.g., in...). Figure 12 (From top to bottom in the example). The gate driver circuitry control logic 58 can be controlled by control signals res2 and res4, and can be used to place the gate driver circuitry 38 into one of three modes, such as... Figure 13 The signal diagram is shown. In the highest resolution mode (sometimes called normal or native mode), res2 and res4 are low. In this mode, each gate line G is provided with an independent gate line signal from the corresponding register circuit 56. When the gate driver circuit system 38 is placed in a medium resolution mode, where pairs of gate lines G are provided with a common gate line signal (i.e., where pairs of adjacent gate lines G are electrically coupled together and receive the same gate line signal), res2 can be high and res4 can be low. The gate driver circuit system 38 can also operate in a low resolution mode by setting res4 to high and res2 to high. In the low resolution mode, each group of four gate lines G at the output of the circuit system 38 is driven by a common gate line signal.

[0045] If needed, the gate driver circuitry 38 and the display driver circuitry 30 can be dynamically reconfigured. In this way, areas of the display 20 can be configured with gate line signals and data line signals with dynamically adjustable resolution.

[0046] exist Figure 14 An exemplary display driver circuit system for dynamically adjusting the gate line resolution in this type of display is shown. Figure 14 As shown, the gate driver circuitry 38 may include a low-voltage shift register circuitry 60, a level shifter circuitry 62, and an output buffer circuitry 64 (e.g., a circuitry that generates gate line signals G1...GN at a voltage suitable for driving pixel 42). Circuitry 60 may include shift registers such as shift register 66, which loads the gate line signals for each image frame and provides corresponding gate line signals to multiplexer 64. Multiplexer 64 may be controlled by a control signal such as MODE. Figure 15 and Figure 16 The operation of the gate driver circuitry 38 in high-resolution mode and low-resolution mode are shown respectively. When it is desired to drive the gate line independently, the circuitry 38 is placed in high-resolution mode by setting MODE to a low value, as shown below. Figure 15As shown. In this mode, each gate line G1...GN provides a separate gate line signal to the pixel array in the display 20, and adjacent gate lines are isolated from each other. MODE takes a high value when it is desired to combine adjacent gate line pairs and thus halve the resolution, as shown. Figure 16 As shown. When the resolution is halved in this way, adjacent pairs of gate lines are shorted (electrically coupled) together via a multiplexer (switching circuit) 64, and thus provide the same gate line signal to the display 20. During operation, the start signal STV initiates the cascaded gate signals via shift register 66. The clock signal CLK and the output enable signal OE establish the pulse width.

[0047] exist Figure 14 , Figure 15 and Figure 16 In the example, the gate driver circuitry 38 can be positioned in a higher resolution mode or a lower resolution mode, where each multiplexer 64 drives a common gate line signal onto two gate lines. If desired, the multiplexer 64 can drive the common gate line signal onto a different number of gate lines (e.g., three, etc.). The operation of the gate driver circuitry 38 (i.e., the resolution of the gate driver circuitry 38) can be dynamically changed within an image frame so that any desired portion of the display 20 can be selectively provided with gate line signals of reduced resolution.

[0048] Figure 17 This is a circuit diagram of a dynamically adjustable data line driver circuit system (i.e., a data line driver circuit system with adjustable resolution), which has a switch that combines data lines when it is desired to dynamically adjust the data line resolution (e.g., for a system with...). Figure 14 The circuit system 38 or other suitable dynamically adjustable gate driver circuit system provides a display with dynamically adjustable gate line resolution. (e.g., a display with such a dynamic gate line resolution). Figure 17 As shown, the display driver circuitry 30 may include a digital-to-analog converter circuitry 32 (sometimes referred to as a timing controller circuitry) that converts digital image data from path 36 into analog data signals on data lines D1...DN. The column buffer circuitry 72 may have an operational amplifier (column buffer) 78 in each column (i.e., a column buffer associated with each data line). The data line multiplexer circuitry 74 may have a switch (multiplexer) 76 for selectively shorting (electrically coupling) adjacent data lines together. The operational amplifier circuitry 72 and the switch circuitry 74 may be controlled by a control circuitry (e.g., control circuitry 80) within the circuitry 30.

[0049] The column buffer circuit system 72 can obtain unbuffered data signals from the circuit system 32 and can amplify these signals to load them into the pixel 42 via data lines D1...DN. In high-resolution mode, switch 76 is on and adjacent data lines operate independently (e.g., Dn-1 and Dn are electrically isolated from each other and are not shorted together, etc.). In low-resolution mode, the data line multiplexing circuit system is configured to use a common data signal to drive adjacent data lines. Figure 17 As shown on the right, for example, the first column buffer 78 (e.g., amp1) can be used to drive data signals to data lines Dn-1 and Dn (as shown in path 70). Unused column buffers (amplifier amp2 in this example) can be disabled by applying a disable signal to their enable line (En-1) to minimize quiescent current consumption. Similar to the adjustments made to the gate line resolution, Figure 17 The circuit system can dynamically change the resolution of the data lines within an image frame.

[0050] Figure 18 It can be used to map pixel arrays at various resolutions (e.g., Figure 2 The pixel array 42) provides an exemplary data line driver circuit system for data signals (see, for example, a data line driver circuit system for pixel array 42). Figure 4 A simplified diagram of the display driver circuit system 34) (see, for example) Figure 8 ).

[0051] like Figure 18 As shown, the data line driver circuitry may include an adjustable mode shift register circuitry such as an adjustable mode shift register 90. During operation, data to be loaded into the pixel array may be provided to the shift register 90. The shift register 90 may be formed from a series of multi-register register blocks such as exemplary register blocks 90-1, 90-2, and 90-3. Each register block may contain four separate registers 98 interconnected by a multiplexer circuitry such as a multiplexer 99, as shown in circuitry 90-2' for block 90-2. A two-bit mode control signal (resolution mode control signal) SGRP may be provided to the multiplexer circuitry 99, which allows the register block to be placed in a variety of different resolution modes.

[0052] For example, the value of SGRP can be 10, 01, or 00. As shown in the associated multiplexer circuitry 99 of path 92 and circuitry 90-2', in 10 mode, the data input to the first register in the register block can be distributed in parallel with the data inputs to the second, third, and fourth registers 98. In 10 mode, all four registers 98 in the register block are therefore loaded with the same data bits in a single clock cycle (a single pulse of the clock signal SCLK), which is suitable when loading low-resolution data (e.g., quarter-resolution data) of the low-resolution portion of the pixel array. Path 94 and multiplexer circuitry 99 are used to load data into register pairs in parallel during 01 mode. In the first clock cycle of 01 mode, the first bit of the data is loaded into the first and second registers of the register block. In the second clock cycle of 01 mode, the first bit of the data is shifted to the third and fourth registers of the register block, and the second bit of the data is loaded into the first and second registers. When it is desired to load the corresponding portion of the pixel array with half-resolution data, the register block in shift register 90 operates in 01 mode. The register block associated with full-resolution data operates in 00 mode. In 00 mode, four clock cycles are used to load four independent bits of data into the four corresponding registers in the register block.

[0053] Figure 18 Table 100 summarizes the different operating modes (data line resolutions) supported by the register block of register 90. When the resolution mode selection signal SGRP is 00, data is output on data line D at full resolution (one data bit per data line). When the resolution mode selection signal SGRP is 01, data is output on the corresponding data line D at half resolution (each pair of adjacent data lines carries the same number of data bits). When the resolution mode selection signal SGRP is 10, data is output on the corresponding data line D at quarter resolution (each group of four adjacent data lines carries the same number of data bits). Additional resolution modes can be supported if needed. Figure 18 The example using three different resolution modes is merely illustrative.

[0054] Figure 19 This is a simplified diagram of an exemplary gate driver circuitry (horizontal control line circuitry 102) for controlling pixel array 42 in different resolution modes. Any suitable horizontal control signal can be controlled using this type of circuitry (scan signal, emit enable signal, etc.). Figure 19 In the example, a gate line signal is provided to a horizontal control line, such as a gate line G, at the output of the horizontal control line circuit system 102.

[0055] like Figure 19As shown, circuit system 102 receives control signal 110. Circuit system 102 includes shift registers such as shift register 104 and latches such as latch 106. Clock signal CLK is allocated to register 104, latch 106, and shift register formed by a string of gate blocks 108. Shift register 104 receives start pulse control signal STV and, upon receiving signal STV and in response to clock signal CLK, generates sequence control signals for latch 106. In response, latch 106 provides control signals on gate block control line 112 to the corresponding gate block 108 of dynamic configuration block 108.

[0056] Each gate block 108 has four corresponding outputs and two control signal inputs (for receiving two control signals, which are fed by signals on line 112 of the register in latch 106 associated with the most significant bit and the least significant bit of the resolution mode control signal GGRP, respectively).

[0057] The GGRP value can be dynamically adjusted to adjust the mode in which each gate block 108 provides its output signal. In 10 mode (e.g., when the block's GGRP is 10), the four output pulses of the block are identified in parallel within the same clock cycle, thereby loading four consecutive rows of pixels 42 with data in parallel. When the gate module 108 operates in 01 mode, the four output pulses from the block are interleaved in pairs. For example, during a first clock cycle, a first output pulse can be identified simultaneously on the first and second rows of pixels 42 of the block, and during a second clock cycle, a second output pulse can be identified simultaneously on the third and fourth rows of pixels 42 of the block. In 00 mode (e.g., when the block's GGRP is 00), a first output pulse is identified at the output terminal in the first row of the block during the first clock cycle, a second output pulse is identified at the output terminal in the second row of the block during the second clock cycle, a third output pulse is identified at the output terminal in the third row of the block during the third clock cycle, and a fourth output pulse is identified at the output terminal in the fourth row of the block during the fourth clock cycle.

[0058] According to one embodiment, an electronic device is provided, comprising: at least one lens; a pixel array configured to generate light passing through the lens; a data line driver circuit system configured to provide data signals to the pixels via data lines at a dynamically adjustable resolution, the data line driver circuit system including a data line multiplexer circuit system dynamically configured to short adjacent data lines together; gate lines coupled to the pixels; and a gate line driver circuit system configured to provide gate line signals to the pixels via the gate lines at a dynamically adjustable resolution.

[0059] According to another embodiment, the gate line driver circuit system includes a gate line multiplexer that can be configured to short adjacent gate line pairs together.

[0060] According to another embodiment, the gate line driver circuit system includes: a shift register having register circuitry, each of the register circuitry being coupled to a corresponding gate line; and a control circuit system coupled to the shift register, the shift register being configured to place the shift register in different modes.

[0061] According to another implementation, the different modes include at least a first mode and at least a second mode, in which each of the register circuits provides an independent gate line signal to a corresponding gate line coupled to the register circuit, and the second mode is different from the first mode.

[0062] According to another embodiment, the different modes include a third mode, wherein the gate driver circuitry is configured to provide a gate line signal with a first resolution in a first mode, a gate line signal with a second resolution in a second mode, and a gate line signal with a third resolution in a third mode.

[0063] According to another implementation, the data line multiplexer circuit system includes a plurality of switches, each of which is coupled between a corresponding first data line and a second data line.

[0064] According to one embodiment, an electronic device is provided, comprising: at least one lens; a pixel array configured to generate light passing through the lens; a data line; a data line driver circuit system configured to provide data signals to the pixels via the data line at a dynamically adjustable resolution; gate lines coupled to the pixels; and a gate line driver circuit system configured to provide gate line signals to the pixels via the gate lines at a dynamically adjustable resolution, the gate line driver circuit system including a plurality of gate blocks, each of the plurality of gate blocks receiving a resolution mode control signal.

[0065] According to another embodiment, the resolution mode control signal includes a two-bit control signal, and the gate block is configured to operate in at least a first mode, a second mode, and a third mode.

[0066] According to another embodiment, each gate block includes at least a first output, a second output, a third output, and a fourth output, and each gate block is configured to recognize a pulse on the first output, the second output, the third output, and the fourth output simultaneously in a first mode in response to receiving a clock signal.

[0067] According to another embodiment, in the second mode, each gate block is further configured to: recognize a pulse on the first output and the second output in response to receiving a first clock signal; and recognize a pulse on the third output and the fourth output in response to receiving a second clock signal different from the first clock signal.

[0068] According to another embodiment, in the third mode, each gate block is further configured to: recognize a pulse on a first output in response to receiving a first clock signal; recognize a pulse on a second output in response to receiving a second clock signal different from the first clock signal; recognize a pulse on a third output in response to receiving a third clock signal different from the first clock signal and the second clock signal; and recognize a pulse on a fourth output in response to receiving a fourth clock signal different from the first clock signal, the second clock signal and the third clock signal.

[0069] According to another embodiment, the data line driver circuitry includes an adjustable shift register.

[0070] According to another embodiment, the adjustable shift register includes a plurality of shift register blocks, each of which includes at least a first register, a second register, a third register, and a fourth register.

[0071] According to another implementation, each of the shift register blocks is configured to operate in at least a first mode, a second mode, and a third mode, and in the first mode, data is loaded in parallel into the first register, the second register, the third register, and the fourth register.

[0072] According to another implementation, in the second mode, data is loaded into the first and second registers in parallel during the first clock cycle, and shifted from the first and second registers to the third and fourth registers during the second clock cycle, which is different from the first clock cycle.

[0073] According to another implementation, in the third mode, data is loaded into the first register, the second register, the third register, and the fourth register during different clock cycles.

[0074] According to one embodiment, a display is provided, comprising: a pixel array; a gate line driver circuit system having a shift register and a gate line multiplexer, the gate line multiplexer receiving gate line signals from the shift register; gate lines configured to provide gate line signals to the pixel array after the gate line signals have passed through the gate line multiplexer; and a data line driver circuit system having a column buffer circuit system through which data signals pass; and data lines configured to provide data signals from the column buffer circuit system to the pixel array, the data line driver circuit system having a data line multiplexer through which data signals from the column buffer circuit system are transmitted to the data lines.

[0075] According to another embodiment, the data line multiplexer can be configured to operate in at least a first data line multiplexer mode and a second data line multiplexer mode, in which each of the data lines receives an independent data line signal, and in the second data line multiplexer mode, for the pair from the data line multiplexer, each adjacent pair of data lines is provided with a common data line signal.

[0076] According to another embodiment, the gate line multiplexer can be configured to operate in at least a first gate line multiplexer mode and a second gate line multiplexer mode, in which each of the gate lines receives an independent gate line signal from the gate line multiplexer, and in the second gate line multiplexer mode, for the pair from the gate line multiplexer, each adjacent pair of gate lines is provided with a common gate line signal.

[0077] According to another implementation, the data line multiplexer has a plurality of switches, each of which is coupled to a corresponding pair of column buffers in a column buffer circuit system, and each of the plurality of switches is coupled to a corresponding pair of data lines.

[0078] The foregoing description is merely illustrative and various modifications can be made to the described implementation scheme. The described implementation scheme can be implemented independently or in any combination.

[0079] This patent application claims the benefit of provisional patent application No. 62 / 375,201, filed on August 15, 2016, which is incorporated herein by reference in its entirety.

Claims

1. An electronic device, comprising: At least one lens; A pixel array configured to generate light passing through the lens; Data cable; A data line driver circuit system configured to supply data signals to the pixels via the data line at a dynamically adjustable resolution, wherein the data line driver circuit system includes an adjustable shift register, wherein the adjustable shift register includes a plurality of shift register blocks, each of the plurality of shift register blocks including a plurality of separate registers interconnected by a multiplexer circuit system, wherein the plurality of separate registers includes at least a first register, a second register, a third register, and a fourth register, and wherein the multiplexer circuit system includes a first multiplexer, a second multiplexer, and a third multiplexer; A gate line, the gate line being coupled to the pixel; and A gate line driver circuit system configured to provide gate line signals to the pixel via the gate line at a dynamically adjustable resolution.

2. The electronic device of claim 1, wherein each of the shift register blocks is configured to operate in at least a first mode, a second mode, and a third mode, and wherein in the first mode, data is loaded in parallel into the first register, the second register, the third register, and the fourth register.

3. The electronic device of claim 2, wherein in the second mode, data is loaded into the first register and the second register in parallel during a first clock cycle, and shifted from the first register and the second register to the third register and the fourth register during a second clock cycle different from the first clock cycle.

4. The electronic device of claim 3, wherein in the third mode, data is loaded into the first register, the second register, the third register, and the fourth register during different clock cycles.

5. The electronic device according to claim 1, wherein, Each of the first, second, and third multiplexers has a first input output from the multiplexer in a first resolution mode, a second input output from the multiplexer in a second resolution mode, and a third input output from the multiplexer in a third resolution mode.

6. The electronic device according to claim 1, wherein A first register having a first input and a first output provided on a first data line; A second register having a second input and a second output provided on a second data line; The third register has a third input and a third output provided on the third data line; The fourth register has a fourth input and a fourth output provided on the fourth data line; A first multiplexer has a fifth input coupled to a first output, wherein the first multiplexer has a fifth output provided as a second input to a second register; The second multiplexer has a sixth input coupled to the second output, wherein the second multiplexer has a sixth output provided as a third input to the third register; and The third multiplexer has a seventh input coupled to a third output, wherein the third multiplexer has a seventh output provided as a fourth input to a fourth register.

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