Semiconductor structure and fabrication method, memory, memory system, and electronic device

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof, a memory, a memory system and an electronic device. The semiconductor structure comprises: a first semiconductor structure; a first interconnection structure located above the first semiconductor structure and coupled with the first semiconductor structure; wherein a projection of the first interconnection structure on a horizontal plane is a first polygon; a second interconnection structure located above the first interconnection structure and in contact with the first interconnection structure; wherein a projection of the second interconnection structure on the horizontal plane is a second polygon; an overlapping area of the second polygon and the first polygon comprises 10000 square nanometers to 20000 square nanometers; and a second semiconductor structure located above the second interconnection structure and coupled with the second interconnection structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a manufacturing method thereof, a memory, a memory system, and an electronic device. BACKGROUND

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technologies become challenging and costly. Therefore, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory structures can solve the density limitation in planar memory cells, and can improve the integration and bit density of memories by bonding a wafer with peripheral circuits and a wafer with a memory cell array. However, the electrical connection performance between the bonded peripheral circuit wafer and the memory cell array wafer is poor. SUMMARY

[0004] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising:

[0005] a first semiconductor structure;

[0006] a first interconnection structure located above the first semiconductor structure and coupled with the first semiconductor structure; wherein a projection of the first interconnection structure on a horizontal plane is a first polygon;

[0007] a second interconnection structure located above the first interconnection structure and in contact with the first interconnection structure; wherein a projection of the second interconnection structure on the horizontal plane is a second polygon; an overlapping area of the second polygon and the first polygon comprises 10000 square nanometers to 20000 square nanometers;

[0008] a second semiconductor structure located above the second interconnection structure and coupled with the second interconnection structure.

[0009] According to a second aspect of embodiments of the present disclosure, a manufacturing method of a semiconductor structure is provided, comprising:

[0010] forming a first semiconductor structure;

[0011] forming a first interconnection structure on the first semiconductor structure; wherein the first interconnection structure is coupled with the first semiconductor structure; a projection of the first interconnection structure on a horizontal plane is a first polygon;

[0012] forming a second semiconductor structure;

[0013] forming a second interconnection structure on the second semiconductor structure; wherein the second interconnection structure is coupled with the second semiconductor structure; a projection of the second interconnection structure on the horizontal plane is a second polygon;

[0014] bonding the first interconnection structure and the second interconnection structure to make the second interconnection structure contact the first interconnection structure; wherein an overlapping area of the second polygon and the first polygon is 10000 square nanometers to 20000 square nanometers.

[0015] According to a third aspect of the embodiments of the present disclosure, a memory is provided, including the semiconductor structure provided in the first aspect of the embodiments of the present disclosure.

[0016] According to a fourth aspect of the embodiments of the present disclosure, a memory system is provided, including the memory provided in the third aspect of the embodiments of the present disclosure.

[0017] According to a fifth aspect of the embodiments of the present disclosure, an electronic device is provided, including the memory system provided in the fourth aspect of the embodiments of the present disclosure.

[0018] In the embodiments of the present disclosure, by setting the projection of the first interconnection structure on the horizontal plane as the first polygon, and setting the projection of the second interconnection structure on the horizontal plane as the second polygon, and the overlapping area of the second polygon and the first polygon is in the range of 10000 square nanometers to 20000 square nanometers, the effective contact area between the first interconnection structure and the second interconnection structure can be ensured, which is beneficial to improve the electrical connection performance between the first semiconductor structure and the second semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figures la to lc is a schematic diagram of a memory according to an exemplary embodiment;

[0020] Figure 2a and Figure 2b is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0021] Figure 3 is a schematic diagram of an interconnection pattern of a semiconductor structure according to an embodiment of the present disclosure;

[0022] Figure 4 is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The technical solutions of the present disclosure will be described in further detail below in conjunction with the accompanying drawings and examples. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0024] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings and examples. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.

[0025] It can be understood that the meanings of "on", "over" and "above" of the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0026] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0027] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, a layer can be a region of a continuous structure that has a thickness that is less than the thickness of the continuous structure, whether homogenous or heterogeneous. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers.

[0028] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0029] Three-dimensional memory includes a bonded peripheral circuit wafer and a memory cell array wafer, as shown in FIG. 1A, in which a first interconnect structure 11 of the peripheral circuit wafer is aligned and bonded with a second interconnect structure 21 of the memory cell array wafer during a bonding process, so as to achieve electrical connection between the peripheral circuit and the memory cell array. Figure la

[0030] ​However, due to the stress on the peripheral circuit wafer or the memory cell array wafer, the first interconnect structure 11 or the second interconnect structure 21 may be offset (e.g., offset along the x and / or y directions). During the bonding process, the bonding misalignment (MA) window between the first interconnect structure 11 and the second interconnect structure 21 becomes narrower and narrower, resulting in poor alignment between the first interconnect structure 11 and the second interconnect structure 21, which in turn leads to poor electrical connection performance between the bonded peripheral circuit wafer and the memory cell array wafer.

[0031] Figure lb One method of increasing the bonding alignment window is illustrated, namely, increasing the critical dimension (CD) of the interconnect structure, for example, increasing the critical dimension of the first interconnect structure 11. However, this method may reduce the distance between two adjacent first interconnect structures 11. To avoid electrical connection between two adjacent first interconnect structures 11, the spacing p needs to be further increased, and this will cause the first interconnect structure 11 to be in the interconnect region ( Figure la The density within the dashed box increases.

[0032] Figure lc Another method for increasing the bonding alignment window is shown, namely, establishing an Advanced Process Control (APC) system during photolithography to compensate for the bonding alignment window of the first interconnect structure 11 in the peripheral circuit wafer 10, so that the first interconnect structure 11 in the peripheral circuit wafer 10 is aligned and bonded with the second interconnect structure 21 in the memory cell array wafer 20 (e.g., Figure lc (As shown). However, this method sacrifices a larger design window for the overlay (OVL) markers and leads to reduced production efficiency.

[0033] In view of this, the present disclosure provides a semiconductor structure.

[0034] Figure 2a and Figure 2b This is a schematic diagram of a semiconductor structure 100 according to an embodiment of the present disclosure. (Refer to...) Figure 2a As shown, the semiconductor structure 100 includes:

[0035] First semiconductor structure;

[0036] The first interconnect structure 110 is located on top of the first semiconductor structure and coupled to the first semiconductor structure; wherein the projection of the first interconnect structure 110 onto the horizontal plane is a first polygon.

[0037] The second interconnection structure 120 is located above the first interconnection structure 110 and in contact with the first interconnection structure 110; wherein a projection of the second interconnection structure 120 on a horizontal plane is a second polygon; and an overlapping area of the second polygon and the first polygon comprises 10000-20000 square nanometers.

[0038] The second semiconductor structure is located above the second interconnection structure 120 and coupled with the second interconnection structure 120.

[0039] The first semiconductor structure can be a peripheral circuit, and the second semiconductor structure can be a memory stack structure; or the first semiconductor structure can be a memory stack structure, and the second semiconductor structure can be a peripheral circuit.

[0040] The peripheral circuit includes a plurality of transistors, such as P-type transistors or N-type transistors. Each transistor includes a source, a channel, a drain, a gate dielectric layer, and a gate, the channel is located between the source and the drain, the gate covers at least one sidewall of the channel, and the gate dielectric layer is located between the channel and the gate.

[0041] In an example, the first interconnection structure is coupled with the source of the transistor. In another example, the first interconnection structure is coupled with the drain of the transistor. In yet another example, the first interconnection structure is coupled with the gate of the transistor.

[0042] The memory stack structure includes a plurality of memory strings penetrating through a plurality of insulating layers (e.g., silicon oxide) and a plurality of conductive layers (e.g., tungsten metal) arranged in an alternating stack, and the memory stack structure is coupled with the peripheral circuit through the first interconnection structure and the second interconnection structure.

[0043] In an example, the first semiconductor structure, the first interconnection structure 110, the second interconnection structure 120, and the second semiconductor structure (not shown in the figure) are sequentially stacked along a direction perpendicular to a horizontal plane (i.e., xy plane). The first semiconductor structure is coupled with the second semiconductor structure through the first interconnection structure 110 and the second interconnection structure 120.

[0044] In other examples, the second semiconductor structure, the second interconnection structure 120, the first interconnection structure 110, and the first semiconductor structure are sequentially stacked along a direction perpendicular to a horizontal plane.

[0045] In an example, a top surface (a surface relatively far away from the first semiconductor structure) of the first interconnection structure 110 is in contact with a top surface (a surface relatively far away from the second semiconductor structure) of the second interconnection structure 120, for example, the top surface of the first interconnection structure 110 and the top surface of the second interconnection structure 120 are partially in contact or completely in contact.

[0046] In an example, the contact area between the top surface of the first interconnection structure 110 and the top surface of the second interconnection structure 120 includes 10,000 square nanometers to 20,000 square nanometers.

[0047] It should be noted that when the contact area between the top surface of the first interconnection structure 110 and the top surface of the second interconnection structure 120 is small, the contact resistance between the first interconnection structure 110 and the second interconnection structure 120 is large, which will affect the normal transmission of the electrical signal between the first semiconductor structure and the second semiconductor structure. When the contact area between the top surface of the first interconnection structure 110 and the top surface of the second interconnection structure 120 is large, although the contact resistance can be reduced, the alignment between the first interconnection structure 110 and the second interconnection structure 120 and the bonding process are required to be higher.

[0048] Therefore, the effective contact area between the first interconnection structure 110 and the second interconnection structure 120 is ensured. Here, the effective contact area means that the contact resistance between the first interconnection structure 110 and the second interconnection structure 120 meets the electrical connection requirement between the first semiconductor structure and the second semiconductor structure. In actual application, the electrical connection requirement of the semiconductor structure can be designed according to the specific electrical connection requirement.

[0049] In an example, the projection of the first interconnection structure 110 on the xy plane is a first polygon, and the projection of the second interconnection structure 120 on the xy plane is a second polygon. The second polygon at least partially overlaps the first polygon.

[0050] It can be understood that when the top surface of the first interconnection structure 110 and the top surface of the second interconnection structure 120 are in contact, the first interconnection structure 110 and the second interconnection structure 120 at least partially overlap, and therefore, the projection of the first interconnection structure 110 on the xy plane and the projection of the second interconnection structure 120 on the xy plane at least partially overlap, that is, as shown in FIG. 1. Figure 2a

[0051] The composition material of the first interconnection structure 110 and the second interconnection structure 120 includes a conductive material, for example, any one of tungsten, copper, aluminum, platinum, nickel, titanium, titanium nitride, tantalum nitride, or tungsten nitride or a combination thereof.

[0052] In the embodiments of the present disclosure, by setting the projection of the first interconnection structure on the horizontal plane to be a first polygon, and setting the projection of the second interconnection structure on the horizontal plane to be a second polygon, and the overlapping area of the second polygon and the first polygon is in the range of 10,000 square nanometers to 20,000 square nanometers, the effective contact area between the first interconnection structure and the second interconnection structure can be ensured, which is beneficial to improve the electrical connection performance between the first semiconductor structure and the second semiconductor structure.

[0053] ​In addition, by setting the pattern of the first interconnection structure as a first polygon and setting the pattern of the second interconnection structure as a second polygon, only the design pattern of the interconnection structure in the semiconductor structure needs to be improved, without the need to establish an advanced process control system, which is conducive to improving the production efficiency of the semiconductor structure.

[0054] In some embodiments, referring to Figure 2a The semiconductor structure further includes: a plurality of interconnection regions arranged in an array; wherein each interconnection region includes a first interconnection structure 110 and a second interconnection structure 120 in contact with each other;

[0055] The ratio of the projected area of the first interconnection structure 110 in the interconnection region to the area of the interconnection region is less than 25%;

[0056] And / or,

[0057] The ratio of the projected area of the second interconnection structure 120 in the interconnection region to the area of the interconnection region is less than 25%.

[0058] Compared with Figure la In the prior art, the proportion of the first interconnection structure 11 in the interconnection region is 25%, and the proportion of the second interconnection structure 12 in the interconnection region is 25%. In Figure 2a In the example shown in FIG. 10, the pitch p is unchanged (i.e., the interconnection region is unchanged), the size of the first interconnection structure 110 in the y direction is increased, and the size in the x direction is reduced, so that the proportion of the first interconnection structure 110 in the interconnection region is less than 25%, and the size of the second interconnection structure 120 in the x direction is increased, and the size in the y direction is reduced, so that the proportion of the second interconnection structure 120 in the interconnection region is less than 25%.

[0059] Here, the interconnection region refers to a region provided with one first interconnection structure and one second interconnection structure in contact with the one first interconnection structure, i.e., as shown by the dashed box in Figure 2a .

[0060] That is, in the embodiments of the present disclosure, without changing the area of the interconnection region, by reasonably designing the first interconnection structure 110 and the second interconnection structure 120, while ensuring that the effective contact area between the first interconnection structure 110 and the second interconnection structure 120 is met, the proportion of the first interconnection structure 110 in the interconnection region and the proportion of the second interconnection structure 120 in the interconnection region are reduced, which is conducive to reducing the use amount of the interconnection structure and saving production costs.

[0061] In addition, by reducing the proportion of the first interconnection structure 110 or the second interconnection structure 120 in the interconnection region, in the process of performing chemical mechanical polishing to form the first interconnection structure 110, the bubble defect can be reduced, and a relatively flat surface topography can be obtained, which is conducive to increasing the product yield.

[0062] In an example, the ratio of the projected area of the first interconnection structure 110 to the area of the interconnection region is less than 25%, and the ratio of the projected area of the second interconnection structure 120 to the area of the interconnection region is equal to 25%, i.e., the projection of the second interconnection structure 120 in the interconnection region is Figure la In an example, the ratio of the projected area of the first interconnection structure 110 to the area of the interconnection region is equal to 25%, and the ratio of the projected area of the second interconnection structure 120 to the area of the interconnection region is less than 25%, i.e., the projection of the first interconnection structure 110 in the interconnection region is

[0063] In an example, the ratio of the projected area of the second interconnection structure 120 to the area of the interconnection region is less than 25%, and the ratio of the projected area of the first interconnection structure 110 to the area of the interconnection region is equal to 25%, i.e., the projection of the first interconnection structure 110 in the interconnection region is Figure la In an example, the ratio of the projected area of the first interconnection structure 110 to the area of the interconnection region is equal to 25%, and the ratio of the projected area of the second interconnection structure 120 to the area of the interconnection region is less than 25%, i.e., the projection of the first interconnection structure 110 in the interconnection region is

[0064] In addition, as shown in Figure 2a and Figure 2b , as the size of the first interconnection structure 110 in the y direction increases, the bonding alignment window of the second interconnection structure 120 in the y direction increases; as the size of the second interconnection structure 120 in the x direction increases, the bonding alignment window of the first interconnection structure 110 in the x direction increases, so that while ensuring the effective contact area between the first interconnection structure 110 and the second interconnection structure 120, the bonding alignment window between the first interconnection structure 110 and the second interconnection structure 120 can be increased.

[0065] In some embodiments, as shown in Figure 2a and Figure 3 , the shape of the first polygon includes: a rectangle, a cross, a diamond, or an L shape;

[0066] The shape of the second polygon includes: a rectangle, a cross, a diamond, or an L shape.

[0067] The shape of the first polygon or the second polygon is not limited to the rectangle as shown in Figure 2a , but can also be other shapes, such as a cross, a diamond, or an L shape, etc.

[0068] In some embodiments, the shapes of the first polygon and the second polygon are the same. In other embodiments, the shapes of the first polygon and the second polygon are different.

[0069] In some embodiments, when the shapes of the first polygon and the second polygon are rectangles,

[0070] The length of the first polygon in the first direction is greater than the length of the first polygon in the second direction;

[0071] The length of the second polygon in the first direction is less than the length of the second polygon in the second direction;

[0072] wherein the first direction and the second direction are parallel to a horizontal plane, and the first direction is perpendicular to the second direction.

[0073] Referring to Figure 2a As shown in FIG. 1, the length L1 of the first polygon in the y direction is greater than the width W1 of the first polygon in the x direction, and the width W2 of the second polygon in the y direction is less than the length L2 of the second polygon in the x direction.

[0074] As used in the present disclosure, the "y direction" represents the first direction, the "x direction" represents the second direction, and the "z direction" represents the third direction. The "y direction" and the "x direction" are parallel to a horizontal plane, and the "z direction" is perpendicular to the horizontal plane. Hereinafter, the above will not be repeated.

[0075] In Figure la the first interconnection structure 11 and the second interconnection structure 21 have a square projection in the xy plane. In the x direction, in one interconnection region, only a partial region of the first interconnection structure 11 is in contact with the second interconnection structure 21. By arranging the region of the first interconnection structure 11 that is at least partially not in contact with the second interconnection structure 21 in the y direction, the size of the first interconnection structure 11 in the y direction can be increased, i.e., the length of the first polygon in the y direction is greater than the length of the first polygon in the x direction.

[0076] Similarly, in the y direction, in one interconnection region, only a partial region of the second interconnection structure 21 is in contact with the first interconnection structure 11. By arranging the region of the second interconnection structure 21 that is at least partially not in contact with the first interconnection structure 11 in the x direction, the size of the second interconnection structure 21 in the x direction can be increased, i.e., the length of the second polygon in the y direction is less than the length of the second polygon in the x direction.

[0077] In other embodiments, when the first polygon and the second polygon have a rectangular shape, the length of the first polygon in the first direction is less than the length of the first polygon in the second direction, and the length of the second polygon in the first direction is greater than the length of the second polygon in the second direction.

[0078] In Figure la the first interconnection structure 11 and the second interconnection structure 21 have a square projection in the xy plane. In the y direction, in one interconnection region, only a partial region of the first interconnection structure 11 is in contact with the second interconnection structure 21. By arranging the region of the first interconnection structure 11 that is at least partially not in contact with the second interconnection structure 21 in the x direction, the size of the first interconnection structure 11 in the x direction can be increased, i.e., the length of the first polygon in the first direction is less than the length of the first polygon in the second direction.

[0079] Similarly, along the x direction, in one interconnection region, the second interconnection structure 21 only has a partial region in contact with the first interconnection structure 11, by arranging the region of the second interconnection structure 21 which is at least partially not in contact with the first interconnection structure 11 in the x direction in the y direction, the size of the second interconnection structure 21 in the y direction, i.e. the length of the second polygon in the first direction, is greater than the length of the second polygon in the second direction.

[0080] It can be understood that in the embodiments of the present disclosure, when the shapes of the first polygon and the second polygon are rectangles, by arranging the length of the first polygon in the first direction to be greater than the length of the first polygon in the second direction, and the length of the second polygon in the first direction to be less than the length of the second polygon in the second direction, the bonding alignment window between the first interconnection structure and the second interconnection structure can be increased.

[0081] In some embodiments, referring to Figure 2a It can be understood that in the embodiments of the present disclosure, when the shapes of the first polygon and the second polygon are rectangles, by arranging the length of the first polygon in the first direction to be greater than the length of the first polygon in the second direction, and the length of the second polygon in the first direction to be less than the length of the second polygon in the second direction, the bonding alignment window between the first interconnection structure and the second interconnection structure can be increased.

[0082] And / or,

[0083] The length W1 of the first polygon in the second direction is the same as the length W2 of the second polygon in the first direction.

[0084] In an example, the length L1 of the first polygon in the first direction is the same as the length L2 of the second polygon in the second direction, and the length W1 of the first polygon in the second direction is different from the length W2 of the second polygon in the first direction. For example, the length W1 of the first polygon in the second direction is greater than the length W2 of the second polygon in the first direction, or the length W1 of the first polygon in the second direction is less than the length W2 of the second polygon in the first direction.

[0085] In an example, the length L1 of the first polygon in the first direction is different from the length L2 of the second polygon in the second direction, and the length W1 of the first polygon in the second direction is the same as the length W2 of the second polygon in the first direction. For example, the length L1 of the first polygon in the first direction is greater than the length L2 of the second polygon in the second direction, or the length L1 of the first polygon in the first direction is less than the length L2 of the second polygon in the second direction.

[0086] It can be understood that in the embodiments of the present disclosure, the sizes (including the length in the first direction and the length in the second direction) of the first interconnection structure and the second interconnection structure can be designed to be the same or different, which increases the application scenarios of the first interconnection structure and the second interconnection structure.

[0087] In some embodiments, referring to Figure 2aAs shown, the semiconductor structure comprises:

[0088] a plurality of first interconnection structures 110 arranged side by side along a first direction; wherein along the first direction, two adjacent first interconnection structures 110 are spaced apart by a preset distance p and electrically insulated; the first direction is parallel to a horizontal plane;

[0089] a plurality of second interconnection structures 120 arranged side by side along the first direction; wherein along the first direction, two adjacent second interconnection structures 120 are spaced apart by the preset distance p and electrically insulated.

[0090] In an example, the first dielectric layer is located between two first interconnection structures 110 arranged side by side along the y direction. Here, the preset distance p can be the sum of the length of the first interconnection structure 110 in the y direction and the length of the first dielectric layer in the y direction.

[0091] In an example, the second dielectric layer is located between two second interconnection structures 120 arranged side by side along the x direction. Here, the preset distance p can be the sum of the length of the second interconnection structure 120 in the x direction and the length of the second dielectric layer in the x direction.

[0092] The constituent material of the first dielectric layer and the second dielectric layer comprises an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0093] In some embodiments, with reference to Figure 2a As shown, the plurality of first interconnection structures 110 are also arranged side by side along a second direction; wherein along the second direction, two adjacent first interconnection structures 110 are spaced apart by the preset distance p and electrically insulated; the second direction is parallel to the horizontal plane, and the second direction is perpendicular to the first direction;

[0094] The plurality of second interconnection structures 120 are also arranged side by side along the second direction; wherein along the second direction, two adjacent second interconnection structures 120 are spaced apart by the preset distance p and electrically insulated.

[0095] In an example, the first dielectric layer is also located between two first interconnection structures 110 arranged side by side along the x direction. Here, the preset distance p can be the sum of the length of the first interconnection structure 110 in the x direction and the length of the first dielectric layer in the x direction.

[0096] In an example, the second dielectric layer is also located between two second interconnection structures 120 arranged side by side along the y direction. Here, the preset distance p can be the sum of the length of the second interconnection structure 120 in the y direction and the length of the second dielectric layer in the y direction.

[0097] In some embodiments, the length of the first interconnection structure 110 in the first direction is less than the preset distance p and greater than a preset length;

[0098] The length of the second interconnection structure 120 in the second direction is less than the preset distance p and greater than the preset length.

[0099] It should be noted that when the length of the first interconnection structure 110 in the y direction is greater than or equal to the preset distance p, a passage is formed between two first interconnection structures 110 arranged side by side in the y direction, which affects the transmission of electrical signals between the second semiconductor structure and the first semiconductor structure. When the length of the second interconnection structure 120 in the x direction is greater than or equal to the preset distance p, a passage is formed between two second interconnection structures 120 arranged side by side in the x direction, which affects the transmission of electrical signals between the second semiconductor structure and the first semiconductor structure.

[0100] In the embodiments of the present disclosure, by setting the length of the first interconnection structure in the first direction to be less than the preset distance and the length of the second interconnection structure in the second direction to be less than the preset distance, electrical insulation between two adjacent first interconnection structures (or second interconnection structures) can be ensured, which is beneficial to ensure the normal transmission of electrical signals between the second semiconductor structure and the first semiconductor structure.

[0101] Here, the preset length can be a feature size of an interconnection structure designed in the prior art. By setting the length of the first interconnection structure in the first direction to be greater than the preset length and the length of the second interconnection structure in the second direction to be greater than the preset length, the bonding alignment window between the first interconnection structure and the second interconnection structure can be increased.

[0102] In other embodiments, the length of the first interconnection structure 110 in the second direction is less than the preset distance p; and the length of the second interconnection structure 120 in the first direction is less than the preset distance p.

[0103] In some embodiments, the preset distance includes 500 nanometers to 20,000 nanometers; and the preset length includes 300 nanometers to 10,000 nanometers.

[0104] Figure 4 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, which includes at least the following steps:

[0105] S100: forming a first semiconductor structure;

[0106] S200: forming a first interconnection structure on the first semiconductor structure; wherein the first interconnection structure is coupled with the first semiconductor structure; and a projection of the first interconnection structure on a horizontal plane is a first polygon;

[0107] S300: forming a second semiconductor structure;

[0108] S400: forming a second interconnect structure on the second semiconductor structure; wherein the second interconnect structure is coupled with the second semiconductor structure; a projection of the second interconnect structure on a horizontal plane is a second polygon;

[0109] S500: bonding the first interconnect structure and the second interconnect structure to make the second interconnect structure contact the first interconnect structure; wherein an overlapping area of the second polygon and the first polygon comprises 10000-20000 square nanometers.

[0110] In step S100, the first semiconductor structure can be a peripheral circuit or a memory stack structure. The peripheral circuit includes a plurality of transistors, for example, P-type transistors or N-type transistors. Each transistor includes a source, a channel, a drain, a gate dielectric layer and a gate. The first substrate can be doped to form a plurality of doped regions by ion implantation or ion diffusion. For example, a first doped region serves as a source of a transistor, a second doped region serves as a drain of a transistor, and a substrate between the first doped region and the second doped region serves as a channel of a transistor. The gate dielectric layer and the gate of the transistor are formed on the channel by a thin film deposition process, and the gate dielectric layer is between the channel and the gate. The memory stack structure includes insulating layers (e.g., silicon oxide) and conductive layers (e.g., tungsten metal) arranged in an alternating stack, and a plurality of memory strings penetrating the insulating layers and the conductive layers. The memory strings are coupled with the peripheral circuit through the first interconnect structure and the second interconnect structure.

[0111] In step S200, a first dielectric layer can be formed on the first semiconductor structure by a thin film deposition process, a first trench is formed in the first dielectric layer by a lithography and etching process, a projection of the first trench on a horizontal plane is a first polygon, and the first trench is filled with a conductive material to form a first interconnect structure 110 as shown in Figure 2a .

[0112] In step S300, a second semiconductor structure can be formed on a second substrate by a thin film deposition, lithography, etching and other processes. The second semiconductor structure can be a memory stack structure or a peripheral circuit.

[0113] In step S400, a second dielectric layer can be formed on the second semiconductor structure by a thin film deposition process, a second trench is formed in the second dielectric layer by a lithography and etching process, a projection of the second trench on a horizontal plane is a second polygon, and the second trench is filled with a conductive material to form a second interconnect structure 120 as shown in Figure 2a .

[0114] In step S500, the first substrate and the second substrate are bonded by a bonding process to make the second interconnect structure contact the first interconnect structure.

[0115] In the embodiments of the present disclosure, by forming the first interconnection structure on the first semiconductor structure and forming the second interconnection structure on the second semiconductor structure, since the projection of the first interconnection structure on the horizontal plane is a first polygon, the projection of the second interconnection structure on the horizontal plane is a second polygon, and the overlapping area of the second polygon and the first polygon is in the range of 10000 square nanometers to 20000 square nanometers, the effective contact area between the first interconnection structure and the second interconnection structure can be guaranteed, and the electrical connection performance between the first semiconductor structure and the second semiconductor structure can be improved.

[0116] In addition, by setting the pattern of the first interconnection structure as the first polygon and setting the pattern of the second interconnection structure as the second polygon, only the design pattern of the interconnection structure in the semiconductor structure needs to be improved, without the need to establish an advanced process control system, and the production efficiency of the semiconductor structure can be improved.

[0117] In some embodiments, the step S200 includes:

[0118] forming a plurality of first interconnection structures arranged side by side along a first direction in the first dielectric layer covering the first semiconductor structure; wherein along the first direction, two adjacent first interconnection structures are apart by a preset distance and electrically insulated; and the first direction is parallel to the horizontal plane.

[0119] For example, a plurality of first grooves arranged side by side along the y direction are formed in the first dielectric layer covering the first semiconductor structure by a photolithography and etching process, and the plurality of first grooves are filled with a conductive material to form a plurality of first interconnection structures 110 arranged side by side along the y direction as shown in FIG. 1B. Figure 2a

[0120] In some embodiments, the step S400 includes:

[0121] forming a plurality of second interconnection structures arranged side by side along a first direction in the second dielectric layer covering the second semiconductor structure; wherein along the first direction, two adjacent second interconnection structures are apart by a preset distance and electrically insulated.

[0122] For example, a plurality of second grooves arranged side by side along the y direction are formed in the second dielectric layer covering the second semiconductor structure by a photolithography and etching process, and the plurality of second grooves are filled with a conductive material to form a plurality of second interconnection structures 120 arranged side by side along the y direction as shown in FIG. 2B. Figure 2a

[0123] In some embodiments, the step S200 further includes:

[0124] ​​forming a plurality of first interconnect structures arranged side by side along the second direction in the first dielectric layer covering the first semiconductor structure; wherein, along the second direction, two adjacent first interconnect structures are spaced apart by a preset distance and electrically insulated; the second direction is parallel to a horizontal plane, and the second direction is perpendicular to the first direction.

[0125] Exemplarily, a plurality of first trenches arranged side by side along the second direction are also formed in the first dielectric layer covering the first semiconductor structure by a photolithography and etching process, and the plurality of first trenches are filled with a conductive material to form the plurality of first interconnect structures 110 arranged side by side along the x direction as shown in FIG. 1. Figure 2a

[0126] In some embodiments, the step S400 further includes:

[0127] forming a plurality of second interconnect structures arranged side by side along the second direction in the second dielectric layer covering the second semiconductor structure; wherein, along the second direction, two adjacent second interconnect structures are spaced apart by a preset distance and electrically insulated.

[0128] Exemplarily, a plurality of second trenches arranged side by side along the second direction are also formed in the second dielectric layer covering the second semiconductor structure by a photolithography and etching process, and the plurality of second trenches are filled with a conductive material to form the plurality of second interconnect structures 120 arranged side by side along the x direction as shown in FIG. 2. Figure 2a

[0129] In some embodiments, the preset distance includes: 500 nanometers to 20,000 nanometers.

[0130] The present disclosure also provides a memory including the semiconductor structure in any of the above embodiments.

[0131] In some embodiments, the memory includes a three-dimensional memory, such as a 3D NAND memory, a three-dimensional phase change memory, a three-dimensional ferroelectric memory, etc.

[0132] The present disclosure also provides a memory system including:

[0133] one or more memories as in any of the above embodiments;

[0134] a memory controller coupled to the memory and configured to control the memory.

[0135] The memory system can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0136] ​​The memory controller can be configured to control operations of the memory, such as read, erase, and program operations.

[0137] In some embodiments, the memory controller is designed for operation in low duty cycle environments, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

[0138] In some embodiments, the memory controller is designed for operation in high duty cycle environments, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which are used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, and the like, as well as enterprise storage arrays.

[0139] The present disclosure also provides an electronic device, which can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, and the like.

[0140] The electronic device can include the memory system described above, and can further include at least one of a central processing unit (CPU) and a cache.

[0141] The above description is merely a specific implementation of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, and all such changes and replacements should be encompassed within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be determined by the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor structure, including peripheral circuitry or a memory array; A first interconnect structure is located on top of and coupled to the first semiconductor structure; wherein the projection of the first interconnect structure onto the horizontal plane is a first polygon. A second interconnect structure is located above and in contact with the first interconnect structure; wherein the projection of the second interconnect structure onto the horizontal plane is a second polygon; the overlapping area of ​​the second polygon and the first polygon includes 10,000 square nanometers to 20,000 square nanometers. A second semiconductor structure, including another of the peripheral circuits or memory array, is located on top of and coupled to the second interconnect structure; The semiconductor structure further includes: a plurality of interconnect regions arranged in an array; wherein each interconnect region includes a first interconnect structure and a second interconnect structure that are in contact with each other; The ratio of the projected area of ​​the first interconnect structure in the interconnect region to the area of ​​the interconnect region is less than 25%; And / or, The ratio of the projected area of ​​the second interconnect structure in the interconnect region to the area of ​​the interconnect region is less than 25%.

2. The semiconductor structure according to claim 1, characterized in that, The shape of the first polygon includes: rectangle, cross, rhombus or L-shape; The shape of the second polygon includes: rectangle, cross, rhombus or L.

3. The semiconductor structure according to claim 2, characterized in that, When the shapes of the first polygon and the second polygon are rectangles The length of the first polygon in the first direction is greater than the length of the first polygon in the second direction; The length of the second polygon in the first direction is less than the length of the second polygon in the second direction; Wherein, the first direction and the second direction are parallel to the horizontal plane, and the first direction is perpendicular to the second direction.

4. The semiconductor structure according to claim 3, characterized in that, The length of the first polygon in the first direction is the same as the length of the second polygon in the second direction; And / or, The length of the first polygon in the second direction is the same as the length of the second polygon in the first direction.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes: A plurality of the first interconnect structures are arranged side by side along a first direction; wherein, along the first direction, two adjacent first interconnect structures are spaced apart by a preset distance and are electrically insulated; the first direction is parallel to the horizontal plane; A plurality of second interconnect structures are arranged side by side along the first direction; wherein, along the first direction, two adjacent second interconnect structures are separated by the preset distance and are electrically insulated from each other.

6. The semiconductor structure according to claim 5, characterized in that, The plurality of first interconnect structures are also arranged side by side along a second direction; wherein, along the second direction, two adjacent first interconnect structures are separated by the preset distance and are electrically insulated; the second direction is parallel to the horizontal plane and perpendicular to the first direction; Multiple second interconnect structures are arranged side by side along the second direction; wherein, along the second direction, two adjacent second interconnect structures are separated by the preset distance and are electrically insulated from each other.

7. The semiconductor structure according to claim 6, characterized in that, The length of the first interconnect structure in the first direction is less than the preset distance and greater than the preset length; The length of the second interconnect structure in the second direction is less than the preset distance and greater than the preset length.

8. The semiconductor structure according to claim 7, characterized in that, The preset distance includes 500 nanometers to 20,000 nanometers; The preset length includes 300 nanometers to 10,000 nanometers.

9. A method for fabricating a semiconductor structure, characterized in that, include: Forming a first semiconductor structure, including peripheral circuitry or a memory array; A first interconnect structure is formed on the first semiconductor structure; wherein the first interconnect structure is coupled to the first semiconductor structure; the projection of the first interconnect structure onto a horizontal plane is a first polygon; Forming a second semiconductor structure, including another in a peripheral circuit or memory array; A second interconnect structure is formed on the second semiconductor structure; wherein the second interconnect structure is coupled to the second semiconductor structure; the projection of the second interconnect structure onto the horizontal plane is a second polygon; The first interconnect structure and the second interconnect structure are bonded so that the second interconnect structure contacts the first interconnect structure; wherein the overlap area between the second polygon and the first polygon includes 10,000 square nanometers to 20,000 square nanometers. The semiconductor structure further includes: a plurality of interconnect regions arranged in an array; wherein each interconnect region includes a first interconnect structure and a second interconnect structure that are in contact with each other; The ratio of the projected area of ​​the first interconnect structure in the interconnect region to the area of ​​the interconnect region is less than 25%; And / or, The ratio of the projected area of ​​the second interconnect structure in the interconnect region to the area of ​​the interconnect region is less than 25%.

10. The method according to claim 9, characterized in that, The step of forming a first interconnect structure on the first semiconductor structure includes: A plurality of first interconnect structures are formed in a first dielectric layer covering the first semiconductor structure, arranged side by side along a first direction; wherein, along the first direction, two adjacent first interconnect structures are spaced apart by a predetermined distance and are electrically insulated; the first direction is parallel to the horizontal plane; The step of forming a second interconnect structure on the second semiconductor structure includes: A plurality of second interconnect structures are formed in a second dielectric layer covering the second semiconductor structure, arranged side by side along the first direction; wherein, along the first direction, two adjacent second interconnect structures are separated by the preset distance and are electrically insulated from each other.

11. The method according to claim 10, characterized in that, The step of forming a first interconnect structure on the first semiconductor structure further includes: A plurality of first interconnect structures are formed in a first dielectric layer covering the first semiconductor structure, arranged side by side along a second direction; wherein, along the second direction, two adjacent first interconnect structures are separated by a preset distance and are electrically insulated from each other; the second direction is parallel to the horizontal plane and perpendicular to the first direction. The step of forming a second interconnect structure on the second semiconductor structure further includes: A plurality of second interconnect structures are formed in a second dielectric layer covering the second semiconductor structure, arranged side by side along the second direction; wherein, along the second direction, two adjacent second interconnect structures are separated by the preset distance and are electrically insulated from each other.

12. The method according to claim 10, characterized in that, The preset distance includes 500 nanometers to 20,000 nanometers.

13. A memory, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 8.

14. The memory according to claim 13, characterized in that, The memory includes 3D NAND memory.

15. A memory system, characterized in that, include: One or more memories as described in claim 13 or 14; A memory controller, coupled to the memory and configured to control the memory.

16. An electronic device, characterized in that, Includes the memory system as described in claim 15.

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