Multi-chip filter silicon-based fan-out package structure and method
By etching cavities on a silicon substrate and filling them with dielectric layers, combined with passivation and redistribution layers, a high degree of integration and miniaturized packaging of multi-chip filters was achieved, solving the problems of complexity and large size of traditional packaging technologies.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI ZHONGWEI GAOKE ELECTRONICS
- Filing Date
- 2022-06-21
- Publication Date
- 2026-05-29
AI Technical Summary
Existing filter packaging technologies suffer from complex processes, large size, and high cost, making it difficult to meet the demands for high integration and miniaturization.
A multi-chip filter silicon-based fan-out package structure is adopted. By etching stepped and flat-bottomed cavities on the silicon substrate and filling the gap dielectric layer, an oscillation cavity is formed. The chip is integrated and packaged using a passivation layer, a redistribution layer and interconnect bumps.
This reduces process complexity, improves packaging hermetrism and integration, shrinks filter size, and achieves highly efficient wafer-level packaging.
Smart Images
Figure CN115064532B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit packaging technology, specifically a silicon-based fan-out packaging structure and method for a multi-chip filter. Background Technology
[0002] In recent years, 5G technology has received significant attention both domestically and internationally. As a component used in its radio frequency (RF) front-end to filter out signals outside specific frequency bands, filters have become highly sought after in the market. Simultaneously, with the increasing complexity of application scenarios and the growing demands for miniaturization and reliability in electronic products, filter packaging technology is also rapidly developing. Whether it's the initial use of high-resistivity silicon capping bonded to the chip at the wafer level by J. Tian, or the subsequent development of improved chip-scale packaging (CSP), the optimization trend in filter chip packaging is towards high integration, low cost, small size, and superior performance. For filter products, the filter chip and related functional chips are typically integrated into a single package. Traditional packaging integration schemes suffer from drawbacks such as large size, complex processes, and high cost. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a silicon-based fan-out packaging structure and method for multi-chip filters that can reduce process complexity, shrink size, and have good oscillation cavity sealing.
[0004] According to the technical solution provided by the present invention, the multi-chip filter silicon-based fan-out package structure includes a gap dielectric layer, a filter chip, other functional chips, a silicon substrate, a passivation layer, a first redistribution layer, an insulating layer, a second redistribution layer, and interconnect bumps.
[0005] A stepped first cavity and a flat-bottomed second cavity are etched on the front side of the silicon substrate. A gap dielectric layer is provided in the gap between the front side of the filter chip, the side of the filter chip and the upper stepped sidewall of the first cavity, and in the gap between the front side of other functional chips, the side of other functional chips and the sidewall of the second cavity, so that an oscillation cavity is formed below the filter chip. The solder pads of the filter chip and other functional chips are all facing down. Through holes are formed on the back side of the silicon substrate and corresponding to the positions of the solder pads of the filter chip and other functional chips. A passivation layer is provided on the back side of the silicon substrate, the hole wall of the through hole, the front side of the silicon substrate and the gap dielectric layer on the front side of the silicon substrate. A first redistribution layer is provided in the through hole and on part of the passivation layer. An insulating layer is covered on the back side of the passivation layer outside the first redistribution layer. A second redistribution layer is connected to the back side of the first redistribution layer. Interconnect bumps are connected to the back side of the second redistribution layer.
[0006] Preferably, the passivation layer has a thickness of 1-10 μm and is made of inorganic materials, polymer materials, or organic and inorganic composite materials.
[0007] Preferably, the insulation layer has a thickness of 5-30 μm and is made of resin or polyimide.
[0008] The above-mentioned multi-chip filter silicon-based fan-out packaging method includes the following steps:
[0009] S1. Provide a silicon substrate, and etch a stepped first cavity and a flat-bottomed second cavity on the front side of the silicon substrate.
[0010] S2. The filter chip with an organic adhesive coating on its surface is embedded in the upper step of the first cavity with the solder pad facing down. Other functional chips with an organic adhesive coating on their surface are embedded in the second cavity with the solder pad facing down. The gaps between the front and side of the filter chip and the sidewall of the upper step of the first cavity, and the gaps between the front and side of the other functional chips and the sidewall of the second cavity are filled with a gap medium to form a gap medium layer.
[0011] S3. Create through holes on the back side of the silicon substrate, corresponding to the positions of the solder pads of the filter chip and other functional chips.
[0012] S4. Prepare passivation layers on the back side of the silicon substrate, the hole walls of the vias, and the front side of the silicon substrate, and remove the passivation layers on the pads of the filter chip and other functional chips.
[0013] S5. A first redistribution layer is prepared inside the via and on part of the passivation layer;
[0014] S6. Cover the back of a portion of the passivation layer with an insulating layer;
[0015] S7. First, prepare a second redistribution layer on the back side of the first redistribution layer that is not covered by the insulating layer. Then, make interconnect bumps on the back side of the second redistribution layer to make the second redistribution layer electrically connected to the outside. Finally, cut along the dicing path to obtain the multi-chip interconnection circuit and complete the final packaging.
[0016] Preferably, in step S2, the gap between the side of the filter chip and the upper step sidewall of the first cavity, and the gap between the side of the other functional chip and the sidewall of the second cavity are all 10-50 μm.
[0017] Preferably, after the gap dielectric filling in step S2, the gap dielectric layer on the front of the filter chip and the gap dielectric layer on the front of other functional chips are lower than or flush with the front of the silicon substrate. The planar difference between the gap dielectric layer on the front of the filter chip and the front of the silicon substrate is 0-30µm, and the planar difference between the gap dielectric layer on the front of other functional chips and the front of the silicon substrate is 0-30µm.
[0018] Preferably, in step S3, through-holes are fabricated on the back side of the silicon substrate at the locations of the solder pads corresponding to the filter chip and other functional chips using a dry etching process. The diameter of the through-holes is 10-50 μm, and the opening offset is less than 10 μm.
[0019] Preferably, in step S4, laser ablation is used to remove the passivation layer on the pads of the filter chip and other functional chips.
[0020] Preferably, the first redistribution layer is prepared using a silicon-based fan-out packaging wiring method, and the material of the first redistribution layer is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, and Au.
[0021] Preferably, the second redistribution layer is prepared using a silicon-based fan-out packaging wiring method, and the material of the first redistribution layer is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, and Au.
[0022] This invention effectively improves the packaging of filter chips and other functional chips, realizes advanced wafer-level packaging, reduces process complexity, provides good sealing of the oscillation cavity, achieves integration of filter chips and other functional chips, and reduces size. Attached Figure Description
[0023] Figure 1 This is a structural diagram of the silicon substrate after step S1.
[0024] Figure 2 This is a structural diagram of the multi-chip after processing in step S2.
[0025] Figure 3 This is a structural diagram of the through hole after step S3.
[0026] Figure 4 This is a structural diagram of the passivation layer after step S4.
[0027] Figure 5 This is a structural diagram of the first redistribution layer formed after the passivation layer is partially removed following step S5.
[0028] Figure 6 This is a structural diagram of the insulation layer after step S6.
[0029] Figure 7 This is the packaging structure diagram after step S7. Detailed Implementation
[0030] The present invention will be further described below with reference to specific embodiments.
[0031] A multi-chip filter silicon-based fan-out package structure includes a gap dielectric layer 1, a filter chip 2, other functional chips 3, a silicon substrate 4, a passivation layer 5, a first redistribution layer 6, an insulating layer 7, a second redistribution layer 8, and interconnect bumps 9.
[0032] A stepped first cavity 41 and a flat-bottomed second cavity 42 are etched on the front side of the silicon substrate 4. A gap dielectric layer 1 is provided in the gap between the front side of the filter chip 2, the side of the filter chip 2 and the upper stepped sidewall of the first cavity 41, and in the gap between the front side of other functional chips 3, the side of other functional chips 3 and the sidewall of the second cavity 42, so that an oscillation cavity is formed below the filter chip 2. The solder pads of the filter chip 2 and other functional chips 3 are all facing down. Through holes 43 are formed on the back side of the silicon substrate 4 and corresponding to the solder pad positions of the filter chip 2 and other functional chips 3. A passivation layer 5 is provided on the back side of the silicon substrate 4, the hole wall of the through hole 43, the front side of the silicon substrate 4 and the gap dielectric layer 1 located on the front side of the silicon substrate 4. A first redistribution layer 6 is provided in the through hole 43 and on part of the passivation layer 5. An insulating layer 7 is covered on the back side of the passivation layer 5 outside the first redistribution layer 6. A second redistribution layer 8 is connected to the back side of the first redistribution layer 6. An interconnect bump 9 is connected to the back side of the second redistribution layer 8.
[0033] The passivation layer 5 has a thickness of 1-10 μm and is made of inorganic materials, polymer materials, or organic and inorganic composite materials.
[0034] The insulation layer 7 has a thickness of 5-30 μm and is made of resin or polyimide.
[0035] In this invention, the number of filter chips 2 can be increased or decreased as needed, and the number of other functional chips 3 can also be increased or decreased as needed.
[0036] In this invention, other functional chips 3 can be low-noise amplifier chips, radio frequency switch chips, radio frequency antenna chips, low-noise amplifier chips, etc.
[0037] The above-mentioned multi-chip filter silicon-based fan-out packaging method includes the following steps:
[0038] S1. A silicon substrate 4 is provided, and a stepped first cavity 41 and a flat-bottomed second cavity 42 are etched on the front side of the silicon substrate 4, such as... Figure 1 As shown;
[0039] S2. A filter chip 2 coated with an organic adhesive material is embedded in the upper step of the first cavity 41 with the solder pad facing down. Other functional chips 3 coated with the organic adhesive material are embedded in the second cavity 42 with the solder pad facing down. A gap medium is filled in the gaps between the front and side surfaces of the filter chip 2 and the sidewall of the upper step of the first cavity 41, and in the gaps between the front and side surfaces of the other functional chips 3 and the sidewall of the second cavity 42, forming a gap medium layer 1. Figure 2 As shown;
[0040] S3. Through holes 43 are fabricated on the back side of the silicon substrate 4, corresponding to the positions of the solder pads of the filter chip 2 and other functional chips 3, such as... Figure 3 As shown;
[0041] S4. A passivation layer 5 is prepared on the back side of the silicon substrate 4, the hole wall of the via 43, and the front side of the silicon substrate 4. The passivation layer 5 on the pads of the filter chip 2 and other functional chips 3 is then removed. Figure 4 As shown;
[0042] S5. A first redistribution layer 6 is prepared within the via 43 and on part of the passivation layer 5, such as... Figure 5 As shown;
[0043] S6. Cover a portion of the back side of the passivation layer 5 with an insulating layer 7, such as... Figure 6 As shown;
[0044] S7. First, a second redistribution layer 8 is fabricated on the back side of the first redistribution layer 6, which is not covered by the insulating layer 7. Then, interconnect bumps 9 are fabricated on the back side of the second redistribution layer 8 to achieve electrical connection between the second redistribution layer 8 and the outside. Finally, the circuit is cut along the dicing line to obtain the multi-chip interconnect circuit, completing the final packaging. Figure 7 As shown.
[0045] The material of the interstitial medium layer 1 includes dry film, organic stacked film, and other membrane materials with similar functions.
[0046] In step S2, the gap between the side of the filter chip 2 and the upper step sidewall of the first cavity 41, and the gap between the side of the other functional chip 3 and the sidewall of the second cavity 42 are all 10-50um.
[0047] After the gap dielectric filling in step S2, the gap dielectric layer 1 on the front of the filter chip 2 and the gap dielectric layer 1 on the front of the other functional chip 3 are lower than or flush with the front of the silicon substrate 4. The planar difference between the gap dielectric layer 1 on the front of the filter chip 2 and the front of the silicon substrate 4 is 0-30um, and the planar difference between the gap dielectric layer 1 on the front of the other functional chip 3 and the front of the silicon substrate 4 is 0-30um.
[0048] In step S3, through-holes are fabricated on the back side of the silicon substrate 4 at the positions corresponding to the solder pads of the filter chip 2 and other functional chips 3 using a dry etching process. The diameter of the through-hole is 10-50 μm, and the opening offset is less than 10 μm.
[0049] In step S4, laser ablation is used to remove the passivation layer 5 on the pads of the filter chip 2 and other functional chips 3.
[0050] The first redistribution layer 6 is fabricated using a silicon-based fan-out packaging and wiring method. The material of the first redistribution layer 6 is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, and Au.
[0051] The second redistribution layer 8 is fabricated using a silicon-based fan-out packaging wiring method, and the material of the first redistribution layer 6 is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, and Au.
[0052] This invention differs from the traditional packaging process of first packaging and then assembling. Instead, it is based on an advanced silicon-based fan-out packaging method, combined with the characteristics of the filter chip 2, to achieve system-level packaging. To achieve modular wafer-level packaging, a silicon substrate 4 with excellent thermal conductivity and sealing properties is used as the substrate, allowing two or more different functional chips to be packaged on the same platform, which can improve packaging efficiency and save packaging costs.
Claims
1. A multi-chip filter silicon-based fan-out package structure, comprising a gap dielectric layer (1), a filter chip (2), other functional chips (3), a silicon substrate (4), a passivation layer (5), a first redistribution layer (6), an insulating layer (7), a second redistribution layer (8), and interconnect bumps (9); Its characteristics are: A stepped first cavity (41) and a flat-bottomed second cavity (42) are etched on the front side of the silicon substrate (4). A gap dielectric layer (1) is provided on the front side of the filter chip (2), the gap between the side of the filter chip (2) and the upper stepped sidewall of the first cavity (41), and on the front side of other functional chips (3), the gap between the side of other functional chips (3) and the sidewall of the second cavity (42), so that an oscillation cavity is formed below the filter chip (2). The solder pads of the filter chip (2) and other functional chips (3) are all facing down. On the back side of the silicon substrate (4) and corresponding to the filter chip (41) 2) Through holes (43) are formed at the solder pad positions of other functional chips (3). Passivation layers (5) are provided on the back side of the silicon substrate (4), the hole wall of the through holes (43), the front side of the silicon substrate (4), and the gap dielectric layer (1) located on the front side of the silicon substrate (4). A first redistribution layer (6) is provided in the through holes (43) and on part of the passivation layer (5). An insulating layer (7) is covered on the back side of the passivation layer (5) outside the first redistribution layer (6). A second redistribution layer (8) is connected to the back side of the first redistribution layer (6). Interconnect bumps (9) are connected to the back side of the second redistribution layer (8). The packaging method for the multi-chip filter silicon-based fan-out package structure includes the following steps: S1. Provide a silicon substrate (4) and etch a stepped first cavity (41) and a flat-bottomed second cavity (42) on the front side of the silicon substrate (4). S2. The filter chip (2) with the surface coated with organic adhesive material is embedded in the upper step of the first cavity (41) with the solder pad facing down. Other functional chips (3) with the surface coated with organic adhesive material are embedded in the second cavity (42) with the solder pad facing down. The gap between the front side of the filter chip (2), the side side of the filter chip (2) and the side wall of the upper step of the first cavity (41), and the gap between the front side of the other functional chips (3), the side side of the other functional chips (3) and the side wall of the second cavity (42) are filled with gap medium to form a gap medium layer (1). S3. A through hole (43) is made on the back side of the silicon substrate (4) and at the positions of the solder pads of the filter chip (2) and other functional chips (3). S4. A passivation layer (5) is prepared on the back side of the silicon substrate (4), the hole wall of the via (43) and the front side of the silicon substrate (4), and the passivation layer (5) on the pads of the filter chip (2) and other functional chips (3) is removed. S5. A first redistribution layer (6) is prepared in the via (43) and on a portion of the passivation layer (5); S6. Cover the back of the passivation layer (5) with an insulating layer (7); S7. First, prepare a second rewiring layer (8) on the back side of the first rewiring layer (6) that is not covered by the insulating layer (7). Then, make interconnect bumps (9) on the back side of the second rewiring layer (8) so that the second rewiring layer (8) is electrically connected to the outside. Finally, cut along the dicing path to obtain a multi-chip interconnect circuit and complete the final packaging.
2. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: The passivation layer (5) has a thickness of 1-10 μm and is made of inorganic material, polymer material or organic and inorganic composite material.
3. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: The insulation layer (7) has a thickness of 5-30 μm and is made of resin or polyimide.
4. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: In step S2, the gap between the side of the filter chip (2) and the upper step sidewall of the first cavity (41) and the gap between the side of the functional chip (3) and the sidewall of the second cavity (42) are both 10-50um.
5. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: After the gap dielectric filling in step S2, the gap dielectric layer (1) on the front of the filter chip (2) and the gap dielectric layer (1) on the front of the other functional chip (3) are lower than or flush with the front of the silicon substrate (4). The planar difference between the gap dielectric layer (1) on the front of the filter chip (2) and the front of the silicon substrate (4) is 0-30um, and the planar difference between the gap dielectric layer (1) on the front of the other functional chip (3) and the front of the silicon substrate (4) is 0-30um.
6. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: In step S3, through holes are made on the back of the silicon substrate (4) and at the positions of the solder pads of the filter chip (2) and other functional chips (3) using a dry etching process. The diameter of the through holes is 10-50um and the opening offset is less than 10um.
7. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: In step S4, laser ablation is used to remove the passivation layer (5) on the pads of the filter chip (2) and other functional chips (3).
8. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: The first redistribution layer (6) is fabricated using a silicon-based fan-out packaging wiring method. The material of the first redistribution layer (6) is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, and Au.
9. The multi-chip filter silicon-based fan-out package structure as described in claim 1, characterized in that: The second redistribution layer (8) is fabricated using a silicon-based fan-out packaging wiring method, and the material of the first redistribution layer (6) is one or more of Cu, Ti, TiW, V, Ni, W, Sn, Ag, and Au.