Embedded flash memory

Abstract

The present invention provides an embedded flash memory, which includes a first conductive layer. A first conductive portion of the first conductive layer is located on a bit line and is electrically connected to the bit line, and a second conductive portion of the first conductive layer is located on a word line and is electrically connected to the word line. A second conductive layer is located on the first conductive layer. The second conductive layer includes at least two third conductive portions that are arranged in the same layer and are separated from each other. The third conductive portion is located on a control gate and is electrically connected to the control gate. With such an arrangement, only two conductive layers are required to achieve the electrical connection between the bit line, the word line, and the control gate and an external circuit, reducing the conductive layers in the embedded flash memory, lowering the cost, and since only two conductive layers are used and only the design rule of the first conductive layer in the two conductive layers is the most compact, it is easy to be compatible with a logic process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an embedded flash memory. Background Art

[0002] In an embedded flash memory, an interconnection structure is usually formed to electrically connect various devices in the embedded flash memory. In the interconnection structure, there are usually multiple conductive layers, and the electrical connection is achieved through these conductive layers. In the existing embedded flash memories, in order to achieve the electrical connection between the word line, the control gate, and the bit line and an external circuit, usually three conductive layers are required, and as the miniaturization of the embedded flash memory progresses, it becomes difficult to be compatible with the logic process. Summary of the Invention

[0003] An object of the present invention is to provide an embedded flash memory to reduce the number of conductive layers in the embedded flash memory and achieve compatibility with the logic process.

[0004] To solve the above technical problems, the present invention provides an embedded flash memory, which includes:

[0005] A substrate, on which a control gate is formed;

[0006] A word line, located on the substrate and penetrating through the control gate, and the top surface of the word line is higher than the top surface of the control gate;

[0007] A bit line, located on the substrate and on a side of the control gate away from the word line;

[0008] A first conductive layer, including at least two first conductive portions and at least two second conductive portions that are arranged in the same layer and separated from each other. The first conductive portions are located on the bit line and electrically connected to the bit line, and the second conductive portions are located on the word line and electrically connected to the word line;

[0009] A second conductive layer, located on the first conductive layer, and the second conductive layer includes at least two third conductive portions that are arranged in the same layer and separated from each other. The third conductive portions are located on the control gate and electrically connected to the control gate.

[0010] Optionally, in the embedded flash memory, the embedded flash memory further includes a metal silicide layer, the metal silicide layer is located on the top of the word line, and the word line is electrically connected to the second conductive portion through the metal silicide layer.

[0011] Optionally, in the embedded flash memory, one second conductive portion is provided at each of the two end portions of the metal silicide layer.

[0012] Optionally, in the embedded flash memory, the embedded flash memory further includes at least two first conductive plugs located between the metal silicide layer and the second conductive portion, and the second conductive portion is electrically connected to the metal silicide layer through the first conductive plugs.

[0013] Optionally, in the embedded flash memory, the first conductive layer further includes a connecting portion, which is disposed on the same layer as the first conductive portion and the second conductive portion, the connecting portion is located on the control gate, and the third conductive portion is electrically connected to the control gate through the connecting portion.

[0014] Optionally, in the embedded flash memory, the embedded flash memory further includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer stacked in sequence from bottom to top. The first interlayer dielectric layer covers the metal silicide layer, the control gate, the bit line, and the substrate; the first conductive plugs are located in the first interlayer dielectric layer, the first conductive portion, the second conductive portion, and the connecting portion are all located in the second interlayer dielectric layer, and the third conductive portion is located in the third interlayer dielectric layer.

[0015] Optionally, in the embedded flash memory, the embedded flash memory further includes at least two second conductive plugs located in the first interlayer dielectric layer, the second conductive plugs are located between the control gate and the connecting portion, and the connecting portion is electrically connected to the control gate through the second conductive plugs.

[0016] Optionally, in the embedded flash memory, the embedded flash memory further includes at least two third conductive plugs located in the third dielectric layer, the third conductive plugs are located between the third conductive portion and the connecting portion, and the third conductive portion is electrically connected to the connecting portion through the third conductive plugs.

[0017] Optionally, in the embedded flash memory, the materials of the first interlayer dielectric layer, the second interlayer dielectric layer, and the third dielectric layer are all silicon oxide and / or silicon nitride.

[0018] Optionally, in the embedded flash memory, the materials of the first conductive layer and the second conductive layer are both copper or aluminum.

[0019] In the embedded flash memory provided by the present invention, the embedded flash memory includes a first conductive layer. A first conductive portion of the first conductive layer is located on a bit line and is electrically connected to the bit line, and a second conductive portion of the first conductive layer is located on a word line and is electrically connected to the word line. A second conductive layer is located on the first conductive layer. The second conductive layer includes at least two third conductive portions that are arranged in the same layer and separated from each other. The third conductive portion is located on a control gate and is electrically connected to the control gate. Since the bit line is electrically connected to the first conductive portion of the first conductive layer, the word line is electrically connected to the second conductive portion of the first conductive layer, and the control gate is electrically connected to the third conductive portion of the second conductive layer, only two conductive layers are required to achieve the electrical connection between the bit line, the word line, the control gate and an external circuit, reducing the conductive layers in the embedded flash memory, lowering the cost, and since only two conductive layers are used and only the design rule of the first conductive layer in the two conductive layers is the most compact, it is easy to be compatible with a logic process. Description of the Drawings

[0020] Figure 1 is a schematic structural diagram of the embedded flash memory according to an embodiment of the present invention;

[0021] Figure 2 is a schematic cross-sectional view of the embedded flash memory according to an embodiment of the present invention;

[0022] Among them, the description of the reference numerals is as follows:

[0023] 100 - Substrate; 101 - Control gate; 102 - Word line; 103 - Bit line; 104 - Floating gate; 110 - First conductive portion; 111 - Second conductive portion; 112 - Connection portion; 120 - Third conductive portion; 130 - Metal silicide layer; 140 - First conductive plug; 150 - Second conductive plug; 160 - Third conductive plug; 170 - First interlayer dielectric layer; 180 - Second interlayer dielectric layer; 190 - Third interlayer dielectric layer. Detailed Embodiments

[0024] The following further details the embedded flash memory proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0025] Figure 1 is a schematic structural diagram of the embedded flash memory according to an embodiment of the present invention. As Figure 1As shown in the figure, this embodiment provides an embedded flash memory, which includes: a substrate 100, on which a control gate 101 is formed; a word line 102, located on the substrate 100 and penetrating through the control gate 101, and the top surface of the word line 102 is higher than the top surface of the control gate 101; a bit line 103, located on the substrate 100 and on the side of the control gate 101 away from the word line 102; a first conductive layer, including at least two first conductive parts 110 and at least two second conductive parts 111 that are arranged in the same layer and separated from each other. The first conductive parts 110 are located on the bit line 103 and are electrically connected to the bit line 103, and the second conductive parts 111 are located on the word line 102 and are electrically connected to the word line 102; a second conductive layer, located on the first conductive layer, and the second conductive layer includes at least two third conductive parts 120 that are arranged in the same layer and separated from each other. The third conductive parts 120 are located on the control gate 101 and are electrically connected to the control gate 101.

[0026] Since the bit line 103 is electrically connected to the first conductive parts 110 of the first conductive layer, the word line 102 is electrically connected to the second conductive parts 111 of the first conductive layer, and the control gate 101 is electrically connected to the third conductive parts 120 of the second conductive layer, therefore, only two conductive layers are required to achieve the electrical connection between the bit line 103, the word line 102, the control gate 101 and the external circuit, reducing the conductive layers in the embedded flash memory, lowering the cost, and since only two conductive layers are adopted, and only the design rule of the first conductive layer in the two conductive layers is the most compact, it is easy to be compatible with the logic process.

[0027] In this embodiment, the material of the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may also be germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0028] In this embodiment, the material of the control gate 101 may be doped polysilicon. In other embodiments, the material of the control gate 101 may be metal.

[0029] It should be noted that a floating gate 104 is also formed between the control gate 101 and the substrate 100, and a gate dielectric layer is formed between the floating gate 104 and the control gate 101. In this embodiment, for better elaborating the invention content of this embodiment, the description and illustration of the gate dielectric layer are omitted.

[0030] In this embodiment, the material of the word line 102 may be doped polysilicon. The material of the bit line 103 may be metal, such as tungsten, copper or aluminum. The bit line 103 is used to achieve the electrical connection between the source-drain regions in the substrate 100 and the external circuit.

[0031] As Figure 1 shown, the embedded flash memory further includes a metal silicide layer 130, which is located on top of the word line 102, and the word line 102 is electrically connected to the second conductive part 111 through the metal silicide layer 130.

[0032] As Figure 1 shown, one second conductive part 111 is provided at each of the two end portions of the metal silicide layer 130. The second conductive parts 111 at the two end portions of the metal silicide layer 130 are separated from each other, thereby realizing the connection between the word line 102 and an external circuit.

[0033] In this embodiment, the embedded flash memory further includes at least two first conductive plugs 140, which are located between the metal silicide layer 130 and the second conductive part 111, and the second conductive part 111 is electrically connected to the metal silicide layer 130 through the first conductive plugs 140.

[0034] Among them, the material of the first conductive plug 140 can be tungsten. In other embodiments, the material of the third plug can also be other conductive materials, such as Co, Ru, W, Ag, Au, Pt, Ni, Ti, Al or Cu, etc.

[0035] As Figure 1 shown, the first conductive layer further includes a connection part 112, which is arranged on the same layer as the first conductive part 110 and the second conductive part 111. The connection part 112 is located on the control gate 101, and the third conductive part 120 is electrically connected to the control gate 101 through the connection part 112. That is, in the first conductive layer and the second conductive layer, the design rule of the first conductive layer is more compact than that of the second conductive layer. Since the first conductive layer is located under the second conductive layer, it is easy to be compatible with the logic process. Among them, the material of the first conductive layer can be copper or aluminum.

[0036] As Figure 1 shown, the embedded flash memory further includes at least two second conductive plugs 150, which are located between the control gate 101 and the connection part 112, and the connection part 112 is electrically connected to the control gate 101 through the second conductive plugs 150. And it further includes at least two third conductive plugs 160, which are located between the third conductive part 120 and the connection part 112, and the third conductive part 120 is electrically connected to the connection part 112 through the third conductive plugs 160.

[0037] In this embodiment, the materials of the third conductive plug 160, the second conductive plug 150, and the first conductive plug 140 can be the same to reduce stress.

[0038] Figure 2 This is a cross-sectional schematic diagram of the embedded flash memory according to an embodiment of the present invention. As Figure 2 shown, the embedded flash memory further includes a first interlayer dielectric layer 170, a second interlayer dielectric layer 180, and a third interlayer dielectric layer 190 stacked in sequence from bottom to top. The first interlayer dielectric layer 170 covers the metal silicide layer 130, the control gate 101, the bit line 103, and the substrate 100.

[0039] In this embodiment, the materials of the first interlayer dielectric layer 170, the second interlayer dielectric layer 180, and the third interlayer dielectric layer 190 are all insulating materials. For example, the materials of the first interlayer dielectric layer 170, the second interlayer dielectric layer 180, and the third interlayer dielectric layer 190 all include silicon oxide. Silicon oxide is a commonly used and low-cost interlayer dielectric material in the process, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the interlayer dielectric layer. Alternatively, the materials of the first interlayer dielectric layer 170, the second interlayer dielectric layer 180, and the third dielectric layer can all include silicon oxide and silicon nitride.

[0040] As Figure 2 shown, both the first conductive plug 140 and the second conductive plug 150 are located in the first interlayer dielectric layer 170. Among them, the first conductive plug 140 penetrates the first interlayer dielectric layer 170 on the metal silicide layer 130 from the top of the first interlayer dielectric layer 170 to achieve electrical connection with the metal silicide layer 130. The second conductive plug 150 penetrates the first interlayer dielectric layer 170 on the control gate 101 from the top of the first interlayer dielectric layer 170 to achieve electrical connection with the control gate 101.

[0041] In this embodiment, before forming the first conductive plug 140 and the second conductive plug 150, it is necessary to first etch the first interlayer dielectric layer 170 to form a first through hole exposing the metal silicide layer 130 and a second through hole exposing the control gate 101, then fill the first through hole and the second through hole with a conductive material (such as tungsten), and finally through a planarization process, the first conductive plug 140 and the second conductive plug 150 are formed. According to the etching process, when forming the first through hole for accommodating the first conductive plug 140 and the second through hole for forming the second conductive plug 150, the cross-sectional shapes of the first through hole and the second through hole both present an inverted trapezoid of "wide at the top and narrow at the bottom", so that the cross-sectional shapes of the first conductive plug 140 and the second conductive plug 150 in the trench and the through hole also present an inverted trapezoid of "wide at the top and narrow at the bottom".

[0042] In this embodiment, the first conductive portion 110, the second conductive portion 111, and the connecting portion 112 are all located in the second interlayer dielectric layer 180. Specifically, the first conductive portion 110 penetrates through the second interlayer dielectric layer 180 and is aligned with the bit line 103 to achieve electrical connection with the bit line 103. The second conductive portion 111 penetrates through the second interlayer dielectric layer 180 and is aligned with the first conductive plug 140 to achieve electrical connection with the metal silicide layer 130 through the first conductive plug 140. The connecting portion 112 penetrates through the second interlayer dielectric layer 180 and is aligned with the second plug to achieve electrical connection with the control gate 101 through the second plug.

[0043] In this embodiment, the third conductive plug 160 and the third conductive portion 120 are located in the third interlayer dielectric layer 190. Among them, the third conductive portion 120 is located on the third conductive plug 160. The third conductive plug 160 penetrates through a partial thickness of the third interlayer dielectric layer 190 and is aligned with the connecting portion 112 to achieve electrical connection with the connecting portion 112. The third conductive portion 120 penetrates through a partial thickness of the interlayer dielectric layer from the top of the third interlayer dielectric layer 190 and is aligned with the third conductive plug 160 to achieve electrical connection with the connecting portion 112 through the third conductive plug 160, thereby achieving electrical connection with the control gate 101. Electrical connection between the control gate 101 and an external circuit can be achieved through the third conductive portion.

[0044] In summary, in the embedded flash memory provided by the embodiment of the present invention, since the bit line is electrically connected to the first conductive portion of the first conductive layer, the word line is electrically connected to the second conductive portion of the first conductive layer, and the control gate is electrically connected to the third conductive portion of the second conductive layer, only two conductive layers are required to achieve electrical connection between the bit line, the word line, the control gate and an external circuit, reducing the conductive layers in the embedded flash memory, reducing the cost, and since only two conductive layers are adopted and only the design rule of the first conductive layer in the two conductive layers is the most compact, it is easy to be compatible with the logic process.

[0045] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. An embedded flash memory, characterized in that, The embedded flash memory includes: a substrate on which a control gate is formed; a word line located on the substrate and penetrating through the control gate, with the top surface of the word line higher than the top surface of the control gate; a bit line located on the substrate and on a side of the control gate away from the word line; a first conductive layer including at least two first conductive parts, at least two second conductive parts and connection parts that are arranged in the same layer and separated from each other. The first conductive parts are located on the bit line and electrically connected to the bit line. The second conductive parts are located on the word line and electrically connected to the word line. The connection parts are arranged in the same layer as the first conductive parts and the second conductive parts, and the connection parts are located on the control gate; a second conductive layer located on the first conductive layer. The second conductive layer includes at least two third conductive parts that are arranged in the same layer and separated from each other. The third conductive parts are located on the control gate and electrically connected to the control gate through the connection parts.

2. The embedded flash memory according to claim 1, wherein The embedded flash memory further includes a metal silicide layer located on the top of the word line. The word line is electrically connected to the second conductive part through the metal silicide layer.

3. The embedded flash memory according to claim 2, characterized in that, One second conductive part is provided at each of the two end portions of the metal silicide layer.

4. The embedded flash memory according to claim 2, wherein, The embedded flash memory further includes at least two first conductive plugs located between the metal silicide layer and the second conductive part. The second conductive part is electrically connected to the metal silicide layer through the first conductive plug.

5. The embedded flash memory according to claim 2, characterized in that, The embedded flash memory further includes a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer that are stacked in sequence from bottom to top. The first interlayer dielectric layer covers the metal silicide layer, the control gate, the bit line and the substrate. The first conductive plug is located in the first interlayer dielectric layer. The first conductive part, the second conductive part and the connection part are all located in the second interlayer dielectric layer. The third conductive part is located in the third interlayer dielectric layer.

6. The embedded flash memory according to claim 5, wherein, The embedded flash memory further includes at least two second conductive plugs located in the first interlayer dielectric layer. The second conductive plugs are located between the control gate and the connection part. The connection part is electrically connected to the control gate through the second conductive plugs.

7. The embedded flash memory according to claim 5, wherein, The embedded flash memory further includes at least two third conductive plugs located in the third interlayer dielectric layer. The third conductive plugs are located between the third conductive part and the connection part. The third conductive part is electrically connected to the connection part through the third conductive plugs.

8. The embedded flash memory according to claim 5, wherein The materials of the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer are all silicon oxide and / or silicon nitride.

9. The embedded flash memory according to claim 1, wherein, The materials of the first conductive layer and the second conductive layer are both copper or aluminum.

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