A storage structure and a preparation method thereof, a memory and a storage system

Abstract

The application relates to a storage structure and a preparation method thereof, a memory and a storage system. The preparation method comprises the following steps: forming a stack layer, the stack layer comprising a sub-stack layer, the sub-stack layer comprising an interlayer sacrificial layer and a first conductor layer on the interlayer sacrificial layer; forming a step structure and an insulating medium layer covering the step structure, each step of the step structure corresponding to at least one sub-stack layer; forming a contact hole penetrating through the stack layer and the insulating medium layer at each step, and filling a sacrificial material in the contact hole; replacing the interlayer sacrificial layer with a second conductor layer; removing the sacrificial material in the contact hole, and forming a landing layer in the contact hole corresponding to a part of the first conductor layer through epitaxial growth; and filling a conductive contact structure on the landing layer closest to the insulating medium layer in the contact hole, so that a conductive contact structure with a proper length can be manufactured without relying on high-precision control of a deep-hole etching process, and the precision requirement of the deep-hole etching process is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a storage structure, a preparation method thereof, a memory and a storage system. BACKGROUND

[0002] Memory is a new storage mode emerging with the development of semiconductor technology, and is paid more and more attention. With the market's increasing demand for high-density and large-capacity memory, the size of the memory must be continuously reduced. According to the material and structural characteristics of the memory itself, when the number of electronic devices that can be accommodated in the memory reaches the limit, the storage density cannot be improved by reducing the size of the memory. In this case, how to ensure the reliability of the storage unit under the condition of reducing the size of the memory has become a hot spot of attention.

[0003] In the preparation process of the memory, as the etching depth increases, the etching process will be more complex. In the deep etching process, the quality of etching will directly affect the reliability of the memory, and then affect the storage density and read-write speed of the memory. SUMMARY

[0004] In view of the problems in the prior art, the present application provides a storage structure, a preparation method thereof, a memory and a storage system, which can still improve the reliability of the memory under the condition of reducing the size of the memory.

[0005] In order to at least partially solve the above problems, the present application provides a preparation method of a storage structure, comprising:

[0006] forming a stack layer, the stack layer comprising a plurality of sub-stack layers arranged in layers, the sub-stack layer comprising an interlayer sacrificial layer and a first conductor layer on the interlayer sacrificial layer;

[0007] forming a step structure based on the stack layer and an insulating medium layer covering the step structure, the step structure comprising a plurality of steps, each step corresponding to at least one sub-stack layer;

[0008] forming a contact hole penetrating through the stack layer and the insulating medium layer at each step, and filling a sacrificial material in the contact hole;

[0009] replacing the interlayer sacrificial layer with a second conductor layer;

[0010] removing the sacrificial material in the contact hole, and forming a landing layer in the contact hole corresponding to the first conductor layer by epitaxial growth;

[0011] filling a conductive contact structure in the contact hole on the landing layer closest to the insulating medium layer.

[0012] In some embodiments, the sub-stack further comprises an interlayer insulating layer, and the first conductor layer is located between the interlayer sacrificial layer and the interlayer insulating layer.

[0013] In some embodiments, the interlayer insulating layer is in contact with the first conductor layer.

[0014] In some embodiments, the forming a stepped structure based on the stack and covering the stepped structure with an insulating medium layer comprises:

[0015] forming a stepped structure based on the stack;

[0016] filling an insulating medium layer on the stepped structure and performing a planarization process;

[0017] wherein the contact hole penetrates through the insulating medium layer and the stack under the insulating medium layer.

[0018] In some embodiments, before replacing the interlayer sacrificial layer with a second conductor layer, the method further comprises:

[0019] forming a virtual trench hole penetrating through the insulating medium layer and the stack under the insulating medium layer at a position of each level of the stepped structure other than the contact hole;

[0020] filling a dielectric material in the virtual trench hole.

[0021] In some embodiments, at least three virtual trench holes are formed at each level of the stepped structure, and the virtual trench holes are arranged around the contact hole.

[0022] In some embodiments, before replacing the interlayer sacrificial layer with a second conductor layer, the method further comprises:

[0023] forming a gate slit penetrating through the sub-stack structure;

[0024] the replacing the interlayer sacrificial layer with a second conductor layer comprises: removing the interlayer sacrificial layer of the sub-stack via the gate slit to form a void; filling a conductive material into the void via the gate slit to obtain a second conductor layer.

[0025] In some embodiments, the material of the first conductor layer comprises polysilicon.

[0026] To at least partially solve the above problems, the embodiments of the present application further provide a storage structure, comprising: a stack structure, the stack structure comprising a plurality of sub-stack structures arranged in layers, the sub-stack structure comprising a gate structure layer, the stack structure further comprising a step structure, the step structure comprising a plurality of steps, each step corresponding to at least one sub-stack structure; and an insulating medium layer covering the step structure;

[0027] a contact hole located at each step and penetrating the insulating medium layer and the stack structure;

[0028] wherein the contact hole has at least a landing layer corresponding to the gate structure layer closest to the insulating medium layer and a conductive contact structure located in the insulating medium layer and electrically connected to the landing layer closest to the insulating medium layer.

[0029] In some embodiments, the sub-stack structure further comprises an interlayer insulating layer located on the gate structure layer.

[0030] In some embodiments, the contact hole has a plurality of landing layers corresponding to each gate structure layer.

[0031] In some embodiments, in the same contact hole, two adjacent landing layers are arranged at intervals along the extension direction of the contact hole.

[0032] In some embodiments, the storage structure further comprises a virtual channel structure, the virtual channel structure being arranged at a position of each step other than the contact hole, the virtual channel structure penetrating the insulating medium layer and the stack structure.

[0033] In some embodiments, each step is provided with one contact channel and at least three virtual channel structures, the virtual channel structures being arranged around the contact channel.

[0034] To at least partially solve the above problems, the embodiments of the present application further provide a storage structure, comprising: a stack structure, the stack structure comprising a plurality of sub-stack structures arranged in layers, the sub-stack structure comprising a gate structure layer, the stack structure further comprising a step structure, the step structure comprising a plurality of steps, each step corresponding to at least one sub-stack structure; and an insulating medium layer covering the step structure;

[0035] To at least partially solve the above problems, the embodiments of the present application further provide a storage system, comprising: a controller and a storage as any of the above, the controller being coupled to the storage and used for controlling the storage to store data.

[0036] The embodiment of the present application provides a storage structure, a preparation method thereof, a memory and a storage system. The storage structure is prepared by forming a stack layer, the stack layer comprises a plurality of sub-stack layers arranged in layers, each sub-stack layer comprises an interlayer sacrificial layer and a first conductor layer on the interlayer sacrificial layer, a step structure is formed based on the stack layer, and an insulating medium layer covers the step structure, the step structure comprises a plurality of steps, each step corresponds to at least one sub-stack layer, then a contact hole penetrating through the stack layer and the insulating medium layer is formed at each step, and a sacrificial material is filled in the contact hole, then the interlayer sacrificial layer is replaced by a second conductor layer, then the sacrificial material in the contact hole is removed, and a landing layer is formed in the contact hole corresponding to the first conductor layer by epitaxial growth, then a conductive contact structure is filled in the contact hole on the landing layer closest to the insulating medium layer, so that the conductive contact structure can contact the second conductor layer through the landing layer and the first conductor layer, the conductive contact structure with a proper length can be prepared without relying on high-precision control of a deep hole etching process, the precision requirement of the deep hole etching process is reduced, the reliability of electrical connection between the conductive contact structure and the second conductor layer is improved, and the reliability of the storage structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0038] Figure 1 The flowchart of the preparation method of the storage structure provided by the embodiment of the present application is shown in the figure.

[0039] Figures 2A-2H The cross-sectional structure of the storage structure in the preparation method of the storage structure provided by the embodiment of the present application is shown in the figure.

[0040] Figure 3 The top view of the local step area in the storage structure provided by the embodiment of the present application is shown in the figure.

[0041] Figure 4 The schematic block diagram of the storage system provided by the embodiment of the present application is shown in the figure.

[0042] In the figure: 100, storage structure; 110, semiconductor substrate; 120, stacked layer; 1201, sub-stacked layer; 1202, sub-stacked structure; 121, interlayer insulating layer; 122, interlayer sacrificial layer; 123, first conductor layer; 124, second conductor layer; 125, step structure; 1251, step; 1251a, first step; 1251b, second step; 130, virtual channel hole; 131, dielectric material; 140, contact hole; 141, sacrificial material; 142, landing layer; 143, conductive contact structure; 150, insulating dielectric layer; 200, storage system; 210, controller; 220, memory; 300, host. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application belong to the scope of protection of the present application.

[0044] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present application.

[0045] It should be understood that when a component is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or intervening components can also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0046] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes that are between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and contact layers (where contacts, interconnect lines, and one or more dielectric layers are formed).

[0047] As used herein, the term "memory" refers to a memory having vertically oriented array structures on a laterally oriented substrate, such that the array structures extend in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0048] It should be noted that the diagrams provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the diagrams, the diagrams are not drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type can also be more complex.

[0049] Please refer to Figure 1 , Figure 1 The flowchart of the preparation method of the storage structure provided in the embodiments of the present application includes the following steps S101-S106, wherein:

[0050] S101. Form a stack layer, the stack layer includes a plurality of sub-stack layers arranged in layers, the sub-stack layer includes an interlayer sacrificial layer and a first conductor layer on the interlayer sacrificial layer;

[0051] S102. Form a step structure based on the stack layer and an insulating medium layer covering the step structure, the step structure includes multiple levels of steps, each level of the step corresponds to at least one of the sub-stack layers;

[0052] S103. Form a contact hole penetrating through the stack layer and the insulating medium layer at each level of the step, and fill a sacrificial material in the contact hole;

[0053] S104. Replace the interlayer sacrificial layer with a second conductor layer;

[0054] S105. Remove the sacrificial material in the contact hole, and form a landing layer in the contact hole corresponding to the part of the first conductor layer by epitaxial growth;

[0055] S106. Fill a conductive contact structure in the contact hole on the landing layer closest to the insulating medium layer.

[0056] In the conductive contact structure formed by the method, the conductive contact structure is formed by forming a contact hole penetrating through the stack layer and the insulating dielectric layer at each step after forming the step structure and the insulating dielectric layer, filling a sacrificial material in the contact hole, performing a gate replacement process, and removing the sacrificial material in the contact hole to expose the contact hole again, and then forming a landing layer in the exposed contact hole corresponding to the first conductor layer by epitaxial growth, and then filling the conductive contact structure on the landing layer closest to the insulating dielectric layer in the contact hole. The conductive contact structure formed in this way can realize good electrical contact with the second conductor layer through the landing layer and the first conductor layer, and does not need to rely on the control accuracy of the deep hole etching process for manufacturing, effectively avoiding the problem that the deep hole is too deep or too shallow due to low control accuracy, and then the conductive contact structure filled in the deep hole is too short or too long, and cannot realize effective electrical contact with the second conductor layer. The accuracy requirement of the deep hole etching process is reduced, the reliability of the electrical connection between the conductive contact structure and the second conductor layer is improved, and the reliability of the storage structure is improved.

[0057] The following will be described in detail Figures 2A-2H Further description will be given to the steps S101-S106, and the steps S101-S106 are described in detail as follows. Figures 2A-2H is a cross-sectional structure schematic diagram of the storage structure 100 in different process steps in the preparation method of the storage structure 100 provided by the embodiments of the present application, and specifically:

[0058] S101. Form a stack layer 120, the stack layer 120 includes a plurality of sub-stack layers 1201 stacked, and the sub-stack layer 1201 includes an interlayer sacrificial layer 122 and a first conductor layer 123 on the interlayer sacrificial layer 122.

[0059] In some embodiments, before the step S101, the preparation method of the storage structure can further include the step of providing a semiconductor substrate 110, and at this time, the step S101 specifically includes: forming the stack layer 120 on the semiconductor substrate 110.

[0060] For details, please refer to Figure 2A and Figure 2B The semiconductor substrate 110 can be formed by grinding, etching, chemical mechanical polishing and other processes on a wafer. The semiconductor substrate 110 can be silicon, germanium, silicon germanium substrate, silicon on insulator or germanium on insulator, etc. In some embodiments, the semiconductor substrate 110 can be a substrate including other elemental semiconductors or compound semiconductors, and can also be a laminated structure, such as a laminated structure of silicon or silicon germanium, and can also be a sapphire substrate, a blue sapphire substrate, a glass substrate and other insulating substrates.

[0061] The stack layer 120 can include a plurality of interlayer insulating layers 121, interlayer sacrificial layers 122, and first conductor layers 123, and is stacked on the semiconductor substrate 110. The material of the interlayer insulating layer 121 includes, but is not limited to, silicon oxide, such as aluminum oxide, hafnium oxide, tantalum oxide, etc. The interlayer sacrificial layer 122 can be silicon nitride. The first conductor layer 123 is formed by epitaxial growth, and can be formed by any one of silicon, gallium, arsenic, and cobalt.

[0062] Specifically, the stack layer 120 is formed by a plurality of sub-stack layers 1201, each of which includes an interlayer insulating layer 121, an interlayer sacrificial layer 122, and a first conductor layer 123. The interlayer insulating layer 121, the interlayer sacrificial layer 122, and the first conductor layer 123 are stacked in the vertical direction of the extension direction of the semiconductor substrate 110. The interlayer insulating layer 121 is located on the first conductor layer 123, and the first conductor layer 123 is located on the interlayer sacrificial layer 122. The interlayer insulating layer 121 is in direct contact with the first conductor layer 123, and the first conductor layer 123 is in direct contact with the interlayer sacrificial layer 122.

[0063] In an embodiment, the sub-stack layer 1201 can be formed by sequentially stacking the interlayer sacrificial layer 122, the first conductor layer 123, and the interlayer insulating layer 121. In each sub-stack layer 1201, the interlayer sacrificial layer 122 is in contact with the first conductor layer 123, and the first conductor layer 123 is in contact with the interlayer insulating layer 121, so that the first conductor layer 123 is located between the interlayer sacrificial layer 122 and the interlayer insulating layer 121. In the data storage process, the interlayer insulating layer 121 can play a protective role for the stack layer 120, and can prevent the stored carriers from entering the semiconductor substrate 110, thereby reducing the loss of carriers. The interlayer sacrificial layer 122 can reserve space for the replacement of the gate in the subsequent process, and can also make the interlayer sacrificial layer 122 and the interlayer insulating layer 121 have different etching selectivities, so as to improve the etching effect of the contact hole in the subsequent process. The first conductor layer 123 can grow outwardly, so as to be able to fill the contact hole in the subsequent process. The deposition method of the interlayer insulating layer 121 and the interlayer sacrificial layer 122 can adopt, but is not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition such as thermal oxidation, evaporation, sputtering, and various methods.

[0064] In S102, a step structure 125 including a plurality of levels of steps 1251 is formed based on the stack layer 120, and an insulating medium layer 150 covering the step structure 125 is formed.

[0065] In one embodiment, in order to ensure good electrical connection between the first conductor layer 123 and the subsequently formed contact structure, the first conductor layer 123 can be ion doped to improve the electrical conductivity of the first conductor layer 123 when the first conductor layer 123 is formed. The appropriate doping concentration can be selected based on actual electrical requirements.

[0066] In some embodiments, the step S102 can specifically include: forming a stepped structure 125 based on the stack layer 120; filling the insulating medium layer 150 on the stepped structure 125 and performing a planarization process.

[0067] The stack layer 120 includes a core region and a stepped region, and the stepped structure 125 is formed by the stack layer 120 of the stepped region. For details, please refer to Figure 2C The extension length of each sub-stack layer 1201 in the stepped structure 125 decreases successively from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110, forming a plurality of steps 1251.

[0068] The side surface of each sub-stack layer 1201 can be perpendicular to the semiconductor substrate 110, or the side surface of each sub-stack layer 1201 can be inclined at an angle.

[0069] In one embodiment, as shown in Figure 2C Since the extension length of each sub-stack layer 1201 along the direction of the semiconductor substrate 110 decreases successively from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110, the position to which the other side surface of each sub-stack layer 1201 extends successively approaches the aligned side surface from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110. In another embodiment, the center line of each sub-stack layer 1201 is aligned in the direction perpendicular to the semiconductor substrate 110. Since the extension length of each sub-stack layer 1201 along the direction of the semiconductor substrate 110 decreases successively from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110, the positions to which the two side surfaces of each sub-stack layer 1201 extend are symmetrical relative to the center line, and both successively approach the center line from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110.

[0070] In one embodiment, as shown in Figure 2C The extension length of each sub-stack layer 1201 along the direction of the semiconductor substrate 110 decreases successively from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110. However, in other embodiments, the extension length of each sub-stack layer 1201 along the direction of the semiconductor substrate 110 can also decrease successively by irregular amounts from the surface of the semiconductor substrate 110 to the direction away from the semiconductor substrate 110.

[0071] In one embodiment, such as Figure 2C As shown, the stepped structure 125 is formed based on the stacked layer 120, and each step 1251 corresponds to at least one sub-stacked layer 1201. For example, each step 1251 can correspond to one sub-stacked layer 1201 or two sub-stacked layers 1202. The formation of the stepped structure 125 specifically includes: using a photoresist trimming process, etching away a portion of at least one sub-stacked layer 1201 on the stacked layer 120 that is furthest from the semiconductor substrate 110, so that the extension length of the at least one sub-stacked layer 1201 furthest from the semiconductor substrate 110 in the extension direction of the semiconductor substrate 110 is less than the extension length of the at least one sub-stacked layer furthest from the semiconductor substrate 110 in the extension direction of the semiconductor substrate 110. Length; a portion of at least one sub-stacked layer 1201 on the stacked layer 120 that is second furthest from the semiconductor substrate 110 is etched away, such that the extension length of at least one sub-stacked layer 1201 that is second furthest from the semiconductor substrate 110 in the extension direction of the semiconductor substrate 110 is less than the extension length of at least one sub-stacked layer 1201 that is third furthest from the semiconductor substrate 110 in the extension direction of the semiconductor substrate 110; and so on, until the extension length of at least one sub-stacked layer 1201 that is second furthest from the semiconductor substrate 110 in the extension direction of the semiconductor substrate 110 is less than the extension length of at least one sub-stacked layer 1201 that is closest to the semiconductor substrate 110 in the extension direction of the semiconductor substrate 110.

[0072] In this embodiment, an insulating dielectric layer 150 can be deposited on the stepped structure 125 using a high-density plasma process. The insulating dielectric layer 150 can be made of silicon oxide, which can protect the outer wall of the stepped structure 125, thereby ensuring the stability of each sub-stacked layer 1201 in the stepped structure 125.

[0073] Among them, the height of each step 1251 of the stepped structure 125 can decrease sequentially from the direction away from the semiconductor substrate 110 toward the semiconductor substrate 110, so that the first step 1251a, which is farthest from the semiconductor substrate 110, has the highest height, and the second step 1251b, which is closest to the semiconductor substrate 110, has the lowest height.

[0074] Step S103: Form contact holes 140 at each step 1251 that penetrate the stacked layer 120 and the insulating dielectric layer 150, and fill the contact holes 140 with sacrificial material 141.

[0075] Among them, see Figure 2D In the stepped structure 125, contact holes 140 are formed on each step 1251 away from the surface of the semiconductor substrate 110 and toward the semiconductor substrate 110, and the contact holes penetrate the first conductor layer 123.

[0076] S104: Replace the interlayer sacrificial layer 122 with a second conductor layer 124.

[0077] In some embodiments, before step S104, the method for preparing the storage structure 100 can further comprise: forming a dummy trench hole 130 through the insulating dielectric layer 150 and the stack layer 120 under the insulating dielectric layer 150 at a position other than the contact hole 140 of each level step 1251; and filling the dummy trench hole 130 with a dielectric material 131.

[0078] In some embodiments, before step S104, the method for preparing the storage structure 100 can further comprise: forming a dummy trench hole 130 through the insulating dielectric layer 150 and the stack layer 120 under the insulating dielectric layer 150 at a position other than the contact hole 140 of each level step 1251; and filling the dummy trench hole 130 with a dielectric material 131. Figure 2D Figure 2E In some embodiments, before step S104, the method for preparing the storage structure 100 can further comprise: forming a dummy trench hole 130 through the insulating dielectric layer 150 and the stack layer 120 under the insulating dielectric layer 150 at a position other than the contact hole 140 of each level step 1251; and filling the dummy trench hole 130 with a dielectric material 131.

[0079] In some embodiments, before step S104, the method for preparing the storage structure 100 can further comprise: forming a dummy trench hole 130 through the insulating dielectric layer 150 and the stack layer 120 under the insulating dielectric layer 150 at a position other than the contact hole 140 of each level step 1251; and filling the dummy trench hole 130 with a dielectric material 131. ​

[0080] In other embodiments, the dummy channel holes 130 and the contact holes 140 can be formed in different etching processes, such as first forming the contact holes 140 through a hard mask, then removing the hard mask, and then forming the dummy channel holes 130 through another hard mask.

[0081] In one embodiment, please refer to Figure 3 , Figure 3 A top view of a partial stepped region of the storage structure 100 is provided in the embodiment of the present application. In the embodiment, a contact hole 140 can be formed on each step 1251 of the stepped structure 125, and at least three dummy channel holes 130 can be formed on each step 1251 of the stepped structure 125 other than the position of the contact hole 140, and the contact hole 140 and the dummy channel holes 130 can both penetrate the stack layer 120 and reach the semiconductor substrate 110. In the process of replacing the interlayer sacrificial layer 122 in the stack layer 120 with the second conductor layer 124, the sacrificial material 141 filled in the contact hole 140 on each step 1251 and the dielectric material 131 filled in the dummy channel holes 130 can both have a supporting effect.

[0082] Specifically, the at least three dummy channel holes 130 can be arranged around the contact hole 140 and symmetrically distributed, so that in the process of removing the sacrificial material 141 in the contact hole 140, the dielectric material 131 filled in the at least three dummy channel holes 130 can have a good supporting effect on each sub-stack layer 1201 in the stepped structure 125, greatly avoiding the collapse phenomenon, thereby improving the overall reliability of the storage structure 100.

[0083] S105: removing the sacrificial material 141 in the contact hole 140, and forming a landing layer 142 in the contact hole 140 corresponding to the first conductor layer 123 by epitaxial growth.

[0084] In the embodiment, please refer to Figure 2E , Figure 2F and Figure 2G In the embodiment, the first conductor layer 123 can extend to the inner wall of the contact hole 140 to form a landing layer 142 by epitaxial growth, each first conductor layer 123 corresponds to a landing layer 142, and in the same contact hole 140, two adjacent landing layers 142 are arranged in the thickness direction of the stack layer 120, that is, there is a gap Q between the two.

[0085] S106: filling a conductive contact structure 143 in the contact hole 140 on the landing layer 142 closest to the insulating dielectric layer 150.

[0086] In the embodiment, please refer to Figure 2G and Figure 2HThe conductive contact structure 143 can be filled in the contact hole 140 of each step 1251, and the conductive contact structure 143 is connected with the landing layer 142 formed on the end of the corresponding step 1251 farthest from the semiconductor substrate 110. The material of the conductive contact structure 143 can be tungsten. Since the first conductor layer 123 and the second conductor layer 124 are directly in contact, the landing layer 142 is formed by epitaxial growth of the first conductor layer 123, the conductive contact structure 143 can be reliably electrically connected to the corresponding second conductor layer 124 through the first conductor layer 123, thereby improving the performance of the storage structure 100.

[0087] To at least partially solve the above problems, please refer to Figure 2H The embodiment of the present application also provides a storage structure 100, wherein the storage structure 100 comprises a stack structure, the stack structure comprises a plurality of sub-stack structures 1202 arranged in a stack, the sub-stack structure 1202 comprises a gate structure layer (i.e. the first conductor layer 123 and the second conductor layer 124), the stack structure further comprises a step structure 125, the step structure 125 comprises a plurality of steps 1251, each step 1251 corresponds to at least one sub-stack structure 1202; and an insulating medium layer 150 covering the step structure 125. The storage structure 100 further comprises a contact hole 140 located at each step 1251 and penetrating the stack structure and the insulating medium layer 150, the contact hole 140 at least has a landing layer 142 corresponding to the gate structure layer closest to the insulating medium layer 150, and a conductive contact structure 143 located in the insulating medium layer 150 and electrically connected with the landing layer 142 closest to the insulating medium layer 150.

[0088] In some embodiments, the storage structure 100 can further comprise a semiconductor layer, which can be the semiconductor substrate 110 or a common source layer formed after the semiconductor substrate 110 is removed, depending on the actual product.

[0089] In some embodiments, the sub-stack structure 1202 further comprises an interlayer insulating layer 121 located on the gate structure layer.

[0090] In some embodiments, the contact hole 140 has a plurality of landing layers 142 corresponding to each gate structure layer.

[0091] In some embodiments, in the same contact hole 140, two adjacent landing layers 142 are arranged at intervals along the extension direction of the contact hole 140.

[0092] In some embodiments, the storage structure 100 further comprises a virtual channel structure, the virtual channel structure is arranged at a position of each step 1251 other than the contact hole 140, and the virtual channel structure penetrates the insulating medium layer 150 and the stack structure.

[0093] The dummy trench structure includes a dummy trench hole 130 and a dielectric material 131 filled in the dummy trench hole 130.

[0094] In some embodiments, the step 1251 at each level is provided with one contact hole 140 and at least three dummy trench structures, the dummy trench structures are arranged around the contact hole 140 and can be symmetrically distributed.

[0095] It should be understood that the structure and manufacturing process of each component of the storage structure 100 in the embodiments of the present application can refer to the above-mentioned embodiments of the preparation method of the storage structure 100, and will not be repeated hereinafter.

[0096] In order to at least partially solve the above problems, the embodiments of the present application also provide a memory, which can be a three-dimensional memory, such as a three-dimensional flash memory, a three-dimensional non-volatile memory, the memory can include any one of the above-mentioned storage structures, and a peripheral circuit coupled to the storage structure.

[0097] Based on the memory and the preparation method thereof described in the above embodiments, the embodiments of the present application also provide a storage system 200, which can be implemented as a general flash memory storage device, a solid state disk, a card type storage device, a peripheral component interconnect type storage device, a compact flash card, a smart media card or a memory stick, etc. For details, please refer to Figure 4 As shown, the storage system 200 includes a controller 210 and any one of the above-mentioned storage 220, the controller 210 is coupled to the storage 220 and used to control the storage 220 to store data.

[0098] Specifically, the storage system 200 includes a controller 210 and one or more storage 220, the storage system 200 can communicate with the host 300 through the controller 210, wherein the controller 210 can be connected to one or more storage 220 via a channel in one or more storage 220. Each storage 220 can be managed by the controller 210 via a channel in the storage 220.

[0099] According to the above embodiments, the storage structure preparation method, the storage structure 100, the memory 220 and the storage system 200 in the embodiments of the present application, by forming the stacked layer 120, the stacked layer 120 includes a plurality of sub-stacked layers 1201 arranged in layers, the sub-stacked layer 1201 includes an interlayer sacrificial layer 122 and a first conductor layer 123 located on the interlayer sacrificial layer 122, and based on the stacked layer 120, a step structure 125 is formed, and an insulating medium layer 150 covering the step structure 125, the step structure 125 includes a plurality of steps 1251, each step 1251 corresponds to at least one sub-stacked layer 1201, then a contact hole 140 penetrating the stacked layer 120 and the insulating medium layer 150 is formed at each step 1251, and the contact hole 140 is filled with a sacrificial material 141, then the interlayer sacrificial layer 122 is replaced with a second conductor layer 124, then the sacrificial material 141 in the contact hole 140 is removed, and a landing layer 142 is formed in the contact hole 140 corresponding to the first conductor layer 123 by epitaxial growth, then the landing layer 142 closest to the insulating medium layer 150 in the contact hole 140 is filled with a conductive contact structure 143, so that the conductive contact structure 143 can realize good electrical contact with the second conductor layer 124 through the landing layer 142 and the first conductor layer 123, without relying on the high precision control of the deep hole etching process to make the conductive contact structure 143 of appropriate length, reducing the precision requirement of the deep hole etching process, improving the reliability of the electrical connection between the conductive contact structure 143 and the second conductor layer 124, and further improving the reliability of the storage structure 100.

[0100] In the description of the present application, it should be understood that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0101] In the present application, unless otherwise explicitly specified and limited, for example, it can be fixedly connected or integrated; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise explicitly limited, and for those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0102] It has to be noted that, as used herein, the terms "includes", "including", "has", "having" or the like are intended to be open-ended: the foregoing terms are used to indicate inapplicability of any limitations to the following discussed alternatives. Notwithstanding replacement of the term "comprising" by the terms "consisting essentially of or "consisting of", the enumerated steps or components are still open-ended and do not exclude additional steps or components.

[0103] While the embodiments of the application have been shown and described herein, it is to be understood that the application is not limited to these embodiments. Rather, many modifications, changes and substitutions are intended to fall within the scope of the present application, which is limited only by the scope of the following claims and the equivalence thereof.

Claims

1. A method for producing a storage structure, characterized by, The method comprises the following steps: forming a stack layer, the stack layer comprising a plurality of sub-stack layers arranged in a stack, the sub-stack layers comprising an interlayer sacrificial layer and a first conductor layer on the interlayer sacrificial layer; forming a stepped structure based on the stack layer, the stepped structure comprising a plurality of steps, each step corresponding to at least one sub-stack layer; forming a contact hole through the stack layer and an insulating medium layer covering the stepped structure at each step, and filling a sacrificial material in the contact hole; replacing the interlayer sacrificial layer with a second conductor layer; removing the sacrificial material in the contact hole, and forming a landing layer in the contact hole by epitaxial growth at a position corresponding to the first conductor layer; filling a conductive contact structure in the contact hole on the landing layer closest to the insulating medium layer, the conductive contact structure being electrically connected to the landing layer closest to the insulating medium layer.

2. The method of claim 1, wherein The sub-stack layer further comprises an interlayer insulating layer, and the first conductor layer is located between the interlayer sacrificial layer and the interlayer insulating layer.

3. The method of claim 2, wherein the step of depositing the first material is performed by atomic layer deposition. The interlayer insulating layer is in contact with the first conductor layer.

4. The method of claim 1, wherein The step of forming a stepped structure based on the stack layer and covering the stepped structure with an insulating medium layer comprises: forming a stepped structure based on the stack layer; filling an insulating medium layer on the stepped structure and performing a planarization process; The contact hole penetrates through the insulating medium layer and the stack layer under the insulating medium layer.

5. The method of claim 1, wherein Before replacing the interlayer sacrificial layer with a second conductor layer, the method further comprises: forming a dummy trench hole through the insulating medium layer and the stack layer under the insulating medium layer at a position of each step other than the contact hole; filling a dielectric material in the dummy trench hole.

6. The method of claim 5, wherein the step of depositing the first material is performed by atomic layer deposition. At least three dummy trench holes are formed at each step, and the dummy trench holes are arranged around the contact hole.

7. The method of claim 1, wherein Before replacing the interlayer sacrificial layer with a second conductor layer, the method further comprises: forming a gate slit through the sub-stack structure; The step of replacing the interlayer sacrificial layer with a second conductor layer comprises: removing the interlayer sacrificial layer of the sub-stack layer through the gate slit to form a void; filling a conductive material into the void through the gate slit to obtain a second conductor layer.

8. The method of claim 1, wherein The material of the first conductor layer comprises polysilicon.

9. A storage structure, characterized by, The method comprises: a stack structure comprising a plurality of sub-stack structures arranged in a stack, the sub-stack structures comprising a gate structure layer, the stack structure further comprising a stepped structure, the stepped structure comprising a plurality of steps, each step corresponding to at least one sub-stack structure; an insulating medium layer covering the stepped structure; a contact hole at each step and penetrating through the insulating medium layer and the stack structure; The contact hole has at least a landing layer corresponding to the gate structure layer closest to the insulating medium layer and a conductive contact structure in the insulating medium layer and electrically connected to the landing layer closest to the insulating medium layer.

10. The memory structure of claim 9, wherein, The sub-stack structure further comprises an interlayer insulating layer on the gate structure layer.

11. The memory structure of claim 9, wherein, The contact hole has a plurality of landing layers corresponding to each gate structure layer.

12. The storage structure of claim 11, wherein, In the same contact hole, two adjacent landing layers are arranged at intervals along the extension direction of the contact hole.

13. The storage structure of claim 9, wherein, The storage structure further comprises a virtual channel structure, which is arranged at a position different from the contact hole at each level of the step and penetrates the insulating medium layer and the stack structure.

14. The storage structure of claim 13, wherein: One contact hole and at least three virtual channel structures are arranged at each level of the step, and the virtual channel structures are arranged around the contact hole.

15. A memory, comprising: Comprising: The storage structure according to any one of claims 9 to 14; A peripheral circuit coupled to the storage structure.

16. A storage system, characterized by Comprising: The memory according to claim 15; A controller coupled to the memory and used for controlling the memory to store data.

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