A high-voltage gallium oxide PN junction diode and its preparation method

Abstract

The present invention discloses a high-voltage gallium oxide PN junction diode and a preparation method thereof, which mainly solves the problem that the existing technology cannot effectively improve the reverse breakdown voltage of the device and has a large on-resistance. From bottom to top, it comprises: a cathode metal (1), a gallium oxide substrate (2), a gallium oxide lightly doped epitaxial layer (3), a semiconductor dielectric layer (4), and an anode metal (5). The two ends of the semiconductor dielectric layer (4) use spin-on glass (SOG) as an edge dielectric to form an inverted trapezoidal groove structure in the middle of the upper part of the gallium oxide lightly doped epitaxial layer. A p-type semiconductor material is deposited in the groove as a middle end dielectric to increase the edge peak electric field. The present invention improves the breakdown voltage, reduces the on-resistance, and improves the withstand voltage of the gallium oxide device, and can be used in electronic systems for communications, power electronics, signal processing, and aerospace.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide PN junction diode, which can be used in electronic systems of communications, power electronics, signal processing, and aerospace. Technical Background

[0002] Gallium oxide, an emerging ultra-wide bandgap semiconductor material, is becoming a research hotspot due to its large bandgap and high theoretical breakdown electric field. Advances in material growth, the low cost of growing large single crystals, and increasingly advanced epitaxial growth techniques have enabled the initial scalability of gallium oxide production, demonstrating its enormous potential. The wide bandgap enables lower power loss and higher conversion efficiency in power electronics applications, leading to rapid development.

[0003] With the rapid development of gallium oxide single crystal growth technology, as well as the realization of high-quality epitaxy and controllable n-type doping, gallium oxide has broad application prospects in power electronics. Although the maximum breakdown electric field of currently reported gallium oxide devices has exceeded the theoretical limits of GaN and SiC, there is still a significant gap to reach the theoretical limit of gallium oxide, and there is still much room for improvement in the withstand voltage characteristics of gallium oxide.

[0004] Ma Xiaohua and others disclosed "A high breakdown voltage gallium oxide power diode and its preparation method" in patent document application number 202111069074.7, which uses a thin NiO layer with P-type characteristics and a β-Ga2O3 drift layer to form a heterogeneous PN junction structure to reduce the peak electric field at the edge of the device, improve the interface characteristics between the anode metal and gallium oxide, reduce reverse leakage current, and increase the breakdown voltage of the gallium oxide diode.

[0005] Wang B et al. published “High-voltage vertical Ga2O3 power rectifiers operational at high temperatures up to 600K” in Applied Physics Letters. They used an edge dielectric layer structure with spin-on glass (SOG) to increase the peak electric field at the edge of the device and improve the breakdown voltage of the gallium oxide diode.

[0006] Although the above method can improve the reverse breakdown voltage of the device, the improvement effect is limited. At the same time, it seriously increases the forward on-resistance and power consumption of the device. In addition, the preparation process of the beveled mesa structure is complex and the process is tedious. Summary of the Invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide a high-voltage gallium oxide PN junction diode and a preparation method thereof, so as to further improve the reverse breakdown voltage, reduce the forward on-resistance and power consumption of the device, and reduce the process complexity.

[0008] To achieve the above purpose, the technical solutions of the present invention are as follows:

[0009] 1. A high-voltage gallium oxide PN junction diode, comprising, from bottom to top, a cathode metal, a gallium oxide substrate, a lightly doped gallium oxide epitaxial layer, a semiconductor dielectric layer, and an anode metal. The semiconductor dielectric layer has spin-on-glass (SOG) as an edge dielectric at both ends, forming an inverted trapezoidal groove structure. A p-type semiconductor material is deposited within the groove as a mid-end dielectric to enhance the edge electric field, thereby increasing the device's breakdown voltage.

[0010] Furthermore, the p-type semiconductor material deposited in the groove may be nickel oxide, copper oxide or tin oxide.

[0011] Furthermore, the cathode metal is Ti / Au, and the thickness of the first layer of Ti close to the gallium oxide substrate is 20-50 nm, and the thickness of the second layer of Au metal is 100-400 nm.

[0012] Furthermore, the thickness of the gallium oxide substrate is 300 to 650 μm, and the effective doping carrier concentration is 10 18 ~10 19 cm -3 , the doping ion types are Si ions or Sn ions.

[0013] Furthermore, the thickness of the gallium oxide lightly doped epitaxial layer is 3 to 15 μm, and the doping carrier concentration is 10 16 ~10 18 cm -3 .

[0014] Furthermore, the anode metal of the PN junction diode is Ni / Au metal, and the thickness of the first layer of metal Ni is 45-60 nm, and the thickness of the second layer of metal Au is 200-400 nm.

[0015] 2. A method for manufacturing a high-voltage gallium oxide PN diode, comprising the following steps:

[0016] 1) Cleaning the gallium oxide substrate with acetone, isopropyl alcohol, and deionized water in sequence;

[0017] 2) using hydride vapor phase epitaxy (HVPE) to grow a lightly doped gallium oxide layer on the front of the cleaned gallium oxide substrate, depositing an ohmic cathode metal on the back of the gallium oxide substrate by magnetron sputtering in an argon atmosphere, and performing ohmic annealing on the ohmic cathode metal;

[0018] 3) Depositing a semiconductor dielectric layer on the gallium oxide epitaxial layer:

[0019] 3a) using a spin coater to spin-coat the spin-on glass (SOG) onto the surface of the gallium oxide epitaxial layer;

[0020] 3b) forming a photolithographic pattern on the surface of the spin-on-glass (SOG) using photolithography technology. A BOE solution prepared by mixing 2 ml of 49% hydrofluoric acid with 68 ml of deionized water was used to immerse and etch the SOG. The mask pattern formed by the photoresist was transferred to the SOG, forming an inverted trapezoidal groove in the gallium oxide epitaxial layer.

[0021] 3c) Setting the magnetron sputtering process conditions: power of 100 W, oxygen to argon ratio of 50%, processing time of 80-120 minutes, pressure of 10 mtorr, and ambient temperature of 25° C.;

[0022] 3d) depositing a p-type semiconductor material with a thickness of 11 to 30 nm in the inverted trapezoidal groove by magnetron sputtering, wherein the p-type semiconductor material and the edge spin-on glass (SOG) together constitute a semiconductor dielectric layer with an inverted trapezoidal groove structure;

[0023] 4) Anode pattern is formed on the front surface of the semiconductor dielectric layer using a photolithography process, and anode metal is deposited by electron beam evaporation according to the anode pattern and then peeled off to complete device fabrication.

[0024] Compared with the existing technology, the present invention has the following advantages:

[0025] First, compared to conventional gallium oxide PN junction diodes that do not have an angled dielectric layer structure, the present invention utilizes a semiconductor dielectric layer with an inverted trapezoidal groove structure, which not only allows the peak electric field to be primarily concentrated at both ends of the device, but also effectively reduces the peak electric field and improves the device's breakdown voltage.

[0026] Secondly, since the present invention uses spin-on glass (SOG) as an etching mask, compared with the existing traditional process for preparing gallium oxide PN junction diodes, there is no need for multi-step photolithography and etching. Only wet etching is needed to form an inverted trapezoidal groove structure, so the preparation process is simple.

[0027] Third, the present invention uses spin-on-glass (SOG) as the edge dielectric layer. Since the dielectric constant and critical field strength of the spin-on-glass (SOG) are relatively large, the breakdown voltage of the device can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural diagram of a gallium oxide PN diode according to the prior art solution.

[0029] Figure 2This is a schematic structural diagram of the high-voltage gallium oxide PN junction diode of the present invention.

[0030] Figure 3 Made for this invention Figure 2 Implementation flow chart of gallium oxide PN junction diode. DETAILED DESCRIPTION

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the present invention is further described below with reference to the embodiments and accompanying drawings required for the technical description of the present invention. However, the present invention is not limited to these embodiments, and those skilled in the art will appreciate that the present invention can also be implemented in other embodiments without these specific details.

[0032] Reference Figure 2 The high-voltage gallium oxide PN junction diode of the present invention comprises: a cathode metal 1, a gallium oxide substrate 2, a gallium oxide lightly doped epitaxial layer 3, a semiconductor dielectric layer 4 and an anode metal 5.

[0033] The cathode metal 1 is located on the back of the gallium oxide substrate 2 and is made of Ti / Au, with the thickness of Ti being 20 to 50 nm and the thickness of Au being 100 to 400 nm.

[0034] The gallium oxide substrate 2 has a thickness of 300 to 650 μm and a doping concentration of 10 18 ~10 19 cm -3 ;

[0035] The gallium oxide lightly doped epitaxial layer 3 is located on the gallium oxide substrate 2 and has a thickness of 3 to 15 μm and a doping concentration of 10 16 ~10 18 cm -3 ;

[0036] The semiconductor dielectric layer 4 has an inverted trapezoidal groove structure and is located on the lightly doped gallium oxide epitaxial layer 3. Its edge dielectric is made of spin-on-glass (SOG). P-type semiconductor material is deposited in the groove as the middle dielectric. The p-type semiconductor material and the edge spin-on-glass (SOG) together constitute the semiconductor dielectric layer 4 to enhance the edge electric field, thereby increasing the breakdown voltage of the device.

[0037] The anode metal 5 is located on the semiconductor dielectric layer 4 and is made of Ni / Au, with the thickness of Ni being 45-60 nm and the thickness of Au being 200-400 nm.

[0038] Reference Figure 3 The present invention provides a method for producing Figure 2 The following three embodiments of the device structure are:

[0039] Example 1: A high-voltage gallium oxide PN junction diode is manufactured by depositing nickel oxide material in an inverted trapezoidal groove of a semiconductor dielectric layer with a depth of 11 nm.

[0040] Step 1: Cleaning the gallium oxide substrate material.

[0041] The thickness of the gallium oxide substrate 2 is selected to be 650 μm, and the effective doping carrier concentration is 2×10 18 cm -3 The doped ion type was Sn ion, and the surface was ultrasonically cleaned for 3 minutes using acetone-isopropanol-deionized water at an ultrasonic intensity of 2.0, and then dried using nitrogen gas.

[0042] Step 2: Using the hydride vapor phase epitaxy (HVPE) method, a lightly doped gallium oxide epitaxial layer is prepared on the front side of the cleaned gallium oxide substrate.

[0043] 2.1) In the high temperature reaction zone of the HVPE vertical reactor, HCl is reacted with high purity metallic Ga at 850°C to produce GaCl and GaCl3;

[0044] 2.2) The GaCl and GaCl3 generated in the high temperature reaction zone are pushed into the low temperature reaction zone, and the gallium oxide substrate 2 is placed face up in the low temperature reaction zone of the HVPE vertical reactor. The GaCl and GaCl3 react with oxygen at 600°C on the gallium oxide substrate to generate a 10 μm thick and 2×10 16 cm -3 Gallium oxide epitaxial layer 3.

[0045] Step 3: Prepare cathode metal.

[0046] Metal Ti / Au is deposited on the back of the gallium oxide substrate 2 by magnetron sputtering, with the thickness of the first Ti layer close to the gallium oxide substrate being 20 nm and the thickness of the second Au metal layer being 400 nm, to form the cathode metal 1 .

[0047] Step 4: Ohmic contact metal annealing.

[0048] The cathode metal was annealed in a nitrogen atmosphere using an annealing furnace at a temperature of 470° C. for 1 minute.

[0049] Step 5: Prepare the semiconductor dielectric layer.

[0050] 5.1) Preparation of spin-on-glass (SOG) deposition mask layer:

[0051] 5.1.1) Spin-coat a layer of spin-on-glass (SOG) on the annealed gallium oxide epitaxial layer 3 using the following spin-coating conditions: spin-coating speed of 3000 rpm, spin-coating time of 17 s, and bake on a 200°C hot plate for 1 minute to form a SOG mask layer.

[0052] 5.1.2) Using photolithography technology, prepare a mask pattern on the surface of the spin-on-glass (SOG) using photoresist;

[0053] 5.1.3) Prepare a BOE solution using 2 ml of 49% hydrofluoric acid and 68 ml of deionized water. Immerse the sample in this etching solution to etch the spin-on-glass (SOG). Transfer the photoresist mask pattern to the SOG, forming an 11 nm thick inverted trapezoidal groove in the gallium oxide epitaxial layer 3.

[0054] 5.1.4) Ultrasonic cleaning of the samples with the spin-on-glass (SOG) mask layer was performed using acetone-isopropyl alcohol-deionized water at an ultrasonic intensity of 2.0 for 3 minutes, followed by drying with nitrogen to remove the photoresist on the surface of the SOG.

[0055] 5.2) Preparation of nickel oxide dielectric layer:

[0056] 5.2.1) Using photolithography technology, use photoresist to form the required nickel oxide deposition pattern on the spin-on-glass (SOG) surface;

[0057] 5.2.2) Set the process conditions to 10 mTorr chamber pressure, 25°C deposition temperature, 100 W power, 50% oxygen concentration, and an O2 / Ar flow rate of 12 / 6 sccm. Use a nickel target to sputter the nickel oxide deposition pattern for 80 minutes, forming an 11 nm thick nickel oxide dielectric layer in the inverted trapezoidal groove.

[0058] 5.2.3) Nickel oxide stripping:

[0059] The sample with the nickel oxide dielectric layer deposited was placed in an acetone solution and ultrasonically cleaned at an ultrasonic intensity of 2.0 for 3 minutes; the ultrasonically cleaned sample was then boiled in a deposited dielectric stripping solution at 60°C for 15 minutes; the sample after boiling the dielectric stripping solution was then ultrasonically cleaned in acetone-isopropanol-deionized water at an ultrasonic intensity of 2.0 for 3 minutes, and then dried with nitrogen to remove the nickel oxide outside the nickel oxide photolithography pattern area;

[0060] 5.3) The nickel oxide dielectric layer deposited in the middle of the gallium oxide epitaxial layer 3 and the spin-on glass (SOG) spin-coated on the edge of the gallium oxide epitaxial layer 3 together form the semiconductor dielectric layer 4.

[0061] Step 6: Prepare anode metal.

[0062] 6.1) Using photolithography technology, anode patterns are prepared on the surface of the semiconductor dielectric layer 4 using photoresist;

[0063] 6.2) Electron beam evaporation was used to deposit metal Ni / Au on the anode pattern, with the thickness of the first metal Ni layer being 45 nm and the thickness of the second metal Au layer being 400 nm.

[0064] 6.3) Using N-methylpyrrolidone solution to wash away the photoresist, that is, to remove the metal material deposited on the semiconductor dielectric layer 4 where there is no photolithographic pattern, thus completing the device fabrication.

[0065] Example 2: A high-voltage gallium oxide PN junction diode is manufactured by forming an inverted trapezoidal groove in a semiconductor dielectric layer with a thickness of 27 nm and depositing copper oxide material in the groove.

[0066] Step 1: Gallium oxide material cleaning.

[0067] The thickness of the gallium oxide substrate 2 is selected to be 600 μm, and the effective doping carrier concentration is 2×10 19 cm -3 The doped ion type was Sn ion, and the surface was ultrasonically cleaned for 3 minutes using acetone-isopropanol-deionized water at an ultrasonic intensity of 2.0, and then dried using nitrogen gas.

[0068] Step 2: Using the hydride vapor phase epitaxy (HVPE) method, a lightly doped gallium oxide epitaxial layer is prepared on the front side of the cleaned gallium oxide substrate.

[0069] First, in the high-temperature reaction zone of the HVPE vertical reactor, HCl reacts with high-purity metallic Ga at 850°C to produce GaCl and GaCl3;

[0070] Then, the GaCl and GaCl3 generated in the high-temperature reaction zone are pushed into the low-temperature reaction zone, and the gallium oxide substrate 2 is placed face up in the low-temperature reaction zone of the HVPE vertical reactor to react with GaCl and GaCl3 and oxygen at 600°C to generate a 2×10-30-1 ... 17 cm -3 Gallium oxide epitaxial layer 3.

[0071] Step 3: Prepare cathode ohmic metal.

[0072] A magnetron sputtering method is used to deposit metal Ti / Au on the back side of the gallium oxide substrate 2, with the thickness of the first Ti layer close to the gallium oxide substrate being 30 nm and the thickness of the second Au metal layer being 300 nm, to form a cathode metal 1;

[0073] The cathode metal was annealed in a nitrogen atmosphere using an annealing furnace at a temperature of 470° C. for 2 minutes.

[0074] Step 4: Prepare a semiconductor dielectric layer.

[0075] 4a) Preparation of spin-on-glass (SOG) deposition mask layer:

[0076] 4a1) Spin-on-glass (SOG) was spin-coated on the annealed gallium oxide epitaxial layer 3 at a speed of 2000 rpm for 15 seconds using a spinner, and then baked on a hot plate at 200° C. for 1 minute to form a spin-on-glass (SOG) mask layer;

[0077] 4a2) using photolithography technology to prepare a mask pattern on the surface of the spin-on-glass (SOG) using photoresist;

[0078] 4a3) A BOE solution was prepared using 2 ml of 49% hydrofluoric acid and 68 ml of deionized water. The gallium oxide epitaxial layer was immersed in the solution to etch the spin-on-glass (SOG). The mask pattern formed by the photoresist was transferred to the SOG, forming an inverted trapezoidal groove with a thickness of 27 nm.

[0079] 4a4) The devices prepared with the spin-on-glass (SOG) mask layer were ultrasonically cleaned using acetone-isopropyl alcohol-deionized water at an ultrasonic intensity of 2.0 for 3 minutes, and then blown dry with nitrogen to remove the photoresist on the surface of the spin-on-glass (SOG).

[0080] 4b) Preparation of copper oxide dielectric layer:

[0081] 4b1) Using photolithography technology, a photoresist is used to form the required copper oxide deposition pattern on the surface of the spin-on-glass (SOG).

[0082] 4b2) The sample with the prepared copper oxide deposition pattern was placed in a magnetron sputtering apparatus. Under the process conditions of an intracavity pressure of 8 mTorr, a deposition temperature of 25°C, a power of 100 W, an intracavity oxygen concentration of 50%, and a gas flow rate of O2 / Ar of 12 / 6 sccm, a copper target was used for sputtering on the copper oxide deposition pattern for 120 minutes, forming a copper oxide dielectric layer with a thickness of 27 nm in the inverted trapezoidal groove.

[0083] 4b3) Copper oxide stripping:

[0084] The sample with the deposited oxygen copper dielectric layer was ultrasonically cleaned in an acetone solution at an ultrasonic intensity of 2.0 for 3 minutes; the ultrasonically cleaned sample was then boiled in a deposition dielectric stripping solution at 60°C for 15 minutes; the sample after boiling in the dielectric stripping solution was then ultrasonically cleaned in acetone-isopropanol-deionized water at an ultrasonic intensity of 2.0 for 3 minutes, and then dried with nitrogen to remove copper oxide outside the copper oxide photolithography pattern area;

[0085] 4c) The copper oxide dielectric layer deposited in the middle of the gallium oxide epitaxial layer 3 and the spin-on glass (SOG) spin-coated on the edge of the gallium oxide epitaxial layer 3 together form the semiconductor dielectric layer 4.

[0086] Step 5: Prepare the anode metal.

[0087] 5a) using photolithography technology to prepare an anode pattern on the surface of the semiconductor dielectric layer 4 using photoresist;

[0088] 5b) Electron beam evaporation is used to deposit metal Ni / Au on the anode pattern, with the thickness of the first metal Ni layer being 50 nm and the thickness of the second metal Au layer being 300 nm.

[0089] 5c) Using N-methylpyrrolidone solution to wash away the photoresist, that is, to remove the metal material deposited on the semiconductor dielectric layer 4 where there is no photolithographic pattern, thus completing the device fabrication.

[0090] Example 3: Manufacturing a high-voltage gallium oxide PN junction diode with an inverted trapezoidal groove of 18 nm in thickness in a semiconductor dielectric layer and depositing tin oxide material in the groove.

[0091] Step A: Gallium oxide material cleaning.

[0092] The thickness of the gallium oxide substrate 2 is selected to be 300 μm, and the effective doping carrier concentration is 1×10 19 cm -3 The doped ion type was Sn ion, and the surface was ultrasonically cleaned for 3 minutes using acetone-isopropanol-deionized water at an ultrasonic intensity of 2.0, and then dried using nitrogen gas.

[0093] Step B: using the hydride vapor phase epitaxy (HVPE) method to prepare a lightly doped gallium oxide epitaxial layer on the front side of the cleaned gallium oxide substrate.

[0094] B1) in a high temperature reaction zone of an HVPE vertical reactor, HCl is reacted with high purity metallic Ga at 850°C to produce GaCl and GaCl3;

[0095] B2) The GaCl and GaCl3 generated in the high-temperature reaction zone are pushed into the low-temperature reaction zone, and the gallium oxide substrate 2 is placed face up in the low-temperature reaction zone of the HVPE vertical reactor, so that the GaCl and GaCl3 react with oxygen at 600°C to generate a 9 μm thick and 1×10-4 doping concentration gallium oxide on the gallium oxide substrate. 16 cm -3 Gallium oxide epitaxial layer 3.

[0096] Step C: Preparation of cathode ohmic metal.

[0097] Metal Ti / Au is deposited on the back of the gallium oxide substrate 2 by magnetron sputtering to form a cathode metal 1 with a thickness of 390 nm, wherein the thickness of the first Ti layer close to the gallium oxide substrate is 40 nm, and the thickness of the second Au metal layer is 350 nm.

[0098] Step D: Ohmic contact metal annealing.

[0099] The cathode metal was annealed in an annealing furnace under a nitrogen atmosphere with an annealing temperature of 500° C. and an annealing time of 1 minute.

[0100] Step E: preparing a semiconductor dielectric layer.

[0101] E1) Preparation of spin-on-glass (SOG) deposition mask layer:

[0102] E1.1) Spin-coat a layer of spin-on glass (SOG) onto the annealed gallium oxide epitaxial layer 3 using the following spin-coating conditions: 3000 rpm, 15 s, and bake on a 200°C hot plate for 1 minute.

[0103] E1.2) Using photolithography technology, prepare a mask pattern on the surface of the spin-on-glass (SOG) using photoresist;

[0104] E1.3) Prepare a BOE solution using 2 ml of 49% hydrofluoric acid and 68 ml of deionized water. Immerse the sample with the mask pattern in the solution to etch the spin-on-glass (SOG) film. This transfers the mask pattern formed by the photoresist to the SOG film, forming an inverted trapezoidal groove structure with a thickness of 18 nm.

[0105] E1.4) Ultrasonic clean the sample with the spin-on-glass (SOG) mask layer using acetone-isopropyl alcohol-deionized water at an ultrasonic intensity of 2.0 for 3 minutes, and then blow dry with nitrogen to remove the photoresist on the surface of the SOG.

[0106] E2) Preparation of tin oxide dielectric layer:

[0107] E2.1) Using photolithography technology, use photoresist to form the required tin oxide deposition pattern on the spin-on-glass (SOG) surface.

[0108] E2.2) Place the sample with the prepared tin oxide deposition pattern into a magnetron sputtering apparatus. Set the process conditions to 10 mTorr, 25°C deposition temperature, 100 W power, 55% oxygen concentration, and an O2 / Ar flow rate of 12 / 6 sccm. Use a tin target to sputter the tin oxide deposition pattern for 90 minutes, forming an 18 nm thick tin oxide dielectric layer within the inverted trapezoidal grooves.

[0109] E2.3) Tin oxide peeling:

[0110] The sample with the deposited oxide tin dielectric layer was placed in an acetone solution and ultrasonically cleaned at an ultrasonic intensity of 2.0 for 3 minutes; the ultrasonically cleaned sample was then boiled in a deposition dielectric stripping solution at 60°C for 15 minutes;

[0111] E2.4) After the dielectric stripping solution has been boiled, ultrasonically clean the sample using acetone, isopropyl alcohol, and deionized water at an ultrasonic intensity of 2.0 for 3 minutes. Then, blow dry with nitrogen to remove any tin oxide outside the tin oxide photolithography pattern.

[0112] E2.5) The tin oxide dielectric layer in the middle of the gallium oxide epitaxial layer 3 and the spin-on glass (SOG) at the edge of the gallium oxide epitaxial layer 3 together form a semiconductor dielectric layer 4 .

[0113] Step F: Preparation of anode metal.

[0114] Using photolithography technology, anode pattern A is first prepared on the surface of semiconductor dielectric layer 4 using photoresist. Then, Ni metal with a thickness of 45nm and Au with a thickness of 400nm are deposited on the anode pattern by electron beam evaporation to form anode metal. Finally, N-methylpyrrolidone solution is used to wash away the photoresist, that is, to remove the metal material deposited on the semiconductor dielectric layer 4 without the photolithographic pattern, and the device is completed.

[0115] The above descriptions are only three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, various modifications and changes in form and details can be made without departing from the principles and structure of the present invention. For example, the choice of spin-on glass (SOG) can use any of P-type, N-type or neutral; the oxide material can be any of nickel oxide, copper oxide, and tin oxide; the oxide medium deposition is not limited to magnetron sputtering deposition, and laser pulse deposition can also be used; the anode and cathode metal preparation method is not limited to electron beam evaporation, and any of magnetron sputtering or thermal evaporation methods can also be used; however, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a high-voltage gallium oxide PN diode, characterized in that: The following steps are involved: 1) cleaning the gallium oxide substrate (2) in sequence with acetone, isopropanol, and deionized water; 2) using a hydride vapor phase epitaxy (HVPE) method to epitaxially grow a lightly doped gallium oxide layer (3) on the front side of the cleaned gallium oxide substrate (2), using magnetron sputtering in an argon atmosphere to deposit an ohmic cathode metal (1) on the back side of the gallium oxide substrate, and performing ohmic annealing on the ohmic cathode metal (1); 3) Depositing a semiconductor dielectric layer (4) on the gallium oxide epitaxial layer (3): 3a) using a spin coating machine to spin-coat the spin-on glass (SOG) onto the surface of the gallium oxide epitaxial layer (3); 3b) forming a photolithographic pattern on the surface of the spin-on-glass (SOG) using photolithography technology. A BOE solution prepared by mixing 2 ml of 49% hydrofluoric acid with 68 ml of deionized water was used to immerse and etch the SOG to transfer the mask pattern formed by the photoresist to the SOG, forming an inverted trapezoidal groove structure. 3c) Setting the magnetron sputtering process conditions: power of 100 W, oxygen to argon ratio of 50%, processing time of 80-120 minutes, pressure of 10 mtorr, and ambient temperature of 25° C.; 3d) depositing a p-type semiconductor material with a thickness of 11 to 30 nm in the inverted trapezoidal groove by magnetron sputtering, wherein the p-type semiconductor material and the edge spin-on glass (SOG) together form a semiconductor dielectric layer (4); 4) A photolithography process is used to form an anode pattern on the front surface of the semiconductor dielectric layer (4), and an anode metal (5) is deposited by electron beam evaporation according to the anode pattern and then peeled off to complete the device manufacturing.

2. The method according to claim 1, characterized in that In the step 2), a lightly doped gallium oxide layer (3) is grown on the front side of the cleaned gallium oxide substrate (2) using hydride vapor phase epitaxy (HVPE) technology, which is achieved as follows: 2a) Setting hydride vapor phase epitaxy (HVPE) process conditions: in an ammonia atmosphere, in a high-temperature reaction zone of a hydride vapor phase epitaxy (HVPE) vertical reactor, reacting hydrogen chloride gas with high-purity metallic Ga at a temperature of 800-900° C. to produce GaCl and GaCl3; 2b) placing the cleaned gallium oxide substrate (2) into an HVPE vertical reactor; 2c) pushing the GaCl and GaCl3 generated in the high-temperature reaction zone into the low-temperature reaction zone, and then placing the gallium oxide substrate (2) face-up in the low-temperature reaction zone of the HVPE vertical reactor, and causing the high-temperature reaction zone products GaCl and GaCl3 to react with oxygen at a temperature of 500-650° C. to form a gallium oxide epitaxial layer (3) on the gallium oxide substrate (2).

3. The method according to claim 1, characterized in that In step 2), magnetron sputtering is used to deposit an ohmic cathode metal on the back of the gallium oxide substrate. The process conditions are: power of 100-300 W, sputtering time of 30-90 minutes, pressure of 6-12 mtorr, and ambient temperature of 25°C.

4. The method according to claim 1, characterized in that The annealing of the ohmic cathode metal in step 2) is performed in a nitrogen atmosphere at a temperature of 400-500° C. and for a time of 1-3 minutes.

5. The high-voltage gallium oxide PN junction diode prepared by the method according to claim 1, comprising, from bottom to top: A cathode metal (1), a gallium oxide substrate (2), a lightly doped gallium oxide epitaxial layer (3), a semiconductor dielectric layer (4) and an anode metal (5) are provided, wherein both ends of the semiconductor dielectric layer (4) use spin-on-glass (SOG) as an edge dielectric to form an inverted trapezoidal groove structure, and a p-type semiconductor material is deposited in the groove as a middle-end dielectric to enhance the edge electric field, thereby enhancing the breakdown voltage of the device.

6. The diode according to claim 5, characterized in that The thickness of the semiconductor dielectric layer (4) with the inverted trapezoidal groove structure is 11-27 nm, and the p-type semiconductor material deposited in the groove can be nickel oxide, copper oxide or tin oxide.

7. The diode according to claim 5, characterized in that The cathode metal (1) is Ti / Au, and the thickness of the first layer of Ti close to the gallium oxide substrate (2) is 20-50 nm, and the thickness of the second layer of Au metal is 100-400 nm.

8. The diode according to claim 5, characterized in that The thickness of the gallium oxide substrate (2) is 300 to 650 μm, and the effective doping carrier concentration is 10 18 ~10 19 cm -3 , the doping ion types are Si ions or Sn ions.

9. The diode according to claim 5, characterized in that The thickness of the gallium oxide lightly doped epitaxial layer (3) is 3 to 15 μm, and the doping carrier concentration is 10 16 ~10 18 cm -3 .

10. The diode according to claim 5, characterized in that The PN junction diode anode metal (6) adopts Ni / Au metal, and the thickness of the first metal layer Ni is 45-60nm, and the thickness of the second metal layer Au is 200-400nm.

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