Method for manufacturing a semiconductor device

Abstract

The present application relates to a method for manufacturing a semiconductor device. The manufacturing method includes: providing a substrate; forming monitoring holes in a non-device processing area of the substrate, and forming process holes in a device processing area of the substrate; wherein, the monitoring holes at least include a first hole portion and a second hole portion with different depths; filling gate materials in the process holes and the monitoring holes to form a gate material layer; wherein, the gate materials are different from the materials of the substrate; etching the portions of the gate material layer located in the process holes and the monitoring holes synchronously to form grooves in the process holes; determining whether the depth of the bottom edge of the grooves meets the manufacturing requirements by the remaining situation of the gate materials in the monitoring holes. The method for manufacturing a semiconductor device of the present application can directly monitor online the depth of the bottom edge of the grooves formed after etching the gate material layer, timely detect abnormalities, and avoid many subsequent adverse effects.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing, and particularly to a method for manufacturing a semiconductor device. Background Art

[0002] An IGBT (Insulated Gate Bipolar Transistor) is a composite fully controlled voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). It has the advantages of both the high input impedance of the MOSFET and the low on-state voltage drop of the BJT, and is widely used in fields such as rail transit, smart grid, aerospace, electric vehicles, and new energy equipment.

[0003] In the manufacturing process of IGBT semiconductor devices, it is necessary to etch polysilicon to form a groove, which is roughly arc-shaped with higher sides and a lower center. Controlling the depth of the bottom edge of the groove is an important part of the process. If the bottom edge of the groove is too shallow, there will be residues, and if it is too deep, a channel cannot be formed. Currently, it is impossible to directly measure the depth of the bottom edge of the groove online. Only the thickness of the gate oxide layer after polysilicon etching can be used to indirectly reflect the depth of the bottom edge of the groove, but it cannot reflect the morphology or abnormal depth of the bottom edge of the groove. Usually, only abnormal gate threshold voltages can be found during the wafer testing process, which will cause many adverse effects. Summary of the Invention

[0004] Based on the above defects in the prior art, one of the purposes of this application is to provide a method for manufacturing a semiconductor device, which can directly monitor the depth of the bottom edge of the groove formed after etching the gate material layer online, timely detect abnormalities, and avoid many subsequent adverse effects.

[0005] To this end, this application provides the following technical solutions.

[0006] This application provides a method for manufacturing a semiconductor device, and the manufacturing method includes:

[0007] Providing a substrate;

[0008] Forming a monitoring hole in the non-device processing area of the substrate, and forming a process hole in the device processing area of the substrate; wherein, the monitoring hole at least includes a first hole portion and a second hole portion with different depths.

[0009] Fill the process hole and the monitoring hole with a gate material to form a gate material layer; wherein, the gate material is different from the material of the substrate;

[0010] Etch the part of the gate material layer located in the process hole and the part located in the monitoring hole synchronously to form a groove in the process hole;

[0011] Determine whether the depth of the bottom edge of the groove meets the preparation requirements based on the remaining situation of the gate material in the monitoring hole.

[0012] In at least one embodiment, the depth of the first hole portion is not less than the minimum value of the acceptable numerical range, the depth of the second hole portion is not greater than the maximum value of the acceptable numerical range, and the depth of the second hole portion is greater than the depth of the first hole portion;

[0013] Wherein, the acceptable numerical range refers to the numerical range when the depth of the bottom edge of the groove meets the preparation requirements.

[0014] In at least one embodiment, the monitoring hole further includes a third hole portion, and the depth of the third hole portion is greater than the depth of the first hole portion and less than the depth of the second hole portion.

[0015] In at least one embodiment, the first hole portion, the second hole portion and the third hole portion are interconnected to form a stepped hole, or

[0016] The first hole portion, the second hole portion and the third hole portion are arranged separately.

[0017] In at least one embodiment, the depth of the third hole portion is set to be equal to the expected value of the depth of the bottom edge of the groove.

[0018] In at least one embodiment, the depth of the first hole portion is equal to the minimum value of the acceptable numerical range, and the depth of the second hole portion is equal to the maximum value of the acceptable numerical range.

[0019] In at least one embodiment, the depth range of the first hole portion is from 0.08 μm to 0.12 μm, and the depth range of the second hole portion is from 0.28 μm to 0.32 μm.

[0020] In at least one embodiment, forming the monitoring hole in the non-device processing area of the substrate includes:

[0021] Form a mask layer on the substrate;

[0022] Pattern the mask layer based on a halftone mask;

[0023] Etch the substrate based on the patterned mask layer to form the monitoring holes.

[0024] In at least one embodiment, forming monitoring holes in the non-device processing area of the substrate and forming process holes in the device processing area of the substrate includes:

[0025] Form a mask layer on the substrate;

[0026] Pattern the mask layer based on a halftone mask;

[0027] Etch the substrate based on the patterned mask layer to simultaneously form the monitoring holes and the process holes.

[0028] In at least one embodiment, the semiconductor device is an insulated gate bipolar transistor.

[0029] Advantageous Effects

[0030] The present application provides a method for manufacturing a semiconductor device. By forming monitoring holes in the non-device processing area of the substrate and forming process holes in the device processing area of the substrate, the monitoring holes at least include a first hole portion and a second hole portion with different depths. The portions of the gate material layer located in the process holes and in the monitoring holes are etched synchronously. By monitoring the remaining situation of the gate material in the monitoring holes, it is determined whether the depth of the bottom edge of the groove etched in the process holes meets the manufacturing requirements, realizing on-line monitoring of the depth of the bottom edge of the groove, and thus being able to detect abnormalities in a timely manner and avoid many subsequent adverse effects. Description of the Drawings

[0031] Figure 1 Shows a schematic diagram of the structure formed after depositing polysilicon in the semiconductor device manufacturing process provided by the related art.

[0032] Figure 2 Shows Figure 1 The schematic diagram of the structure formed after the polysilicon in is etched.

[0033] Figure 3 Shows a flowchart of the method for manufacturing a semiconductor device provided by an embodiment of the present application.

[0034] Figure 4 Shows a schematic diagram of the structure of the monitoring holes of the first embodiment of the present application.

[0035] Figures 5a to 5d Shows a schematic diagram of the structure of the monitoring holes in the preparation process of the first embodiment.

[0036] Figure 5e Shows a schematic diagram of the structure of the monitoring holes and the process holes after the preparation of the first embodiment is completed.

[0037] Figure 5f The structural schematic diagram after forming a gate material layer by depositing a gate material at a monitoring hole and a process hole of the first embodiment is shown.

[0038] Figure 5g Shown is Figure 5f the schematic diagram of the structure formed after etching the gate material layer in

[0039] Figure 6 The structural schematic diagram of the monitoring hole of the second embodiment of the present application is shown.

[0040] Figures 7a to 7d The structural schematic diagram of the monitoring hole of the second embodiment during the preparation process is shown.

[0041] Figure 7e The structural schematic diagram of the monitoring hole and the process hole of the second embodiment after the preparation is completed is shown.

[0042] Figure 7f The structural schematic diagram after forming a gate material layer by depositing a gate material at the monitoring hole and the process hole of the second embodiment is shown.

[0043] Figure 7g Shown is Figure 7f the schematic diagram of the structure formed after etching the gate material layer in

[0044] Description of reference numerals

[0045] 10, polysilicon; 20, groove; 30, substrate; h, distance between the bottom edge of the groove and the top surface of the substrate;

[0046] 100, device processing area; 200, non-device processing area;

[0047] 1, substrate; 2, stepped hole; 21, first hole part; 22, second hole part; 23, third hole part;

[0048] 3, hard mask layer; 4, photoresist layer; 5, gate material layer;

[0049] 6, monitoring hole; 61, first hole part; 62, second hole part; 63, third hole part;

[0050] 7, process hole. Detailed implementation manners

[0051] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0052] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0053] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals denote like elements throughout.

[0054] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. And when discussing the second element, component, region, layer, or portion, it does not imply that the present application necessarily has a first element, component, region, layer, or portion.

[0055] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and not to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] To fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0058] Related Art

[0059] Figure 1 The figure shows a schematic diagram of the structure formed after depositing polysilicon in the semiconductor device manufacturing process provided by the related art, as Figure 1 shown, a gate material layer 10 is deposited and formed on a substrate 30. Figure 2 The figure shows Figure 1 a schematic diagram of the structure formed after etching the polysilicon in Figure 2As shown, after etching the gate material layer 10, a groove 20 is formed. During the process of fabricating a semiconductor device, controlling the depth h of the bottom edge of the groove 20 (i.e., the distance between the top edge of the gate material layer 10 and the top surface of the substrate 30) is a crucial step. If the bottom edge of the groove 20 is too shallow, residues will remain; if it is too deep, a channel cannot be formed. Currently, it is not possible to directly measure the depth of the bottom edge of the groove 20 online. Only the thickness of the gate oxide layer (not shown in the figure) after etching the gate material layer 10 can indirectly reflect the depth of the bottom edge of the groove 20, but it cannot reflect the topography or abnormal depth of the bottom edge of the groove 20. Usually, an abnormal gate threshold voltage can only be detected during the wafer testing process, which will cause many adverse effects.

[0060] In the present application, the "device processing area" refers to the cell area on the substrate for fabricating semiconductor devices; the "non-device processing area" refers to the scribe line area on the substrate outside the device processing area. During the process of fabricating a semiconductor device, the holes formed in the device processing area are called "process holes", and the holes formed in the non-device processing area are called "monitoring holes".

[0061] In the present application, the "depth" of any hole refers to the distance between the bottom surface of the hole and the top surface of the substrate.

[0062] The following will Figure 3 describe in detail the method for fabricating a semiconductor device according to the present application with reference to FIGS. 7.

[0063] In the present embodiment, as Figure 3 shown, the method for fabricating a semiconductor device includes:

[0064] Step S1: Provide a substrate;

[0065] Step S2: Form monitoring holes in the non-device processing area of the substrate and process holes in the device processing area of the substrate; wherein, the monitoring holes include at least two first hole portions and second hole portions with different depths;

[0066] Step S3: Fill the process holes and the monitoring holes with a gate material to form a gate material layer; wherein, the gate material is different from the material of the substrate;

[0067] Step S4: Simultaneously etch the portions of the gate material layer within the process holes and within the monitoring holes to form a groove within the process holes;

[0068] Step S5: Determine whether the depth of the bottom edge of the groove meets the fabrication requirements by monitoring the remaining amount of the gate material in the monitoring holes.

[0069] By forming monitoring holes in the non-device processing area of the substrate and process holes in the device processing area of the substrate, the monitoring holes at least include a first hole portion and a second hole portion with different depths. The portions of the gate material layer located in the process holes and the monitoring holes are etched synchronously. By monitoring the remaining situation of the gate material in the monitoring holes, it is determined whether the depth of the bottom edge of the groove etched in the process holes meets the preparation requirements, realizing the on-line monitoring of the depth of the bottom edge of the groove, and thus being able to detect abnormalities in time and avoid many subsequent adverse effects.

[0070] In this application, the monitoring holes have various structural forms. Two implementation manners of the monitoring holes are introduced below.

[0071] In the first implementation manner, as Figure 4 shown, the monitoring hole can be formed as a stepped hole 2, and the stepped hole 2 includes a first hole portion 21, a third hole portion 23, and a second hole portion 22 arranged in sequence from top to bottom.

[0072] The stepped hole 2 is formed through the Figures 5a to 5d shown preparation process.

[0073] Specifically, as Figure 5a shown, first, a hard mask layer 3 is formed on the substrate 1; wherein, the material of the substrate 1 can be single crystal silicon, and the material of the hard mask layer 3 can be silicon nitride, silicon oxide, silicon oxynitride or other materials;

[0074] Then, as Figure 5b shown, a patterned photoresist layer 4 is formed on the hard mask layer 3 through a photolithography process, wherein a stepped hole is formed in the photoresist layer 4 by using a halftone mask (the light transmittance of different regions is different);

[0075] Next, as Figure 5c shown, the hard mask layer 3 is etched based on the patterned photoresist layer 4 to pattern the hard mask layer 3 and form a stepped hole on the hard mask layer 3;

[0076] Finally, as Figure 5d shown, the substrate 1 is etched based on the patterned hard mask layer 3 to form a stepped hole 2 in the substrate 1.

[0077] The processed stepped hole 2 and process hole 7 are as Figure 5e shown. The process hole 7 is formed in the device processing area 100, and the stepped hole 2 is formed in the non-device processing area 200.

[0078] During the preparation process of the semiconductor device, the process holes formed in the device processing area of the substrate 1 and the monitoring holes in the non-device processing area are filled with gate material by deposition synchronously to form a gate material layer 5 on the substrate 1. Figure 5fIt shows the situation after the gate material is deposited at the stepped hole 2 and the process hole 7 to form the gate material layer 5. After the deposition is completed, etching is carried out synchronously. Figure 5g It shows the situation after the gate material layer 5 deposited at the monitoring hole and the process hole 7 is etched (the top surface of the gate material layer 5 is actually roughly formed into an arc shape that is high on both sides and low in the middle). At this time, it is possible to judge whether the depth of the bottom edge of the groove formed in the process hole meets the preparation requirements by observing the remaining situation of the gate material in the monitoring hole. Specifically as follows.

[0079] First of all, it should be noted that for the depth of the bottom edge of the groove, it is not necessary to reach an ideal value. The actual depth of the bottom edge of the groove within a certain numerical range can meet the preparation requirements, that is, the depth of the bottom edge of the groove has an acceptable numerical range. Therefore, the first hole portion 21 and the second hole portion 22 can be constructed according to this acceptable numerical range. That is, the depth of the first hole portion 21 can be not less than the minimum value of the acceptable numerical range, the depth of the second hole portion 22 can be not greater than the maximum value of the acceptable numerical range, and the depth of the second hole portion 22 is greater than the depth of the first hole portion 21. In this way, as long as the remaining situation of the material layer in the first hole portion 21 and the second hole portion 22 is observed by using an optical device, it is possible to know whether the depth of the bottom edge of the groove is acceptable. Among them, it should be understood that the depth of the first hole portion 21 refers to the distance between the bottom surface of this hole portion and the top surface of the substrate 1, the depth of the second hole portion 22 refers to the distance between the bottom surface of this hole portion and the top surface of the substrate 1, and the depth of the following third hole portion 23 refers to the distance between the bottom surface of this hole portion and the top surface of the substrate 1.

[0080] Specifically, as Figure 5f shown, through observation by an optical device, it can be found that there is gate material remaining on the second hole portion 22 and there is no gate material remaining on the first hole portion 21. Then it can be judged that the depth of the bottom edge of the groove is between the depths of the first hole portion 21 and the second hole portion 22, belonging to the acceptable range and meeting the preparation requirements. It can be understood that if there is gate material remaining on the first hole portion 21, it is judged that the bottom edge of the groove is too shallow, and if there is no gate material remaining on the second hole portion 22, it is judged that the bottom edge of the groove is too deep. It should be understood that in order to be able to better observe the remaining situation of the gate material in the monitoring hole, the material of the gate material layer 5 and the material of the substrate 1 should be different. Supplementary note is that in addition to observing the remaining situation of the gate material in the first hole portion 21 and the second hole portion 22 by using an optical device, it is also possible to measure the depths of the first hole portion 21 and the second hole portion 22 by using a measuring device to judge whether there is gate material remaining in the holes.

[0081] It can be understood that if one aims to prepare the depth of the bottom edge of the groove to be close to the optimal expected depth value, thereby reducing the depth difference between the first hole portion 21 and the second hole portion 22, the range of values that can be monitored will become smaller. Inevitably, the possibility of preparing a groove that meets the preparation requirements will be reduced (because if it is not within the above-mentioned monitorable value range, it will be considered not meeting the preparation requirements, but in fact it may meet the preparation requirements), which will have an adverse impact on the preparation of semiconductor devices. Therefore, preferably, the depth of the first hole portion 21 is equal to the minimum value of the acceptable value range, and the depth of the second hole portion 22 is equal to the maximum value of the acceptable value range. In this way, on the premise of meeting the preparation requirements, the depth difference between the first hole portion 21 and the second hole portion 22 can be maximized, and the range of values that can be monitored can be maximized, which is beneficial to the efficient preparation of semiconductor devices.

[0082] In this embodiment, the depth of the third hole portion 23 is greater than the depth of the first hole portion 21 and less than the depth of the second hole portion 22. Further, the depth of the third hole portion 23 can be equal to the expected depth value of the bottom edge of the groove, or the depth of the third hole portion 23 is the average value of the sum of the depths of the first hole portion 21 and the second hole portion 22. By providing the third hole portion 23, there can be one more object for observation, improving the reliability of observation. At the same time, the range in which the depth of the bottom edge of the groove is located can be determined more precisely. Of course, it should be understood that providing the third hole portion 23 is a more optimal solution, but it is not necessary. In addition, in order to have more objects for observation and further improve the reliability of observation, more hole portions with depths between the first hole portion 21 and the second hole portion 22 can also be provided.

[0083] In this embodiment, the expected depth of the bottom edge of the groove is approximately 0.2 μm, the depth of the first hole portion 21 is 0.1 μm, the depth of the second hole portion 22 is 0.3 μm, and the depth of the third hole portion 23 is 0.2 μm. Of course, the present application is not limited thereto, and the depths of each hole portion can also be within a reasonable range. For example, the depth range of the first hole portion 21 is from 0.08 μm to 0.12 μm, the depth range of the second hole portion 22 is from 0.28 μm to 0.32 μm, and the depth range of the third hole portion 23 is from 0.18 μm to 0.22 μm.

[0084] It should be supplemented that the deposition of the gate material at the process hole and the monitoring hole does not have to be carried out synchronously, and can also be carried out separately, as long as the same conditions are used for deposition for the same time. In addition, due to the differences in the structures of the process hole and the monitoring hole itself, after the gate material is deposited, the top surfaces of the gate material layers 5 at the process hole and the monitoring hole are often not absolutely in the same plane. However, some deviations that exist do not affect determining whether the depth of the bottom edge of the groove formed in the process hole meets the preparation requirements by observing the remaining situation of the gate material in the monitoring hole, and the existing deviations are within an acceptable range.

[0085] In the second embodiment, as Figure 6 shown, the monitoring hole 6 may include three separately arranged first hole portions 61, second hole portions 62, and third hole portions 63.

[0086] The monitoring hole in this embodiment is formed through the Figures 7a to 7d preparation process shown.

[0087] Specifically, as Figure 7a shown, a hard mask layer 3 is first formed on the substrate 1; wherein, the material of the substrate 1 may be single-crystalline silicon, and the material of the hard mask layer 3 may be silicon nitride, silicon oxide, silicon oxynitride, or other materials;

[0088] Then, as Figure 7b shown, a patterned photoresist layer 4 is formed on the hard mask layer 3 through a photolithography process, wherein three separate holes are formed in the photoresist layer 4 by using a halftone mask plate (the light transmittance of different regions is different);

[0089] Next, as Figure 7c shown, the hard mask layer 3 is etched based on the patterned photoresist layer 4 to pattern the hard mask layer 3 and form three separate holes in the hard mask layer 3;

[0090] Finally, as Figure 7d shown, the substrate 1 is etched based on the patterned hard mask layer 3 to form three separate first hole portions 61, second hole portions 62, and third hole portions 63 in the substrate 1.

[0091] After processing, the monitoring hole 6 and the process hole 7 are as Figure 7e shown, the process hole 7 is formed in the device processing area 100, and the monitoring hole 6 is formed in the non-device processing area 200.

[0092] During the preparation process of the semiconductor device, the gate material deposition is synchronously performed on the process hole 7 and the monitoring hole 6 formed in the device processing area of the substrate 1 to form a gate material layer 5 on the substrate 1, Figure 7f shows the situation after the gate material is deposited at the monitoring hole 6 and the process hole 7 to form the gate material layer 5. After the deposition is completed, etching is synchronously performed, Figure 7g shows the situation after the gate material layer 5 deposited at the monitoring hole 6 and the process hole 7 is etched (the top surface of the remaining gate material layer 5 is actually roughly formed into an arc shape with higher sides and lower middle). At this time, the depth of the bottom edge of the groove formed in the process hole can be judged by observing the remaining situation of the gate material in the monitoring hole 6. Specifically as follows.

[0093] As described in the first embodiment, the depth of the bottom edge of the groove only needs to be within an acceptable value range to meet the preparation requirements. Therefore, in this embodiment, similar to the first embodiment, the depth of the first hole 61 is set to be not less than the minimum value of the acceptable value range, the depth of the second hole 62 is set to be not greater than the maximum value of the acceptable value range, and the depth of the second hole 62 is greater than the depth of the first hole 61. In this way, as long as an optical device is used to observe the residual situation of the gate material in the first hole 61 and the second hole 62, it can be known whether the depth of the bottom edge of the groove is acceptable. It should be understood that the depth of the first hole 61 refers to the distance between the bottom surface of the hole and the top surface of the substrate 1, the depth of the second hole 62 refers to the distance between the bottom surface of the hole and the top surface of the substrate 1, and the depth of the following third hole 63 refers to the distance between the bottom surface of the hole and the top surface of the substrate 1.

[0094] Specifically, as Figure 7g shown, through observation with an optical device, it can be found that there is residual gate material in the second hole 62 and no residual gate material in the first hole 61. Then, it can be judged that the depth of the bottom edge of the groove is between the depths of the first hole 61 and the second hole 62, belonging to the acceptable range and meeting the preparation requirements. It can be understood that if there is residual gate material in the first hole 61, it is judged that the bottom edge of the groove is too shallow; if there is no residual gate material in the second hole 62, it is judged that the bottom edge of the groove is too deep. It should be understood that in order to be able to observe the residual situation of the gate material, the materials of the gate material layer 5 and the substrate 1 should be different. Additionally, in addition to observing the residual situation of the gate material in the first hole 61 and the second hole 62 through an optical device, it is also possible to measure the depths of the first hole 61 and the second hole 62 with a measuring device to determine whether there is residual gate material in the holes.

[0095] Similarly, similar to the first embodiment, in order to improve the preparation efficiency of semiconductor devices, on the premise of meeting the preparation requirements, the difference between the depth of the first hole 61 and the depth of the second hole 62 can be maximized. That is, the depth of the first hole 61 can be equal to the minimum value of the acceptable value range, and the depth of the second hole 62 can be equal to the maximum value of the acceptable value range.

[0096] In this embodiment, similarly, the depth of the third hole portion 63 is greater than the depth of the first hole portion 61 and less than the depth of the second hole portion 62. Further, the depth of the third hole portion 63 may be equal to the desired depth value of the bottom edge of the groove, or the depth of the third hole portion 63 may be equal to the average value of the depths of both the first hole portion 61 and the second hole portion 62. By providing the third hole portion 63, there can be one more object for observation, improving the reliability of observation. At the same time, the range in which the depth of the bottom edge of the groove is located can also be determined more precisely. Of course, it should be understood that providing the third hole portion 63 is a more optimal solution, but it is not necessarily required. In addition, in order to have more objects for observation and further improve the reliability of observation, more hole portions with depths between the first hole portion 21 and the second hole portion 22 may also be provided.

[0097] In this embodiment, the desired depth of the bottom edge of the groove is approximately 0.2 μm, the depth of the first hole portion 61 is set to 0.1 μm, the depth of the second hole portion 62 is set to 0.3 μm, and the depth of the third hole portion 63 is 0.2 μm. Of course, the present application is not limited thereto, and the depths of the respective hole portions may also be within a reasonable range. For example, the depth range of the first hole portion 21 is from 0.08 μm to 0.12 μm, the depth range of the second hole portion 22 is from 0.28 μm to 0.32 μm, and the depth range of the third hole portion 23 is from 0.18 μm to 0.22 μm.

[0098] It should be supplementary noted that, in order to ensure the reliability and accuracy of determining whether the depth of the bottom edge of the groove meets the preparation requirements by observing the residue of the gate material in the monitoring hole, the bottom surface of the first hole portion in any of the above embodiments should be set as a plane perpendicular to the thickness direction of the substrate. Preferably, the bottom surfaces of the second hole portion and the third hole portion are also set as planes perpendicular to the thickness direction of the substrate.

[0099] It should be particularly noted that the above has introduced two embodiments of the monitoring hole, but the present application is not limited thereto, and the present application does not exclude the case where the monitoring hole is configured to simultaneously include a stepped hole and separately provided holes.

[0100] In the present application, in the process step of forming the monitoring hole and the process hole, a mask layer is first formed on the substrate 1, and then the mask layer is patterned based on a halftone mask plate. The substrate 1 is etched based on the patterned mask layer to simultaneously form the monitoring hole and the process hole. In this way, using the halftone mask plate to simultaneously form the monitoring hole and the process hole in one process step is conducive to reducing the process steps and improving the preparation efficiency. Among them, it can be understood that the mask layer may include a photoresist layer and a hard mask layer, and the patterning of the mask layer described above may include patterning the photoresist layer and the hard mask layer in sequence.

[0101] In the present application, the gate material may be polysilicon or a metal material.

[0102] In the present application, the method for manufacturing a semiconductor device is applicable to manufacturing an IGBT semiconductor device. Of course, the present application is not limited thereto, and the method for manufacturing a semiconductor device of the present application is also applicable to manufacturing other semiconductor devices that require monitoring the depth of the bottom edge of the groove formed by etching the gate material layer during the manufacturing process.

[0103] By adopting the above technical solution, the method for manufacturing a semiconductor device according to the present application has at least the following advantages:

[0104] (1) In the method for manufacturing a semiconductor device of the present application, by forming a monitoring hole in the non-device processing area of the substrate and a process hole in the device processing area of the substrate, the monitoring hole includes at least two first hole portions and second hole portions with different depths, etching the portion of the gate material layer located in the process hole and the portion located in the monitoring hole simultaneously, and determining whether the depth of the bottom edge of the groove meets the manufacturing requirements by monitoring the remaining situation of the gate material in the monitoring hole, realizing the on-line monitoring of the depth of the bottom edge of the groove, and thus being able to detect abnormalities in a timely manner and avoid many subsequent adverse effects.

[0105] (2) In the method for manufacturing a semiconductor device of the present application, making the depth of the first hole portion equal to the minimum value of the acceptable numerical range and the depth of the second hole portion equal to the maximum value of the acceptable numerical range, maximizing the monitorable numerical range on the premise of meeting the manufacturing requirements, which is beneficial to the efficient manufacturing of semiconductor devices.

[0106] (3) In the method for manufacturing a semiconductor device of the present application, by using a halftone mask to pattern the mask layer in the device processing area and the non-device processing area of the substrate simultaneously, etching the substrate based on the patterned mask layer to form the monitoring hole and the process hole simultaneously, forming the monitoring hole and the process hole in one process step, which is beneficial to reducing the process steps and improving the manufacturing efficiency.

[0107] It should be understood that the above embodiments are all exemplary and do not cover all possible embodiments included in the claims. Without departing from the scope of the present application, various deformations and changes can be made on the basis of the above embodiments. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only represent several embodiments of the present application and do not limit the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The preparation method includes: providing a substrate; forming a monitoring hole in a non-device processing area of the substrate, and forming a process hole in a device processing area of the substrate; wherein, the monitoring hole at least includes a first hole portion and a second hole portion with different depths; filling the process hole and the monitoring hole with a gate material to form a gate material layer; wherein, the gate material is different from the material of the substrate; etching the portions of the gate material layer located in the process hole and the monitoring hole synchronously to form a groove in the process hole; determining whether the depth of the bottom edge of the groove meets the preparation requirements according to the remaining situation of the gate material in the monitoring hole.

2. The preparation method according to claim 1, wherein The depth of the first hole portion is not less than the minimum value of the acceptable numerical range, the depth of the second hole portion is not greater than the maximum value of the acceptable numerical range, and the depth of the second hole portion is greater than the depth of the first hole portion; wherein, the acceptable numerical range refers to the numerical range when the depth of the bottom edge of the groove meets the preparation requirements.

3. The preparation method according to claim 2, characterized in that, The monitoring hole further includes a third hole portion, and the depth of the third hole portion is greater than the depth of the first hole portion and less than the depth of the second hole portion.

4. The preparation method according to claim 3, characterized in that, The first hole portion, the second hole portion and the third hole portion are interconnected to form a stepped hole, or the first hole portion, the second hole portion and the third hole portion are arranged separately.

5. The preparation method according to claim 3, characterized in that, The depth of the third hole portion is set to be equal to the expected value of the depth of the bottom edge of the groove.

6. The preparation method according to claim 2, characterized in that, The depth of the first hole portion is equal to the minimum value of the acceptable numerical range, and the depth of the second hole portion is equal to the maximum value of the acceptable numerical range.

7. The preparation method according to claim 6, characterized in that, The depth range of the first hole portion is from 0.08 μm to 0.12 μm, and the depth range of the second hole portion is from 0.28 μm to 0.32 μm.

8. The preparation method according to any one of claims 1 to 7, characterized in that, The forming of the monitoring hole in the non-device processing area of the substrate includes: forming a mask layer on the substrate; patterning the mask layer based on a halftone mask; etching the substrate based on the patterned mask layer to form the monitoring hole.

9. The preparation method according to any one of claims 1 to 7, characterized in that, The forming of the monitoring hole in the non-device processing area of the substrate and the forming of the process hole in the device processing area of the substrate include: forming a mask layer on the substrate; patterning the mask layer based on a halftone mask; etching the substrate based on the patterned mask layer to form the monitoring hole and the process hole simultaneously.

10. The preparation method according to claim 1, characterized in that, The semiconductor device is an insulated gate bipolar transistor.

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