Signal processing device, signal processing method, and program

Abstract

The present technology relates to a signal processing apparatus, a signal processing method, and a program capable of improving noise resistance in high line density recording. Partial response (PR) equalization is performed on a reproduction signal of a multi-valued code with an ML value of 3 or more, and maximum likelihood decoding is performed on the equalized signal obtained by the PR equalization. The present technology can be applied to, for example, recording and reproducing apparatuses such as optical discs.

Description

Technical Field

[0001] The present technology relates to a signal processing apparatus, a signal processing method, and a program, and more particularly, to a signal processing apparatus, a signal processing method, and a program capable of improving noise resistance, for example, in high line density recording. Background Art

[0002] For example, Patent Document 1 discloses a technique for combining noise prediction maximum likelihood (NPML) and a crosstalk canceller, which effectively exhibits the decoding performance of Viterbi decoding as maximum likelihood decoding by whitening the noise of a reproduction signal from an optical disc while canceling crosstalk from adjacent tracks on a binary recording optical disc.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: JP 6504245 B2 Summary of the Invention

[0006] Technical Problem

[0007] In recent years, in high line density recording, improvement in noise resistance has been demanded.

[0008] The present technology has been made in view of this situation, and the present technology can improve noise resistance in high line density recording.

[0009] Solution to the Problem

[0010] A signal processing apparatus or program according to the present technology is a signal processing apparatus including: an equalization unit configured to perform partial response (PR) equalization on a reproduction signal of a multi-valued code having an ML value ≥ 3; and a decoding unit configured to perform maximum likelihood decoding on the equalized signal obtained by the PR equalization; or a program that causes a computer to function as the signal processing apparatus.

[0011] A signal processing method according to the present technology is a signal processing method including the steps of: performing partial response (PR) equalization on a reproduction signal of a multi-valued code having an ML value ≥ 3; and performing maximum likelihood decoding on the equalized signal obtained by the PR equalization.

[0012] In the signal processing apparatus, signal processing method, and program according to the present technology, partial response (PR) equalization is performed on a reproduction signal of a multi-valued code having an ML ≥ 3, and maximum likelihood decoding is performed on the equalized signal obtained by the PR equalization.

[0013] The signal processing apparatus may be an independent apparatus or may be an internal block included in one apparatus.

[0014] A program can be provided by transmitting the program via a transmission medium or by recording the program on a recording medium. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram showing an exemplary configuration of an embodiment of an optical disc recording / reproducing apparatus to which the present technology is applied.

[0016] Figure 2 is a cross-sectional view showing an exemplary configuration of the optical pickup 101.

[0017] Figure 3 is a plan view showing an exemplary configuration of the light receiving surface of the photodetector 6.

[0018] Figure 4 is a view showing an example of laser irradiation of the optical disc 100.

[0019] Figure 5 is a view showing the decoding performance of binary codes and multi-value codes when recording binary codes and multi-value codes on the optical disc 100 at a high line density.

[0020] Figure 6 is a view showing a method of representing a multi-value code.

[0021] Figure 7 is a view showing a code generation model for generating a multi-value edge code (a multi-value code represented by the multi-value edge code).

[0022] Figure 8 is a view showing the code generation model when the maximum consecutive number k is limited to 1.

[0023] Figure 9 is a view showing a transition matrix indicating the state transition of the code generation model for generating a multi-value edge code with ML = 5 and a maximum consecutive number k = 1.

[0024] Figure 10 is a view showing the relationship between the coding ratio and coding efficiency in a multi-value code with ML = 5 and the maximum consecutive number k.

[0025] Figure 11 is a view showing the specifications of a block code composed of multi-value codes with ML = 5 in the case where the maximum consecutive number k = 4;

[0026] Figure 12 is a view showing a 9-bit / 4-cell code with k = 4 and ML = 5.

[0027] Figure 13 is a view showing some of 500 s0→s0 codes and 500 s1→s0 codes and the state transition when generating the s0→s0 codes and s1→s0 codes.

[0028] Figure 14 It is a diagram showing some of 100 s0→s1 codes and 100 s1→s1 codes, and the state transitions when generating the s0→s1 codes and s1→s1 codes.

[0029] Figure 15 It is a diagram showing the minimum transition pattern that appears in the sequence of multi - bit codes with ML = 5.

[0030] Figure 16 It is a diagram showing the minimum transition pattern that appears in the sequence of multi - bit codes with ML = 5.

[0031] Figure 17 It is a diagram showing the start consecutive length and end consecutive length of 500 s0→s0 codes and 100 s0→s1 codes among 600 candidate codes of a 9 - bit / 4 - cell code with k = 4 and ML = 5.

[0032] Figure 18 It is a diagram showing an example of a code look - up table (LUT), in which 512 block codes (which are 9 - bit / 4 - cell codes with k = 4 and ML = 5) are associated with binary data (which is user data obtained by encoding the block codes).

[0033] Figure 19 It is a diagram showing an example of a code look - up table (LUT), in which 512 block codes (9 - bit / 4 - cell codes with k = 4 and ML = 5) are associated with binary data (which is user data obtained by encoding the block codes).

[0034] Figure 20 It is a diagram showing an example of a code look - up table (LUT), in which 512 block codes (9 - bit / 4 - cell codes with k = 4 and ML = 5) are associated with binary data (which is user data obtained by encoding the block codes).

[0035] Figure 21 It is a diagram showing an example of a code look - up table (LUT), in which 512 block codes (9 - bit / 4 - cell codes with k = 4 and ML = 5) are associated with binary data (which is user data obtained by encoding the block codes).

[0036] Figure 22 It is a diagram showing an example of a code look - up table (LUT), in which 512 block codes (9 - bit / 4 - cell codes with k = 4 and ML = 5) are associated with binary data (which is user data obtained by encoding the block codes).

[0037] Figure 23It is a diagram showing an example of a code lookup table (LUT), in which 512 block codes (9-bit / 4-cell codes with k = 4 and ML = 5) are associated with binary data (user data obtained by encoding the block codes).

[0038] Figure 24 It is a diagram showing recording / playing a multi-level code on an optical disc 100.

[0039] Figure 25 It is a block diagram showing an exemplary configuration of a data detection processing unit 105.

[0040] Figure 26 It is a diagram showing an exemplary configuration of a PR memory model.

[0041] Figure 27 It is a diagram showing an exemplary configuration of a multi-input adaptive equalization unit 14.

[0042] Figure 28 It is a diagram showing an exemplary configuration of an FIR filter as an adaptive equalizer 20 + c.

[0043] Figure 29 It is a diagram showing an exemplary configuration of a noise predictor 15.

[0044] Figure 30 It is a diagram showing an example of a trellis of reduced Viterbi decoding incorporating DFE and NPML.

[0045] Figure 31 It is a diagram showing an exemplary configuration of a Viterbi decoder 320 included in a detection unit 16.

[0046] Figure 32 It is a diagram showing an operation example of the Viterbi decoder 320.

[0047] Figure 33 It is a diagram further showing an operation example of the Viterbi decoder 320.

[0048] Figure 34 It is a diagram showing a path memory PM of an ACS unit 330 - pq pq of an exemplary configuration.

[0049] Figure 35 It is a diagram showing storing an equalization reference level r t (s i ,s j ) + Δr t (b t ) of an exemplary configuration of an equalization reference storage unit.

[0050] Figure 36It is a diagram showing an exemplary configuration of the whitening coefficient update unit 19.

[0051] Figure 37 It is a diagram showing an exemplary configuration of the whitening reference storage unit that stores the whitening reference level MR4.

[0052] Figure 38 It is a diagram showing the decoding performance of the recording / reproducing apparatus.

[0053] Figure 39 It is a diagram showing the tap coefficient f cl and the equalization error e' t obtained by simulation.

[0054] Figure 40 It is a diagram showing the cell error rate obtained by simulation.

[0055] Figure 41 It is a block diagram showing an exemplary configuration of another embodiment of the optical disc recording / reproducing apparatus to which the present technology is applied.

[0056] Figure 42 It is a diagram showing an example in which the optical disc 100 is irradiated with laser light by three signal reproduction units 411 to 413.

[0057] Figure 43 It is a block diagram showing an exemplary configuration of an embodiment of a computer to which the present technology is applied. Detailed Embodiments

[0058] <Embodiment of the Optical Disc Recording / Reproducing Apparatus to which the Present Technology is Applied>

[0059] Figure 1 It is a block diagram showing an exemplary configuration of an embodiment of an optical disc recording / reproducing apparatus (hereinafter referred to as a "recording / reproducing apparatus") to which the present technology is applied.

[0060] As Figure 1 shown, the recording / reproducing apparatus includes: an optical pickup 101 for recording and reproducing information on an optical disc 100 as an optical recording medium; and a spindle motor 102 for rotating the optical disc 100. In order to move the optical pickup 101 in the radial direction of the optical disc 100, a screw mechanism (screw feed motor) 103 is provided.

[0061] As the optical disc 100, a high-density optical disc such as a Blu-ray Disc (BD((registered trademark))) can be adopted. BD is a high-density optical disc with a recording capacity of approximately 25 gigabytes (GB) for a single-sided single layer and approximately 50 GB for a single-sided double layer. In the BD standard, in order to make the beam spot diameter small, the light source wavelength is set to 405 nm, and the numerical aperture NA of the objective lens is set to a large value of 0.85. In the CD standard, the light source wavelength is 780 nm, NA is 0.45, and the spot diameter is 2.11 μm. In the DVD standard, the light source wavelength is 650 nm, NA is 0.6, and the spot diameter is 1.32 μm. In the BD standard, the spot diameter can be reduced to 0.58 μm.

[0062] In addition, regarding BD, by shortening the channel bit length (i.e., the mark length) and achieving high density in the track density direction, the BDXL (registered trademark) with a large capacity of 100 GB for three layers and 128 GB for four layers has been put into practical use.

[0063] To increase the new recording capacity, data is recorded in both the groove track and the land track. For example, an optical disc called an Archive Disc (AD) can be adopted as the optical disc 100. The engraved part is called a groove, and the track formed by the groove is called a groove track. When manufacturing an optical disc, the groove is defined as the part irradiated with a laser, the area between adjacent grooves is called a land, and the track formed by the land is called a land track. In addition, when a multi-layer optical disc has multiple laminated information recording layers, the recording capacity can be further increased.

[0064] When the optical disc 100 capable of performing high-density recording is mounted on a recording / reproducing device, the optical disc 100 is rotated and driven by a spindle motor 102 at a constant linear velocity (CLV) or a constant angular velocity (CAV) during recording / reproduction. During reproduction, the marks formed in the tracks on the optical disc 100 are read by an optical pickup (optical head) 101. During data recording on the optical disc 100, user data is recorded as phase change marks or pigment change marks in the tracks on the optical disc 100 by the optical pickup 101.

[0065] When the optical disc 100 is a recordable disc, for example, recording marks are recorded on the tracks formed by wobbling grooves by phase change marks. In the case of a BD with 23.3 GB per layer, for example, the phase change marks are recorded at a linear density of 0.12 μm / bit and 0.08 μm / channel bit according to the RLL(1,7)PP modulation scheme (RLL: run length limited, and PP: parity-preserving / forbidden minimum transition run length (rmtr)). When the optical disc 100 is a BD with 25 GB / layer, a BDXL with 32 GB / layer, and a BDXL with 33.4 GB / layer, recording is performed at a density corresponding to the channel bit length according to the type of the disc. For example, the densities are 0.0745 μm / channel bit, 0.05826 μm / channel bit, and 0.05587 μm / channel bit, respectively. When the channel clock period is “T”, the mark length is from 2T to 8T. For example, when the optical disc 100 is a disc only for recording, no grooves are formed, but data modulated according to the RLL(1,7)PP modulation scheme is recorded as an emboss pit array.

[0066] In the inner circumferential region of the optical disc 100, for example, physical information of the optical disc 100 and the like are recorded as management information only for reproduction by emboss pits or wobbling grooves. The management information and the like are read by the optical pickup 101. In addition, the optical pickup 101 also reads the ADIP information embedded in the wobbling of the groove track on the optical disc 100.

[0067] In the optical pickup 101, a laser diode serving as a laser light source, a photodetector for detecting the reflected light, an objective lens serving as an output end of the laser, and an optical system for irradiating the disc recording surface of the optical disc 100 with the laser via the objective lens and guiding the reflected light of the laser to the photodetector are configured. The objective lens in the optical pickup 101 is movably held in the tracking direction and the focusing direction by a biaxial mechanism. The entire optical pickup 101 is regarded as being movable in the radial direction of the disc by a screw mechanism 103. When a drive current is supplied from the laser driver 113 to the laser diode of the optical pickup 101, the laser diode generates laser light.

[0068] When the light reflected from the optical disc 100 is detected (received) by the photodetector, an electrical signal corresponding to the amount of light received by the reflected light in the photodetector is supplied to the matrix circuit 104. The matrix circuit 104 includes a current-voltage conversion circuit and a matrix calculation / amplification circuit, and generates necessary signals by performing matrix calculation processing using the output current, which serves as an electrical signal from a plurality of light receiving elements serving as the photodetector. Considering the signal transmission quality, the current-voltage conversion circuit may be formed in the photodetector instead of the matrix circuit 104. The matrix circuit 104 generates a reproduction signal (RF signal) corresponding to the information recorded on the optical disc 100, a focus error signal and a tracking error signal for servo control. In addition, the matrix circuit 104 generates a push-pull signal as a signal related to the wobbling of the groove, that is, a signal for detecting the wobbling.

[0069] The reproduction signal generated by the matrix circuit 104 is supplied to the data detection processing unit 105, the focus error signal and the tracking error signal are supplied to the optical block servo circuit 111, and the push-pull signal is supplied to the wobbling signal processing circuit 106.

[0070] The data detection processing unit 105 performs multi-level processing on the reproduction signal. For example, the data detection processing unit 105 performs A / D conversion on the RF signal, reproduction clock generation by a phase-locked loop (PLL), partial response (PR) equalization, Viterbi decoding used as maximum likelihood decoding, etc., to reproduce (decode) the multi-level code recorded on the optical disc 100 according to the partial response maximum likelihood decoding (PRML detection scheme). The data detection processing unit 105 supplies the multi-level code as the information reproduced from the optical disc 100 to the encoding / decoding unit 107 at the subsequent stage. The multi-level code is a code with an ML (≥3) value greater than or equal to a ternary value. Details of the multi-level code will be described below. The multi-level code is disclosed in the earlier application JP2018-202533A filed by the present applicant.

[0071] The encoding / decoding unit 107 performs modulation on the information during decoding and performs recording on the multi-level code during reproduction. That is, the encoding / decoding unit 107 performs decoding (channel decoding), deinterleaving, ECC decoding, address decoding, etc. during reproduction, and performs ECC encoding, interleaving, encoding (channel encoding) during recording.

[0072] During reproduction, the multi-level code decoded by the data detection processing unit 105 is supplied to the encoding / decoding unit 107. The encoding / decoding unit 107 performs decoding for the multi-level code, ECC decoding for performing error correction, etc., to reproduce the information as the user data recorded on the optical disc 100.

[0073] The information generated by the encoding / decoding unit 107 is sent to the host I / F 108 and sent to the host device 200 based on instructions from the system controller 110. The host device 200 is, for example, a computer device or an audio-visual (AV) system device.

[0074] During recording / playback on the optical disc 100, processing for ADIP information is performed. That is, the push-pull signal, which is a signal related to the wobbling of the groove generated by the matrix circuit 104, is regarded as wobbling data digitized in the wobbling signal processing circuit 106. The PLL generates a clock synchronized with the push-pull signal. The wobbling data is demodulated by the ADIP demodulation processing unit 116 into a data stream including the ADIP address, and the data stream is provided to the address decoder 109. The address decoder 109 decodes the data stream including the ADIP address to obtain the ADIP address and provides the ADIP address to the system controller 110.

[0075] During recording, information as user data is provided from the host device 200 to the encoding / decoding unit 107 via the host I / F 108. The encoding / decoding unit 107 performs addition of an error correction code (ECC encoding), interleaving, addition of a subcode, encoding into a multilevel code, etc. on the information as user data. Here, a multilevel code can be recorded on the optical disc 100 and a binary code can also be recorded. As a scheme for encoding (modulating) into a binary code, for example, there is run length limited code modulation such as the RLL(1,7)PP modulation scheme.

[0076] The multilevel code obtained by the encoding / decoding unit 107 is provided to the write strategy unit 114. The write strategy unit 114 performs waveform adjustment of the laser drive pulse on the characteristics of the recording layer, the spot shape of the laser, the recording linear velocity, etc. as recording compensation processing. Then, the write strategy unit 114 outputs the laser drive pulse corresponding to the multilevel code to the laser driver 113.

[0077] The laser driver 113 causes a current to flow through the laser diode in the optical pickup 101 based on the laser drive pulse that has undergone the recording compensation processing and performs laser irradiation. Thereby, marks corresponding to the multilevel code (information of user data encoded in the multilevel code) are formed on the optical disc 100.

[0078] The optical block servo circuit 111 generates various servo drive signals for focusing, tracking, and threading based on the focus error signal and the tracking error signal generated by the matrix circuit 104, and performs servo operations. That is, the optical block servo circuit 111 generates a focus drive signal and a tracking drive signal based on the focus error signal and the tracking error signal, and the driver 118 drives the focus coil and the tracking coil of the biaxial mechanism in the optical pickup 101. Thereby, a tracking servo loop and a focus servo loop are formed by the optical pickup 101, the matrix circuit 104, the optical block servo circuit 111, the driver 118, and the biaxial mechanism.

[0079] In addition, the optical block servo circuit 111 performs a track jump operation by turning off the tracking servo loop according to a track jump instruction from the system controller 110 and outputting a pump drive signal. In addition, the optical block servo circuit 111 generates a thread drive signal based on a thread error signal obtained as a low-pass component of the tracking error signal, access execution control from the system controller 110, and the like. The thread driver 115 drives the thread mechanism 103 according to the thread drive signal generated by the optical block servo circuit 111.

[0080] The spindle servo circuit 112 controls the CLV rotation of the spindle motor 102. The spindle servo circuit 112 obtains the clock generated from the wobble signal of the PLL as the current rotation speed information of the spindle motor 102, and generates a spindle error signal by comparing the rotation speed information with predetermined CLV reference speed information. Since the reproduction clock obtained by the PLL in the data detection processing unit 105 is used as the current rotation speed information of the spindle motor 102 during data reproduction, the spindle servo circuit 112 generates a spindle error signal by comparing the rotation speed information with predetermined CLV reference speed information. The spindle servo circuit 112 generates a spindle drive signal according to the spindle error signal, supplies the spindle drive signal to the spindle driver 117, and performs the CLV rotation of the spindle motor 102 according to the spindle drive signal.

[0081] The spindle servo circuit 112 generates a spindle drive signal according to the spindle kick / brake control signal from the system controller 110, and performs start, stop, acceleration, or deceleration operations of the spindle motor 102 according to the spindle drive signal.

[0082] As described above, various operations of the servo system and the recording / reproducing system are controlled by a system controller 110 formed of a microcomputer. The system controller 110 performs various types of processing according to commands given from a host device 200 via a host I / F 108. For example, when a write command is output from the host device 200, the system controller 110 moves the optical pickup 101 to an address to be written first. The system controller 110 causes the encoding / decoding unit 107 to modulate information (e.g., video data or audio data) that is user data transmitted from the host device 200. Then, when the laser driver 113 drives laser emission according to the multi-value code obtained by modulation, the information as user data is recorded as a multi-value code.

[0083] In addition, for example, when a read command for requesting transmission of information recorded on the optical disc 100 is provided from the host device 200, the system controller 110 performs seek operation control for the purpose of the address where the information is recorded. That is, the system controller 110 outputs a seek command for specifying an address to the optical block servo circuit 111, and performs an access operation of the optical pickup 101 to lock the address specified by the seek command. Thereafter, the system controller 110 performs operation control necessary for transmitting the information (multi-value code) requested according to the read command to the host device 200. That is, the system controller 110 reads information from the optical disc 100, causes the data detection processing unit 105 and the encoding / decoding unit 107 to perform necessary processing, and transmits the information requested according to the read command to the host device 200.

[0084] Figure 1 The recording / reproducing device in [description] is a recording / reproducing device connected to the host device 200. However, a type of recording and reproducing device not connected to other devices may be adopted. When a type of recording / reproducing device not connected to other devices is adopted, the configuration of a manipulation unit or a display unit or the configuration of an input / output interface unit for the outside is different from Figure 1 the configuration of [description]. For example, in the recording / reproducing device, a terminal unit is formed that performs recording or reproduction according to user manipulation and inputs and outputs various information. Of course, any other various configurations may be regarded as an exemplary configuration of the recording / reproducing device.

[0085] Figure 2 is a cross-sectional view showing an exemplary configuration of the optical pickup 101.

[0086] For example, the optical pickup 101 records information on the optical disc 100 and reproduces information from the optical disc 100 using a laser (light beam) with a wavelength λ of 405 nm. The laser is emitted from a semiconductor laser (laser diode (LD)) 1.

[0087] The laser passes through the collimator lens 2, the polarization beam splitter (PBS) 3, and the objective lens 4 and irradiates the optical disc 100. The polarization beam splitter 3 has a separation surface that, for example, allows approximately 100% of the P-polarized light to pass through and reflects approximately 100% of the S-polarized light. In the optical disc 100, the laser is reflected in the recording layer. The light reflected from the recording layer of the optical disc 100 returns to the same optical path and is incident on the polarization beam splitter 3. Approximately 100% of the reflected light incident on the polarization beam splitter 3 is reflected by inserting a λ / 4 element (not shown).

[0088] The reflected light reflected from the polarization beam splitter 3 is converged on the light receiving surface of the photodetector 6 via the lens 5. The photodetector 6 receives the reflected light on the light receiving surface, performs photoelectric conversion, and outputs an output current corresponding to the amount of light received by the reflected light.

[0089] Figure 3 is a plan view showing an exemplary configuration of the light receiving surface of the photodetector 6.

[0090] For example, as Figure 3 shown, along two dividing lines that divide the surface into three regions in the tangential direction (track direction) of the optical disc 100 and two dividing lines that divide the surface into three regions in the radial direction, the light receiving surface is divided into five regions 6a, 6b, 6c, 6d1, and 6d2.

[0091] In the photodetector 6, the reflected light is received in the regions 6a, 6b, 6c, 6d1, and 6d2 of the light receiving surface and output currents corresponding to five systems are output.

[0092] Figure 3 The division of the light receiving surface in Figure 3 is only exemplary. As a method of dividing the light receiving surface, various division examples can be assumed in addition to the division of

[0093] Figure 4 is a diagram showing an example of laser irradiation of the optical disc 100.

[0094] When the track TK of the optical disc 100 is the reproduction target track, the laser is irradiated onto a plurality of adjacent tracks including the track TK. For example, as Figure 4 shown, the laser is irradiated so that the light spot SP is formed in the track TK, the adjacent track TK-1 adjacent to the track TK on the inner peripheral side, and the adjacent track TK+1 adjacent to the track TK on the outer peripheral side of the track TK. Therefore, the reflected light of the laser includes the reflected light of the laser from each of the tracks TK, TK-1, and TK+1. The reflected light is received in the regions 6a, 6b, 6c, 6d1, and 6d2 of the photodetector 6.

[0095] Figure 2The components of an optical pickup 101 for obtaining a reproduction signal corresponding to information recorded on an optical disc 100 are shown. In Figure 2 , signals for generating a focus error signal output to an optical block servo circuit 111 via a matrix circuit 104 and a tracking error signal or a push-pull signal output to a wobble signal processing circuit 106 via the matrix circuit 104 are omitted. Any of various configurations other than the configuration shown in Figure 2 can be adopted as the configuration of the optical pickup 101.

[0096] In an embodiment, as Figure 3 described, the light receiving surface of a photodetector 6 is divided into regions 6a to 6d2, a cross-section of reflected light from the optical disc 100 is divided into a plurality of regions corresponding to the regions 6a to 6d2, and output currents serving as electrical signals corresponding to the light reception amount of each region are obtained. Here, as a method for obtaining electrical signals for each region divided from the cross-section of the reflected light, a method other than the method of dividing the light receiving surface of the photodetector 6 can be adopted.

[0097] For example, a method can be adopted in which an optical path conversion element that divides the reflected light into a plurality of light beams is arranged on the optical path that passes through an objective lens 4 and reaches the photodetector 6 to divide the cross-section of the reflected light into a plurality of regions, and a plurality of photodetectors receive the plurality of light beams divided from the reflected light by the optical path conversion element. As the optical path conversion element, a diffractive element such as a holographic optical element or a reflective element such as a microlens array or a microprism can be adopted.

[0098] In an embodiment, laser irradiation is performed such that a light spot SP is formed on a plurality of tracks TK, TK-1, and TK+1, as Figure 4 shown. Therefore, the reflected light of the laser includes the reflected light of the laser from each of the tracks TK, TK-1, and TK+1. Therefore, the reproduction signal generated from the reflected light includes not only the reproduction signals of a plurality of signal channels, that is, the reproduction signal of the track TK (the reproduction signal obtained when the laser is irradiated only on the track TK), but also the reproduction signals of the adjacent tracks TK-1 and TK+1.

[0099] <Decoding performance of binary code and multi-level code>

[0100] Figure 5 is a diagram showing the decoding performance of a binary code and a multi-level code when the binary code and the multi-level code are recorded on the optical disc 100 at a high line density.

[0101] The inventors of the present specification have found that the decoding (detection) performance of information is further improved in the case of performing multi-level recording compared to the case of performing binary recording. This technology is based on this finding.

[0102] Binary recording is to record binary codes on the optical disc 100, and multi-valued recording is to record multi-valued codes on the optical disc 100.

[0103] In Figure 5 the horizontal axis represents the line density recorded on the optical disc 100, and the line density is expressed as a ratio to the line density of AD2 with a capacity of 500 gigabytes (GB). AD2 is an optical disc on which data can be recorded at a high line density and is described in, for example, the "White Paper: Archival Disc Technology 2nd Edition" in July 2018.

[0104] In Figure 5 the vertical axis represents the signal-to-noise ratio (SNR) required to obtain a cell error rate (cER) of 1e-4 (0.0001), which is called the required SNR. A cell (c) at cER means one of the multi-valued codes (one value) and is equivalent to one bit in the binary code. The n cells are the multi-valued codes of n rows. The code length of the multi-valued code is expressed in units of cells.

[0105] As the required SNR is smaller, the desired cER can be obtained even from a coarse noise signal (a signal with a large amount of noise). Therefore, a small required SNR means good decoding performance of the code (information).

[0106] In Figure 5 the required SNR obtained through simulations performed by the inventors of this specification is plotted for the binary code and the quaternary code as a multi-valued code with ML = 4.

[0107] In Figure 5 Binary-ISI = 11 represents the required SNR of the binary code when the inter-symbol interference (ISI) length (K to be described below) is 11T. Binary-ISI = 13 represents the required SNR of the binary code when the ISI length is 13T. Quaternary-ISI = 3 represents the required SNR of the quaternary code when the ISI length is 3T. Quaternary-ISI = 4 represents the required SNR of the quaternary code when the ISI length is 4T.

[0108] In Figure 5 the required SNR of AD2 is represented by a dashed line.

[0109] In Figure 5 for example, Binary-ISI = 11 at a line density of 110% is approximately 32.3 dB, and Quaternary-ISI = 3 is approximately 29.5 dB. Therefore, it can be confirmed that the quaternary code has a stronger noise resistance (SNR) of 32.3 - 29.5 = 2.8 dB than the binary code and has good decoding performance.

[0110] That is, by adopting a multi-valued code, compared with the case of adopting a binary code, the noise resistance can be further improved, and thus the decoding performance can be improved.

[0111] <Method of representing multi-valued code>

[0112] Figure 6 A diagram showing a method of representing a multi-valued code.

[0113] As described above, one (a value) of the multi-valued codes with ML value ≥ 3 is assumed to be a cell. Here, n cells are an n-row multi-valued code. The code length of the multi-valued code is represented by cells.

[0114] A multi-valued code with an ML value can be represented as a multi-valued marginal code with the ML value.

[0115] The multi-valued marginal code is a code representing the value (level) of the multi-valued code by the margin. The margin indicates the amount of change from the previous value of the multi-valued code, and the margins are counted so that 0 to ML - 1 used as a multi-valued code with an ML value are rotated.

[0116] For example, when two consecutive cells of a multi-valued code with ML = 5 are 00, the amount of change from the first cell 0 (starting from the beginning) to the second cell 0 is 0. Therefore, the margin between the two cells is 0.

[0117] For example, when two consecutive cells of a multi-valued code with ML = 5 are 01, the amount of change from the first cell 0 to the second cell 1 is 1. Therefore, the margin between the two cells is 1.

[0118] For example, when two consecutive cells of a multi-valued code with ML = 5 are 13, the amount of change from the first cell 1 to the second cell 3 is 2. Therefore, the margin between the two cells is 2.

[0119] For example, when two consecutive cells of a multi-valued code with ML = 5 are 32, when counting, the amount of change from the first cell 3 to the second cell 2 is 4, thus rotating 0 to 4 = ML - 1. Therefore, the margin between the two cells is 4.

[0120] Therefore, for example, as Figure 6 shown, the multi-valued marginal code representing the multi-valued code 00113322... with ML = 5 is *0102040...*. * represents the value determined according to the previous value of the leading 0 of the multi-valued code 00113322...

[0121] When the multi - level code (the value (level) of the multi - level code) at time t (t - th) is represented as l(t) and the multi - level marginal code at time t is represented as c(t), the multi - level marginal code c(t) satisfies the expression l(t)=(l(t - 1)+c(t))%ML. % represents the modulo operator and A%B represents the remainder when A is divided by B.

[0122] As described above, information as user data is encoded (modulated) into a multi - level marginal code representing a multi - level code. The multi - level code whose value changes according to the multi - level marginal code, that is, the multi - level code l(t) obtained through the expression l(t)=(l(t - 1)+c(t))%ML, is recorded on the optical disc 100. The multi - level code (that is, the multi - level code whose value changes according to the multi - level marginal code) recorded in this way is reproduced from the optical disc 100.

[0123] <Code generation model>

[0124] Figure 7 A diagram showing a code generation model for generating a multi - level marginal code (a multi - level code represented by the multi - level marginal code).

[0125] The code generation model has a state that only indicates the number of consecutive zeros, that is, the number of cases where the marginal 0 is the number of consecutive zeros that are consecutive. Therefore, when the maximum number of consecutive zeros as the maximum number of consecutive zeros is represented by k, the code generation model has a total of k + 1 states: the state s0 indicating that the number of consecutive zeros is 0, the state s1 indicating that the number of consecutive zeros is 1,..., and the state s#k indicating that the number of consecutive zeros is k.

[0126] When 0 is output as the multi - level marginal code, the code generation model transitions to the state s#k', where the state s#k' indicates that the marginal 0 is the number of consecutive zeros k' (≤k) that are consecutive (including 0). When any one of 1 to ML - 1 is output as the multi - level marginal code, the code generation model transitions to the state s0, where the state s0 indicates that the number of consecutive zeros is 0. In the state s#k indicating that the number of consecutive zeros is the maximum number of consecutive zeros k, only one of 1 to ML - 1 other than 0 is output as the multi - level marginal code. After outputting this one multi - level marginal code of 1 to ML - 1, the code generation model transitions to the state s0.

[0127] The multi - level marginal code is generated through the above - mentioned state transition of the code generation model.

[0128] Generally, for a channel code (recording modulation code) recorded on a recording medium, in order to ensure the frequency for obtaining information for detecting a phase error in a PLL or the like that generates a channel clock, that is, in order to ensure the frequency of the conversion (change) of the value of the channel code, a so - called k - limit is performed, and the k - limit is used to limit the maximum value of the number of consecutive times the same value appears.

[0129] Figure 8 It is a diagram showing a code generation model when the maximum consecutive number k is limited to 1.

[0130] In the case where the maximum consecutive number k = 1, the code generation model is configured to indicate a state s0 with a consecutive zero number of 0 and a state s1 with a consecutive zero number of 1.

[0131] In the case of state s0, one of 0 to ML - 1 can be output as a multi - ary marginal code. When 0 is output as the multi - ary marginal code in state s0, the state of the code generation model transitions from state s0 to state s1. When one of 1 to ML - 1 is output as the multi - ary marginal code, the state of the code generation model transitions from state s0 to state s0.

[0132] In the case of state s1, 0 is not output as the multi - ary marginal code, and any one of 1 to ML - 1 can be output except 0. In the case of state s1, any one of 1 to ML - 1 is output as the multi - ary marginal code, and the state of the code generation model transitions from state s1 to state s0.

[0133] Hereinafter, taking the multi - ary marginal code with the value of the multi - ary code being ML = 5 as an example, the generation of the multi - ary marginal code (the multi - ary code represented by the multi - ary marginal code) by the code generation model will be described.

[0134] <Multi - ary marginal code with ML = 5>

[0135] Figure 9 It is a diagram showing a transition matrix indicating the state transition of a code generation model for generating a multi - ary marginal code with ML = 5 and a maximum consecutive number k = 1.

[0136] In Figure 9 In the transition matrix, each row represents the state of the source of the state transition, and each column represents the state of the destination of the state transition. The element in the i - th row and j - th column indicates the number in the case of the number of state transitions from state s#i to state s#j in the code generation model.

[0137] In the code generation model for generating a multi - ary marginal code with ML = 5 and a maximum consecutive number k = 1 (hereinafter also referred to as the code generation model with k = 1 and ML = 5), as the state transition from state s0 to state s0, there are four state transitions of outputting multi - ary marginal codes 1, 2, 3, and 4. As the state transition from state s0 to state s1, there is one state transition of outputting multi - ary marginal code 0. As the state transition from state s1 to state s0, there are four state transitions of outputting multi - ary marginal codes 1 to 4. There is no state transition from state s1 to state s1.

[0138] The theoretical limit of the coding ratio of the multi - ary marginal code (the multi - ary code represented by the multi - ary marginal code) generated by the code generation model (state transition) with k = 1 and ML = 5 can be obtained as the Shannon capacity. The Shannon capacity can be obtained using the eigenvalues of the transition matrix indicating the state transition of the code generation model.

[0139] Figure 9 The transition matrix of is a matrix with two rows and two columns. Therefore, (at most) two eigenvalues are obtained. In some cases, the eigenvalues are complex numbers. However, among the eigenvalues of the transition matrix, the maximum value of the eigenvalues with positive values is the theoretical limit of the coding ratio called the Shannon capacity.

[0140] When j is Figure 9 the imaginary unit in the two eigenvalues EV[0] and EV[1] of the transition matrix of , EV[0] ≈ 4.828427 + j0 and EV[1] ≈ - 0.82843 + j0. Thus, the Shannon capacity of the multi - ary marginal code (the multi - ary code represented by the multi - ary marginal code) generated by the code generation model with k = 1 and ML = 5 is (about) 4.828427, which is the maximum value among the eigenvalues with positive real values among the two eigenvalues EV[0] and EV[1].

[0141] The Shannon capacity indicates the number of symbols (symbol number) that can be represented per cell by the multi - ary code (represented by the multi - ary marginal code) generated by the code generation model, and due to the limitation of the maximum consecutive number k, the Shannon capacity is a value less than ML. A Shannon capacity of 4.828427 means that each cell of the multi - ary code can represent 4.828427 values (symbols).

[0142] When encoding into a multi - ary code (multi - ary encoding), for example, a certain number of bits of binary data is converted into a multi - ary code (a sequence of multi - ary codes), which is a multi - row arrangement of cells with values equal to or greater than 1. Thus, the coding ratio should be expressed in units of bits / cell.

[0143] By calculating the binary logarithm of the Shannon capacity 4.828427, the maximum number of bits of binary data for the theoretical limit of the coding ratio (theoretical limit coding ratio) that can be assigned to the multi - ary code can be obtained, that is, the maximum number of bits of binary data that can be assigned to one cell of the multi - ary code, which is (about) 2.271553 = log 2 4.828427.

[0144] Figure 10 A diagram showing the relationship between the coding ratio and coding efficiency in the multi - ary code with ML = 5 and the maximum consecutive number k.

[0145] Here, the theoretical limit coding ratio with the maximum consecutive number k = ∞ in the multi - ary code with ML = 5 is (about) 2.32 ≒ log 2 5, but in the case of the maximum consecutive number k = ∞, Figure 10 the coding efficiency represents the ratio of the coding ratio to the theoretical limit coding ratio of 2.32.

[0146] From Figure 10 it can be determined that for the multi - ary code with ML = 5, when the maximum consecutive number k is equal to or greater than 2, the coding ratio rapidly approaches the theoretical limit coding ratio, and thus, the coding efficiency becomes more than 99%.

[0147] Here, as a coding scheme for the multi - ary code, for example, assume a scheme of converting m - bit binary data into a block code with a fixed length (n cells) composed of a sequence of multi - ary codes of n cells (a sequence of multi - ary edge codes representing block codes) so that this coding scheme can be installed as a circuit. Hereinafter, a block code composed of a sequence of multi - ary codes of n cells and composed of a multi - ary code with ML = 5 (represented as a multi - ary edge code) will be described.

[0148] <Block code>

[0149] Figure 11 A diagram showing the specifications of a block code composed of a multi - ary code with ML = 5 in the case where the maximum consecutive number k = 4;

[0150] In Figure 11 the code length n represents the code length of the block code with a fixed length, that is, the number of cells in the multi - ary code (sequence of multi - ary codes) configuring the block code. The number of symbols Ns is the number of symbols that can be expressed by the multi - ary code with ML = 5 of n cells, that is, the number of codewords of the block code composed of the multi - ary code with ML = 5 of n cells, and due to the limitation of the maximum consecutive number k = 4, Ns is a value equal to or less than 5 to the power of n. The number of binary data bits B is the number of bits of binary data that can be encoded (assigned) into the multi - ary code with ML = 5 of n cells and whose maximum integer value is equal to or less than log 2 (Ns). The coding ratio R represents the value obtained by dividing the number of binary data bits B by the code length n. The coding efficiency Ef represents the ratio of the coding ratio R to the theoretical limit coding ratio (about 2.32) of the multi - ary code with k = 4 and ML = 5 (generated by the code generation model).

[0151] Hereinafter, the generation of an efficient block code with a coding efficiency of 97% and a code length n of four cells among the block codes composed of the multi - ary code with k = 4 and ML = 5 (represented as a multi - ary edge code of the multi - ary code) shown in Figure 11 will be described.

[0152] In a block code composed of a multi - ary code with k = 4 and ML = 5 and a code length n of 4 cells, 9 - bit binary data B is encoded into a block code composed of a multi - ary code of 4 cells. This block code is also called a 9 - bit / 4 - cell code with k = 4 and ML = 5.

[0153] Figure 12 is a diagram showing a 9 - bit / 4 - cell code with k = 4 and ML = 5.

[0154] A multi - ary marginal code (a sequence of multi - ary marginal codes) constituting a 9 - bit / 4 - cell code with k = 4 and ML = 5 (representing a multi - ary code) can be generated by starting from a certain state in a code generation model with k = 4 and ML = 5 and performing four state transitions. Here, the state reached after performing four state transitions is assumed to be the final state.

[0155] Figure 12 Shows multiple block codes: a block code constituted by a sequence of multi - ary marginal codes generated by performing four state transitions with state s0 used as the initial state and the final state respectively (hereinafter also called s0→s0 code); a block code constituted by a sequence of multi - ary marginal codes generated by performing four state transitions with states s0 and s1 used as the initial state and the final state respectively (hereinafter also called s0→s1 code); a block code constituted by a sequence of multi - ary marginal codes generated by performing four state transitions with states s1 and s0 used as the initial state and the final state respectively (hereinafter also called s1→s0 code); and a block code constituted by a sequence of multi - ary marginal codes generated by performing four state transitions with state s1 used as the initial state and the final state respectively (hereinafter also called s1→s1 code).

[0156] The number of s0→s0 codes is 500, and the number of s0→s1 codes is 100. The number of s1→s0 codes is 500, and the number of s1→s1 codes is 100.

[0157] Figure 13 is a diagram showing some of the 500 s0→s0 codes and 500 s1→s0 codes and the state transitions when generating s0→s0 codes and s1→s0 codes.

[0158] Figure 13 A of shows some of the 500 s0→s0 codes and the state transitions when generating s0→s0 codes, and Figure 13 B of shows some of the 500 s1→s0 codes and the state transitions when generating s1→s0 codes.

[0159] The inventors of this specification confirmed that although the methods of state transitions between the 500 s0→s0 codes and the 500 s1→s0 codes are not the same, the same codes can be obtained.

[0160] That is, 500 s0→s0 codes of the first block code composed of the multi-edge code sequences generated when performing four state transitions by using state s0 and state 0 (the first state and the second state) as the initial state and the final state respectively are common with 500 s1→s0 codes of the second block code composed of the multi-edge code sequences generated when performing four state transitions by using state s1 and s0 (the third state and the fourth state) as the initial state and the final state respectively.

[0161] Figure 14 is a diagram showing some of 100 s0→s1 codes and 100 s1→s1 codes and the state transitions when generating the s0→s1 codes and the s1→s1 codes.

[0162] Figure 14 A of shows some of 100 s0→s1 codes and the state transitions when generating the s0→s1 codes, and Figure 14 B of shows some of 100 s1→s1 codes and the state transitions when generating the s1→s1 codes.

[0163] The inventors of the present specification confirmed that the same codes can be obtained even if the methods of state transition between 100 s0→s1 codes and 100 s1→s1 codes are inconsistent.

[0164] That is, 100 s0→s1 codes of the first block code composed of the multi-edge code sequences generated when performing four state transitions by using state s0 and s1 (the first state and the second state) as the initial state and the final state respectively are common with 100 s1→s1 codes of the second block code composed of the multi-edge code sequences generated when performing four state transitions by using state s1 and s1 (the third state and the fourth state) as the initial state and the final state respectively.

[0165] As described above, a total of 600 block codes, including 500 s0→s0 codes and 100 s0→s1 codes generated when using state s0 as the initial state to perform four state transitions, match (are common with) a total of 600 block codes, including 500 s1→s0 codes and 100 s1→s1 codes generated when using state s1 as the initial state to perform four state transitions.

[0166] Therefore, when using the block code generated by performing four state transitions with the above-mentioned state s0 or s1 as the initial state for channel coding, when encoding new 9-bit binary data, there is no need to monitor the final state when encoding the immediately preceding 9-bit binary data or the initial state when encoding the immediately following 9-bit binary data. That is, binary data encoding can be performed on the condition that the final state when encoding the immediately preceding binary data and the initial state when encoding the immediately following binary data are state s0 or s1.

[0167] In the 9-bit / 4-cell code with k = 4 and ML = 5, the 600 block codes generated by performing four state transitions with state s0 as the initial state (or the 600 block codes generated by performing four state transitions with state s1 as the initial state) are regarded as candidate codes for the adopted code used in encoding.

[0168] Among the 600 candidate codes, 512 = 2 9 adopted codes used for encoding 9-bit binary data (assigned to 9-bit binary data) are selected.

[0169] <Repeat Minimum Transition Run (RMTR)>

[0170] Figure 15 and Figure 16 are diagrams showing the minimum transition pattern that appears in the sequence of the multi-valued code with ML = 5.

[0171] Figure 15 shows the minimum transition pattern that occurs in the multi-valued code when repeating 41 in the multi-valued edge code (block code composed of multi-valued edge codes) with ML = 5. Figure 16 shows the minimum transition pattern that appears in the multi-valued code when repeating 23 in the multi-valued edge code with ML = 5.

[0172] The minimum transition pattern is a pattern in which the change of the same value (level) repeats at the minimum period.

[0173] In optical recording, due to the low reproduction gain of high frequencies, there are restrictions on performing Repeat Minimum Transition (RMTR). For example, in the 17PP code and 110 Parity Complementary Word Assignment (PCWA) code, which are binary channel codes (binary codes), RMTR is restricted to 6 and 2 respectively. The 17PP code is a code obtained by modulating (encoding) the RLL(1,7)PP modulation scheme. The 110 PCWA code is disclosed in JP 4998472 B2.

[0174] By restricting RMTR, the frequent occurrence of the minimum transition pattern can be suppressed, and further, the high-frequency components of the reproduced signal can be suppressed.

[0175] A method for restricting the execution of RMTR on a multi - valued code of an ML value will be described.

[0176] In a multi - valued code (sequence of multi - valued codes) of an ML value, a minimum transition pattern appears when the multi - valued edge code c(t) satisfies the expression (c(t)+c(t + 1)) % ML = 0.

[0177] Here, the expression (c(t)+c(t + 1)) % ML = 0 is also referred to as the modulo edge condition.

[0178] For example, when the multi - valued edge code c(t) is 4 and the multi - valued edge code c(t + 1) is 1, the modulo edge condition is satisfied. Let the number of times the modulo edge condition is repeatedly satisfied, that is, the consecutive length of the minimum transition pattern, be the consecutive length of the modulo edge. For example, in the multi - valued edge codes (representing multi - valued codes) of four cells that make up a 9 - bit / 4 - cell code, the first and second multi - valued edge codes and the second and third multi - valued edge codes satisfy the modulo edge condition. However, when the third and fourth multi - valued edge codes do not satisfy the modulo edge condition, the consecutive length of the modulo edge is 2.

[0179] As Figure 6 shown, the multi - valued code l(t) obtained according to the expression l(t)=(l(t - 1)+c(t)) % ML is recorded on the optical disc 100.

[0180] Therefore, when 41 that satisfies the modulo edge condition continues as the multi - valued edge code in the multi - valued code with ML = 5, the minimum transition pattern continues in the multi - valued code.

[0181] That is, for example, when the (immediately preceding) multi - valued code l(t - 1) is 0 and 41 that satisfies the modulo edge condition continues as the multi - valued edge code, the multi - valued code l(t) at time t is (l(t - 1)+c(t)) % ML=(0 + 4) % 5 = 4. The multi - valued code l(t + 1) at time t + 1 is (l(t)+c(t + 1)) % ML=(4 + 1) % 5 = 0. Further, the multi - valued code l(t + 2) at time t + 2 is (l(t + 1)+c(t + 2)) % ML=(0 + 4) % 5 = 4. In this way, the multi - valued code becomes a minimum transition pattern that repeats 0 and 4.

[0182] As described above, when 41 that satisfies the modulo edge condition continues as the multi - valued edge code and the immediately preceding multi - valued code is 0, as Figure 15 shown, the multi - valued code becomes a minimum transition pattern that repeats 0 and 4.

[0183] As Figure 15 shown, when the immediately preceding (adjacent previous) multi - valued code is 1, the multi - valued code becomes a minimum transition pattern that repeats 1 and 0. As Figure 15As shown, when the immediately preceding multi - code is 2, the multi - code becomes the minimum conversion pattern in which 2 and 1 are repeated. As Figure 15 shown, when the immediately preceding multi - code is 3, the multi - code becomes the minimum conversion pattern in which 3 and 2 are repeated. As Figure 15 shown, when the immediately preceding multi - code is 4, the multi - code becomes the minimum conversion pattern in which 4 and 3 are repeated.

[0184] As described above, when 32 that satisfies the modulo edge condition continues as the multi - edge code and the immediately preceding multi - code is 0, as Figure 16 shown, the multi - code becomes the minimum conversion pattern in which 0 and 3 are repeated.

[0185] As Figure 16 shown, when the immediately preceding multi - code is 1, the multi - code becomes the minimum conversion pattern in which 1 and 4 are repeated. As Figure 16 shown, when the immediately preceding multi - code is 2, the multi - code becomes the minimum conversion pattern in which 2 and 0 are repeated. As Figure 16 shown, when the immediately preceding multi - code is 3, the multi - code becomes the minimum conversion pattern in which 3 and 1 are repeated. As Figure 16 shown, when the immediately preceding multi - code is 4, the multi - code becomes the minimum conversion pattern in which 4 and 2 are repeated.

[0186] When 14 or 23 that satisfies the modulo edge condition continues as the multi - edge code, the minimum conversion pattern also appears in the multi - code.

[0187] The occurrence of the minimum conversion pattern in the multi - code can be restricted by limiting the continuous length of the modulo edges that continuously satisfy the modulo edge condition.

[0188] Figure 17 is a diagram showing the start - continuous length and end - continuous length of 500 s0→s0 codes (also s1→s0 codes) and 100 s0→s1 codes (also 100 s1→s1 codes) among 600 candidate codes of a 9 - bit / 4 - cell code with k = 4 and ML = 5.

[0189] The start - continuous length refers to the continuous length of the modulo edges at the head of the block code, that is, the number of times the modulo edge condition is continuously satisfied from the head cell to the end cell. The end - continuous length refers to the continuous length of the modulo edges at the end part of the block code, that is, the number of times the modulo edge condition is continuously satisfied from the end cell to the head cell.

[0190] In Figure 17 each row represents the start - continuous length and each column represents the end - continuous length. The value of the field with start - continuous length i and end - continuous length j represents the number of candidate codes with start - continuous length i and end - continuous length j.

[0191] Figure 17 A of FIG. shows the start run length and the end run length in 500 s0→s0 codes among 600 candidate codes of a 9-bit / 4-cell code with k = 4 and ML = 5. Figure 17 B of FIG. shows the start run length and the end run length in 100 s0→s1 codes among 600 candidate codes of a 9-bit / 4-cell code with k = 4 and ML = 5.

[0192] In Figure 17 , among 500 s0→s0 codes, there are 336 block codes (hereinafter referred to as (i,j) codes) in which the start run length i is restricted to 0 and the end run length j is restricted to 0, 68 (0,1) codes, 16 (0,2) codes, 4 (0,3) codes, 52 (1,0) codes, 12 (1,1) codes, and 12 (2,0) codes. Among 100 s0→s1 codes, there are 84 (0,0) codes, 12 (1,0) codes, and 4 (2,0) codes.

[0193] Among 600 candidate codes of a 9-bit / 4-cell code with k = 4 and ML = 5, there is no candidate code in which the middle part (i.e., the second cell and the third cell) except for the head and the end part satisfies the modulo edge condition. Therefore, the 600 candidate codes of the 9-bit / 4-cell code with k = 4 and ML = 5 can be said to be block codes in which the run length of the modulo edge of the middle part (hereinafter also referred to as the middle run length) is restricted to 0.

[0194] In a multi-code (multi-edge code) with a certain ML value, RMTR is expressed as the run length of the minimum transition pattern.

[0195] The minimum transition pattern can be expressed not only when the minimum transition pattern appears in one block code, but also when the modulo edge condition is satisfied between the end multi-edge code of a certain block code and the head multi-edge code of the next block code.

[0196] For example, as Figure 17As shown, among the 600 candidate codes of the 9-bit / 4-cell code with k = 4 and ML = 5, there are 336 s0→s0 codes, where both the start consecutive length and the end consecutive length are 0. For example, 1334 and 1111 are candidate codes (s0→s0 codes) with both the start consecutive length and the end consecutive length being 0. Between the candidate codes 1334 and 1111 with both the start consecutive length and the end consecutive length being 0, when the candidate code 1111 continues after the candidate code 1334, the row 41 of the end multiple-edge code 4 (= c(t)) of the candidate code 1334 and the head multiple-edge code 1 (= c(t + 1)) of the candidate code 1111 satisfies the modulo-edge condition. Thus, even when only candidate codes with both the start consecutive length and the end consecutive length being 0 are used as the adopted code, the RMTR is 1.

[0197] As described above, the RMTR cannot be restricted to a value less than the start consecutive length + end consecutive length + 1, which is obtained by adding 1 to the sum of the start consecutive length and the end consecutive length. Here, the start consecutive length + end consecutive length + 1 is also referred to as the minimum length of the modulo edge.

[0198] To restrict the RMTR value to a smaller value, as the first condition, it is necessary to select candidate codes with smaller start consecutive length and end consecutive length as the adopted code. As the second condition, it is necessary to exclude candidate codes with an intermediate consecutive length greater than the minimum length of the modulo edge from the adopted codes (candidate codes).

[0199] As described above, among the 600 candidate codes of the 9-bit / 4-cell code with k = 4 and ML = 5, since the intermediate consecutive length is 0, the second condition is satisfied.

[0200] Thus, for the 600 candidate codes of the 9-bit / 4-cell code with k = 4 and ML = 5, by selecting the adopted code according to the first condition, the RMTR can be restricted to a smaller value.

[0201] Therefore, according to the present technology, as described below, 512 (= 2 Figure 17 ) candidate codes required for 9-bit encoding are selected as the adopted code from the 600 candidate codes of the 9-bit / 4-cell code with k = 4 and ML = 5 in 9 .

[0202] First, among the 600 candidate codes in Figure 17 , only codes close to the quantity are selected as the adopted code, such that the (0,0) codes with both the start consecutive length i and the end consecutive length j restricted to 0 become 512, which is the number of adopted codes required for 9-bit encoding (also referred to as the number of necessary codes hereinafter).

[0203] That is, in Figure 17Among the 500 s0→s0 codes in A, 336 (0,0) codes with the starting consecutive length i restricted to 0 and the ending consecutive length j restricted to 0 are selected as the adopted codes.

[0204] Among Figure 17 the 100 s0→s1 codes in B, 84 (0,0) codes with the starting consecutive length i restricted to 0 and the ending consecutive length j restricted to 0 are selected as the adopted codes.

[0205] Next, among Figure 17 the 600 candidate codes, only 92 of the (1,0) and (0,1) codes with one of the starting consecutive length i and the ending consecutive length j restricted to 1 and the other restricted to 0 are selected as the adopted codes, where 92 is the deficit with respect to the required number of codes 512.

[0206] That is, for example, among Figure 17 the 500 s0→s0 codes in A, 46 of the 68 (0,1) codes with the starting consecutive length i restricted to 0 and the ending consecutive length j restricted to 1, and 46 of the 52 (1,0) codes with the starting consecutive length i restricted to 1 and the ending consecutive length j restricted to 2 are selected as the adopted codes.

[0207] In the encoding of the multi - code, as described above, a code set of block codes selected from 512 adopted codes that are 9 - bit / 4 - cell codes with k = 4 and ML = 5 can be used. In this case, the RMTR of the block codes configuring the code set is 3 = 1 + 1 + 1, which is the minimum length of the modulo edge.

[0208] Here, the block codes configuring the code set can be said to be block codes with restricted starting consecutive length, ending consecutive length, and middle consecutive length.

[0209] Furthermore, the block codes configuring the code set can be said to be block codes with the middle consecutive length restricted to less than the minimum length of the modulo edge.

[0210] By excluding candidate codes that do not satisfy the second condition (i.e., the middle consecutive length is greater than the minimum length of the modulo edge) from the adopted codes, when the number of candidate codes that can be selected as adopted codes is less than the required number of codes, adopted codes are selected from candidate codes with a middle consecutive length greater than the minimum length of the modulo edge. In this case, the RMTR is greater than the minimum length of the modulo edge and is the maximum value of the middle consecutive length of the adopted codes.

[0211] Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23FIG. is a diagram showing an example of a code look-up table (LUT), in which 512 block codes of a 9-bit / 4-cell code with k = 4 and ML = 5 are associated with binary data as user data obtained by encoding the block codes.

[0212] In the code LUT, as Figure 17 described, the block code selected as the adopted code (the multi-valued edge code of the four cells constituting the block code) is registered in association with the binary data as user data. In Figures 18 to 23 the code LUT of, for example, the binary data 0 (here, zero represented by 9 bits) in Figure 18 is encoded as the block code (the multi-valued edge code of the four cells constituting the block code) 1111.

[0213] <Recording and Reproduction of Multi-Valued Codes on Optical Disc 100>

[0214] Figure 24 FIG. is a diagram showing recording / reproduction of multi-valued codes on optical disc 100.

[0215] In binary recording, marks representing 0 or 1 of the binary code are formed along the track of optical disc 100.

[0216] In multi-valued recording, marks having a size corresponding to the value (element) of the multi-valued code (in Figure 24 the size in the radial direction in ) are formed along the track of optical disc 100.

[0217] In optical disc 100 where multi-valued recording is performed, the difference in the size of the marks is represented as the step density (strength or weakness of light intensity) of the reflected light at the time of reproduction.

[0218] For example, when a quaternary code is recorded on optical disc 100, an electric signal is output from photodetector 6, in which the density of the reflected light corresponding to the four values of 0 to 3 taken by the quaternary code is convolved with the optical reproduction characteristics of the recording / reproducing apparatus.

[0219] <Data Detection Processing Unit 105>

[0220] Figure 25 FIG. is a block diagram showing an exemplary configuration of data detection processing unit 105.

[0221] In optical pickup 101, the output currents output from regions 6a, 6b, 6c, 6d1, and 6d2 of photodetector 6 are respectively referred to as detection signals S6a, S6b, S6c, S6d1, and S6d2.

[0222] The detection signals S6a, S6b, S6c, S6d1, and S6d2 are supplied from the optical pickup 101 to the matrix circuit 104. The matrix circuit 104 generates a reproduction signal based on the detection signals S6a to S6d2 supplied from the optical pickup 101, and supplies the reproduction signal to the data detection processing unit 105.

[0223] For example, the matrix circuit 104 generates reproduction signals Sa, Sb, Sc, and Sd for four signal channels, and supplies the reproduction signals Sa, Sb, Sc, and Sd to the data detection processing unit 105.

[0224] The reproduction signal Sa is a signal corresponding to the detection signal S6a, and the reproduction signal Sb is a signal corresponding to the detection signal S6b. The reproduction signal Sc is a signal corresponding to the detection signal S6c, and the reproduction signal Sd is a signal corresponding to the sum value of the detection signals S6d1 and S6d2.

[0225] The data detection processing unit 105 includes an analog-to-digital converter (ADC) 11, to which the reproduction signals Sa to Sd supplied from the matrix circuit 104 are supplied. A clock for the ADC 11 is formed by the PLL 12. The reproduction signals Sa to Sd supplied from the matrix circuit 104 are converted into digital data by the ADC 11.

[0226] The gains of the reproduction signals Sa, Sb, Sc, and Sd converted into digital data are adjusted by an automatic gain control (AGC) 13.

[0227] Furthermore, the data detection processing unit 105 includes a multi-input adaptive equalization unit 14, a noise predictor 15, a detection unit 16, a delay unit 17, an equalization error calculation unit 18, and a whitening coefficient update unit 19.

[0228] The reproduction signals Sa, Sb, Sc, and Sd that have undergone gain adjustment are supplied from the AGC 13 to the multi-input adaptive equalization unit 14. The reproduction signals Sa, Sb, Sc, and Sd for the four signal channels at the time t after gain adjustment supplied from the AGC 13 to the multi-input adaptive equalization unit 14 are respectively represented as reproduction signals x 1t 、x 2t 、x 3t 、and x 4t .

[0229] The multi-input adaptive equalization unit 14 performs adaptive PR equalization (adaptive equalization) on the reproduction signals x 1t 、x 2t 、x 3t 、and x 4t . By the reproduction signals x 1t to x 4tPR equalization of, reproduced signal x 1t to x 4t (which is the target) is equalized to approximate an ideal PR waveform. The multi-input adaptive equalization unit 14 generates an equalized signal y' 1t 、x 2t 、x 3t 、and x 4t by adding the results of adaptive PR equalization of and outputs the equalized signal y' t 。In the multi-input adaptive equalization unit 14, the filter coefficients for PR equalization are updated so that the equalization error e' t between the equalized signal y' t and the reference level is small. The ideal PR waveform is the ideal (true) waveform obtained when the sequence of multi-level codes recorded on the optical disc 100 achieves PR's ISI. The sample values constituting this waveform are referred to as the reference level.

[0230] The output of the multi-input adaptive equalization unit 14 (equalized signal y' t ) can be used as the signal input to the PLL 12. In this case, the initial value (initial coefficient) of the filter coefficients of the multi-input adaptive equalization unit 14 is set to a predetermined value.

[0231] The equalized signal y' t is supplied to the noise predictor 15 and the delay unit 17. The noise predictor 15 performs filtering processing for whitening the crosstalk noise (noise including crosstalk) from the adjacent tracks TK-1 and TK+1 included in the equalized signal y' t and outputs a whitened signal z t , and the whitened signal z t is the whitened equalized signal y' t .

[0232] The whitened signal z t as the output of the noise predictor 15 is supplied to the detection unit 16. The detection unit 16 obtains a multi-level code DT by performing multi-level processing for detecting the values that can be taken by the multi-level code from the whitened signal z t from the noise predictor 15. The multi-level code DT is supplied to the Figure 1 in the encoding / decoding unit 107 to be demodulated (decoded).

[0233] The delay unit 17 delays the equalized signal y' t from the multi-input adaptive equalization unit 14 and supplies the delayed equalized signal y' t to the equalization error calculation unit 18. In the delay unit 17, the equalized signal y' t 。In the delay unit 17, the equalized signal y' tis delayed until the detection unit 16 has obtained a sequence of multi - level codes (multi - level code sequence) in which a reference level of the equalization signal y’ t can be obtained.

[0234] The equalization error calculation unit 18 obtains the output (equalization signal) y’ of the multi - input adaptive equalization unit 14 provided via the delay unit 17 t The equalization error with respect to the reference level (the equalization error between the equalization signal y’ t and the reference level) e’ t . The equalization error calculation unit 18 provides the equalization error e’ t as a control signal for adaptive equalization to the multi - input adaptive equalization unit 14. The equalization error calculation unit 18 provides the equalization error e’ t to the whitening coefficient update unit 19.

[0235] The whitening coefficient update unit 19 adaptively updates the filter coefficients of the noise predictor 15, which is a whitening filter, according to the whitening error w’ t obtained from the equalization error e’ from the equalization error calculation unit 18 t and provides the updated filter coefficients to the noise predictor 15.

[0236] Hereinafter, before describing the multi - input adaptive equalization unit 14, the noise predictor 15, the detection unit 16, the equalization error calculation unit 18, and the whitening coefficient update unit 19 in detail, PRML for decoding (detecting) multi - level codes in the data detection processing unit 105 will be described.

[0237] Figure 26 is a diagram showing an exemplary configuration of a PR memory model.

[0238] In PRML, considering a PR memory model (transmission path of the recording / reproducing system) representing the recording / reproducing system, the signal obtained from the recording / reproducing system is decoded.

[0239] The PR memory model is a model representing a waveform sequence in which the reproduction of past input data from the input to the recording / reproducing system is disturbed by PR characteristics. The number of past input data that interfere with the input data at the current time t + 1 is called the ISI length (constraint length).

[0240] Viterbi decoding, which is a maximum - likelihood decoding considering the state and state transition of the PR memory model, is PRML.

[0241] For example, by using a quaternary code taking four values of 0, 1, 2, and 3 as the multi-valued code, 0, 1, 2, and 3 as the quaternary code are assumed to take signal values of -3, -1, +1, and +3 in the NRZ expression. The NRZ expression of the signal as the multi-valued code is assumed to be the NRZ multi-valued value.

[0242] In Figure 26 one of -3, -1, +1, and +3 as the NRZ multi-valued value is provided to the PR memory model.

[0243] In Figure 26 the PR memory model, the reproduced ISI length is 3(T) and the PR characteristics are subject to an inter-symbol interference waveform sequence of PR(1.0, 1.8, 0.9).

[0244] That is, in Figure 26 the PR memory model includes delay units 301 and 302, multipliers 304, 305, and 306, and an adder 307.

[0245] The NRZ multi-valued value as the input data provided (input) to the PR memory model is provided to the delay unit 301 and the multiplier 304.

[0246] The delay unit 301 delays the NRZ multi-valued value provided to the PR memory model by one clock and provides the delayed NRZ multi-valued value to the delay unit 302 and the multiplier 305.

[0247] The delay unit 302 delays the NRZ multi-valued value from the delay unit 301 by one clock and provides the delayed NRZ multi-valued value to the multiplier 306.

[0248] The multiplier 304 multiplies the NRZ multi-valued value provided to the PR memory model (i.e., the NRZ multi-valued value at the current time) by 1.0 and provides the multiplied value obtained as a result to the adder 307.

[0249] The multiplier 305 multiplies the NRZ multi-valued value from the delay unit 301 (i.e., the NRZ multi-valued value one clock before the current time) by 1.8 and provides the multiplied value obtained as a result to the adder 307.

[0250] The multiplier 306 multiplies the NRZ multi-valued value from the delay unit 302 (i.e., the NRZ multi-valued value two clocks before the current time) by 0.9 and provides the multiplied value obtained as a result to the adder 307.

[0251] The adder 307 adds the multiplied values from the multipliers 304 to 306 and outputs the added value obtained as a result as a value of the interference sequence subject to PR interference.

[0252] Figure 27 is a diagram showing an exemplary configuration of the multi-input adaptive equalization unit 14.

[0253] In Figure 27 the multi-input adaptive equalization unit 14 includes adaptive equalizers 21, 22, 23, and 24 and an adder 25.

[0254] The reproduced signals x 1t , x 2t , x 3t and x 4t from four signal channels of the AGC 13 at time t are supplied to the adaptive equalizers 21, 22, 23, and 24. In Figure 27 order to supply the reproduced signals x 1t to x 4t from four signal channels of the AGC 13 to the multi-input adaptive equalization unit 14, the multi-input adaptive equalization unit 14 includes adaptive equalizers 21 to 24 corresponding to the four signal channels. The multi-input adaptive equalization unit 14 includes the same number of adaptive equalizers as the number of signal channels of the reproduced signals supplied from the AGC 13 to the multi-input adaptive equalization unit 14.

[0255] The adaptive equalizers 21 to 24 are configured with finite impulse response (FIR) filters and have parameters of the number of taps of the FIR filter, the calculation accuracy (bit resolution), and the update coefficient μ (update gain of the adaptive calculation) when updating the filter coefficients. It is assumed that each of the adaptive equalizers 21, 22, 23, and 24 has a tap length L. According to the design specifications of the adaptive equalizer, the tap lengths of the adaptive equalizers 21 to 24 can be changed to L 1 , L 2 , L 3 and L 4 , respectively. Appropriate values are set for each parameter of the FIR filter through simulation or the like.

[0256] An equalization error e' t as a control signal for adaptive equalization (coefficient control value for adaptive control) is supplied from the equalization error calculation unit 18 to the adaptive equalizers 21 to 24.

[0257] The adaptive equalizer 20 + c (where c = 1, 2, 3, and 4) performs a filtering process of the FIR filter (filtering) on the target reproduced signal x 1t to x 4t in the c-th signal channel among the reproduced signals x ct from four signal channels of the AGC 13. The adaptive equalizer 20 + c outputs the filtered signal y ctOutput to adder 25.

[0258] Adder 25 adds the filtered signals y 1t , y 2t , y 3t and y 4t at time t from adaptive equalizers 21, 22, 23, and 24, and outputs the added value obtained as a result as the equalized signal y’ t at time t. The target waveform of the equalized signal y’ t is a waveform (ideal PR waveform) obtained by performing a convolution calculation on the multi - code (sequence) decoded (detected) by the detection unit 16 and the PR characteristics representing the recording / reproducing apparatus (transmission path of the recording / reproducing apparatus).

[0259] Figure 28 is a diagram showing an exemplary configuration of the FIR filter having a tap length L as the adaptive equalizer 20 + c.

[0260] The adaptive equalizer 20 + c includes (L - 1) delay units 30 - 1 to 30 - (L - 1), L multipliers 31 - 0 to 31 - (L - 1), and an adder 34, and configures an FIR filter with L taps.

[0261] In addition, the adaptive equalizer 20 + c includes L calculators 32 - 0 to 32 - (L - 1) and L integrators 33 - 0 to 33 - (L - 1).

[0262] The reproduction signal x at time t is supplied from the AGC 13 to the first delay unit 30 - 1 ct . The delay unit 30 - 1 supplies the reproduction signal x ct obtained by delaying the reproduction signal x supplied from the AGC 13 at time t by one clock c(t-1) to the subsequent delay unit 30 - 2 and calculator 32 - 1.

[0263] The len - th delay unit 30 - len (where len = 2, 3,..., and L - 2) supplies the reproduction signal x c(t-(len-1)) obtained by delaying the reproduction signal x from the previous - stage delay unit 30 - (len - 1) by one clock c(t-len) to the subsequent delay unit 30 - (len + 1) and calculator 32 - len.

[0264] The last delay unit 30 - (L - 1) supplies the signal x c(t-(L-2)) obtained by delaying the reproduction signal x from the previous - stage delay unit 30 - (L - 2) by one clock c(t-(L-1)) to the calculator 32 - (L - 1).

[0265] The first multiplier 31-0 is supplied with the reproduced signal x at time t from the AGC 13 ct . The multiplier 31-0 multiplies the reproduced signal x from the AGC 13 ct by the tap coefficient C 0 (C 0 is the number of filter coefficients), and supplies the obtained multiplication value as a result to the adder 34.

[0266] The len-th multiplier 31-len (where len = 1, 2,..., and L-1) multiplies the reproduced signal x from the delay unit 30-len c(t-len) by the tap coefficient C len , and supplies the obtained multiplication value as a result to the adder 34.

[0267] The first calculator 32-0 is supplied with the reproduced signal x from the AGC 13 ct and the equalization error e' at time t from the equalization error calculation unit 18 t .

[0268] The calculator 32-0 uses the reproduced signal x from the AGC 13 ct and the equalization error e' at time t from the equalization error calculation unit 18 t to perform a calculation such as -μ × e' t × x ct , and supplies the obtained calculation value -μ × e' t × x ct to the integrator 33-0. Here, an example where μ = 1 is shown in Figure 28 .

[0269] The len-th calculator 32-len (where len = 1, 2,..., and L-1) is supplied with the reproduced signal x from the delay unit 30-len c(t-len) and the equalization error e' at time t from the equalization error calculation unit 18 t .

[0270] The calculator 32-len uses the reproduced signal x from the delay unit 30-len c(t-len) and the equalization error e' at time t from the equalization error calculation unit 18 t to perform a calculation such as -μ × e' t × x c(t-len) , and supplies the obtained calculation value -μ × e' t × x c(t-len) to the integrator 33-len. Here, as described above, in Figure 28An example in which μ = 1 is set is shown.

[0271] The integrator 33-len (where len = 0, 1, ..., and L-1) integrates the calculated value -μ×e' from the calculator 32-len t ×x c(t-len) and updates the filter coefficient C of the multiplier 31-len according to the integral value obtained as a result. len .

[0272] Therefore, in the adaptive equalizer 20+c, as a result, the filter coefficients Clen (where len = 0, 1, ..., and L-1) for equalization are thus based on the equalization error e' at time t t , the reproduced signal x at time t corresponding to len = 0 from the AGC 13 ct , and the reproduced signal x from the delay unit 30-len (len = 1, 2, ..., and L-1) c(t-len) are sequentially updated.

[0273] The adaptive equalizer 20+c performs adaptive equalization by updating the filter coefficient C. len

[0274] When the integrator 33-len integrates the calculated value, the update responsiveness of the filter coefficient C is adjusted by setting the update coefficient μ. As described above, an example in which μ = 1 is set is shown in len . Figure 28 An example in which μ = 1 is set is shown.

[0275] The adder 34 adds each multiplied value from the multipliers 31-0 to 31-(L-1) and outputs the added value obtained as a result as the filtered signal y at time t. ct

[0276] The adaptive equalizers 21, 22, 23, and 24 with the above configuration perform adaptive equalization on the signals obtained by linearly combining the reproduced signals x 1t , x 2t , x 3t , and x 4t from the AGC 13 and the signals delayed by the delay units 30-len (where len = 2, 3, ..., L-1) respectively installed in the adaptive equalizer 21, that is, aiming at the ideal PR waveform, and perform equalization on the amplitude components of the signals obtained by linearly combining the reproduced signals x 1t , x 2t , x 3t , x 4t and the delayed signals, and optimize the error of the frequency components and the phase distortion.

[0277] In adaptive equalization, the tap coefficients C of the adaptive equalizers 21, 22, 23, and 24 are updated according to the calculated values -μ×e' in the calculators 32-0 to 32-(L-1) respectively installed in the adaptive equalizers 21, 22, 23, and 24 t ×x c(t-len) (where len = 0, 1,..., L-1). Thus, the tap coefficients C to C are updated in the direction of minimizing (approaching 0) the square (square error) of the equalization error e' according to the gradient method 0 to C L-1 . Thus, the tap coefficients C to C are updated in the direction of minimizing (approaching 0) the square (square error) of the equalization error e' according to the gradient method t to C 0 to C L-1 .

[0278] In the direction where the tap coefficients C to C in the adaptive equalizer have frequency characteristics equalized to the target ideal PR waveform, the equalization error e' is used to adaptively control the equalization signal y' at time t, which is represented as the sum value of the filtered signals y, y, y, and y output from the adaptive equalizers 21, 22, 23, and 24 0 to C L-1 to C t to C 1t and y 2t and y 3t and y 4t output from the adaptive equalizers 21, 22, 23, and 24 t .

[0279] Through the signal processing in the multi-input adaptive equalization unit 14, the equalization signal y' becomes an equalization signal y' that is adaptively equalized to reproduce the target track TK. In the signal for reproducing the target track TK, unnecessary signals (such as crosstalk noise) from adjacent tracks are reduced from the signal that is noise (which includes crosstalk noise superimposed on the reproduction signals from the target track TK and adjacent tracks TK-1 and TK+1) through the aforementioned adaptive equalization process, and the reproduction signals from each signal channel c are used in the adaptive equalization process t to C t to C

[0280] In the multi-input adaptive equalization unit 14, crosstalk noise and the like from adjacent tracks TK-1 and TK+1 that cannot be removed in the adaptive equalization process remain in the equalization signal y' obtained by adding the filtered signals y, y, y, and y output from the adaptive equalizers 21, 22, 23, and 24 1t and y 2t and y 3t and y 4t output from the adaptive equalizers 21, 22, 23, and 24 t .

[0281] Therefore, the noise predictor 15 can be provided at a subsequent stage of the multi-input adaptive equalization unit 14. Accordingly, the data detection processing unit 105 can have the function of NPML. NPML is disclosed in E. Eleftheriou and W. Hirt, "Noise-Predictive Maximum-Likelihood (NPML) Detection for the Magnetic Recording Channel" (hereinafter referred to as Document A).

[0282] The noise predictor 15 whitens the crosstalk noise remaining in the equalized signal y' t by performing a filtering process of a whitening filter on the equalized signal y' t output from the multi-input adaptive equalization unit 14.

[0283] The filtered signals y 1t , y 2t , y 3t , and y 4t obtained in the multi-input adaptive equalization unit 14 can be expressed by Expression (1) using the reproduction signals x 1t , x 2t , x 3t , and x 4t .

[0284] [Mathematical Expression 1]

[0285]

[0286] The vector f ct is a vector having a length L and having tap coefficients C 0 at time t of the signal channel c (adaptive equalizer 20 + c) to C L-1 as elements. The vector x ct is a vector having a length L and having sample values x ct of the reproduction signal x ct , x c(t-1) ,......, and x c(t-(L-1)) as elements, and the reproduction signal is the target of the filtering process using the tap coefficients C 0 at time t to C L-1 .

[0287] The equalized signal y' lt to y 4t obtained by adding the filtered signals y t can be expressed in Expression (2).

[0288] [Mathematical Expression 2]

[0289]

[0290] f c1 represents the first tap coefficient C of the signal channel c (adaptive equalizer 20 + c). 1 . K represents the ISI length, and the ISI length is the length (time) at which the ISI of the target PR (target PR) appears.

[0291] c m represents K coefficients c 0 、c 1 、...、c K-1 among which is equal to the m-th coefficient of the ISI length K of the impulse response of the target PR (of the ISI). Hereinafter, the coefficient c m is also referred to as the PR coefficient c m .

[0292] a t represents the NRZ multilevel value, and the NRZ multilevel value is the non-return-to-zero (NRZ) expression of the signal value at the moment t (on the channel) of the multicode recorded on the optical disc 100. When the ML value takes the value (element) of the multicode from 0 to ML - 1 at the moment t and is represented by b t , for example, the NRZ multilevel value a can be obtained through the expression a t = 2 × b t - (ML - 1). t .

[0293] As a sequence of n cells of a plurality of cells of the multicode (multicode value) b t represents an n-bit number in the ML base. The sequence of NRZ multilevel values a t corresponding to the sequence of n cells of the multicode b t represents the sequence of the plurality of cells of the multicode b t as a value centered on direct current (DC).

[0294] Hereinafter, when a quaternary code with ML = 4 is used as the multicode, the NRZ multilevel value a t of the quaternary code (quaternary code value) b t = {0, 1, 2, 3} is a t = {-3, -1, +1, +3}.

[0295] v t represents the error between the level of the target PR and the equalized signal y' t at the moment t. w t represents the noise including the crosstalk noise remaining in the equalized signal y' t at the moment t.

[0296] By making the equalized signal y't Passing through the noise predictor 15 can whiten the frequency components of the noise w t and thus suppress the branch metrics in the Viterbi decoding of the detection unit 16.

[0297] The whitened signal z output by the noise predictor 15 t can be expressed by Expression (3).

[0298] [Mathematical Expression 3]

[0299]

[0300] Figure 29 is a diagram showing an exemplary configuration of the noise predictor 15.

[0301] The noise predictor 15 is configured with a FIR filter that includes N-stage delay units 41-1 to 41-N, N multipliers 42-1 to 42-N, and an adder 43.

[0302] When the equalization signal y' of the multi-input adaptive equalization unit 14 t is input, the N-stage delay units 41-1 to 41-N delay and output each sample of the equalization signal y'. t That is, the delay units 41-1 to 41-N delay the equalization signal y' input to the delay units 41-1 to 41-N t by one clock and output it.

[0303] The N multipliers 42-1 to 42-N multiply the output of the delay unit 41-len (i.e., the equalization signal y' t-l and the tap coefficient p len ).

[0304] The adder 43 calculates the sum of the equalization signal y' that is the input to the delay unit 41-1 in the first stage t and the value that is -1 times the output of the multipliers 42-1 to 42-N, and outputs the calculated value obtained as a result as the whitened signal z t .

[0305] As the tap coefficients p of the multipliers 42-1 to 42-N 1 to p N , the tap coefficients p obtained by the whitening coefficient update unit 19 are set len (where len = 1, 2,..., and N).

[0306] The noise predictor 15 supplies the whitened signal z output by the adder 43 t to the detection unit 16.

[0307] The detection unit 16 includes a Viterbi decoder that performs Viterbi decoding, for example, as maximum likelihood decoding. The detection unit 16 serves as a decoding unit that decodes (detects) the multi-code DT from the whitened signal z t by performing Viterbi decoding, which is a multi-process of the whitened signal z t .

[0308] The Viterbi decoder includes blocks (circuits) corresponding to a plurality of states, the number of which is the same as the number of values obtained by consecutive units of a predetermined length, and connection lines that connect the blocks corresponding to these states to each other and correspond to branches indicating transitions (state transitions) between states. The Viterbi decoder effectively detects the most reliable multi-code sequence among all possible multi-code sequences.

[0309] In an actual circuit, the Viterbi decoder includes a memory (register) called a state metric memory that stores the state metric of each state (up to the state). The Viterbi decoder includes a register called a path memory that stores the multi-code sequence up to the state (the multi-code sequence measured up to the state). In addition, the Viterbi decoder has a function of calculating the branch metric in each branch.

[0310] Various multi-code sequences can be associated with the paths reaching each state in a one-to-one relationship. For a path, a path metric is calculated. The path metric indicates the error between the ideal PR waveform and the actually obtained equalized signal y’ t (the waveform of the equalized signal y’ t ). In the ideal PR waveform, the multi-code sequence corresponding to each path is affected by the ISI of the PR. The path metric can be obtained by sequentially adding the state transitions (i.e., the branch metrics of the branches) that make up the path.

[0311] The Viterbi decoder selects, at each state at each time, the minimum value of the path metric of the path having a branch of the state at the previous time below the ML reaching the state as the state metric of the state. At each state, the path metric of the path having the branch is calculated by adding the branch metric of the branch to the subsequent time state to the state metric of the state. Hereinafter, the selection of the minimum value of the path metric as the state metric and the calculation of the path metric are similarly repeated.

[0312] The final (latest) branch of the path for which the path metric is used as a state metric is called the selected branch. When the path metric is selected as the state metric, the Viterbi decoder adds the multi - code corresponding to the selected branch to the stored value of the path memory in the state at the previous time when reaching that state, and stores the multi - code in the path memory. Thus, in the path memory of each state, the surviving path as the path reaching that state is stored in the form of a sequence of multi - codes corresponding to the branches constituting the surviving path.

[0313] Then, for example, the maximum - likelihood path is selected as the decoding result of Viterbi decoding, and the maximum - likelihood path is the path in which the state metric reaches the minimum state at a predetermined time (the time of the final state of the path when a path of a predetermined length is obtained). The sequence of multi - codes representing the maximum - likelihood path as the decoding result of Viterbi decoding is the sequence of multi - codes of the multi - code DT.

[0314] Hereinafter, the branch - metric calculation methods in each of ordinary Viterbi decoding, Viterbi decoding with decision - feedback equalization (DFE) introduced, Viterbi decoding with NPML introduced, and Viterbi decoding with DFE and NPML introduced will be described.

[0315] Here, ordinary Viterbi decoding is Viterbi decoding without DFE and NPML introduced. Viterbi decoding with DFE introduced is Viterbi decoding with DFE but without NPML introduced. Viterbi decoding with NPML introduced is Viterbi decoding with NPML but without DFE introduced.

[0316] When ordinary Viterbi decoding is performed in the detection unit 16, the data detection processing unit 105 (see Figure 25 ) does not include the noise predictor 15.

[0317] In ordinary Viterbi decoding, for example, the branch metric λ i from the state s j at time t - 1 to the state s t (s i , s j ) at time t is calculated using Expression (4).

[0318] [Mathematical formula 4]

[0319]

[0320] In Expression (4), r t (s i , s j ) on the right - hand side of the second line represents Σ(c m ×a t-m ) on the right - hand side of the first line, and Δr on the right - hand side of the second linet (b t ) represents v on the right side of the first row, that is, v in expression (2). t , that is, v in expression (2). t . c m represents the m-th PR coefficient, as described in expression (2).

[0321] Vector b t (b with an arrow shown above t ) is a vector with the K latest multi-codes b t , b t-1 ,..., and b t-(K-1 ) traced back from time t as elements, and can be represented by expression (5). As described in expression (2), the conversion between the multi-code b t and the NRZ multi-value a t can be performed using the expression a t = 2 × b t - (ML - 1).

[0322] [Mathematical formula 5]

[0323]

[0324] In expression (4), r t (s i , s j ) + Δr t (b t ) represents the reference level of the equalization signal y’ t , and there are ML^K reference levels, which is equal to the number of ML-ary of the multi-row multi-code of K cells represented as b t to b t-(K-1) . A^B represents the B-th power of A.

[0325] As described above, since the reference level r t (s i , s j ) + Δr t (b t ) is the reference level of the equalization signal y’ t , so the reference level r t (s i , s j ) + Δr t (b t ) is also called the equalization reference level.

[0326] When v t = 0, ML^K equalization reference levels r t (s i,s j ) + Δr t (b t )。

[0327] In the Viterbi decoding with DFE introduced, for example, the branch metric λ is calculated using expression (6). t (s i ,s j )。

[0328] [Mathematical formula 6]

[0329]

[0330] In expression (6), the vector b t is a vector with the latest M latest multi - ary codes b t , b t-1 ,..., and b t-(M-1) as elements, starting from time t and can be expressed by expression (7).

[0331] [Mathematical formula 7]

[0332]

[0333] Expressions (6) and (7) are the same as expressions (4) and (5), except that M is used instead of K.

[0334] In equation (6), as in equation (4), r t (s i , s j ) + Δr t (b t ) represents the reference level (equalization reference level) of the equalized signal y'. t Here, although there are ML^K reference levels r t to b t-(K-1) indicated by MR1 of expression (4) and equal to the number of ML - ary of the multi - line multi - ary code of K cells represented as b t (s i , s j ) + Δr t (b t ), there are ML^M reference levels r t to b t-(K-1) indicated by MR2 of expression (6) and equal to the number of ML - ary of the multi - line multi - ary code of M cells represented as b t (s i , s j ) + Δr t (b t )。

[0335] Here, when assuming a PR of a certain impulse response in the recording / reproducing system of the optical disc 100, the assumed PR (ideal PR) is also referred to as the assumed PR.

[0336] In the recording / reproducing system of the actual optical disc 100, in some cases, minute interference exceeding the ISI length of the assumed PR occurs. In addition to the assumed PR, the PR considering the minute interference is also referred to as the extended PR.

[0337] Hereinafter, K represents the ISI length of the assumed PR, and M represents the ISI length of the extended PR. The ISI lengths K and M are assumed to have a relationship of the expression K ≤ M.

[0338] Since the actually occurring minute interference is considered in the Viterbi decoding, the extended PR considering the minute interference actually occurring in the assumed PR is combined in the Viterbi decoding, so that the branch metric is suppressed and the decoding performance (detection accuracy) of the multi - code can be improved.

[0339] Here, the number of states of the Viterbi decoding is the (ISI length - 1) - th power of the number of values ML taken for each cell. Therefore, when the ISI length of the PR is long, the number of states increases, and thus the circuit size of the Viterbi decoder may increase.

[0340] When K < M, the ISI length M in the Viterbi decoding combining the extended PR is longer than the ISI length K in the Viterbi decoding combining the assumed PR. When only the Viterbi decoding combining the extended PR is performed, the decoding performance of the multi - code is improved, but the circuit size may increase.

[0341] Therefore, the states taken in the Viterbi decoding combining the assumed PR can be used as the states taken in the Viterbi decoding combining the extended PR. In this case, the number of states of the Viterbi decoding combining the extended PR is reduced from the original number of states ML^(M - 1) to the number of states ML^(K - 1) of the Viterbi decoding combining the assumed PR. Therefore, the decoding performance of the multi - code can be improved while suppressing the increase in the circuit size.

[0342] As described above, in the Viterbi decoding combining the extended PR, the Viterbi decoding in which the number of states is reduced to the number of states of the Viterbi decoding combining the assumed PR is also referred to as the reduced Viterbi decoding. When K = M, the reduced Viterbi decoding is the ordinary Viterbi decoding.

[0343] In the reduced Viterbi decoding including the ordinary Viterbi decoding, there are ML^M reference levels, which is the ISI length power of the number of values ML taken for each cell.

[0344] In reduced Viterbi decoding with DFE introduced, at most ML^M reference levels are stored in the storage unit. Among the reference levels stored in the storage unit, the reference levels of the latest M (>K) cells addressed (designated) in the multi-code sequence are read. The multi-code sequence is a candidate for the decoding result (hereinafter also referred to as the temporary decoding result) of Viterbi decoding for constructing a path including the branch whose branch metric is to be calculated, and is used for branch metric calculation.

[0345] Then, path metric calculation of the path including the branch whose branch metric is to be calculated is performed using the branch metric obtained as a result of the branch metric calculation. Further, using the path metric obtained as a result of the path metric calculation, the multi-code sequence corresponding to the path with the minimum path metric is obtained as a new temporary decoding result.

[0346] In reduced Viterbi decoding with DFE introduced, the reference levels stored in the storage unit are updated according to the equalization error e’ t so that the equalization error e’ t is reduced. The updated reference levels among the reference levels stored in the storage unit are addressed using M cells in the multi-code sequence as the temporary decoding result.

[0347] As described above, in reduced Viterbi decoding with DFE introduced, the temporary decoding result (decision) of M (>K) cells is fed back, and the reference levels are updated, and thus a DFE that performs feedback can be configured. According to the DFE, the reference levels are updated by the feedback of the temporary decoding result of M (>K) cells, and thus the influence of interference exceeding the assumed ISI length K of the PR in the interference of the extended PR is suppressed in the branch metric calculation. As a result, as described above, in reduced Viterbi decoding with a reduced number of states, deterioration of decoding performance can be suppressed.

[0348] The configuration of the DFE is disclosed in Figure 3 Document A.

[0349] In Viterbi decoding with NPML introduced, for example, the branch metric λ is calculated by Expression (8) t (s i ,s j ).

[0350] [Mathematical Expression 8]

[0351]

[0352] In Expression (8), the vector b t is represented in the above Expression (5).

[0353] In Expression (8), r on the right side of the third rowt (s i ,s j ) and r t-len (s i ,s j ) respectively represent Σ(c m ×a t-m ) and Σ(c m ×a t-len-m ) on the right side of the second row. Δr t (b t ) and Δr t (b t-len ) on the right side of the third row represent v t and v t-len on the right side of the second row.

[0354] In addition, in Expression (8), N represents the number of taps of the noise predictor 15, and p len represents the len-th tap coefficient among the N tap coefficients (filter coefficients) of the noise predictor 15.

[0355] In Expression (8), y’ t - (Σ(c m ×a t-m ) + v t ) on the right side of the first row represents the noise w t in Expression (2). Σ[p len ×{y’ t-len - (Σ(c m ×a t-len-m ) + v t-len )}] on the right side of the first row represents the estimated value of the noise w t whitened by the noise predictor 15.

[0356] Therefore, in the Viterbi decoding with NPML introduced, the square of the error between the estimated value of the noise w t and the whitened noise w t is obtained as the branch metric λ t (s i ,s j ).

[0357] In Expression (8), z t represents the whitened signal, which is the equalized signal y’ t whitened by the noise predictor 15.

[0358] In addition, in Expression (8), r t (s i ,s j ) + Δr t (b t) - Σ[p len ×{r t-len (s i , s j ) + Δr t (b t-len )}] represents the reference level of the whitened signal z t . The whitened signal z t is the equalized signal y' whitened by the noise predictor 15 t . There are ML^(K + N) reference levels r t to b t-(K+N-1) of the multi - row multi - ary code of K + N cells indicated by MR3 and equal to the number of ML - ary, where r t (s i , s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i , s j ) + Δr t (b t-len )}].

[0359] As described above, since the reference level r t (s i , s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i , s j ) + Δr t (b t-len )}] is the reference level of the whitened signal z t (obtained by whitening the equalized signal y') t , so the reference level r t (s i , s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i , s j ) + Δr t (b t-len )}] is also called the whitened reference level.

[0360] The whitened reference level r t (s i , s j ) + Δr t (bt ) - Σ[p len ×{r t-len (s i , s j ) + Δr t (b t-len )}] The equalization reference level r t (s i , s j ) + Δr t (b t )( and r t-len (s i , s j ) + Δr t (b t-len )) can be obtained.

[0361] In the Viterbi decoding with NPML introduced, at most ML^(N + K) reference levels are stored in the storage unit. Among the reference levels stored in the storage unit, the reference level addressed by the latest N + K cells in the multi - code sequence, which is the temporary decoding result constituting the path including the branch for which the branch metric is calculated, is read and used for branch metric calculation.

[0362] Using the branch metric obtained as a result of branch metric calculation, path metric calculation of the path including the branch for which the branch metric is calculated is performed. Further, using the path metric obtained as a result of path metric calculation, the multi - code sequence corresponding to the path with the minimum path metric is obtained as the new temporary decoding result.

[0363] In the Viterbi decoding with NPML introduced, the reference level stored in the storage unit is updated according to the equalization error e’ t such that the equalization error e’ t is reduced. The updated reference level among the reference levels stored in the storage unit is addressed by N + K cells in the multi - code sequence used as the temporary decoding result.

[0364] As described above, in the Viterbi decoding with NPML introduced, the temporary decoding result (decision) of N + K cells is fed back and the reference level is updated. Therefore, the DFE can be configured in the same way as the reduced Viterbi decoding with DFE introduced.

[0365] In the Viterbi decoding with DFE and NPML introduced, for example, the branch metric λ is calculated using Expression (9) t (s i , s j ).

[0366] [Mathematical Expression 9]

[0367]

[0368] Except for using M instead of K, the expression (9) is the same as the expression (8). Therefore, the branch metric λ is obtained in the expression (9). t (s i ,s j ) is the reduced Viterbi decoding of the Viterbi decoding.

[0369] In the expression (9), r indicated by MR4 t (s i ,s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i ,s j ) + Δr t (b t-len )}] represents the reference level (whitening reference level) of the whitened signal z t , and the whitened signal z t is the equalized signal y' whitened by the noise predictor 15 t , as in the expression (8).

[0370] Here, although there are ML^(K + N) whitening reference levels r t to b t-(K+N-1) of the ML-ary number of the multi-line multi-ary code of K + N cells indicated by MR3 in the expression (8) and equal to the number of ML-ary of the multi-line multi-ary code of K + N cells represented as b t (s i ,s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i ,s j ) + Δr t (b t-len )}], but there are ML^(M + N) whitening reference levels r t to b t-(M+N-1) of the ML-ary number of the multi-line multi-ary code of M + N cells indicated by MR4 in the expression (9) and equal to the number of ML-ary of the multi-line multi-ary code of M + N cells represented as b t (s i ,s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i ,s j ) + Δr t (bt-len )}]。

[0371] The whitening reference level r indicated by MR4 t (s i ,s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i ,s j ) + Δr t (b t-len )}] can use the equalization reference level r t (s i ,s j ) + Δr t (b t )(and r t-len (s i ,s j ) + Δr t (b t-len )) to obtain.

[0372] In the expression (9), the branch metric λ of the Viterbi decoding with DFE and NPML is introduced t (s i ,s j ) with the equalization reference level r t (s i ,s j ) + Δr t (b t ) and the whitening signal z obtained through the whitened equalized signal y’ t and the tap coefficients p of the noise predictor 15 t 、as well as the convolution of len with the equalization reference level r t-len (s i ,s j ) + Δr t (b t-len ) is represented.

[0373] In the Viterbi decoding with DFE and NPML introduced, at most ML^(M + N) reference levels are stored in the storage unit. Among the reference levels stored in the storage unit, the reference level addressed by the latest M + N cells in the multi - code sequence is read and used for branch metric calculation, and the multi - code sequence is the temporary decoding result that constitutes the path of the target branch including branch metric calculation.

[0374] Perform path metric calculation for a path including a target branch for branch metric calculation using the branch metric obtained as a result of the branch metric calculation. Further, using the path metric obtained as a result of the path metric calculation, obtain a multi - ary code sequence corresponding to the path with the minimum path metric as a new temporary decoding result.

[0375] In reduced Viterbi decoding incorporating DFE and NPML, the reference level stored in the storage unit is updated according to the equalization error e'. t such that the equalization error e' t is reduced. The updated reference level among the reference levels stored in the storage unit is addressed using M + N units in the multi - ary code sequence as the temporary decoding result.

[0376] In Expression (9), by setting N = 0 and M = K, the branch metric calculation of ordinary Viterbi decoding can be represented. In Expression (9), by setting N>0 and M = K, the branch metric calculation of Viterbi decoding incorporating NPML can be represented. Further, in Expression (9), by setting N = 0 and M>K, the branch metric calculation of Viterbi decoding incorporating DFE can be expressed.

[0377] Therefore, the description of Viterbi decoding (i.e., Viterbi decoding incorporating DFE and NPML) that performs branch metric calculation using Expression (9) is a description of one of ordinary Viterbi decoding, Viterbi decoding incorporating DFE, and Viterbi decoding incorporating NPML according to the values of N and M.

[0378] Therefore, hereinafter, instead of describing each of ordinary Viterbi decoding, Viterbi decoding incorporating DFE, Viterbi decoding incorporating NPML, and Viterbi decoding incorporating DFE and NPML, reduced Viterbi decoding incorporating DFE and NPML and decoding the multi - ary code will be described.

[0379] Figure 30 is a diagram showing an example of a trellis of reduced Viterbi decoding incorporating DFE and NPML.

[0380] Here, for example, assume that ML = 4 is set, and a quaternary code taking b t = 0, 1, 2, and 3 is used as the multi - ary code.

[0381] Further, for example, assume that the assumed PR is PR(1, 2, 1) with an ISI length K = 3, and the extended PR is PR(1, 2, 1, 0.2, 0.1) with an ISI length M = 5. In this case, assume that the PR coefficient c m of the assumed PR is c 0 = 1, c1 = 2, and c 2 = 1. The PR coefficient c of the extended PR m is c 0 = 1, c 1 = 2, c 2 = 1, c 3 = 0.2 and c 4 = 0.1.

[0382] The multi - code b t has a minimum run length (the minimum number of consecutive zeros) d of d = 0, and the number of taps N of the noise predictor 15 is N = 1.

[0383] In addition, it is assumed that the RMTR described in Figure 15 and Figure 16 is limited to 1 or less.

[0384] The RMTR is equivalent to the number of consecutive occurrences that satisfy the expressions b t , b t-1 , b t-2 ,.... for the quaternary - code sequence b t != b t-1 and b t = b t-2 . A!= B means A is not equal to B.

[0385] When the RMTR is limited to 1 or less, for example, {1, 3, 1, 0}, {1, 3, 1, 1}, or {1, 3, 1, 2} are allowed as quaternary - code sequences because the RMTR is 1.

[0386] On the other hand, for example, {1, 3, 1, 3} is not allowed as a quaternary - code sequence because the RMTR is 2.

[0387] The number of states of the trellis for reduced - complexity Viterbi decoding is ML^(K - 1)=4^(3 - 1)=16, which is equal to the number of ML - ary (cases) represented by the number of cells, where the number of cells is the ISI length K - 1 of the assumed PR, as Figure 30 shown. Each of the 16 states is represented as state qr using a row qr of 2 - cell ML - ary. q and r represent one - digit ML - ary.

[0388] The number of branches from the state at time t - 1 to a state at time t (can reach) is ML. Thus, in the trellis, the total number of branches to the ML^(K - 1) states at time t is ML×ML^(K - 1)=ML^K = 4^3 = 64.

[0389] In the state qr at time t - 1, it represents where the quaternary - code b tThe branch of the state transition of the new new temporary decoding result at time t = p is represented as the branch pqr of the ML-ary row pqr using 3 cells.

[0390] In this case, the state qr represented by the ML-ary qr of the last 2 cells of the branch pqr represents the state before the state transition, and the state pq represented by the ML-ary pq of the first 2 cells of the branch pqr represents the state after the state transition. For example, the branch 100 represents the state transition from state 00 to state 10.

[0391] Although the total number of branches is ML^K = 64, the number of whitening reference levels MR4 used for the branch metric calculation of Expression (9) (which can be used) is ML^(M+N) = 4^(5+1) = 4^6, as described in Expression (9). The number of whitening reference levels MR4 for the branch metric calculation of one branch can be ML^(M+N) / ML^K = ML^(M+N-K).

[0392] According to the coding rules when coding the multi-code (coding rules of the multi-code), for example, the minimum running length d, RMTR, etc., the states and branches (state transitions) of the trellis are restricted, and Viterbi decoding can be performed.

[0393] In Figure 30 the trellis, when RMTR is restricted to 1 or less, there are unadopted states (forbidden states), unadopted branches (forbidden branches), or unavailable whitening reference levels MR4 (forbidden reference levels).

[0394] The branches indicating the state transitions to unadopted states, the branch metric calculations for unadopted branches, and the branch metric calculations performed using unavailable whitening reference levels MR4 can be omitted (excluded from the execution target).

[0395] <Viterbi decoder>

[0396] Figure 31 is a diagram showing an exemplary configuration of the Viterbi decoder 320 included in the detection unit 16.

[0397] The Viterbi decoder 320 is a Viterbi decoder for recovering the quaternary code described in Figure 30 and includes an add-compare-select (ACS) unit 330-pq corresponding to each of the 16 states pq of the trellis. As Figure 30 described, pq is the ML-ary row of 2 cells representing the state pq.

[0398] The ACS unit 330-pq includes a path memory PM pq and a selector SELpq , state metric memory SM pq and adder ADD pq .

[0399] Path memory PM pq stores a quaternary code sequence as a temporary decoding result, and the temporary decoding result corresponds to a surviving path that reaches state pq by backtracking from the quaternary code that is the temporary decoding result at the latest moment.

[0400] where the state metric sm of state qr qr and the branch metric bm of the branch from state qr to state pq (representing a state transition) pqr are added, and the path metric sm of the path reaching state pq via state qr qr +bm pqr is provided from the ACS unit 330-qr corresponding to state qr (in state qr, the state transition to state pq is feasible) to the selector SEL pq .

[0401] For example, it is possible to transition from each of state 10, state 11, state 12, and state 13 to state 31. Therefore, the ACS unit 330-31 corresponding to state 31 is provided with connection lines (not shown) corresponding to the branches indicating state transitions and from each of the ACS unit 330-10 corresponding to state 10, the ACS unit 330-11 corresponding to state 11, the ACS unit 330-12 corresponding to state 12, and the ACS unit 330-13 corresponding to state 13.

[0402] The following path metrics are provided from each of the ACS unit 330-10 corresponding to state 10, the ACS unit 330-11 corresponding to state 11, the ACS unit 330-12 corresponding to state 12, and the ACS unit 330-13 corresponding to state 13 to the selector SEL of the ACS unit 330-31 corresponding to state 31 via the connection lines corresponding to the branches 31 .

[0403] where the state metric sm of state 10 10 and the branch metric bm of the branch from state 10 to state 31 310 are added and the path metric sm of the path reaching state 31 via state 10 10 +bm 310 is provided from the ACS unit 330-10 corresponding to state 10 to the selector SEL31 of the ACS unit 330-31 corresponding to state 31.

[0404] Among them, the state metric sm of state 11 11 and the branch metric bm of the branch from state 11 to state 31 311 are added, and the path metric sm of the path reaching state 31 via state 11 11 +bm 311 is provided to the selector SEL of the ACS unit 330-31 corresponding to state 31 from the ACS unit 330-11 corresponding to state 11 31 .

[0405] Among them, the state metric sm of state 12 12 and the branch metric bm of the branch from state 12 to state 31 312 are added, and the path metric sm of the path reaching state 31 via state 12 12 +bm 312 is provided to the selector SEL of the ACS unit 330-31 corresponding to state 31 from the ACS unit 330-12 corresponding to state 12 31 .

[0406] Among them, the state metric sm of state 13 13 and the branch metric bm of the branch from state 13 to state 31 313 are added, and the path metric sm of the path reaching state 31 via state 13 13 +bm 313 is provided to the selector SEL of the ACS unit 330-31 corresponding to state 31 from the ACS unit 330-13 corresponding to state 13 31 .

[0407] Selector SEL pq selects the minimum path metric among the path metrics provided to the selector SEL pq as the new state metric sm of state pq pq , and provides the selected minimum path metric to the state metric memory SM pq .

[0408] State metric memory SM pq stores the state metric sm from the selector SEL pq pq .

[0409] Adder ADD pq obtains the path metric sm of the path reaching state p'p by adding the state metric sm stored in the state metric memory SM pq to the branch metric bm of the branch to state p'p pq p’pq ​​​pq +bm p’pq In state p'p, the state transition from state pq is feasible. p' represents a digit in the ML number system, just like p, q, and r.

[0410] In the adder ADD of the ACS unit 330-pq corresponding to state pq pq and the selector SEL of the ACS unit 330-p'p corresponding to state p'p p’p there is a connection line (not shown) corresponding to the branch representing the state transition, where the state transition from state pq in state p'p is feasible.

[0411] Adder ADD pq Via this connection line, the path metric sm pq +bm p’pq is provided to the selector SEL of the ACS unit 330-p'p corresponding to state p'p. p’p .

[0412] For example, the state transitions from state 31 to states 03, 13, 23, and 33 are feasible.

[0413] Therefore, the adder ADD of the ACS unit 330-31 corresponding to state 31 31 obtains the path metric sm of the path reaching state 03 via state 31 by adding 31 the state metric sm 031 and the branch metric bm of the branch from state 31 to state 03 31 +bm 031 , and provides the path metric sm 31 +bm 031 to the ACS unit 330-03 corresponding to state 03 (not shown).

[0414] Similarly, adder ADD 31 obtains the path metric sm of the path reaching state 13 via state 31 by adding 31 the state metric sm 131 and the branch metric bm of the branch from state 31 to state 13 31 +bm 131 , and provides this path metric sm 31 +bm 131 to the ACS unit 330-13 corresponding to state 13.

[0415] In addition, adder ADD 31 obtains the path metric sm of the path reaching state 23 via state 31 by adding 31 the state metric sm231 Add them to obtain the path metric sm of the path reaching state 23 via state 31 31 +bm 231 and provide this path metric sm 31 +bm 231 to the ACS unit 330-23 (not shown) corresponding to state 23.

[0416] Adder ADD 31 By adding the state metric sm 31 and the branch metric bm of the branch from state 31 to state 33 331 to obtain the path metric sm of the path reaching state 33 via state 31 31 +bm 331 and provide this path metric sm 31 +bm 331 to the ACS unit 330-33 (not shown) corresponding to state 33.

[0417] The Viterbi decoder 320 has a function of performing branch metric calculation, and the branch metric bm obtained through this function p’pq is provided to the adder ADD pq .

[0418] Figure 32 is a diagram showing an operation example of the Viterbi decoder 320.

[0419] When assuming that the multi-code b t = 3 as the temporary decoding result at the latest time t, an example of state transition to state 31 will be given and the operation of the Viterbi decoder 320 in Figure 32 will be described Figure 31 .

[0420] When the quaternary code b t = 3 as the temporary decoding result at time t, the states at the immediately preceding time t - 1 when it is possible to transition to state 31 are states 10, 11, 12, and 13.

[0421] Figure 32 shows information about states 10, 11, 12, and 13 at time t - 1.

[0422] In Figure 32 , "temporary decoding result" represents the row of the multi-code b t = 3 as the temporary decoding result at the latest time t and the storage content of the path memory PM pq of the state pq (ACS unit 330-pq corresponding to state pq) at time t - 1, that is, the quaternary code sequence PM as the temporary decoding resultpq 。

[0423] Path memory PM pq Stores a time series of quaternary code sequences as temporary decoding results before time t-1.

[0424] Figure 32 The multi-code b as a temporary decoding result is shown on the right side of "temporary decoding result" t =3 and the quaternary code sequence PM pq Specific example of a row.

[0425] At Figure 32 For example, the specific example {310231...} of the temporary decoding result in state 10 indicates the quaternary code b as the temporary decoding result at time t t =3, the quaternary code b as the temporary decoding result at time t-1 t-1 =1, the quaternary code b as the temporary decoding result at time t-2 t-2 =0, the quaternary code b as the temporary decoding result at time t-3 t-3 =2, the quaternary code b as the temporary decoding result at time t-4 t-4 =3, the quaternary code b as the temporary decoding result at time t-5 t-5 =1,...

[0426] The path memory PM in state pq at time t pq Can store such a quaternary code, which is the temporary decoding result for dly moments from time t back to time t-(dly-1). dly represents the path memory length, that is, the number (maximum number) of quaternary codes that can be stored by the path memory PM pq And is, for example, M+N or greater.

[0427] At Figure 32 The "equalization reference address" is the address of the storage area that stores the equalization reference level r t (s i ,s j )+Δr t (b t ). The equalization reference level is obtained from the whitening reference level MR4(r t (s i ,s j )+Δr t (b t )-Σ[p len ×{r t-len (s i ,s j )+Δr t(b t-len )}])'s equalization reference level r t (s i , s j ) + Δr t (b t )(and r t-len (s i , s j ) + Δr t (b t-len )) from the storage unit.

[0428] As will be described in detail below, the equalization reference storage unit (which is the storage unit storing the equalization reference level r t (s i , s j ) + Δr t (b t )) has a storage area storing the equalization reference level r t (s i , s j ) + Δr t (b t ). The value of the equalization reference level is updated according to the initial value obtained by convolution calculation with the extended PR feature (convolution calculation with the impulse response of the extended PR).

[0429] The storage area of the equalization reference storage unit is used as the address at the stored value of the path memory PM pq . The path memory PM pq stores the quaternary code sequence corresponding to the path to a state.

[0430] PM pq (t1:t2) represents the quaternary code sequence of the quaternary codes bt1 and bt2, and the quaternary codes bt1 and bt2 are the temporary decoding results at times t1 and t2 stored in the path memory PM pq in the state pq.

[0431] For example, in the equalization reference storage unit, by using the quaternary code sequence {31023} as the equalization reference address, the equalization reference level r for branch metric calculation of the branch from state 10 to state 31 is read from the storage area addressed at this equalization reference address {31023} t (s i , s j ) + Δr t (b t ), where in this quaternary code sequence {31023}, the multi - code b as the temporary decoding result at the latest time t t= 3 is added to the quaternary code sequence PM that is the temporary decoding result stored in the path memory PM10 in the state 10 at time t-1 pq (t-1:t-(M-1)) = PM pq (t-1:t-(5-1)) = the head (the most significant unit) of {1023}.

[0432] In Figure 32 , the “Initial value” to the right of the “Equalization reference address” represents the equalization reference level r stored in the storage area of the equalization reference storage unit addressed by the equalization reference address t (s i ,s j ) + Δr t (b t )'s initial value. This equalization reference level r t (s i ,s j ) + Δr t (b t )'s initial value can be obtained by the convolution calculation of the extended PR feature and the NRZ multivalue sequence, and the NRZ multivalue is the NRZ expression of the quaternary code sequence used as the equalization reference address.

[0433] In Figure 32 , the “Whitening reference address” is the address of the storage area where the whitening reference level MR4 stored in the storage unit for storing the expression (9) for branch metric calculation is read. The whitening reference level MR4 is r t (s i ,s j ) + Δr t (b t ) - Σ[p len ×{r t-len (s i ,s j ) + Δr t (b t-len )}]).

[0434] As will be described in detail below, the whitening reference storage unit used as the storage unit for storing the whitening reference level MR4 has a storage area for storing the whitening reference level MR4, and the value of the whitening reference level MR4 is updated from the initial value obtained by the convolution calculation with the extended PR feature.

[0435] Similar to the equalization reference storage unit, the storage area of the whitening reference storage unit is addressed by the stored value of the path memory PM pq , and the path memory PM pq stores the quaternary code sequence corresponding to the path to a state.

[0436] For example, in the whitening reference storage unit, by using the quaternary code sequence {310231} as the whitening reference address, the whitening reference level MR4 for branch metric calculation of the branch from state 10 to state 31 is read from the storage area addressed at the whitening reference address {310231}. In the quaternary code sequence {310231}, the multicode b t = 3 that is the temporary decoding result at the latest time t is added to the quaternary code sequence PM pq (t - 1:t-(M + N - 1)) that is the temporary decoding result stored in the path memory PM10 of state 10 at time t - 1. pq (t - 1:t-(5 + 1 - 1)) = the head of {10231}.

[0437] In Figure 32 , the "initial value" on the right side of the "whitening reference address" indicates the initial value of the whitening reference level MR4 stored in the storage area of the whitening reference storage unit addressed by the whitening reference address. The initial value of the whitening reference level MR4 can use the equalization reference level r t (s i , s j ) + Δr t (b t ) to obtain.

[0438] In Figure 32 , the "branch metric" indicates the branch metrics bm 310 , bm 311 , bm 312 and bm 313 of the branches from states 10, 11, 12, and 13 to state 31.

[0439] For example, assume that the whitening signal z t at time t is 1.5 and the whitening reference level MR4 is the initial value.

[0440] As shown in expression (9), since the branch metric calculation is the calculation of the square of the difference between the whitening signal z t and the whitening reference level MR4, the branch metrics bm 310 , bm 311 , bm 312 and bm 313 of the branches can be obtained as follows.

[0441] bm 310 = λ t (s 10 , s 31 ) = (1.5 - (-1.445)) 2 = 8.673025

[0442] bm 311 = λ t (s 11 , s 31 ) = (1.5 - 0.505) 2 = 0.990025

[0443] bm 312 = λ t (s 12 , s 31 ) = (1.5 - 1.507) 2 = 4.9E - 05

[0444] bm 313 = λ t (s 13 , s 31 ) = (1.5 - 3.861) 2 = 5.574321

[0445] In Figure 32 , the "state metric" indicates the state metric sm of state pq stored in the state metric memory SM pq of state pq. In pq . In Figure 32 , the state metrics sm 10 , sm 11 , sm 12 and sm 13 are 2.1341, 4.6109, 0.0221, and 3.2319 respectively.

[0446] In Figure 32 , the "path metric" indicates the path metrics sm of the paths reaching state 31 via states 10, 11, 12, and 13 respectively 10 + bm 310 , sm 11 + bm 311 , sm 12 + bm 312 and sm 13 + bm 313 .

[0447] By adding the state metric sm pq of state pq and the branch metric bm p’pq of the branch from state pq to state p'p, the path metric of the path reaching state p'p via state pq can be obtained as follows.

[0448] The path metric of the path reaching state 31 via state 10

[0449] sm 10 + bm310 =2.13141+8.673025=10.807125

[0450] The path metric for the path from state 11 to state 31

[0451] sm 11 +bm 311 =4.6109+0.990025=5.600925

[0452] The path metric for the path from state 12 to state 31

[0453] sm 12 +bm 312 =0.0221+4.9E-05=0.022149

[0454] The path metric for the path from state 13 to state 31

[0455] sm 13 +bm 313 =3.2319+5.574321=8.806221

[0456] As described, the Viterbi decoder 320 obtains the path metrics sm in adders ADD10, ADD11, ADD12, and ADD13 in states 10, 11, 12, and 13. 10 +bm 310 、sm 11 +bm 311 、sm 12 +bm 312 and sm 13 +bm 313 Each one of them.

[0457] Path metric sm 10 +bm 310 、sm 11 +bm 311 、sm 12 +bm 312 , and sm 13 +bm 313 The adders ADD10, ADD11, ADD12, and ADD13 in states 10, 11, 12, and 13 are supplied to the selector SEL in state 31. 31 .

[0458] Select the path metric sm 12 +bm 312 = 0.022149, i.e., the selector SEL provided to state 31 31 The path metric sm 10 +bm310 , sm 11 + bm 311 , sm 12 + bm 312 , and sm 13 + bm 313 among them, and provides it to the state metric memory SM31.

[0459] The state metric memory SM31 of state 31 receives the minimum path metric from the selector SEL 31 sm 12 + bm 312 = 0.022149 and stores it as the state metric sm of state 31 31 .

[0460] In addition, the path memory PM31 of state 31 is updated by adding the multi - code, which is the temporary decoding result at the latest time t, to the sequence of dly - 1 quaternary codes. The sequence of dly - 1 quaternary codes is stored in the path memory PM12 of state 12 and is the temporary decoding result that immediately precedes reaching state 31 in the path where the minimum path metric sm 31 selected by the selector SEL 12 + bm 312 = 0.022149 is passed through.

[0461] That is, the path memory PM31 of state 31 is updated to the sequence of dly quaternary codes obtained by adding the multi - code b t = 3, which is the temporary decoding result at the latest time t, to the head of the sequence of quaternary codes PM12(t - 1:t-(dly - 1)), which is the temporary decoding result stored in the path memory PM12 of state 12.

[0462] Figure 33 is a diagram further showing an operation example of the Viterbi decoder 320.

[0463] Figure 33 shows any aspect of the path (branch) reaching state 31 in the case where the quaternary code b t = 3 is the temporary decoding result at time t.

[0464] In the case where the quaternary code b t = 3 is the temporary decoding result at time t, the path reaching state 31 passes through any one of states 10, 11, 12, and 13.

[0465] In Figure 33 , for states 10, 11, 12, and 13, the state metric sm described in Figure 32 is shown.10 , sm 11 , sm 12 , and sm 13 and the path metric sm of the path reaching state 31 10 +bm 310 , sm 11 +bm 311 , sm 12 +bm 312 , and sm 13 +bm 313 .

[0466] In addition, as Figure 33 shown, as shown by the solid line in the figure, the path metric sm 10 +bm 310 , sm 11 +bm 311 , sm 12 +bm 312 , and sm 13 +bm 313 among them, the path metric sm as the minimum path metric 12 +bm 312 = 0.022149, and the path metric sm 12 +bm 312 = 0.022149 becomes the state metric sm of state 31 31 .

[0467] In Figure 32 , the quaternary code sequence as the temporary decoding result stored in the path memory PM13 of state 13 at time t - 1 is {13120...}.

[0468] In the case where the quaternary code b t = 3 of the temporary decoding result at time t, when selecting the path reaching state 31 via state 13 at time t - 1 (selecting the path metric sm of the path reaching state 31 13 +bm 313 as the state metric sm of state 31 31 ), the corresponding temporary decoding result of this path is the quaternary code sequence {313120...}, in which the quaternary code b t = 3 of the temporary decoding result at time t is added to the head of the quaternary code sequence {13120...} as the temporary decoding result stored in the path memory PM13 of state 13.

[0469] For the head 3131 of the quaternary code sequence {313120...}, RMTR = 2 is set.

[0470] In this case, as Figure 30 described, since RMTR is limited to 1 or less, the quaternary code sequence 3131 with RMTR = 2 cannot be taken as the decoding result of Viterbi decoding.

[0471] Therefore, the branch from state 13 to state 31 can be restricted, as Figure 33 indicated by the × in

[0472] When the branch from state 13 to state 31 is restricted, in addition to the path metrics sm 10 +bm 310 、sm 11 +bm 311 、sm 12 +bm 312 、and sm 13 +bm 313 among the path metrics of the paths including the restricted branch sm 13 +bm 313 outside, the selector SEL 31 of state 31 selects the path metric sm 12 +bm 312 = 0.022149, which is the minimum path metric among the path metrics sm 10 +bm 310 、sm 11 +bm 311 、and sm 12 +bm 312 among them.

[0473] As Figure 30 described, the trellis states and branches (state transitions) can be restricted by the coding rules (coding rules of the multicode) encoded into the multicode (e.g., the minimum travel length d or RMTR) to perform Viterbi decoding.

[0474] Here, the restriction on a specific state pq of the trellis includes not providing the ACS unit 330-pq corresponding to the state pq and not using the ACS unit 330-pq even though the ACS unit 330-pq is provided in the Viterbi decoder 320. Similarly, the restriction on a branch includes not providing the connection line corresponding to the branch among the connection lines between the ACS units 330-pq in the Viterbi decoder 320, and not selecting the path metric provided from the connection line even though the connection line is provided.

[0475] The restrictions on the states pq of the grid and branches include: Although the ACS unit 330-pq is provided, the ACS unit 330-pq corresponding to the state pq is not used; and although the connection lines between the ACS units 330-pq corresponding to the branches are provided, the path metrics provided from the connection lines corresponding to the restricted branches are not selected. Thus, when the coding rule is changed, countermeasures can be easily taken by the restrictions on the states and branches of the changed coding rule, without having to manufacture the Viterbi decoder 320 again.

[0476] Figure 34 To show the path memory PM of the ACS unit 330-pq pq Diagram of an exemplary configuration.

[0477] Path memory PM pq Is configured with a memory capable of storing dly quaternary codes.

[0478] In Figure 34 The path memory PM pq Stores the quaternary code b as the temporary decoding result at the latest time t at the left end t , and sequentially stores the quaternary codes b as the temporary decoding results at the past times t-1, t-2,..., and t-(dly-1) toward the right t-1 , b t-2 ,..., and b t-(dly-1) .

[0479] As Figure 32 Described, the quaternary code sequence used as the temporary decoding result stored in the path memory PM pg Is used as the address when reading the equalization reference level r for branch metric calculation from the equalization reference storage unit and the whitening reference storage unit t (s i , s j ) + Δr t (b t ) and the whitening reference level MR4 of expression (9).

[0480] That is, the quaternary code sequence PM from the beginning to the Mth of the temporary decoding result stored in the path memory PM pq (t:t-(M-1)) = {b pq , b t ,..., b t-1} is used as the address of the equalization reference level r t-(M-1) (s t , s i ) + Δr j ) + Δr t (b t ).

[0481] The quaternary code sequence PM of the temporary decoding result stored in the path memory PM from the beginning to the (M + N)-th pq is used as the address of the whitening reference level MR4. pq (t: t - (M + N - 1)) = {b t , b t-1 ,..., b t-(M+N-1)}

[0482] Figure 35 is a diagram showing an exemplary configuration of an equalization reference storage unit storing the equalization reference level r t (s i , s j ) + Δr t (b t ).

[0483] The equalization reference storage unit 350 is provided, for example, in the detection unit 16 (see Figure 25 ).

[0484] Here, in the multi-input adaptive equalization unit 14, the tap coefficient f clen (C len ) of the signal channel c (adaptive equalizer 20 + c) with length len is updated based on the least mean square (LMS) algorithm such that the mean square error of the equalization error e’ t obtained by the equalization error calculation unit 18 is minimized.

[0485] The equalization error calculation unit 18 calculates the equalization error e’ t , which is the difference between the equalization reference level r t (s i , s j ) + Δr t (b t ) and the equalization signal y’ t output by the multi-input adaptive equalization unit 14 and provided at the timing adjusted by the delay unit 17. Then, the equalization error calculation unit 18 supplies the equalization error e’ t to the adaptive equalizers 21 to 24 of the multi-input adaptive equalization unit 14 to control the tap coefficient f clen .

[0486] The equalization reference level r t (s i , s j ) + Δr t (b t ) uses the quaternary code sequence PM pq (t: t - (M - 1)) = {b t , b t-1 ,..., b t-(M-1)}Address and read from the equalization reference storage unit 350, and the quaternary code sequence is stored in the path memory PM pq as the temporary decoding result therein.

[0487] The equalization error e’ t can be output from the multi-input adaptive equalization unit 14, and can be used as the equalization reference level r through the expression (10) t-d (s i , s j ) + Δr t (b t-d ) and the difference between the equalization signal y’ t-d is obtained. The timing of the equalization signal y’ t-d is adjusted by delaying the time d in the delay unit 17.

[0488] [Mathematical formula 10]

[0489]

[0490] [r + Δr](b t-d ) represents the equalization reference level r addressed by the time series of multiple rows of the M temporary decoding results before the moment t - d t-d (s i , s j ) + Δr t (b t-d ) where the quaternary code b t-d as the temporary decoding result in the equalization reference storage unit 350 in this time series is the header.

[0491] In this embodiment, the equalization reference level [r + Δr](b t ) stored in the equalization reference storage unit 350 is periodically updated according to the gradient method of the expression (11).

[0492] [Mathematical formula 11]

[0493]

[0494] [r + Δr] t (b t ) represents the equalization reference level [r + Δr](b t ) at a specific moment t. [r + Δr] t+1 (b t ) represents the equalization reference level [r + Δr](b t ) at the next moment t + 1, that is, the updated equalization reference level [r + Δr](b t ).

[0495] γ represents an update coefficient for adjusting the update amount of the equalization reference level [r + Δr](b t ) during update.

[0496] The equalization reference storage unit 350 updates the equalization reference level [r + Δr](b t ) according to the equalization error e', t such that the mean square error of the equalization error e' t is minimized by Equation (11).

[0497] The equalization reference storage unit 350 includes ML^M = 4^5 storage areas 51-(v), delay units 52-(v), adders 53-(v), switches 54-(v), and one switch 55. (v) represents an ML = 4-ary system with M = 5 digits, that is, a quaternary code sequence of 5 cells. Therefore, here, as an ML = 4-ary system, (v) takes values (integer values) in the range from 00000 to 33333.

[0498] The storage area 51-(v) is a storage area specified using the quaternary code sequence (v) of 5 cells as an address. The storage area 51-(v) stores the equalization reference level [r + Δr](b t ) updated by Expression (11).

[0499] The delay unit 52-(v) delays the equalization reference level [r + Δr](b t ) stored in the storage area 51-(v) by one time instance, and provides the delayed equalization reference level [r + Δr](b t ) to the adder 53(v).

[0500] The adder 53-(v) adds the equalization reference level [r + Δr](b t ) provided from the delay unit 52-(v) to -γ×2×e' t obtained from the equalization error e' provided from the equalization error calculation unit 18. The adder 53-(v) uses the added value [r + Δr](b t ) - γ×2×e' t obtained by addition as the updated equalization reference level [r + Δr](b t ) and provides it to the switch 54-(v). t

[0501] When the quaternary code sequence PM pq of M = 5 cells in the path memory PM pq stored as a temporary decoding result is PM t-d (t - d:t - (M - 1) - d) = {b t-1-d , b t-(M-1)-d}} = {b t-d , b t-1-d , b t-2-d , b t-3-d , b t-(5-1)-d}, when it is (v), switch 54-(v) conducts. When switch 54-(v) conducts, the updated equalization reference level [r + Δr](b t ) provided by adder 53-(v) is provided to storage area 51-(v) and stored in a rewritten form. Thus, the equalization reference level [r + Δr](b t ) stored in storage area 51-(v) is updated.

[0502] When the quaternary code sequence PM pq of M = 5 cells as the temporary decoding result stored in path memory PM pq (t:t-(M - 1)) = {b t , b t-1 ,..., b t-(M-1)}} = {b t , b t-1 , b t-2 , b t-3 , b t-(5-1)} is (v), switch 55 selects storage area 51-(v) and reads the equalization reference level [r + Δr](b t ) stored in storage area 51-(v).

[0503] Therefore, the temporary decoding result stored in path memory PM pq is used as the address for reading the equalization reference level [r + Δr](b t ) stored in storage area 51-(v).

[0504] In switch 55, for example, the equalization reference level [r + Δr](b t ) read from storage area 51-(v) is used to calculate the equalization error e' t or the whitening reference level MR4.

[0505] In the equalization reference storage unit 350 with the above configuration, the initial value of the equalization reference level [r + Δr](b t ) is set and stored in storage area 51-(v).

[0506] The initial value of the equalization reference level [r + Δr](b t ) stored in storage area 51-(v) can be obtained from the quaternary code sequence {b t , b t-1 ,..., b t-(M-1)The sequence {a t , a t-1 ,..., a t-(M-1)} of NRZ multiple values of the NRZ expression of} is convolved with the PR coefficients {c 0 , c 1 ,..., c M-1} of the extended PR to calculate a t × c 0 + a t-1 × c 1 +... + a t-(M-1) × c M-1 to obtain.

[0507] In this case, here, the PR coefficient c m of the extended PR is {c 0 , c 1 , c 2 , c 3 , c 4} = {1, 2, 1, 0.2, 0.1}, as Figure 30 described.

[0508] When the quaternary code sequence {b t , b t-1 ,..., b t-(M-1)} = {b t , b t-1 , b t-2 , b t-3 , b t-(5-1)} indicated by (v) is, for example, {3, 1, 0, 2, 3}, the sequence {a t , a t-1 , a t-2 , a t-3 , a t-(5-1)} of NRZ multiple values corresponding to {3, 1, 0, 2, 3} is {3, -1, -3, 1, 3}.

[0509] In this case, the convolution value obtained by convolving the NRZ multiple value sequence {3, -1, -3, 1, 3} corresponding to the quaternary code sequence {3, 1, 0, 2, 3} indicated by (v) with the extended PR feature {1, 2, 1, 0.2, 0.1} is 3×1 + (-1)×2 + (-3)×1 + 1×0.2 + 3×0.1 = -1.5. This convolution value -1.5 is stored as the initial value of the equalization reference level [r + Δr](b t ) in the storage area 51 - 31023.

[0510] The equalization reference level [r + Δr](b t ) stored in the storage area 51 - (v) is cyclically updated from the initial value stored in this way.

[0511] That is, the equalization reference level [r + Δr](b stored in the storage area 51-(v) and delayed by one moment in the delay unit 52-(v) t ) is supplied to the adder 53-(v).

[0512] The adder 53-(v) adds the equalization reference level [r + Δr](b supplied from the delay unit 52-(v) t ) to the equalization error e' supplied from the equalization error calculation unit 18 t to obtain -γ × 2 × e'. t The adder 53-(v) adds the added value [r + Δr](11) obtained by the addition t+1 (b t ) = [r + Δr] t (b t ) - γ × 2 × e'. t as the updated equalization reference level [r + Δr](b t ) and supplies it to the switch 54-(v).

[0513] On the other hand, in the case of the quaternary code sequence PM pq of M = 5 cells as the temporary decoding result stored in the path memory PM pq (t - d:t - (M - 1) - d) = {b t-d , b t-1-d ,..., b t-(M-1)-d} = {b t-d , b t-1-d , b t-2-d , b t-3-d , bt - (5 - 1) - d}, when it is the timing of (v), the switch 54-(v) is turned on.

[0514] When the switch 54-(v) is turned on, the updated equalization reference level [r + Δr] t+1 (b t ) supplied from the adder 53-(v) is supplied to the storage area 51-(v) and stored in a rewritten form. Thus, the equalization reference level [r + Δr](b of the storage area 51-(v) t ) is updated to the equalization reference level [r + Δr] t+1 (b t ).

[0515] In the case of the quaternary code sequence PM pq of M = 5 cells as the temporary decoding result stored in the path memory PM pq (t:t - (M - 1)) = {b t , b t-1,...,b t-(M-1)} = {b t , b t-1 , bt-2, bt-3, bt-(5-1)} is the timing of (v), the switch 55 selects the storage area 51-(v) and reads the equalization reference level [r + Δr] stored in the storage area 51-(v) t (b t ).

[0516] Therefore, the temporary decoding result {b pq} stored in the path memory PM t , b t-1 ,..., b t-(M-1)} is set as the address, and the equalization reference level [r + Δr] is read from the storage area 51-(v) specified by the address {b t , b t-1 ,..., b t-(M-1)} t (b t ).

[0517] Then, for example, the equalization reference level [r + Δr] read from the storage area 51-(v) t (b t ) is used to calculate the equalization error e’ t or the whitening reference level MR4

[0518] Here, when the branch from state si to state sj is restricted by the coding rule, an access is generated in the storage area 51-(v) addressed by the quaternary code sequence including M = 5 cells of the quaternary code sequence that is the temporary decoding result corresponding to the branch, that is, the storage area where the reading of the equalization reference level [r + Δr] t (b t ) etc. is restricted (not executed)

[0519] The whitening reference level MR4 calculated using the equalization reference level [r + Δr] read from the storage area 51-(v) t (b t ) is used for the branch metric calculation of expression (9). The equalization error e’ t is used to update the L tap coefficients f of the signal channel c (adaptive equalizer 20 + c) in the multi-input adaptive equalization unit 14 clen (C len ) and update the N tap coefficients p of the noise predictor 15 len .

[0520] Considering that the equalized signal y’ t is represented in expression (2), with respect to the tap coefficient f clenBy taking the partial derivative of the square (variance) of the equalization error e' expressed in Expression (10) t The partial derivative value obtained is expressed in Expression (12).

[0521] [Mathematical Expression 12]

[0522]

[0523] In the multi-input adaptive equalization unit 14, the tap coefficients f of the signal channel c (adaptive equalizer 20 + c) are updated by Expression (13) using the partial derivative value of Expression (12) clen (C len )

[0524] [Mathematical Expression 13]

[0525] f clen (t + l) = f clen (t) - α·2·e' t ·X C(t-len ) ...(13)

[0527] F clen F(t) represents the tap coefficient f at time t clen , that is, the tap coefficient f before update clen , and f clen (t + 1) represents the tap coefficient f at time t + 1 clen , that is, the tap coefficient f after update clen .

[0528] α represents an update coefficient for showing the update amount of the tap coefficient f clen during update

[0529] In Expression (13), the tap coefficient f clen is updated so that the squared error of the equalization error e' t is minimized according to the equalization error e' t .

[0530] Figure 36 is a diagram showing an exemplary configuration of the whitening coefficient update unit 19

[0531] As with the noise predictor 15 shown in Figure 29 , Figure 25 the whitening coefficient update unit 19 in

[0532] Since the delay unit 371-l, the multiplier 372-l, and the adder 373 are similar to the delay unit 41-l, the multiplier 42-l, and the adder 43 in Figure 29 , their descriptions will be omitted.

[0533] In Figure 29 , in the noise predictor 15, the input of the delay unit 41-1 is the equalization signal y’ provided by the multi-input adaptive equalization unit 14 t . However, in the whitening coefficient update unit 19, the input of the delay unit 371-1 is the equalization error e’ provided by the equalization error calculation unit 18 t .

[0534] In Figure 29 , in the noise predictor 15, the output of the adder 43 is the whitened signal z t . In the whitening coefficient update unit 19, the output of the adder 373 is the noise w equivalent to the expression (2) t of the signal w’ t .

[0535] In Figure 36 , in the whitening coefficient update unit 19, the signal w’ is obtained by using the equalization error e’ through the expression (14) t . t .

[0536] [Mathematical formula 14]

[0537]

[0538] The signal w’ t is the error between the equalization error e’ t and the whitened equalization error e’ obtained by whitening the equalization error e’ t , and is also referred to as the whitening error w’ t . t .

[0539] For the tap coefficient p len , the partial differential value obtained by performing the partial differential of the square (squared error) of the whitening error w’ t represented in the expression (14) is represented by the expression (15).

[0540] [Mathematical formula 15]

[0541]

[0542] In the whitening coefficient update unit 19, the tap coefficient p is updated through the expression (16) using the partial differential value of the expression (15) len .

[0543] [Mathematical formula 16]

[0544] p len (t + 1)= p len (t)+β·2·w’ t ·e t-len ...(16)

[0546] p len (t) represents the tap coefficient p at time t len , that is, the tap coefficient p before update len , p len (t + 1) represents the tap coefficient p at time t + 1 len , that is, the tap coefficient p after update len .

[0547] β represents the update coefficient for showing the update amount of the tap coefficient p during update len of the tap coefficient p

[0548] In expression (16), the tap coefficient p len is updated so that the squared error of the whitening error w’ t is minimized according to the whitening error w’ t of the tap coefficient p

[0549] As described above, the tap coefficient p updated by the whitening coefficient update unit 19 len is provided to Figure 29 the noise predictor 15 in t and set. Therefore, in the noise predictor 15, the noise w t included in the equalized signal y’ in expression (2)

[0550] The tap coefficient p updated by the whitening coefficient update unit 19 len is not only provided to the noise predictor 15, but also provided to the detection unit 16. In the detection unit 16, the tap coefficient p len is used for the branch metric calculation of expression (9), more specifically, for updating the whitening reference level MR4 for branch metric calculation

[0551] Therefore, in the detection unit 16, Viterbi decoding suitable for the state where the noise predictor 15 is set in the previous stage of the detection unit 16 is realized, that is, Viterbi decoding introducing NPML is realized

[0552] Figure 37 is a diagram showing an exemplary configuration of the whitening reference storage unit for storing the whitening reference level MR4

[0553] The whitening reference storage unit 390 is provided, for example, in the detection unit 16 (see Figure 25 ).

[0554] In the branch metric calculation of Expression (9), when obtaining the whitening reference level MR4, the tap coefficient p len is used to perform a convolution calculation Σ[p t-len ×{r i (s j , s t ) + Δr t-len (b len )}] with the equalization reference level r t-len (s i , s j ) + Δr t (b t-len ) to perform a large number of multiply-accumulate operations.

[0555] When the detection unit 16 is configured with a digital circuit and performs Viterbi decoding, the digital circuit must operate at high speed. In such a high-speed operation, it is difficult to complete the calculation of the whitening reference level MR4 within one clock.

[0556] Therefore, the whitening reference storage unit 390 for storing the whitening reference level MR4 is provided in the detection unit 16, and the whitening reference level MR4 can be appropriately calculated and stored in the whitening reference storage unit 390.

[0557] In this case, the whitening reference level MR4 is addressed using the quaternary code sequence PM pq (t:t-(M+N-1)) = {b t , b t-1 ,..., b t-(M+N-1)} (which is the temporary decoding result stored in the path memory PM pq ) and the whitening reference level MR4 is read from the whitening reference storage unit 390. Therefore, the whitening reference level MR4 required for branch metric calculation can be obtained quickly.

[0558] The whitening reference storage unit 390 includes ML^(M+N) = 4^(5+1) storage areas 56-(u), switches 57-(u), and one switch 58. (u) represents an ML = 4-ary of M+N = 5+1 = 6 bits, that is, a quaternary code sequence of 6 cells. Therefore, here, as the ML = 4-ary, (u) takes values in the range of 000000 to 333333.

[0559] The storage area 56-(u) is a storage area specified using the quaternary code sequence (u) of 6 cells as an address. The storage area 56-(u) is obtained by the expression on the right side of Expression (9), r t (si , s j ) + Δr t (b t ) - Σ{p len × {r t-len (s i , s j ) + Δr t (b t-len )}} stores the tap coefficients p of the noise predictor 15 len updated whitening reference level MR4.

[0560] Hereinafter, as in the case of Figure 35 , the equalization reference level r t (s i , s j ) + Δr t (b t ) is expressed as the variable [r + Δr](b t ), which has the vector bt (the quaternary code bt as the temporary decoding result is the row of the time series of the M temporary decoding results before time t of the header) as the independent variable.

[0561] In this case, the whitening reference level MR4 is expressed as the expression MR4 = [r + Δr](b t ) - Σ{p len × [r + Δr](b t-len )}.

[0562] In an embodiment, as described in Figure 30 , since the number of taps N of the noise predictor 15 = 1, the whitening reference level MR4 is expressed as the expression MR4 = [r + Δr](b t ) - Σ{p len × [r + Δr](b t-len )} = [r + Δr](b t ) - p 1 × [r + Δr](b t-1 ).

[0563] Here, the detection unit 16 uses the equalization reference level [r + Δr](b t-d ) stored in the equalization reference storage unit 350 to obtain the whitening reference level MR4 = [r + Δr](b t-d ) - Σ{p len × [r + Δr](b t-len-d )} = [r + Δr](b t-d ) - p 1 × [r + Δr](b t-1-d ) (see Figure 35 ).

[0564] The switch 57-(u) is provided with the whitening reference level MR4 = [r+Δr](b obtained by the detection unit 16 as described above t-d ) - Σ{p len ×[r+Δr](b t-len-d )} = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d ).

[0565] When the quaternary code sequence PM of M+N = 5+1 = 6 cells, which is the temporary decoding result stored in the path memory PM pq (t-d:t-(M+N-1)-d) = {b pq , b t-d ,..., b t-1-d} = {b t-(M+N-1)-d , b t-d , b t-1-d , b t-2-d , b t-3-d , b t-4-d , b t-(5+1-1)-d} is (u), the switch 57-(u) is turned on. When the switch 57-(u) is turned on, the white reference level MR4 = [r+Δr](b t-d ) - Σ{p len ×[r+Δr](b t-len-d )} = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d ) provided by the detection unit 16 is supplied to the storage area 56-(u) and stored in a rewritten form. Thus, the whitening reference level MR4 stored in the storage area 56-(u) is updated.

[0566] When the quaternary code sequence PM of M+N = 5+1 = 6 cells, which is the temporary decoding result stored in the path memory PM pq (t:t-(M+N-1)) = {b pq , b t ,..., b t-1} = {b t-(M+N-1) , b t , b t-1 , b t-2 , b t-3 , b t-4 , b t-(5+1-1)} is (u), the switch 58 selects the storage area 56-(u) and reads the whitening reference level MR4 stored in the storage area 56-(u).

[0567] Therefore, the temporary decoding result stored in the path memory PMpq is used as the address for reading the whitening reference level MR4 stored in the storage area 56-(u).

[0568] In the switch 58, the whitening reference level MR4 read from the storage area 56-(u) is used for branch metric calculation in, for example, Expression (9).

[0569] In the whitening reference storage unit 390 having the above configuration, the initial value of the whitening reference level MR4 is set and stored in the storage area 56-(u).

[0570] The initial value of the whitening reference level MR4 of the whitening reference storage unit 390 is immediately after the initial value setting of the equalization reference level [r+Δr](b t ) in the equalization reference storage unit 350, and is set using the initial value of the equalization reference level [r+Δr](b t ) stored in the equalization reference storage unit 350.

[0571] According to the expression MR4 = [r+Δr](b t ) - Σ{p len ×[r+Δr](b t-len )}, the initial value of the whitening reference level MR4 stored in the storage area 56-(u) can be obtained using the following initial values:

[0572] The initial value of the equalization reference level [r+Δr](b t ) having the M-bit digital quaternary code sequence {b t ,b t-1 ,...,b t-(M+N-1)} starting from the head of the quaternary code sequence represented by (u) as the independent variable; t ,b t-1 ,...,b t-(M-1)} as the independent variable;

[0573] The initial value of the equalization reference level [r+Δr](b t-1 ) having the M-bit digital quaternary code sequence {b t ,b t-1 ,...,b t-(M+N-1)} starting from the 1+1 = 2nd bit of the head of the quaternary code sequence represented by (u) as the independent variable; t-1 ,b t-1-1 ,...,b t-1-(M-1)} as the independent variable;

[0574] The initial value of the equalization reference level [r+Δr](b t-2) initial value, the equalization reference level has a quaternary code sequence {b represented by (u) t , b t-1 ,..., b t-(M+N-1)} starting from the (2 + 1) = 3rd bit of the header of the M - bit digital quaternary code sequence {b t-2 , b t-2-1 ,..., b t-2-(M-1)} as the independent variable;

[0575] ... the initial value of the equalization reference level [r + Δr](b t-N ) has a quaternary code sequence {b represented by (u) t , b t-1 ,..., b t-(M+N-1)} starting from the (N + 1)th bit of the header of the M - bit digital quaternary code sequence {b t-N , b t-N-1 ,..., b t-N-(M-1)} as the independent variable.

[0576] Therefore, since the initial value of the whitening reference level MR4 can be obtained using the initial value of the equalization reference level [r + Δr](b t ), the initial value can be obtained by the convolution calculation of the extended PR feature and the sequence of NRZ multivalues (i.e., the NRZ expression of the quaternary code sequence used as the address of the equalization reference level [r + Δr](b t )) as in the equalization reference level [r + Δr](b Figure 35 ) described in t .

[0577] In this embodiment, since N = 1, the initial value of the whitening reference level MR4 stored in the storage area 56-(u) can be obtained according to the expression MR4 = [r + Δr](b t ) - p 1 ×[r + Δr](b t-1 ).

[0578] In addition, in the embodiment, the PR coefficient c m of the extended PR is {c 0 , c 1 , c 2 , c 3 , c 4} = {1, 2, 1, 0.2, 0.1}, as described in Figure 30 .

[0579] When the quaternary code sequence {b t , b t-1 ,..., b t-(M+N-1)} represented by (u) = {bt , b t-1 , b t-2 , b t-3 , b t-4 , b t-(5+1-1)}, when it is, for example, {3, 1, 2, 1, 0, 1}, the expression MR4 = [r + Δr](b t ) - p 1 × [r + Δr](b t-1 ) of the vector b t is the quaternary code sequence {31210} of M = 5 - digit numbers starting from the head of {3, 1, 2, 1, 0, 1}. The expression MR4 = [r + Δr](b t ) - p 1 × [r + Δr](b t-1 ) of the vector b t-1 is the quaternary code sequence {12101} of M = 5 - digit numbers starting from the 1 + 1 = 2nd bit from the head of {3, 1, 2, 1, 0, 1}.

[0580] Thus, the initial value of the whitening reference level MR4 stored in the storage area 56 - (312101) is obtained according to the expression MR4 = [r + Δr](31210) 1 × [r + Δr](12101).

[0581] When the sequence of NRZ multi - values {a t , a t-1 , a t-2 , a t-3 , a t-(5-1)} corresponding to the quaternary code sequence {3, 1, 2, 1, 0, 1} indicated by (u) is {3, - 1, 1, - 1, - 3, - 1}.

[0582] In this case, the initial value of the equalization reference level [r + Δr](31210) is the convolution value 3×1+( - 1)×2 + 1×1+( - 1)×0.2+( - 3)×0.1 = 1.5 obtained by convolving the sequence of NRZ multi - values {3, - 1, 1, - 1, - 3} of M = 5 starting from the head of the sequence of NRZ multi - values {a t , a t-1 , a t-2 , a t-3 , a t-(5-1)} = {3, - 1, 1, - 1, - 3, - 1} with the extended PR characteristic {1, 2, 1, 0.2, 0.1}. The sequence of NRZ multi - values {a t , a t-1 , a t-2 , a t-3 , a t-(5-1)}{corresponding to the quaternary code sequence {3, 1, 2, 1, 0, 1} indicated by (u).

[0583] The initial value of the equalization reference level [r + Δr](12101) is obtained by convolving the sequence of NRZ multivalues {-1, 1, -1, -3, -1} starting from the 2 = 1 + 1 bit of the head of the sequence {a t , a t-1 , a t-2 , a t-3 , a t-(5-1)} = {3, -1, 1, -1, -3, -1} with the extended PR feature {1, 2, 1, 0.2, 0.1}, and the convolution value (-1)×1 + 1×2 + (-1)×1 + (-3)×0.2 + (-1)×0.1 = -0.7. The sequence of NRZ multivalues {a t , a t-1 , a t-2 , a t-3 , a t-(5-1)}{corresponds to the quaternary code sequence {3, 1, 2, 1, 0, 1} indicated by (u).

[0584] Immediately after setting the initial value, the detection unit 16 reads the initial value 1.5 of the equalization reference level [r + Δr](31210) stored in the storage area 51-(31210) addressed by (v) = (31210) from the equalization reference storage unit 350.

[0585] In addition, immediately after setting the initial value, the detection unit 16 reads the initial value -0.7 of the equalization reference level [r + Δr](12101) stored in the storage area 51-(12101) addressed by (v) = (12101) from the equalization reference storage unit 350.

[0586] The detection unit 16 obtains the initial value of the whitening reference level MR4 stored in the storage area 56-(312101) according to the expression MR4 = [r + Δr](31210) - p 1 ×[r + Δr](12101) = 1.5 - p 1 ×(-0.7).

[0587] For example, when p1 = 0.01, the initial value of the whitening reference level MR4 stored in the storage area 56-(312101) is [r + Δr](31210) - p 1 ×[r + Δr](12101) = 1.5 - 0.01×(-0.7) = 1.507.

[0588] The value 1.507 is stored as the initial value of the whitening reference level MR4 in the storage area 56-(312101).

[0589] The whitening reference level MR4 stored in the storage area 56-(u) is appropriately updated from the initial value stored as described above.

[0590] That is, for example, assume that b t-d = 3 is the multi - code b t-d (which is the temporary decoding result at time t - d), and the path including the branch from state 12 to state 31 is selected as the path with the minimum path metric.

[0591] In this case, in the quaternary code sequence PM pq (t - d:t-(M + N - 1)-d) = {b t-d = 3,b t-1-d ,...,b t-(M+N-1)-d} = {b t-d = 3,b t-1-d ,b t-2-d ,b t-3-d ,b t-4-d ,b t-(5+1-1)-d} which is the timing of (u), the switch 57-(u) is turned on.

[0592] For example, here, when {b t-d = 3,b t-1-d ,b t-2-d ,b t-3-d ,b t-4-d ,b t-(5+1-1)-d} = {3,1,2,1,0,1}, the switch 57-(312101) is turned on.

[0593] On the other hand, the detection unit 16 uses the quaternary code sequence {b t-d = 3,b t-1-d ,b t-2-d ,b t-3-d ,b t-4-d ,b t-(5+1-1)-d} = {3,1,2,1,0,1} starting from the first M = 5 - digit quaternary code sequence {31210} as the address to read the whitening reference level [r + Δr](31210) stored in the storage area 51-(31210) of the equalization reference storage unit 350.

[0594] In addition, the detection unit 16 uses the quaternary code sequence {b t-d = 3,bt-1-d ,b t-2-d ,b t-3-d ,b t-4-d ,b t-(5+1-1)-d}, taking the quaternary code sequence {12101} of M = 5 digits starting from the second digit of the head of {3, 1, 2, 1, 0, 1} as the address, reads the whitening reference level [r+Δr](12101) stored in the storage area 51-(12101) of the equalization reference storage unit 350.

[0595] The detection unit 16 obtains the updated whitening reference level MR4 according to the expression MR4 = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d ) = [r+Δr](31210) - 0.01×[r+Δr](12101) and provides the updated whitening reference level MR4 to the switch 57-(u).

[0596] When the switch 57-(u) is turned on, the updated white reference level MR4 = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d ) is provided to the storage area 56-(u) and stored in a rewritten form. Thus, the whitening reference level MR4 stored in the storage area 56-(u) is updated to the updated whitening reference level MR4 = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d ).

[0597] In this case, here, in the detection unit 16, according to the expression MR4 = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d ) = [r+Δr](31210) - 0.01×[r+Δr](12101), the updated whitening reference level MR4 is obtained and provided to the switch 57-(u).

[0598] Among the switches 57-(000000) to (333333), the switch 57-(312101) is turned on. Therefore, the updated whitening reference level MR4 = [r+Δr](b t-d ) - p 1 ×[r+Δr](b t-1-d) = [r + Δr](31210) - 0.01 × [r + Δr](12101) is provided from the detection unit 16 via the already-conducted switch 57-(312101) to the storage area 56-(312101).

[0599] In the storage area 56-(312101), the updated whitening reference level MR4 = [r + Δr](b t-d ) - p 1 × [r + Δr](b t-1-d ) = [r + Δr](31210) - 0.01 × [r + Δr](12101) is stored.

[0600] In the quaternary code sequence PM pq of M + N = 5 + 1 = 6 cells that is the temporary decoding result stored in the path memory PM pq (t:t-(M + N - 1)) = {b t , b t-1 ,..., b t-(M+N-1)} = {b t , b t-1 , b t-2 , b t-3 , b t-4 , b t-(5+1-1)} is the timing of (u), the switch 58 selects the storage area 56-(u), and the whitening reference level MR4 stored in the storage area 56-(u) is read.

[0601] Therefore, the temporary decoding result {b pq , b t ,..., b t-1} stored in the path memory PM t-(M+N-1) is set as the address, and the whitening reference level MR4 is read from the storage area 56-(u) specified by the address {b t , b t-1 ,..., b t-(M+N-1)}.

[0602] The whitening reference level MR4 read from the storage area 56-(u) is used for the branch metric calculation of Expression (9).

[0603] As described above, the quaternary code sequence that is the temporary decoding result stored in the path memory PM pq is used as the address to specify the storage area 56-(u) of the whitening reference storage unit 390, the whitening reference level MR4 stored in the storage area 56-(u) is updated and read, and the whitening reference level MR4 is used to perform the branch metric calculation.

[0604] Accordingly, the branch metric calculation can be performed within one clock cycle.

[0605] The actual whitening reference level MR4 is calculated using, for example, the pipeline memory in the detection unit 16. It is difficult to complete the calculation of the whitening reference level MR4 itself within one clock cycle. However, until a new (updated) whitening reference level MR4 is calculated, the branch metric calculation can be performed using the whitening reference level MR4 stored in the storage area 56-(u). As the whitening reference level MR4 stored in the whitening reference storage unit 390 is repeatedly updated, the whitening reference level MR4 gradually approaches an appropriate value.

[0606] That is, in the detection unit 16, the branch metric calculation is completed within one clock cycle by reading the whitening reference level MR4 from the whitening reference storage unit 390, and the following operation is performed: the whitening reference level MR4 stored in the whitening reference storage unit 390 is sequentially updated so that the whitening reference level MR4 converges to an appropriate value.

[0607] Here, when the branch from the state si to the state sj is restricted by the coding rule, a storage area where access is not performed (i.e., a storage area where reading of the whitening reference level MR4 and the like is not performed) is generated in the storage area 56-(u) addressed by the quaternary code sequence including M+N = 5+1 = 6 cells of the quaternary code sequence as the temporary decoding result corresponding to the branch.

[0608] In the case of N = 0, the whitening reference storage unit 390 is unnecessary. In the case of N = 0, the branch metric calculation of Expression (9) is the branch metric calculation of Expression (4) or (6), and it uses the equalization reference level r stored in the equalization reference storage unit 350. t (s i ,s j )+Δr t (b t )=[r+Δr] t (b t ) to perform.

[0609] In the above case, as described in Expression (16), the tap coefficient p of the noise predictor 15 is updated len such that the mean square error of the whitening error w’ t is minimized. In addition, for example, the tap coefficient p of the noise predictor 15 can be updated len such that the whitening error w’ t is smaller and the minimum distance d min is larger.

[0610] For example, as shown in Expression (17), assuming that the combination of patterns that forms the minimum distance between the quaternary code sequences {311310} and {312210} is the i-th combination, the rows of the quaternary codes that form the quaternary code sequences are selected as the elements of the vector, and {311310} and {312210} are represented as vectors A i and B i .

[0611] [Mathematical Expression 17]

[0612]

[0613] In the data detection processing unit 105, the square d min of the minimum distance d min 2 is represented in Expression (18).

[0614] [Mathematical Expression 18]

[0615]

[0616] Vector A _(len+m) indicates a vector having as elements the quaternary codes in the row after the (len + m)-th code from the head of vector A i . This also applies to vector B _(len+m) .

[0617] r'(b t ) with vector b t as the independent variable is represented in Expression (19).

[0618] [Mathematical Expression 19]

[0619]

[0620] When a signal that is proportional to the whitening error w' t and inversely proportional to the minimum distance d min is defined as the error signal E indicating the error of the noise predictor 15, for example, the square of the error signal E is represented in Expression (20).

[0621] [Mathematical Expression 20]

[0622]

[0623] When performing the partial differentiation of the square of the error signal E in Expression (20) with respect to the tap coefficient p len , the partial differential value in Expression (21) can be obtained.

[0624] [Mathematical Expression 21]

[0625]

[0626] The whitening coefficient update unit 19 can update the tap coefficient p by using the partial differential value of Expression (21) through Expression (22). len .

[0627] [Mathematical formula 22]

[0628]

[0629] p len p(t) represents the tap coefficient p at time t len , that is, the tap coefficient p before update len , and p len p(t + 1) represents the tap coefficient p at time t + 1 len , that is, the tap coefficient p after update len .

[0630] β represents an update coefficient for showing the update amount of the tap coefficient p len during update.

[0631] In Expression (22), the tap coefficient p len is updated according to the error signal E such that the square of the error signal E (square error) is minimized. That is, according to the whitening error w’ t and the minimum distance d min to update the tap coefficient p len so that the whitening error w’ t is small and the minimum distance d min is large.

[0632] By using the tap coefficient p obtained in Expression (22) len to update the tap coefficient p of the noise predictor 15 len , a whitening signal z for minimizing the square error of the error signal E can be obtained t , and thus the decoding performance of Viterbi decoding can be improved.

[0633] Subsequently, as Figure 30 described, the trellis state and branches are restricted by the coding rules of the multi - code (for example, minimum run - length d, RMTR, etc.), and Viterbi decoding can be performed.

[0634] Hereinafter, specific examples of Viterbi decoding in which the trellis state and branches are restricted by the coding rules will be described.

[0635] For example, it is assumed that ML = 4, d = 0, K = M = 5, N = 0, PR(1, 2, 3, 2, 1), and RMTR = 1 are set.

[0636] In this case, if there is no restriction of RMTR = 1, the number of grid states is ML^(K - 1) = 4^(5 - 1) = 256 and the number of branches is ML^K = 4^5 = 1024.

[0637] Here, each of a, b, c, d, and e represents a one-digit ML = 4 - ary system. The states in the case where there is no restriction of RMTR = 1 are represented by s(bcde). In addition, when the ML = 4 - ary code as the temporary decoding result at time t is a, the branch from the state s(bcde) at time t - 1 to the state s(abcd) is represented by b(abcde).

[0638] In the case where there is no restriction of RMTR = 1, among the 256 states s(0000) to s(3333), for example, states such as s(0101), s(2121), s(3131), etc. cannot be taken due to the restriction of RMTR = 1, and thus these states are unnecessary.

[0639] In the case where there is no restriction of RMTR = 1, among the 256 states s(0000) to s(3333), there are 244 states that satisfy RMTR = 1.

[0640] In the case where there is no restriction of RMTR = 1, among the 1024 branches b(00000) to b(33333), for example, b(01010), b(01011), b(01012), b(01013), b(21210), b(21211), b(21212), b(21213), etc. cannot be taken due to the restriction of RMTR = 1, and thus these branches are unnecessary.

[0641] In the case where there is no restriction of RMTR = 1, among the 1024 branches b(00000) to b(33333), 940 branches satisfy RMTR = 1.

[0642] Therefore, in this case, by configuring the Viterbi decoder 320 with circuits corresponding to the 244 states and 940 branches (see Figure 31 ), the circuit size can be reduced.

[0643] When the Viterbi decoder 320 is configured with circuits corresponding to the 256 states and 1024 branches taken in the case where there is no restriction of RMTR = 1, the selector SEL pq of the state pq of the transition destination of the state transition is prohibited from selecting the path metric that adds the branch metric of the branch that cannot be taken and the state metric of the state of the transition source of the branch corresponding to that branch. Therefore, it is possible to prevent the survival of the wrong path and suppress the deterioration of the decoding performance.

[0644] Subsequently, for example, assume that there are no restrictions on ML = 4, d = 1, K = M = 3, N = 0, PR(1,2,1), and RMTR.

[0645] In this case, when there is no restriction on d = 1, the number of grid states is ML^(K - 1) = 4^(3 - 1) = 16 and the number of branches is ML^K = 4^3 = 64.

[0646] In the absence of the restriction on d = 1, for the 16 states s(00) to s(33), any state can be taken even if there is a restriction on d = 1.

[0647] In the absence of the restriction on d = 1, among the 64 branches b(000) to b(333), for example, b(101), b(121), b(131), etc. cannot be adopted due to the restriction on d = 1, and thus, they are unnecessary.

[0648] In the absence of the restriction on d = 1, among the 64 branches b(000) to b(333), there are 28 branches that satisfy d = 1.

[0649] Therefore, in this case, by configuring the Viterbi decoder 320 corresponding to the 16 states and 28 branches (see Figure 31 ), the circuit size can be reduced.

[0650] When the Viterbi decoder 32 is configured with a circuit corresponding to the 16 states and 64 branches adopted in the absence of the restriction on d = 1, the selector SEL pq that selects the path metric of the branch metric of the branch added with the branches that cannot be adopted and the state metric of the state that is the transition source of the state transition corresponding to the branch is prohibited. Therefore, the survival of the wrong path can be prevented and the degradation of the decoding performance can be suppressed.

[0651] <Conclusion>

[0652] As described above, in the recording / reproducing apparatus, light is irradiated onto a range of the optical disc 100 including the data detection target (reproduction target) track TK and the adjacent tracks TK - 1 and TK + 1, and the optical disc 100 is an optical recording medium on which a plurality of tracks are formed.

[0653] Furthermore, a reproduction signal x 1t 、x2t and x 3t and x 4t are respectively supplied to the adaptive equalizers 21, 22, 23, and 24 of the multi-input adaptive equalization unit 14.

[0654] Calculate the filtered signals y 1t 、y 2t 、y 3t 、y 4t 、y t obtained by the adaptive equalizers 21, 22, 23, 24, and obtain the equalized signal y'.

[0655] For the equalized signal y' t the crosstalk noise from the adjacent tracks TK-1 and TK+1 (the crosstalk noise remaining in the equalized signal y' t ) is whitened in the noise predictor 15 which acts as a whitening filter. The detection unit 16 performs Viterbi decoding as a multi-variate process on the equalized signal y' t (i.e., the whitened signal z t ) to obtain the multi-variate code DT.

[0656] The equalization error calculation unit 18 obtains the equalization error e' t of the equalized signal y' output from the multi-input adaptive equalization unit 14 with respect to the equalization reference level which is the ideal (true) waveform. t

[0657] In the adaptive equalizers 21, 22, 23, and 24, the tap coefficients f t for adaptive equalization are adaptively updated according to the equalization error e' clen so that the equalization error e' t becomes smaller.

[0658] In the whitening coefficient update unit 19, according to the equalization error e' t and the whitening error w' t between the whitened equalization error obtained by whitening the equalization error e' t the tap coefficients p len of the noise predictor 15 are adaptively updated to make the whitening error w' t become smaller.

[0659] After the crosstalk noise included in the equalized signal y' t is whitened in the noise predictor 15, the equalized signal y' t is processed in the detection unit 16.

[0660] Therefore, the branch metric calculation of Viterbi decoding can be performed with high precision in the detection unit 16, and the decoding performance is improved.​

[0661] Figure 38 A diagram showing the decoding performance of a recording / reproducing apparatus.

[0662] Figure 38 A in shows the equalization target (equalization target value) TPR of the modulation transfer function (MTF) of the reproduced signal when the noise predictor 15 is not provided.

[0663] In Figure 38 A, the horizontal axis represents frequency and the vertical axis represents intensity. This also applies to Figure 38 C.

[0664] In Figure 38 A, the arrow indicates the enhancement by PR equalization.

[0665] In Figure 38 A, the dashed line and the dash-dotted line indicate the crosstalk noise CNZ. This also applies to Figure 38 C.

[0666] The crosstalk noise CNZ is significantly enhanced by PR equalization.

[0667] Figure 38 B of is a diagram showing the selection of the maximum likelihood path in Viterbi decoding when the equalized signal y' t including the significantly enhanced crosstalk noise CNZ is provided to the detection unit 16 as it is.

[0668] For the equalized signal y' t not including the significantly enhanced crosstalk noise CNZ, there is no large difference in the path metric between the path through the correct state sequence as the decoding result and the path through another state sequence, and the accuracy of the selection (detection) of the maximum likelihood path may deteriorate.

[0669] Figure 38 C of shows the equalization target TPR of the MTF of the reproduced signal when the noise predictor 15 is provided.

[0670] When the noise predictor 15 is provided, the crosstalk noise CNZ is whitened and the degree of enhancement by PR equalization is suppressed.

[0671] Figure 38 D of is a diagram showing the selection of the maximum likelihood path in Viterbi decoding when the equalized signal y' t not including the whitened crosstalk noise CNZ, that is, the whitened signal z output by the noise predictor 15, is provided to the detection unit 16.

[0672] For the whitened signal z, a significant difference appears in the path metric between the path passing through the correct state sequence as the decoding result and the path passing through another state sequence, and the path metric of the path passing through the correct state sequence as the decoding result becomes smaller. Therefore, deterioration in the selection accuracy of the maximum likelihood path can be suppressed.

[0673] Generally, by designing the PR to be close to the MTF at high-density recording, enhancement of crosstalk noise can be reduced. However, although the PR is designed, it is difficult to predict in advance the actually occurring ISI.

[0674] Therefore, by providing a noise predictor 15 in which the tap coefficient p len is adaptively updated in the recording / reproducing apparatus, enhancement of crosstalk at high-density recording can be suppressed and decoding performance can be improved.

[0675] Figure 39 is a diagram showing the tap coefficient f t of the equalization error e’ clen obtained by simulation performed by the inventors of the present specification and the frequency characteristics.

[0676] In Figure 39 it, the horizontal axis represents frequency and the vertical axis represents intensity (amplitude).

[0677] In the simulation, as Figure 3 shown, an adaptive equalizer similar to the adaptive equalizers 21 to 24 processes reproduction signals of five signal channels generated from outputs of a photodetector 6 whose light receiving surface is divided into five regions, and generates an equalization signal y’ t .

[0678] A code with ML = 4 is used as the multi-value code, and RMTR = 1 (RMTR is limited to 2 or more) is allowed.

[0679] Recording of the multi-value code (quadrature code in the simulation) is performed on the optical disc 100 at a line density of 110% of AD2, and 93.36 nm is adopted as the length of a pit corresponding to the channel clock (1T).

[0680] In addition, in the simulation, K = M = 5 and N = 0, 1, 2, 3, and 4 are adopted.

[0681] Figure 39 Shows the frequency characteristics of the tap coefficient f clen (XTC coefficient) of an adaptive equalizer that processes reproduction signals of five signal channels of signal channels c = CH1, CH2, CH3, CH4, and CH5.

[0682] In addition, Figure 39Shows the equalization error e’ for the cases of N = 0 (PRML), N = 1 (NPML(1)), N = 2 (NPML(2)), N = 3 (NPML(3)), and N = 4 (NPML(4)). t (EQERROR) frequency characteristics.

[0683] The equalization error e’ in the case of N = 0 (PRML). t In the frequency characteristics of, there are parts enhanced in the low-pass and high-pass aspects. However, by providing the noise predictor 15, that is, by setting N = 1 to 4 in this text, it is confirmed that the equalization error e’ t Is whitened and the enhancement degree is suppressed.

[0684] Figure 40 Is a diagram showing the cell error rate obtained through simulations performed by the inventors of this specification.

[0685] In Figure 40 The horizontal axis represents the number of taps N of the noise predictor 15, and the vertical axis represents the cell error rate (cER).

[0686] As in Figure 39 The case of, simulations for obtaining the cell error rate are carried out.

[0687] Figure 40 Shows the cell error rates of RUB1, RUB2, RUB3, and RUB4 as four recorded Ubit blocks (RUBs) and the average value (cER) of the error rates of the four RUBs 1 to 4.

[0688] Here, RUB is a recording unit for recording data on an optical disc such as AD2.

[0689] In Figure 40 It is confirmed that in the case of N = 1 (NPML(1)), in the case of N = 2 (NPML(2)), in the case of N = 3 (NPML(3)), and in the case of N = 4 (NPML(4)), compared with the case of N = 0 (PRML(0)), the enhancement degree of the equalization error e’ t Is further suppressed, and the cell error rate is improved.

[0690] In the recording / reproducing apparatus, the tap coefficient plen of the noise predictor 15 is adaptively updated, so that the noise predictor 15 adaptively operates to whiten the crosstalk noise included in the equalization signal y’ t Output by the multi-input adaptive equalization unit 14.

[0691] For example, the whitening coefficient update unit 19 can use the equalization error e’ obtained by the equalization error calculation unit 18 t to update the tap coefficient P of the noise predictor 15 len , such that the energy of the crosstalk noise (the whitening error w’ t ) is minimized (Expressions (14) to (16)). Thereby, the whitening of the crosstalk noise is optimized.

[0692] For example, the whitening coefficient update unit 19 can update the tap coefficient P of the noise predictor 15 len , such that the mean square error of the error signal E is minimized (Expressions (20) to (22)), where the error signal E is the crosstalk noise (the whitening error w’ min ) with respect to the minimum distance d in the Viterbi decoding. t )). Thus, the processing of the noise predictor 15 can be optimized corresponding to the execution of the Viterbi decoding.

[0693] In the detection unit 16, the tap coefficient P of the noise predictor 15 updated by the whitening coefficient update unit 19 len is used to perform the branch metric calculation (Expression (9)). Thus, in the detection unit 16, the NPML corresponding to the whitening signal z t obtained via the noise predictor 15 is implemented.

[0694] By using the tap coefficient p of the noise predictor 15 len as a reference level for the branch metric calculation for the Viterbi decoding to perform the calculation, and using the quaternary code sequences b t to b t-(M+N-1) read from the whitening reference storage unit 390 as the temporary decoding result used, the whitening reference level MR4 stored in the whitening reference storage unit 390 can be read, and the load of the branch metric calculation can be reduced.

[0695] <Another Embodiment of the Optical Disc Recording / Reproducing Apparatus Applying the Present Technology>

[0696] Figure 41 FIG. is a block diagram showing an exemplary configuration of another embodiment of a recording / reproducing apparatus (optical disc recording / reproducing apparatus) applying the present technology.

[0697] In the drawings, the same reference numerals are given to the parts corresponding to Figure 1 the case of. Hereinafter, its description will be appropriately omitted.

[0698] In Figure 41 , configurations other than the optical pickup 101, the matrix circuit 104, and the data detection processing unit 105 in Figure 1 are not shown.

[0699] In Figure 1 , as Figure 41 shown, the optical pickup 101, the matrix circuit 104, and the ADC 11, PLL 12, and AGC 13 that constitute the data detection processing unit 105 are configured to reproduce (generate) a reproduction signal x ct of the signal reproduction unit 411.

[0700] Figure 41 The recording / reproducing apparatus in

[0701] not only includes the signal reproduction unit 411, but also includes signal reproduction units 412 and 413 having a configuration similar to that of the signal reproduction unit 411. Figure 41 Therefore, in the recording / reproducing apparatus in

[0702] laser light is emitted from each of the three signal reproduction units 411 to 413 to the optical disc 100. In the three signal reproduction units 411 to 413, the reflected light of the laser light from the optical disc 100 is received, and a reproduction signal corresponding to the light reception amount of the reflected light is generated and output. The reproduction signals output from the three signal reproduction units 411 to 413 are supplied to the multi-input adaptive equalization unit 14. Figure 41 In the recording / reproducing apparatus in Figure 1 , after the multi-input adaptive equalization unit 14 in the data detection processing unit 105, the reproduction signals output from the three signal reproduction units 411 to 413 are subjected to processing similar to the processing of the recording / reproducing apparatus in

[0703] In Figure 41 , three signal reproduction units 411 to 413 are provided. However, two or four or more signal reproduction units may be provided.

[0704] Figure 42 is a diagram showing an example in which the optical disc 100 is irradiated with laser light by the three signal reproduction units 411 to 413.

[0705] When the track TK of the optical disc 100 is the reproduction target track, the laser light is irradiated to a plurality of adjacent tracks including the track TK.

[0706] For example, the laser light irradiated by the signal reproduction unit 411 is irradiated to the track TK and two adjacent tracks TK-1 and TK-2 adjacent to the inner peripheral side of the track TK, thereby forming a light spot SP1.

[0707] The laser light irradiated by the signal reproduction unit 412 is irradiated to the track TK, the track TK-1 adjacent to the inner peripheral side of the track TK, and the track TK+1 adjacent to the outer peripheral side of the track TK, thereby forming a light spot SP2.

[0708] In addition, the laser light irradiated by the signal reproduction unit 413 is irradiated onto the track TK and two adjacent tracks TK+1 and TK+2 adjacent to the outer peripheral side of the track TK, so that a light spot SP3 is formed.

[0709] As described above, after the multi-input adaptive equalization unit 14 of the data detection processing unit 105, processing can be performed on the reproduction signals generated according to the light reception amounts of the reflected light of the laser light irradiated by each of the plurality of signal reproduction units 411 to 413.

[0710] As described above, embodiments of the present technology have been specifically described. However, the embodiments of the present technology are not limited to the above embodiments, and various modifications can be made based on the technical concept of the present technology. For example, the values of the wavelength of the above laser light source, the track pitch, and the recording line density are exemplary and other values can be used. In addition, indicators other than the above indicators can be used as indicators for evaluating the reproduction performance. In addition, the present technology can be applied to a device that only performs one of recording and reproduction on an optical disc.

[0711] <Description of a computer to which the present technology is applied>

[0712] Next, a series of processing steps from the above multi-input adaptive equalization unit 14 to the detection unit 16, the equalization error calculation unit 18, and the whitening coefficient update unit 19 can be executed by hardware or software. When a series of processing steps are executed by software, the program of the software is installed on a general-purpose computer or the like.

[0713] Figure 43 is a block diagram showing an exemplary configuration of an embodiment of a computer installed with a program for executing the above series of processing steps.

[0714] The program can be pre-recorded on the hard disk 905 or the ROM 903 used as a recording medium embedded in the computer.

[0715] Alternatively, the program can be stored (recorded) on a removable recording medium 911 driven by a drive 909. The removable recording medium 911 can be provided as so-called packaged software. Here, examples of the removable recording medium 911 include a floppy disk, a compact disc read-only memory (CD-ROM), a magneto-optical (MO) disk, a digital versatile disc (DVD), a magnetic disk, and a semiconductor memory.

[0716] The program can be installed from the above removable recording medium 911 and can also be downloaded to the computer via a communication network or a broadcast network and can be installed in the embedded hard disk 905. That is, for example, the program can be wirelessly transmitted from a download site to the computer via a digital satellite broadcast artificial satellite, or can be transmitted to the computer in a wired manner via a network such as a local area network (LAN) or the Internet.

[0717] The computer includes a central processing unit (CPU) 902. The input / output interface 910 is connected to the CPU 902 via a bus 901.

[0718] When the user inputs an instruction by operating the input unit 907 through the input / output interface 910, the CPU 902 executes a program stored in the read-only memory (ROM) 903 according to the instruction. Optionally, the CPU 902 loads and executes a program in the hard disk 905 stored in the random access memory (RAM) 904.

[0719] Therefore, the CPU 902 executes processing according to the above flowchart or executes processing configured by the above block diagram. The CPU 902 causes the output unit 906 to output the processing result, causes the communication unit 908 to transmit the processing result, and causes the hard disk 905 to record the processing result via the input / output interface 910 as needed.

[0720] The input unit 907 is configured with a keyboard, a mouse, a microphone, etc. The output unit 906 is configured with a liquid crystal display (LCD), a speaker, etc.

[0721] Here, in this specification, the processing executed by the computer according to the program does not necessarily have to be executed chronologically in the order described in the flowchart. That is, the processing executed by the computer according to the program also includes processing executed separately or in parallel (e.g., parallel processing or processing by an object).

[0722] The program can be a program processed by one computer (processor), or can be distributed and processed by multiple computers. In addition, the program can be a program transmitted to a remote computer for execution.

[0723] Embodiments of the present technology are not limited to the above embodiments, and various modifications can be made within the scope of the present technology without departing from the gist of the present technology.

[0724] For example, the present technology can be configured as cloud computing, in which a function is shared and processed by multiple devices via a network.

[0725] The beneficial effects described in this specification are only exemplary and not restrictive, and other beneficial effects can be achieved.

[0726] The present technology can be configured as follows.

[0727] <1>

[0728] A signal processing device includes:

[0729] An equalization unit configured to perform partial response (PR) equalization on a reproduction signal of a multi-valued code with an ML value ≥ 3; and

[0730] A decoding unit configured to perform maximum likelihood decoding on an equalized signal obtained through PR equalization.

[0731] <2>

[0732] The signal processing apparatus according to <1>, wherein the decoding unit restricts trellis states and branches according to the coding rule of the multi - code, and performs maximum likelihood decoding.

[0733] <3>

[0734] The signal processing apparatus according to <1> or <2>, further comprising:

[0735] A storage unit having a storage area in which, for a reference level used for branch metric calculation, the stored value updates the reference level according to an initial value obtained through convolution calculation with PR, and the storage area is addressed by a stored value of a path memory that stores a sequence of the multi - code corresponding to a path reaching the trellis state.

[0736] Wherein the decoding unit performs the branch metric calculation using the reference level read from the storage unit.

[0737] <4>

[0738] The signal processing apparatus according to <3>, wherein the storage unit is an equalization reference storage unit that stores an equalization reference level, the equalization reference level is a reference level of the equalized signal, and

[0739] wherein the equalization reference level is updated according to an equalization error between the equalized signal and the equalization reference level.

[0740] <5>

[0741] The signal processing apparatus according to <4>, wherein filter coefficients for the PR equalization are updated according to the equalization error.

[0742] <6>

[0743] The signal processing apparatus according to <3>, further comprising:

[0744] A noise predictor configured to whiten noise included in the equalized signal;

[0745] wherein the decoding unit performs maximum likelihood decoding on the whitened signal that is the whitened equalized signal; and

[0746] Among them, filter coefficients of the noise predictor are updated according to a whitening error between an equalization error and a whitened equalization error obtained by whitening the equalization error, where the equalization error is an error between the equalization signal and an equalization reference level that is a reference level of the equalization signal.

[0747] <7>

[0748] The signal processing device according to <6>, wherein the storage unit is a whitening reference storage unit that stores a whitening reference level which is a reference level of the whitened signal, and

[0749] wherein the whitening reference level is updated according to the filter coefficients of the noise predictor.

[0750] <8>

[0751] The signal processing device according to <6> or <7>, wherein filter coefficients for the PR equalization are updated according to the equalization error.

[0752] <9>

[0753] The signal processing device according to <3>, wherein reading the reference level from the storage unit is restricted by the coding rule of the multi - code.

[0754] <10>

[0755] The signal processing device according to any one of <1> to <9>, wherein the reproduction signal is a signal obtained by receiving reflected light of light irradiated on a plurality of adjacent tracks of an optical recording medium on which the multi - code is recorded.

[0756] <11>

[0757] The signal processing device according to <10>, wherein the reproduction signal includes a plurality of reproduction signals obtained from the signal obtained by receiving the reflected light.

[0758] <12>

[0759] A signal processing method includes:

[0760] Performing partial response (PR) equalization on a reproduction signal of a multi - code with ML value ≥ 3; and

[0761] Performing maximum likelihood decoding on the equalization signal obtained by the PR equalization.

[0762] <13>

[0763] A program causes a computer to function as:

[0764] An equalization unit configured to perform partial response (PR) equalization on a reproduction signal of a multi-level code with an ML value ≥ 3; and

[0765] A decoding unit configured to perform maximum likelihood decoding on the equalized signal obtained by PR equalization.

[0766] List of reference numerals

[0767] 1 Semiconductor laser

[0768] 2 Collimator lens

[0769] 3 Polarizing beam splitter

[0770] 4 Objective lens

[0771] 5 Lens

[0772] 6 Photoelectric detector

[0773] 6a, 6b, 6c, 6d1, 6d2 Regions

[0774] 11 ADC

[0775] 12 PLL

[0776] 13 AGC

[0777] 14 Multi-input adaptive equalization unit

[0778] 15 Noise predictor

[0779] 16 Detection unit

[0780] 17 Delay unit

[0781] 18 Equalization error calculation unit

[0782] 19 Whitening coefficient update unit

[0783] 21 to 24 Adaptive equalizer

[0784] 30-1 to 30-(L-1) Delay units

[0785] 31-0 to 31-(L-1) Multipliers

[0786] 34 Adder

[0787] 32-0 to 32-(L-1) Calculators

[0788] 33-0 to 33-(L-1) Integrators

[0789] 41-1 to 41-N Delay units

[0790] 42-1 to 42-N Multipliers

[0791] 43 Adder

[0792] 51-(v) Storage Area

[0793] 52-(v) Delay Unit

[0794] 53-(v) Adder

[0795] 54-(v), 55 Switch

[0796] 56-(u) Storage Area

[0797] 57-(u), 58 Switch

[0798] 100 Optical Disc

[0799] 101 Optical Pickup

[0800] 102 Spindle Motor

[0801] 103 Thread Mechanism

[0802] 104 Matrix Circuit

[0803] 105 Data Detection and Processing Unit

[0804] 106 Wobble Signal Processing Circuit

[0805] 107 Encoding / Decoding Unit

[0806] 108 Host I / F

[0807] 109 Address Decoder

[0808] 110 System Controller

[0809] 111 Optical Block Servo Circuit

[0810] 112 Spindle Servo Circuit

[0811] 113 Laser Driver

[0812] 114 Write Strategy Unit

[0813] 115 Thread Driver

[0814] 116 ADIP Demodulation Processing Unit

[0815] 117 Spindle Driver

[0816] 118 Driver

[0817] 200 Host Device

[0818] 301, 302 Delay Unit

[0819] 304 to 306 Multiplier

[0820] 307 Adder

[0821] 320 Viterbi Decoder

[0822] 330-pq ACS Unit

[0823] 350 Equalization Reference Storage Unit

[0824] 371-1 to 371-N Delay Unit

[0825] 372-1 to 372-N Multiplier

[0826] 373 Adder

[0827] 390 Whitening Reference Storage Unit

[0828] 411 to 413 Signal Reproduction Unit

[0829] 901 Bus

[0830] 902 CPU

[0831] 903 ROM

[0832] 904 RAM

[0833] 905 Hard Disk

[0834] 906 Output Unit

[0835] 907 Input Unit

[0836] 908 Communication Unit

[0837] 909 Driver

[0838] 910 Input / Output Interface

[0839] 911 Removable Recording Medium

Claims

1. A signal processing device, comprising: an equalization unit configured to perform partial response (PR) equalization on a reproduction signal of a multi - ary code with a multi - ary ML value ≥ 3; and a decoding unit configured to perform maximum likelihood decoding on the equalized signal obtained through PR equalization, wherein the decoding unit restricts trellis states and branches according to the coding rule of the multi - ary code and performs the maximum likelihood decoding.

2. The signal processing device according to claim 1, further comprising: a storage unit configured to have a storage area in which a reference level for branch metric calculation is stored, the value of the reference level being updated according to an initial value obtained through convolution calculation with PR, and the storage area being addressed by a stored value of a path memory that stores a sequence of the multi - ary code corresponding to a path reaching the trellis state; wherein the decoding unit performs the branch metric calculation using the reference level read from the storage unit.

3. The signal processing device according to claim 2, wherein the storage unit is an equalization reference storage unit that stores an equalization reference level which is a reference level of the equalized signal, and wherein the equalization reference level is updated according to an equalization error between the equalized signal and the equalization reference level.

4. The signal processing device according to claim 3, wherein filter coefficients for the PR equalization are updated according to the equalization error.

5. The signal processing device according to claim 2, further comprising: a noise predictor configured to whiten noise included in the equalized signal; wherein the decoding unit performs the maximum likelihood decoding on the whitened signal which is the equalized signal after whitening; and wherein filter coefficients of the noise predictor are updated according to a whitening error between the equalization error and a whitened equalization error obtained by whitening the equalization error, the equalization error being an error between the equalized signal and the equalization reference level which is a reference level of the equalized signal.

6. The signal processing device according to claim 5, wherein the storage unit is a whitening reference storage unit that stores a whitening reference level which is a reference level of the whitened signal, and wherein the whitening reference level is updated according to the filter coefficients of the noise predictor.

7. The signal processing device according to claim 5, wherein filter coefficients for the PR equalization are updated according to the equalization error.

8. The signal processing device according to claim 2, wherein reading the reference level from the storage unit is restricted by the coding rule of the multi - ary code.

9. The signal processing device according to claim 1, wherein the reproduction signal is a signal obtained by receiving reflected light of light irradiating a plurality of adjacent tracks of an optical recording medium on which the multi - ary code is recorded.

10. The signal processing device according to claim 9, wherein the reproduction signal includes a plurality of reproduction signals obtained from the signal obtained by receiving the reflected light.

11. A signal processing method, comprising: performing partial response PR equalization on a reproduction signal of a multi - ary code with a multi - ary ML value ≥ 3; and performing maximum likelihood decoding on the equalized signal obtained through PR equalization, wherein the trellis states and branches are restricted by the coding rule of the multi - ary code, and the maximum likelihood decoding is performed.

12. A computer - readable storage medium storing a program which, when executed by a computer, causes the computer to function as: an equalization unit configured to perform partial response PR equalization on a reproduction signal of a multi - ary code with a multi - ary ML value ≥ 3; and a decoding unit configured to perform maximum likelihood decoding on the equalized signal obtained through PR equalization, wherein the decoding unit restricts the trellis states and branches by the coding rule of the multi - ary code and performs the maximum likelihood decoding.

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